1 /* 2 * Copyright (c) 2021 Microchip Technology Inc. and its subsidiaries. 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7 #ifndef _MEC_UART_H 8 #define _MEC_UART_H 9 10 #include <stdint.h> 11 #include <stddef.h> 12 13 #define MCHP_UART_RX_FIFO_MAX_LEN 16u 14 #define MCHP_UART_TX_FIFO_MAX_LEN 16u 15 16 #define MCHP_UART_BAUD_RATE_MIN 50u 17 #define MCHP_UART_BAUD_RATE_MAX 1500000u 18 19 #define MCHP_UART_SPACING 0x400u 20 21 /* 22 * LCR DLAB=0 23 * Transmit buffer(WO), Receive buffer(RO) 24 * LCR DLAB=1, BAUD rate divisor LSB 25 */ 26 #define MCHP_UART_RTXB_OFS 0u 27 #define MCHP_UART_BRGD_LSB_OFS 0u 28 29 /* 30 * LCR DLAB=0 31 * Interrupt Enable Register, R/W 32 * LCR DLAB=1, BAUD rate divisor MSB 33 */ 34 #define MCHP_UART_BRGD_MSB_OFS 1u 35 #define MCHP_UART_IER_OFS 1u 36 #define MCHP_UART_IER_MASK 0x0fu 37 #define MCHP_UART_IER_ERDAI 0x01u /* Received data available and timeouts */ 38 #define MCHP_UART_IER_ETHREI 0x02u /* TX Holding register empty */ 39 #define MCHP_UART_IER_ELSI 0x04u /* Errors: Overrun, Parity, Framing, and Break */ 40 #define MCHP_UART_IER_EMSI 0x08u /* Modem Status */ 41 #define MCHP_UART_IER_ALL 0x0fu 42 43 /* FIFO Contro Register, Write-Only */ 44 #define MCHP_UART_FCR_OFS 2u 45 #define MCHP_UART_FCR_MASK 0xcfu 46 #define MCHP_UART_FCR_EXRF 0x01u /* Enable TX & RX FIFO's */ 47 #define MCHP_UART_FCR_CLR_RX_FIFO 0x02u /* Clear RX FIFO, bit is self-clearing */ 48 #define MCHP_UART_FCR_CLR_TX_FIFO 0x04u /* Clear TX FIFO, bit is self-clearing */ 49 #define MCHP_UART_FCR_DMA_EN 0x08u /* DMA Mode Enable. Not implemented */ 50 #define MCHP_UART_FCR_RX_FIFO_LVL_MASK 0xc0u /* RX FIFO trigger level mask */ 51 #define MCHP_UART_FCR_RX_FIFO_LVL_1 0x00u 52 #define MCHP_UART_FCR_RX_FIFO_LVL_4 0x40u 53 #define MCHP_UART_FCR_RX_FIFO_LVL_8 0x80u 54 #define MCHP_UART_FCR_RX_FIFO_LVL_14 0xc0u 55 56 /* Interrupt Identification Register, Read-Only */ 57 #define MCHP_UART_IIR_OFS 2u 58 #define MCHP_UART_IIR_MASK 0xcfu 59 #define MCHP_UART_IIR_NOT_IPEND 0x01u 60 #define MCHP_UART_IIR_INTID_MASK0 0x07u 61 #define MCHP_UART_IIR_INTID_POS 1u 62 #define MCHP_UART_IIR_INTID_MASK 0x0eu 63 #define MCHP_UART_IIR_FIFO_EN_MASK 0xc0u 64 /* 65 * interrupt values 66 * Highest priority: Line status, overrun, framing, or break 67 * Highest-1. RX data available or RX FIFO trigger level reached 68 * Highest-2. RX timeout 69 * Highest-3. TX Holding register empty 70 * Highest-4. MODEM status 71 */ 72 #define MCHP_UART_IIR_INT_NONE 0x01u 73 #define MCHP_UART_IIR_INT_LS 0x06u 74 #define MCHP_UART_IIR_INT_RX 0x04u 75 #define MCHP_UART_IIR_INT_RX_TMOUT 0x0cu 76 #define MCHP_UART_IIR_INT_THRE 0x02u 77 #define MCHP_UART_IIR_INT_MS 0x00u 78 79 /* Line Control Register R/W */ 80 #define MCHP_UART_LCR_OFS 3u 81 #define MCHP_UART_LCR_WORD_LEN_MASK 0x03u 82 #define MCHP_UART_LCR_WORD_LEN_5 0x00u 83 #define MCHP_UART_LCR_WORD_LEN_6 0x01u 84 #define MCHP_UART_LCR_WORD_LEN_7 0x02u 85 #define MCHP_UART_LCR_WORD_LEN_8 0x03u 86 #define MCHP_UART_LCR_STOP_BIT_1 0x00u 87 #define MCHP_UART_LCR_STOP_BIT_2 0x04u 88 #define MCHP_UART_LCR_PARITY_NONE 0x00u 89 #define MCHP_UART_LCR_PARITY_EN 0x08u 90 #define MCHP_UART_LCR_PARITY_ODD 0x00u 91 #define MCHP_UART_LCR_PARITY_EVEN 0x10u 92 #define MCHP_UART_LCR_STICK_PARITY 0x20u 93 #define MCHP_UART_LCR_BREAK_EN 0x40u 94 #define MCHP_UART_LCR_DLAB_EN 0x80u 95 96 /* MODEM Control Register R/W */ 97 #define MCHP_UART_MCR_OFS 4u 98 #define MCHP_UART_MCR_MASK 0x1fu 99 #define MCHP_UART_MCR_DTRn 0x01u 100 #define MCHP_UART_MCR_RTSn 0x02u 101 #define MCHP_UART_MCR_OUT1 0x04u 102 #define MCHP_UART_MCR_OUT2 0x08u 103 #define MCHP_UART_MCR_LOOPBCK_EN 0x10u 104 105 /* Line Status Register RO */ 106 #define MCHP_UART_LSR_OFS 5u 107 #define MCHP_UART_LSR_DATA_RDY 0x01u 108 #define MCHP_UART_LSR_OVERRUN 0x02u 109 #define MCHP_UART_LSR_PARITY 0x04u 110 #define MCHP_UART_LSR_FRAME 0x08u 111 #define MCHP_UART_LSR_RX_BREAK 0x10u 112 #define MCHP_UART_LSR_THRE 0x20u 113 #define MCHP_UART_LSR_TEMT 0x40u 114 #define MCHP_UART_LSR_FIFO_ERR 0x80u 115 #define MCHP_UART_LSR_ANY 0xffu 116 117 /* MODEM Status Register RO */ 118 #define MCHP_UART_MSR_OFS 6u 119 #define MCHP_UART_MSR_DCTS 0x01u 120 #define MCHP_UART_MSR_DDSR 0x02u 121 #define MCHP_UART_MSR_TERI 0x04u 122 #define MCHP_UART_MSR_DDCD 0x08u 123 #define MCHP_UART_MSR_CTS 0x10u 124 #define MCHP_UART_MSR_DSR 0x20u 125 #define MCHP_UART_MSR_RI 0x40u 126 #define MCHP_UART_MSR_DCD 0x80u 127 128 /* Scratch Register RO */ 129 #define MCHP_UART_SCR_OFS 7u 130 131 /* UART Logical Device Activate Register */ 132 #define MCHP_UART_LD_ACT_OFS 0x330u 133 #define MCHP_UART_LD_ACTIVATE 0x01u 134 135 /* UART Logical Device Config Register */ 136 #define MCHP_UART_LD_CFG_OFS 0x3f0u 137 #define MCHP_UART_LD_CFG_INTCLK 0u 138 #define MCHP_UART_LD_CFG_NO_INVERT 0u 139 #define MCHP_UART_LD_CFG_RESET_SYS 0u 140 #define MCHP_UART_LD_CFG_EXTCLK BIT(0) 141 #define MCHP_UART_LD_CFG_RESET_VCC BIT(1) 142 #define MCHP_UART_LD_CFG_INVERT BIT(2) 143 144 /* BAUD rate generator */ 145 #define MCHP_UART_INT_CLK_24M BIT(15) 146 147 /* 1.8MHz internal clock source */ 148 #define MCHP_UART_1P8M_BAUD_50 2304u 149 #define MCHP_UART_1P8M_BAUD_110 1536u 150 #define MCHP_UART_1P8M_BAUD_150 768u 151 #define MCHP_UART_1P8M_BAUD_300 384u 152 #define MCHP_UART_1P8M_BAUD_1200 96u 153 #define MCHP_UART_1P8M_BAUD_2400 48u 154 #define MCHP_UART_1P8M_BAUD_9600 12u 155 #define MCHP_UART_1P8M_BAUD_19200 6u 156 #define MCHP_UART_1P8M_BAUD_38400 3u 157 #define MCHP_UART_1P8M_BAUD_57600 2u 158 #define MCHP_UART_1P8M_BAUD_115200 1u 159 160 /* 24MHz internal clock source. n = 24e6 / (BAUD * 16) = 1500000 / BAUD */ 161 #define MCHP_UART_24M_BAUD_115200 ((13u) + (MCHP_UART_INT_CLK_24M)) 162 #define MCHP_UART_24M_BAUD_57600 ((26u) + (MCHP_UART_INT_CLK_24M)) 163 164 /** @brief 16550 compatible UART. Size = 1012(0x3f4) */ 165 struct uart_regs { 166 volatile uint8_t RTXB; 167 volatile uint8_t IER; 168 volatile uint8_t IIR_FCR; 169 volatile uint8_t LCR; 170 volatile uint8_t MCR; 171 volatile uint8_t LSR; 172 volatile uint8_t MSR; 173 volatile uint8_t SCR; 174 uint8_t RSVDA[0x330 - 0x08]; 175 volatile uint8_t ACTV; 176 uint8_t RSVDB[0x3f0 - 0x331]; 177 volatile uint8_t CFG_SEL; 178 }; 179 180 #endif /* #ifndef _MEC_MCHP_UART_H */ 181
