1 /***************************************************************************//** 2 * \file cyip_scb_v2.h 3 * 4 * \brief 5 * SCB IP definitions 6 * 7 ******************************************************************************** 8 * \copyright 9 * (c) (2016-2023), Cypress Semiconductor Corporation (an Infineon company) or 10 * an affiliate of Cypress Semiconductor Corporation. 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 *******************************************************************************/ 26 27 #ifndef _CYIP_SCB_V2_H_ 28 #define _CYIP_SCB_V2_H_ 29 30 #include "cyip_headers.h" 31 32 /******************************************************************************* 33 * SCB 34 *******************************************************************************/ 35 36 #define SCB_V2_SECTION_SIZE 0x00010000UL 37 38 /** 39 * \brief Serial Communications Block (SPI/UART/I2C) (CySCB) 40 */ 41 typedef struct { 42 __IOM uint32_t CTRL; /*!< 0x00000000 Generic control */ 43 __IM uint32_t STATUS; /*!< 0x00000004 Generic status */ 44 __IOM uint32_t CMD_RESP_CTRL; /*!< 0x00000008 Command/response control */ 45 __IM uint32_t CMD_RESP_STATUS; /*!< 0x0000000C Command/response status */ 46 __IM uint32_t RESERVED[4]; 47 __IOM uint32_t SPI_CTRL; /*!< 0x00000020 SPI control */ 48 __IM uint32_t SPI_STATUS; /*!< 0x00000024 SPI status */ 49 __IOM uint32_t SPI_TX_CTRL; /*!< 0x00000028 SPI transmitter control */ 50 __IOM uint32_t SPI_RX_CTRL; /*!< 0x0000002C SPI receiver control */ 51 __IM uint32_t RESERVED1[4]; 52 __IOM uint32_t UART_CTRL; /*!< 0x00000040 UART control */ 53 __IOM uint32_t UART_TX_CTRL; /*!< 0x00000044 UART transmitter control */ 54 __IOM uint32_t UART_RX_CTRL; /*!< 0x00000048 UART receiver control */ 55 __IM uint32_t UART_RX_STATUS; /*!< 0x0000004C UART receiver status */ 56 __IOM uint32_t UART_FLOW_CTRL; /*!< 0x00000050 UART flow control */ 57 __IM uint32_t RESERVED2[3]; 58 __IOM uint32_t I2C_CTRL; /*!< 0x00000060 I2C control */ 59 __IM uint32_t I2C_STATUS; /*!< 0x00000064 I2C status */ 60 __IOM uint32_t I2C_M_CMD; /*!< 0x00000068 I2C master command */ 61 __IOM uint32_t I2C_S_CMD; /*!< 0x0000006C I2C slave command */ 62 __IOM uint32_t I2C_CFG; /*!< 0x00000070 I2C configuration */ 63 __IM uint32_t RESERVED3[99]; 64 __IOM uint32_t TX_CTRL; /*!< 0x00000200 Transmitter control */ 65 __IOM uint32_t TX_FIFO_CTRL; /*!< 0x00000204 Transmitter FIFO control */ 66 __IM uint32_t TX_FIFO_STATUS; /*!< 0x00000208 Transmitter FIFO status */ 67 __IM uint32_t RESERVED4[13]; 68 __OM uint32_t TX_FIFO_WR; /*!< 0x00000240 Transmitter FIFO write */ 69 __IM uint32_t RESERVED5[47]; 70 __IOM uint32_t RX_CTRL; /*!< 0x00000300 Receiver control */ 71 __IOM uint32_t RX_FIFO_CTRL; /*!< 0x00000304 Receiver FIFO control */ 72 __IM uint32_t RX_FIFO_STATUS; /*!< 0x00000308 Receiver FIFO status */ 73 __IM uint32_t RESERVED6; 74 __IOM uint32_t RX_MATCH; /*!< 0x00000310 Slave address and mask */ 75 __IM uint32_t RESERVED7[11]; 76 __IM uint32_t RX_FIFO_RD; /*!< 0x00000340 Receiver FIFO read */ 77 __IM uint32_t RX_FIFO_RD_SILENT; /*!< 0x00000344 Receiver FIFO read silent */ 78 __IM uint32_t RESERVED8[46]; 79 __IOM uint32_t EZ_DATA[512]; /*!< 0x00000400 Memory buffer */ 80 __IM uint32_t RESERVED9[128]; 81 __IM uint32_t INTR_CAUSE; /*!< 0x00000E00 Active clocked interrupt signal */ 82 __IM uint32_t RESERVED10[31]; 83 __IOM uint32_t INTR_I2C_EC; /*!< 0x00000E80 Externally clocked I2C interrupt request */ 84 __IM uint32_t RESERVED11; 85 __IOM uint32_t INTR_I2C_EC_MASK; /*!< 0x00000E88 Externally clocked I2C interrupt mask */ 86 __IM uint32_t INTR_I2C_EC_MASKED; /*!< 0x00000E8C Externally clocked I2C interrupt masked */ 87 __IM uint32_t RESERVED12[12]; 88 __IOM uint32_t INTR_SPI_EC; /*!< 0x00000EC0 Externally clocked SPI interrupt request */ 89 __IM uint32_t RESERVED13; 90 __IOM uint32_t INTR_SPI_EC_MASK; /*!< 0x00000EC8 Externally clocked SPI interrupt mask */ 91 __IM uint32_t INTR_SPI_EC_MASKED; /*!< 0x00000ECC Externally clocked SPI interrupt masked */ 92 __IM uint32_t RESERVED14[12]; 93 __IOM uint32_t INTR_M; /*!< 0x00000F00 Master interrupt request */ 94 __IOM uint32_t INTR_M_SET; /*!< 0x00000F04 Master interrupt set request */ 95 __IOM uint32_t INTR_M_MASK; /*!< 0x00000F08 Master interrupt mask */ 96 __IM uint32_t INTR_M_MASKED; /*!< 0x00000F0C Master interrupt masked request */ 97 __IM uint32_t RESERVED15[12]; 98 __IOM uint32_t INTR_S; /*!< 0x00000F40 Slave interrupt request */ 99 __IOM uint32_t INTR_S_SET; /*!< 0x00000F44 Slave interrupt set request */ 100 __IOM uint32_t INTR_S_MASK; /*!< 0x00000F48 Slave interrupt mask */ 101 __IM uint32_t INTR_S_MASKED; /*!< 0x00000F4C Slave interrupt masked request */ 102 __IM uint32_t RESERVED16[12]; 103 __IOM uint32_t INTR_TX; /*!< 0x00000F80 Transmitter interrupt request */ 104 __IOM uint32_t INTR_TX_SET; /*!< 0x00000F84 Transmitter interrupt set request */ 105 __IOM uint32_t INTR_TX_MASK; /*!< 0x00000F88 Transmitter interrupt mask */ 106 __IM uint32_t INTR_TX_MASKED; /*!< 0x00000F8C Transmitter interrupt masked request */ 107 __IM uint32_t RESERVED17[12]; 108 __IOM uint32_t INTR_RX; /*!< 0x00000FC0 Receiver interrupt request */ 109 __IOM uint32_t INTR_RX_SET; /*!< 0x00000FC4 Receiver interrupt set request */ 110 __IOM uint32_t INTR_RX_MASK; /*!< 0x00000FC8 Receiver interrupt mask */ 111 __IM uint32_t INTR_RX_MASKED; /*!< 0x00000FCC Receiver interrupt masked request */ 112 } CySCB_V2_Type; /*!< Size = 4048 (0xFD0) */ 113 114 115 /* SCB.CTRL */ 116 #define SCB_V2_CTRL_OVS_Pos 0UL 117 #define SCB_V2_CTRL_OVS_Msk 0xFUL 118 #define SCB_V2_CTRL_EC_AM_MODE_Pos 8UL 119 #define SCB_V2_CTRL_EC_AM_MODE_Msk 0x100UL 120 #define SCB_V2_CTRL_EC_OP_MODE_Pos 9UL 121 #define SCB_V2_CTRL_EC_OP_MODE_Msk 0x200UL 122 #define SCB_V2_CTRL_EZ_MODE_Pos 10UL 123 #define SCB_V2_CTRL_EZ_MODE_Msk 0x400UL 124 #define SCB_V2_CTRL_CMD_RESP_MODE_Pos 12UL 125 #define SCB_V2_CTRL_CMD_RESP_MODE_Msk 0x1000UL 126 #define SCB_V2_CTRL_MEM_WIDTH_Pos 14UL 127 #define SCB_V2_CTRL_MEM_WIDTH_Msk 0xC000UL 128 #define SCB_V2_CTRL_ADDR_ACCEPT_Pos 16UL 129 #define SCB_V2_CTRL_ADDR_ACCEPT_Msk 0x10000UL 130 #define SCB_V2_CTRL_BLOCK_Pos 17UL 131 #define SCB_V2_CTRL_BLOCK_Msk 0x20000UL 132 #define SCB_V2_CTRL_MODE_Pos 24UL 133 #define SCB_V2_CTRL_MODE_Msk 0x3000000UL 134 #define SCB_V2_CTRL_EC_ACCESS_Pos 28UL 135 #define SCB_V2_CTRL_EC_ACCESS_Msk 0x10000000UL 136 #define SCB_V2_CTRL_ENABLED_Pos 31UL 137 #define SCB_V2_CTRL_ENABLED_Msk 0x80000000UL 138 /* SCB.STATUS */ 139 #define SCB_V2_STATUS_EC_BUSY_Pos 0UL 140 #define SCB_V2_STATUS_EC_BUSY_Msk 0x1UL 141 /* SCB.CMD_RESP_CTRL */ 142 #define SCB_V2_CMD_RESP_CTRL_BASE_RD_ADDR_Pos 0UL 143 #define SCB_V2_CMD_RESP_CTRL_BASE_RD_ADDR_Msk 0x1FFUL 144 #define SCB_V2_CMD_RESP_CTRL_BASE_WR_ADDR_Pos 16UL 145 #define SCB_V2_CMD_RESP_CTRL_BASE_WR_ADDR_Msk 0x1FF0000UL 146 /* SCB.CMD_RESP_STATUS */ 147 #define SCB_V2_CMD_RESP_STATUS_CURR_RD_ADDR_Pos 0UL 148 #define SCB_V2_CMD_RESP_STATUS_CURR_RD_ADDR_Msk 0x1FFUL 149 #define SCB_V2_CMD_RESP_STATUS_CURR_WR_ADDR_Pos 16UL 150 #define SCB_V2_CMD_RESP_STATUS_CURR_WR_ADDR_Msk 0x1FF0000UL 151 #define SCB_V2_CMD_RESP_STATUS_CMD_RESP_EC_BUS_BUSY_Pos 30UL 152 #define SCB_V2_CMD_RESP_STATUS_CMD_RESP_EC_BUS_BUSY_Msk 0x40000000UL 153 #define SCB_V2_CMD_RESP_STATUS_CMD_RESP_EC_BUSY_Pos 31UL 154 #define SCB_V2_CMD_RESP_STATUS_CMD_RESP_EC_BUSY_Msk 0x80000000UL 155 /* SCB.SPI_CTRL */ 156 #define SCB_V2_SPI_CTRL_SSEL_CONTINUOUS_Pos 0UL 157 #define SCB_V2_SPI_CTRL_SSEL_CONTINUOUS_Msk 0x1UL 158 #define SCB_V2_SPI_CTRL_SELECT_PRECEDE_Pos 1UL 159 #define SCB_V2_SPI_CTRL_SELECT_PRECEDE_Msk 0x2UL 160 #define SCB_V2_SPI_CTRL_CPHA_Pos 2UL 161 #define SCB_V2_SPI_CTRL_CPHA_Msk 0x4UL 162 #define SCB_V2_SPI_CTRL_CPOL_Pos 3UL 163 #define SCB_V2_SPI_CTRL_CPOL_Msk 0x8UL 164 #define SCB_V2_SPI_CTRL_LATE_MISO_SAMPLE_Pos 4UL 165 #define SCB_V2_SPI_CTRL_LATE_MISO_SAMPLE_Msk 0x10UL 166 #define SCB_V2_SPI_CTRL_SCLK_CONTINUOUS_Pos 5UL 167 #define SCB_V2_SPI_CTRL_SCLK_CONTINUOUS_Msk 0x20UL 168 #define SCB_V2_SPI_CTRL_SSEL_POLARITY0_Pos 8UL 169 #define SCB_V2_SPI_CTRL_SSEL_POLARITY0_Msk 0x100UL 170 #define SCB_V2_SPI_CTRL_SSEL_POLARITY1_Pos 9UL 171 #define SCB_V2_SPI_CTRL_SSEL_POLARITY1_Msk 0x200UL 172 #define SCB_V2_SPI_CTRL_SSEL_POLARITY2_Pos 10UL 173 #define SCB_V2_SPI_CTRL_SSEL_POLARITY2_Msk 0x400UL 174 #define SCB_V2_SPI_CTRL_SSEL_POLARITY3_Pos 11UL 175 #define SCB_V2_SPI_CTRL_SSEL_POLARITY3_Msk 0x800UL 176 #define SCB_V2_SPI_CTRL_SSEL_SETUP_DEL_Pos 12UL 177 #define SCB_V2_SPI_CTRL_SSEL_SETUP_DEL_Msk 0x1000UL 178 #define SCB_V2_SPI_CTRL_SSEL_HOLD_DEL_Pos 13UL 179 #define SCB_V2_SPI_CTRL_SSEL_HOLD_DEL_Msk 0x2000UL 180 #define SCB_V2_SPI_CTRL_SSEL_INTER_FRAME_DEL_Pos 14UL 181 #define SCB_V2_SPI_CTRL_SSEL_INTER_FRAME_DEL_Msk 0x4000UL 182 #define SCB_V2_SPI_CTRL_LOOPBACK_Pos 16UL 183 #define SCB_V2_SPI_CTRL_LOOPBACK_Msk 0x10000UL 184 #define SCB_V2_SPI_CTRL_MODE_Pos 24UL 185 #define SCB_V2_SPI_CTRL_MODE_Msk 0x3000000UL 186 #define SCB_V2_SPI_CTRL_SSEL_Pos 26UL 187 #define SCB_V2_SPI_CTRL_SSEL_Msk 0xC000000UL 188 #define SCB_V2_SPI_CTRL_MASTER_MODE_Pos 31UL 189 #define SCB_V2_SPI_CTRL_MASTER_MODE_Msk 0x80000000UL 190 /* SCB.SPI_STATUS */ 191 #define SCB_V2_SPI_STATUS_BUS_BUSY_Pos 0UL 192 #define SCB_V2_SPI_STATUS_BUS_BUSY_Msk 0x1UL 193 #define SCB_V2_SPI_STATUS_SPI_EC_BUSY_Pos 1UL 194 #define SCB_V2_SPI_STATUS_SPI_EC_BUSY_Msk 0x2UL 195 #define SCB_V2_SPI_STATUS_CURR_EZ_ADDR_Pos 8UL 196 #define SCB_V2_SPI_STATUS_CURR_EZ_ADDR_Msk 0xFF00UL 197 #define SCB_V2_SPI_STATUS_BASE_EZ_ADDR_Pos 16UL 198 #define SCB_V2_SPI_STATUS_BASE_EZ_ADDR_Msk 0xFF0000UL 199 /* SCB.SPI_TX_CTRL */ 200 #define SCB_V2_SPI_TX_CTRL_PARITY_Pos 4UL 201 #define SCB_V2_SPI_TX_CTRL_PARITY_Msk 0x10UL 202 #define SCB_V2_SPI_TX_CTRL_PARITY_ENABLED_Pos 5UL 203 #define SCB_V2_SPI_TX_CTRL_PARITY_ENABLED_Msk 0x20UL 204 /* SCB.SPI_RX_CTRL */ 205 #define SCB_V2_SPI_RX_CTRL_PARITY_Pos 4UL 206 #define SCB_V2_SPI_RX_CTRL_PARITY_Msk 0x10UL 207 #define SCB_V2_SPI_RX_CTRL_PARITY_ENABLED_Pos 5UL 208 #define SCB_V2_SPI_RX_CTRL_PARITY_ENABLED_Msk 0x20UL 209 #define SCB_V2_SPI_RX_CTRL_DROP_ON_PARITY_ERROR_Pos 8UL 210 #define SCB_V2_SPI_RX_CTRL_DROP_ON_PARITY_ERROR_Msk 0x100UL 211 /* SCB.UART_CTRL */ 212 #define SCB_V2_UART_CTRL_LOOPBACK_Pos 16UL 213 #define SCB_V2_UART_CTRL_LOOPBACK_Msk 0x10000UL 214 #define SCB_V2_UART_CTRL_MODE_Pos 24UL 215 #define SCB_V2_UART_CTRL_MODE_Msk 0x3000000UL 216 /* SCB.UART_TX_CTRL */ 217 #define SCB_V2_UART_TX_CTRL_STOP_BITS_Pos 0UL 218 #define SCB_V2_UART_TX_CTRL_STOP_BITS_Msk 0x7UL 219 #define SCB_V2_UART_TX_CTRL_PARITY_Pos 4UL 220 #define SCB_V2_UART_TX_CTRL_PARITY_Msk 0x10UL 221 #define SCB_V2_UART_TX_CTRL_PARITY_ENABLED_Pos 5UL 222 #define SCB_V2_UART_TX_CTRL_PARITY_ENABLED_Msk 0x20UL 223 #define SCB_V2_UART_TX_CTRL_RETRY_ON_NACK_Pos 8UL 224 #define SCB_V2_UART_TX_CTRL_RETRY_ON_NACK_Msk 0x100UL 225 /* SCB.UART_RX_CTRL */ 226 #define SCB_V2_UART_RX_CTRL_STOP_BITS_Pos 0UL 227 #define SCB_V2_UART_RX_CTRL_STOP_BITS_Msk 0x7UL 228 #define SCB_V2_UART_RX_CTRL_PARITY_Pos 4UL 229 #define SCB_V2_UART_RX_CTRL_PARITY_Msk 0x10UL 230 #define SCB_V2_UART_RX_CTRL_PARITY_ENABLED_Pos 5UL 231 #define SCB_V2_UART_RX_CTRL_PARITY_ENABLED_Msk 0x20UL 232 #define SCB_V2_UART_RX_CTRL_POLARITY_Pos 6UL 233 #define SCB_V2_UART_RX_CTRL_POLARITY_Msk 0x40UL 234 #define SCB_V2_UART_RX_CTRL_DROP_ON_PARITY_ERROR_Pos 8UL 235 #define SCB_V2_UART_RX_CTRL_DROP_ON_PARITY_ERROR_Msk 0x100UL 236 #define SCB_V2_UART_RX_CTRL_DROP_ON_FRAME_ERROR_Pos 9UL 237 #define SCB_V2_UART_RX_CTRL_DROP_ON_FRAME_ERROR_Msk 0x200UL 238 #define SCB_V2_UART_RX_CTRL_MP_MODE_Pos 10UL 239 #define SCB_V2_UART_RX_CTRL_MP_MODE_Msk 0x400UL 240 #define SCB_V2_UART_RX_CTRL_LIN_MODE_Pos 12UL 241 #define SCB_V2_UART_RX_CTRL_LIN_MODE_Msk 0x1000UL 242 #define SCB_V2_UART_RX_CTRL_SKIP_START_Pos 13UL 243 #define SCB_V2_UART_RX_CTRL_SKIP_START_Msk 0x2000UL 244 #define SCB_V2_UART_RX_CTRL_BREAK_WIDTH_Pos 16UL 245 #define SCB_V2_UART_RX_CTRL_BREAK_WIDTH_Msk 0xF0000UL 246 #define SCB_V2_UART_RX_CTRL_BREAK_LEVEL_Pos 24UL 247 #define SCB_V2_UART_RX_CTRL_BREAK_LEVEL_Msk 0x1000000UL 248 /* SCB.UART_RX_STATUS */ 249 #define SCB_V2_UART_RX_STATUS_BR_COUNTER_Pos 0UL 250 #define SCB_V2_UART_RX_STATUS_BR_COUNTER_Msk 0xFFFUL 251 /* SCB.UART_FLOW_CTRL */ 252 #define SCB_V2_UART_FLOW_CTRL_TRIGGER_LEVEL_Pos 0UL 253 #define SCB_V2_UART_FLOW_CTRL_TRIGGER_LEVEL_Msk 0xFFUL 254 #define SCB_V2_UART_FLOW_CTRL_RTS_POLARITY_Pos 16UL 255 #define SCB_V2_UART_FLOW_CTRL_RTS_POLARITY_Msk 0x10000UL 256 #define SCB_V2_UART_FLOW_CTRL_CTS_POLARITY_Pos 24UL 257 #define SCB_V2_UART_FLOW_CTRL_CTS_POLARITY_Msk 0x1000000UL 258 #define SCB_V2_UART_FLOW_CTRL_CTS_ENABLED_Pos 25UL 259 #define SCB_V2_UART_FLOW_CTRL_CTS_ENABLED_Msk 0x2000000UL 260 /* SCB.I2C_CTRL */ 261 #define SCB_V2_I2C_CTRL_HIGH_PHASE_OVS_Pos 0UL 262 #define SCB_V2_I2C_CTRL_HIGH_PHASE_OVS_Msk 0xFUL 263 #define SCB_V2_I2C_CTRL_LOW_PHASE_OVS_Pos 4UL 264 #define SCB_V2_I2C_CTRL_LOW_PHASE_OVS_Msk 0xF0UL 265 #define SCB_V2_I2C_CTRL_M_READY_DATA_ACK_Pos 8UL 266 #define SCB_V2_I2C_CTRL_M_READY_DATA_ACK_Msk 0x100UL 267 #define SCB_V2_I2C_CTRL_M_NOT_READY_DATA_NACK_Pos 9UL 268 #define SCB_V2_I2C_CTRL_M_NOT_READY_DATA_NACK_Msk 0x200UL 269 #define SCB_V2_I2C_CTRL_S_GENERAL_IGNORE_Pos 11UL 270 #define SCB_V2_I2C_CTRL_S_GENERAL_IGNORE_Msk 0x800UL 271 #define SCB_V2_I2C_CTRL_S_READY_ADDR_ACK_Pos 12UL 272 #define SCB_V2_I2C_CTRL_S_READY_ADDR_ACK_Msk 0x1000UL 273 #define SCB_V2_I2C_CTRL_S_READY_DATA_ACK_Pos 13UL 274 #define SCB_V2_I2C_CTRL_S_READY_DATA_ACK_Msk 0x2000UL 275 #define SCB_V2_I2C_CTRL_S_NOT_READY_ADDR_NACK_Pos 14UL 276 #define SCB_V2_I2C_CTRL_S_NOT_READY_ADDR_NACK_Msk 0x4000UL 277 #define SCB_V2_I2C_CTRL_S_NOT_READY_DATA_NACK_Pos 15UL 278 #define SCB_V2_I2C_CTRL_S_NOT_READY_DATA_NACK_Msk 0x8000UL 279 #define SCB_V2_I2C_CTRL_LOOPBACK_Pos 16UL 280 #define SCB_V2_I2C_CTRL_LOOPBACK_Msk 0x10000UL 281 #define SCB_V2_I2C_CTRL_SLAVE_MODE_Pos 30UL 282 #define SCB_V2_I2C_CTRL_SLAVE_MODE_Msk 0x40000000UL 283 #define SCB_V2_I2C_CTRL_MASTER_MODE_Pos 31UL 284 #define SCB_V2_I2C_CTRL_MASTER_MODE_Msk 0x80000000UL 285 /* SCB.I2C_STATUS */ 286 #define SCB_V2_I2C_STATUS_BUS_BUSY_Pos 0UL 287 #define SCB_V2_I2C_STATUS_BUS_BUSY_Msk 0x1UL 288 #define SCB_V2_I2C_STATUS_I2C_EC_BUSY_Pos 1UL 289 #define SCB_V2_I2C_STATUS_I2C_EC_BUSY_Msk 0x2UL 290 #define SCB_V2_I2C_STATUS_I2CS_IC_BUSY_Pos 2UL 291 #define SCB_V2_I2C_STATUS_I2CS_IC_BUSY_Msk 0x4UL 292 #define SCB_V2_I2C_STATUS_S_READ_Pos 4UL 293 #define SCB_V2_I2C_STATUS_S_READ_Msk 0x10UL 294 #define SCB_V2_I2C_STATUS_M_READ_Pos 5UL 295 #define SCB_V2_I2C_STATUS_M_READ_Msk 0x20UL 296 #define SCB_V2_I2C_STATUS_CURR_EZ_ADDR_Pos 8UL 297 #define SCB_V2_I2C_STATUS_CURR_EZ_ADDR_Msk 0xFF00UL 298 #define SCB_V2_I2C_STATUS_BASE_EZ_ADDR_Pos 16UL 299 #define SCB_V2_I2C_STATUS_BASE_EZ_ADDR_Msk 0xFF0000UL 300 /* SCB.I2C_M_CMD */ 301 #define SCB_V2_I2C_M_CMD_M_START_Pos 0UL 302 #define SCB_V2_I2C_M_CMD_M_START_Msk 0x1UL 303 #define SCB_V2_I2C_M_CMD_M_START_ON_IDLE_Pos 1UL 304 #define SCB_V2_I2C_M_CMD_M_START_ON_IDLE_Msk 0x2UL 305 #define SCB_V2_I2C_M_CMD_M_ACK_Pos 2UL 306 #define SCB_V2_I2C_M_CMD_M_ACK_Msk 0x4UL 307 #define SCB_V2_I2C_M_CMD_M_NACK_Pos 3UL 308 #define SCB_V2_I2C_M_CMD_M_NACK_Msk 0x8UL 309 #define SCB_V2_I2C_M_CMD_M_STOP_Pos 4UL 310 #define SCB_V2_I2C_M_CMD_M_STOP_Msk 0x10UL 311 /* SCB.I2C_S_CMD */ 312 #define SCB_V2_I2C_S_CMD_S_ACK_Pos 0UL 313 #define SCB_V2_I2C_S_CMD_S_ACK_Msk 0x1UL 314 #define SCB_V2_I2C_S_CMD_S_NACK_Pos 1UL 315 #define SCB_V2_I2C_S_CMD_S_NACK_Msk 0x2UL 316 /* SCB.I2C_CFG */ 317 #define SCB_V2_I2C_CFG_SDA_IN_FILT_TRIM_Pos 0UL 318 #define SCB_V2_I2C_CFG_SDA_IN_FILT_TRIM_Msk 0x3UL 319 #define SCB_V2_I2C_CFG_SDA_IN_FILT_SEL_Pos 4UL 320 #define SCB_V2_I2C_CFG_SDA_IN_FILT_SEL_Msk 0x10UL 321 #define SCB_V2_I2C_CFG_SCL_IN_FILT_TRIM_Pos 8UL 322 #define SCB_V2_I2C_CFG_SCL_IN_FILT_TRIM_Msk 0x300UL 323 #define SCB_V2_I2C_CFG_SCL_IN_FILT_SEL_Pos 12UL 324 #define SCB_V2_I2C_CFG_SCL_IN_FILT_SEL_Msk 0x1000UL 325 #define SCB_V2_I2C_CFG_SDA_OUT_FILT0_TRIM_Pos 16UL 326 #define SCB_V2_I2C_CFG_SDA_OUT_FILT0_TRIM_Msk 0x30000UL 327 #define SCB_V2_I2C_CFG_SDA_OUT_FILT1_TRIM_Pos 18UL 328 #define SCB_V2_I2C_CFG_SDA_OUT_FILT1_TRIM_Msk 0xC0000UL 329 #define SCB_V2_I2C_CFG_SDA_OUT_FILT2_TRIM_Pos 20UL 330 #define SCB_V2_I2C_CFG_SDA_OUT_FILT2_TRIM_Msk 0x300000UL 331 #define SCB_V2_I2C_CFG_SDA_OUT_FILT_SEL_Pos 28UL 332 #define SCB_V2_I2C_CFG_SDA_OUT_FILT_SEL_Msk 0x30000000UL 333 /* SCB.TX_CTRL */ 334 #define SCB_V2_TX_CTRL_DATA_WIDTH_Pos 0UL 335 #define SCB_V2_TX_CTRL_DATA_WIDTH_Msk 0x1FUL 336 #define SCB_V2_TX_CTRL_MSB_FIRST_Pos 8UL 337 #define SCB_V2_TX_CTRL_MSB_FIRST_Msk 0x100UL 338 #define SCB_V2_TX_CTRL_OPEN_DRAIN_Pos 16UL 339 #define SCB_V2_TX_CTRL_OPEN_DRAIN_Msk 0x10000UL 340 /* SCB.TX_FIFO_CTRL */ 341 #define SCB_V2_TX_FIFO_CTRL_TRIGGER_LEVEL_Pos 0UL 342 #define SCB_V2_TX_FIFO_CTRL_TRIGGER_LEVEL_Msk 0xFFUL 343 #define SCB_V2_TX_FIFO_CTRL_CLEAR_Pos 16UL 344 #define SCB_V2_TX_FIFO_CTRL_CLEAR_Msk 0x10000UL 345 #define SCB_V2_TX_FIFO_CTRL_FREEZE_Pos 17UL 346 #define SCB_V2_TX_FIFO_CTRL_FREEZE_Msk 0x20000UL 347 /* SCB.TX_FIFO_STATUS */ 348 #define SCB_V2_TX_FIFO_STATUS_USED_Pos 0UL 349 #define SCB_V2_TX_FIFO_STATUS_USED_Msk 0x1FFUL 350 #define SCB_V2_TX_FIFO_STATUS_SR_VALID_Pos 15UL 351 #define SCB_V2_TX_FIFO_STATUS_SR_VALID_Msk 0x8000UL 352 #define SCB_V2_TX_FIFO_STATUS_RD_PTR_Pos 16UL 353 #define SCB_V2_TX_FIFO_STATUS_RD_PTR_Msk 0xFF0000UL 354 #define SCB_V2_TX_FIFO_STATUS_WR_PTR_Pos 24UL 355 #define SCB_V2_TX_FIFO_STATUS_WR_PTR_Msk 0xFF000000UL 356 /* SCB.TX_FIFO_WR */ 357 #define SCB_V2_TX_FIFO_WR_DATA_Pos 0UL 358 #define SCB_V2_TX_FIFO_WR_DATA_Msk 0xFFFFFFFFUL 359 /* SCB.RX_CTRL */ 360 #define SCB_V2_RX_CTRL_DATA_WIDTH_Pos 0UL 361 #define SCB_V2_RX_CTRL_DATA_WIDTH_Msk 0x1FUL 362 #define SCB_V2_RX_CTRL_MSB_FIRST_Pos 8UL 363 #define SCB_V2_RX_CTRL_MSB_FIRST_Msk 0x100UL 364 #define SCB_V2_RX_CTRL_MEDIAN_Pos 9UL 365 #define SCB_V2_RX_CTRL_MEDIAN_Msk 0x200UL 366 /* SCB.RX_FIFO_CTRL */ 367 #define SCB_V2_RX_FIFO_CTRL_TRIGGER_LEVEL_Pos 0UL 368 #define SCB_V2_RX_FIFO_CTRL_TRIGGER_LEVEL_Msk 0xFFUL 369 #define SCB_V2_RX_FIFO_CTRL_CLEAR_Pos 16UL 370 #define SCB_V2_RX_FIFO_CTRL_CLEAR_Msk 0x10000UL 371 #define SCB_V2_RX_FIFO_CTRL_FREEZE_Pos 17UL 372 #define SCB_V2_RX_FIFO_CTRL_FREEZE_Msk 0x20000UL 373 /* SCB.RX_FIFO_STATUS */ 374 #define SCB_V2_RX_FIFO_STATUS_USED_Pos 0UL 375 #define SCB_V2_RX_FIFO_STATUS_USED_Msk 0x1FFUL 376 #define SCB_V2_RX_FIFO_STATUS_SR_VALID_Pos 15UL 377 #define SCB_V2_RX_FIFO_STATUS_SR_VALID_Msk 0x8000UL 378 #define SCB_V2_RX_FIFO_STATUS_RD_PTR_Pos 16UL 379 #define SCB_V2_RX_FIFO_STATUS_RD_PTR_Msk 0xFF0000UL 380 #define SCB_V2_RX_FIFO_STATUS_WR_PTR_Pos 24UL 381 #define SCB_V2_RX_FIFO_STATUS_WR_PTR_Msk 0xFF000000UL 382 /* SCB.RX_MATCH */ 383 #define SCB_V2_RX_MATCH_ADDR_Pos 0UL 384 #define SCB_V2_RX_MATCH_ADDR_Msk 0xFFUL 385 #define SCB_V2_RX_MATCH_MASK_Pos 16UL 386 #define SCB_V2_RX_MATCH_MASK_Msk 0xFF0000UL 387 /* SCB.RX_FIFO_RD */ 388 #define SCB_V2_RX_FIFO_RD_DATA_Pos 0UL 389 #define SCB_V2_RX_FIFO_RD_DATA_Msk 0xFFFFFFFFUL 390 /* SCB.RX_FIFO_RD_SILENT */ 391 #define SCB_V2_RX_FIFO_RD_SILENT_DATA_Pos 0UL 392 #define SCB_V2_RX_FIFO_RD_SILENT_DATA_Msk 0xFFFFFFFFUL 393 /* SCB.EZ_DATA */ 394 #define SCB_V2_EZ_DATA_EZ_DATA_Pos 0UL 395 #define SCB_V2_EZ_DATA_EZ_DATA_Msk 0xFFUL 396 /* SCB.INTR_CAUSE */ 397 #define SCB_V2_INTR_CAUSE_M_Pos 0UL 398 #define SCB_V2_INTR_CAUSE_M_Msk 0x1UL 399 #define SCB_V2_INTR_CAUSE_S_Pos 1UL 400 #define SCB_V2_INTR_CAUSE_S_Msk 0x2UL 401 #define SCB_V2_INTR_CAUSE_TX_Pos 2UL 402 #define SCB_V2_INTR_CAUSE_TX_Msk 0x4UL 403 #define SCB_V2_INTR_CAUSE_RX_Pos 3UL 404 #define SCB_V2_INTR_CAUSE_RX_Msk 0x8UL 405 #define SCB_V2_INTR_CAUSE_I2C_EC_Pos 4UL 406 #define SCB_V2_INTR_CAUSE_I2C_EC_Msk 0x10UL 407 #define SCB_V2_INTR_CAUSE_SPI_EC_Pos 5UL 408 #define SCB_V2_INTR_CAUSE_SPI_EC_Msk 0x20UL 409 /* SCB.INTR_I2C_EC */ 410 #define SCB_V2_INTR_I2C_EC_WAKE_UP_Pos 0UL 411 #define SCB_V2_INTR_I2C_EC_WAKE_UP_Msk 0x1UL 412 #define SCB_V2_INTR_I2C_EC_EZ_STOP_Pos 1UL 413 #define SCB_V2_INTR_I2C_EC_EZ_STOP_Msk 0x2UL 414 #define SCB_V2_INTR_I2C_EC_EZ_WRITE_STOP_Pos 2UL 415 #define SCB_V2_INTR_I2C_EC_EZ_WRITE_STOP_Msk 0x4UL 416 #define SCB_V2_INTR_I2C_EC_EZ_READ_STOP_Pos 3UL 417 #define SCB_V2_INTR_I2C_EC_EZ_READ_STOP_Msk 0x8UL 418 /* SCB.INTR_I2C_EC_MASK */ 419 #define SCB_V2_INTR_I2C_EC_MASK_WAKE_UP_Pos 0UL 420 #define SCB_V2_INTR_I2C_EC_MASK_WAKE_UP_Msk 0x1UL 421 #define SCB_V2_INTR_I2C_EC_MASK_EZ_STOP_Pos 1UL 422 #define SCB_V2_INTR_I2C_EC_MASK_EZ_STOP_Msk 0x2UL 423 #define SCB_V2_INTR_I2C_EC_MASK_EZ_WRITE_STOP_Pos 2UL 424 #define SCB_V2_INTR_I2C_EC_MASK_EZ_WRITE_STOP_Msk 0x4UL 425 #define SCB_V2_INTR_I2C_EC_MASK_EZ_READ_STOP_Pos 3UL 426 #define SCB_V2_INTR_I2C_EC_MASK_EZ_READ_STOP_Msk 0x8UL 427 /* SCB.INTR_I2C_EC_MASKED */ 428 #define SCB_V2_INTR_I2C_EC_MASKED_WAKE_UP_Pos 0UL 429 #define SCB_V2_INTR_I2C_EC_MASKED_WAKE_UP_Msk 0x1UL 430 #define SCB_V2_INTR_I2C_EC_MASKED_EZ_STOP_Pos 1UL 431 #define SCB_V2_INTR_I2C_EC_MASKED_EZ_STOP_Msk 0x2UL 432 #define SCB_V2_INTR_I2C_EC_MASKED_EZ_WRITE_STOP_Pos 2UL 433 #define SCB_V2_INTR_I2C_EC_MASKED_EZ_WRITE_STOP_Msk 0x4UL 434 #define SCB_V2_INTR_I2C_EC_MASKED_EZ_READ_STOP_Pos 3UL 435 #define SCB_V2_INTR_I2C_EC_MASKED_EZ_READ_STOP_Msk 0x8UL 436 /* SCB.INTR_SPI_EC */ 437 #define SCB_V2_INTR_SPI_EC_WAKE_UP_Pos 0UL 438 #define SCB_V2_INTR_SPI_EC_WAKE_UP_Msk 0x1UL 439 #define SCB_V2_INTR_SPI_EC_EZ_STOP_Pos 1UL 440 #define SCB_V2_INTR_SPI_EC_EZ_STOP_Msk 0x2UL 441 #define SCB_V2_INTR_SPI_EC_EZ_WRITE_STOP_Pos 2UL 442 #define SCB_V2_INTR_SPI_EC_EZ_WRITE_STOP_Msk 0x4UL 443 #define SCB_V2_INTR_SPI_EC_EZ_READ_STOP_Pos 3UL 444 #define SCB_V2_INTR_SPI_EC_EZ_READ_STOP_Msk 0x8UL 445 /* SCB.INTR_SPI_EC_MASK */ 446 #define SCB_V2_INTR_SPI_EC_MASK_WAKE_UP_Pos 0UL 447 #define SCB_V2_INTR_SPI_EC_MASK_WAKE_UP_Msk 0x1UL 448 #define SCB_V2_INTR_SPI_EC_MASK_EZ_STOP_Pos 1UL 449 #define SCB_V2_INTR_SPI_EC_MASK_EZ_STOP_Msk 0x2UL 450 #define SCB_V2_INTR_SPI_EC_MASK_EZ_WRITE_STOP_Pos 2UL 451 #define SCB_V2_INTR_SPI_EC_MASK_EZ_WRITE_STOP_Msk 0x4UL 452 #define SCB_V2_INTR_SPI_EC_MASK_EZ_READ_STOP_Pos 3UL 453 #define SCB_V2_INTR_SPI_EC_MASK_EZ_READ_STOP_Msk 0x8UL 454 /* SCB.INTR_SPI_EC_MASKED */ 455 #define SCB_V2_INTR_SPI_EC_MASKED_WAKE_UP_Pos 0UL 456 #define SCB_V2_INTR_SPI_EC_MASKED_WAKE_UP_Msk 0x1UL 457 #define SCB_V2_INTR_SPI_EC_MASKED_EZ_STOP_Pos 1UL 458 #define SCB_V2_INTR_SPI_EC_MASKED_EZ_STOP_Msk 0x2UL 459 #define SCB_V2_INTR_SPI_EC_MASKED_EZ_WRITE_STOP_Pos 2UL 460 #define SCB_V2_INTR_SPI_EC_MASKED_EZ_WRITE_STOP_Msk 0x4UL 461 #define SCB_V2_INTR_SPI_EC_MASKED_EZ_READ_STOP_Pos 3UL 462 #define SCB_V2_INTR_SPI_EC_MASKED_EZ_READ_STOP_Msk 0x8UL 463 /* SCB.INTR_M */ 464 #define SCB_V2_INTR_M_I2C_ARB_LOST_Pos 0UL 465 #define SCB_V2_INTR_M_I2C_ARB_LOST_Msk 0x1UL 466 #define SCB_V2_INTR_M_I2C_NACK_Pos 1UL 467 #define SCB_V2_INTR_M_I2C_NACK_Msk 0x2UL 468 #define SCB_V2_INTR_M_I2C_ACK_Pos 2UL 469 #define SCB_V2_INTR_M_I2C_ACK_Msk 0x4UL 470 #define SCB_V2_INTR_M_I2C_STOP_Pos 4UL 471 #define SCB_V2_INTR_M_I2C_STOP_Msk 0x10UL 472 #define SCB_V2_INTR_M_I2C_BUS_ERROR_Pos 8UL 473 #define SCB_V2_INTR_M_I2C_BUS_ERROR_Msk 0x100UL 474 #define SCB_V2_INTR_M_SPI_DONE_Pos 9UL 475 #define SCB_V2_INTR_M_SPI_DONE_Msk 0x200UL 476 /* SCB.INTR_M_SET */ 477 #define SCB_V2_INTR_M_SET_I2C_ARB_LOST_Pos 0UL 478 #define SCB_V2_INTR_M_SET_I2C_ARB_LOST_Msk 0x1UL 479 #define SCB_V2_INTR_M_SET_I2C_NACK_Pos 1UL 480 #define SCB_V2_INTR_M_SET_I2C_NACK_Msk 0x2UL 481 #define SCB_V2_INTR_M_SET_I2C_ACK_Pos 2UL 482 #define SCB_V2_INTR_M_SET_I2C_ACK_Msk 0x4UL 483 #define SCB_V2_INTR_M_SET_I2C_STOP_Pos 4UL 484 #define SCB_V2_INTR_M_SET_I2C_STOP_Msk 0x10UL 485 #define SCB_V2_INTR_M_SET_I2C_BUS_ERROR_Pos 8UL 486 #define SCB_V2_INTR_M_SET_I2C_BUS_ERROR_Msk 0x100UL 487 #define SCB_V2_INTR_M_SET_SPI_DONE_Pos 9UL 488 #define SCB_V2_INTR_M_SET_SPI_DONE_Msk 0x200UL 489 /* SCB.INTR_M_MASK */ 490 #define SCB_V2_INTR_M_MASK_I2C_ARB_LOST_Pos 0UL 491 #define SCB_V2_INTR_M_MASK_I2C_ARB_LOST_Msk 0x1UL 492 #define SCB_V2_INTR_M_MASK_I2C_NACK_Pos 1UL 493 #define SCB_V2_INTR_M_MASK_I2C_NACK_Msk 0x2UL 494 #define SCB_V2_INTR_M_MASK_I2C_ACK_Pos 2UL 495 #define SCB_V2_INTR_M_MASK_I2C_ACK_Msk 0x4UL 496 #define SCB_V2_INTR_M_MASK_I2C_STOP_Pos 4UL 497 #define SCB_V2_INTR_M_MASK_I2C_STOP_Msk 0x10UL 498 #define SCB_V2_INTR_M_MASK_I2C_BUS_ERROR_Pos 8UL 499 #define SCB_V2_INTR_M_MASK_I2C_BUS_ERROR_Msk 0x100UL 500 #define SCB_V2_INTR_M_MASK_SPI_DONE_Pos 9UL 501 #define SCB_V2_INTR_M_MASK_SPI_DONE_Msk 0x200UL 502 /* SCB.INTR_M_MASKED */ 503 #define SCB_V2_INTR_M_MASKED_I2C_ARB_LOST_Pos 0UL 504 #define SCB_V2_INTR_M_MASKED_I2C_ARB_LOST_Msk 0x1UL 505 #define SCB_V2_INTR_M_MASKED_I2C_NACK_Pos 1UL 506 #define SCB_V2_INTR_M_MASKED_I2C_NACK_Msk 0x2UL 507 #define SCB_V2_INTR_M_MASKED_I2C_ACK_Pos 2UL 508 #define SCB_V2_INTR_M_MASKED_I2C_ACK_Msk 0x4UL 509 #define SCB_V2_INTR_M_MASKED_I2C_STOP_Pos 4UL 510 #define SCB_V2_INTR_M_MASKED_I2C_STOP_Msk 0x10UL 511 #define SCB_V2_INTR_M_MASKED_I2C_BUS_ERROR_Pos 8UL 512 #define SCB_V2_INTR_M_MASKED_I2C_BUS_ERROR_Msk 0x100UL 513 #define SCB_V2_INTR_M_MASKED_SPI_DONE_Pos 9UL 514 #define SCB_V2_INTR_M_MASKED_SPI_DONE_Msk 0x200UL 515 /* SCB.INTR_S */ 516 #define SCB_V2_INTR_S_I2C_ARB_LOST_Pos 0UL 517 #define SCB_V2_INTR_S_I2C_ARB_LOST_Msk 0x1UL 518 #define SCB_V2_INTR_S_I2C_NACK_Pos 1UL 519 #define SCB_V2_INTR_S_I2C_NACK_Msk 0x2UL 520 #define SCB_V2_INTR_S_I2C_ACK_Pos 2UL 521 #define SCB_V2_INTR_S_I2C_ACK_Msk 0x4UL 522 #define SCB_V2_INTR_S_I2C_WRITE_STOP_Pos 3UL 523 #define SCB_V2_INTR_S_I2C_WRITE_STOP_Msk 0x8UL 524 #define SCB_V2_INTR_S_I2C_STOP_Pos 4UL 525 #define SCB_V2_INTR_S_I2C_STOP_Msk 0x10UL 526 #define SCB_V2_INTR_S_I2C_START_Pos 5UL 527 #define SCB_V2_INTR_S_I2C_START_Msk 0x20UL 528 #define SCB_V2_INTR_S_I2C_ADDR_MATCH_Pos 6UL 529 #define SCB_V2_INTR_S_I2C_ADDR_MATCH_Msk 0x40UL 530 #define SCB_V2_INTR_S_I2C_GENERAL_Pos 7UL 531 #define SCB_V2_INTR_S_I2C_GENERAL_Msk 0x80UL 532 #define SCB_V2_INTR_S_I2C_BUS_ERROR_Pos 8UL 533 #define SCB_V2_INTR_S_I2C_BUS_ERROR_Msk 0x100UL 534 #define SCB_V2_INTR_S_SPI_EZ_WRITE_STOP_Pos 9UL 535 #define SCB_V2_INTR_S_SPI_EZ_WRITE_STOP_Msk 0x200UL 536 #define SCB_V2_INTR_S_SPI_EZ_STOP_Pos 10UL 537 #define SCB_V2_INTR_S_SPI_EZ_STOP_Msk 0x400UL 538 #define SCB_V2_INTR_S_SPI_BUS_ERROR_Pos 11UL 539 #define SCB_V2_INTR_S_SPI_BUS_ERROR_Msk 0x800UL 540 /* SCB.INTR_S_SET */ 541 #define SCB_V2_INTR_S_SET_I2C_ARB_LOST_Pos 0UL 542 #define SCB_V2_INTR_S_SET_I2C_ARB_LOST_Msk 0x1UL 543 #define SCB_V2_INTR_S_SET_I2C_NACK_Pos 1UL 544 #define SCB_V2_INTR_S_SET_I2C_NACK_Msk 0x2UL 545 #define SCB_V2_INTR_S_SET_I2C_ACK_Pos 2UL 546 #define SCB_V2_INTR_S_SET_I2C_ACK_Msk 0x4UL 547 #define SCB_V2_INTR_S_SET_I2C_WRITE_STOP_Pos 3UL 548 #define SCB_V2_INTR_S_SET_I2C_WRITE_STOP_Msk 0x8UL 549 #define SCB_V2_INTR_S_SET_I2C_STOP_Pos 4UL 550 #define SCB_V2_INTR_S_SET_I2C_STOP_Msk 0x10UL 551 #define SCB_V2_INTR_S_SET_I2C_START_Pos 5UL 552 #define SCB_V2_INTR_S_SET_I2C_START_Msk 0x20UL 553 #define SCB_V2_INTR_S_SET_I2C_ADDR_MATCH_Pos 6UL 554 #define SCB_V2_INTR_S_SET_I2C_ADDR_MATCH_Msk 0x40UL 555 #define SCB_V2_INTR_S_SET_I2C_GENERAL_Pos 7UL 556 #define SCB_V2_INTR_S_SET_I2C_GENERAL_Msk 0x80UL 557 #define SCB_V2_INTR_S_SET_I2C_BUS_ERROR_Pos 8UL 558 #define SCB_V2_INTR_S_SET_I2C_BUS_ERROR_Msk 0x100UL 559 #define SCB_V2_INTR_S_SET_SPI_EZ_WRITE_STOP_Pos 9UL 560 #define SCB_V2_INTR_S_SET_SPI_EZ_WRITE_STOP_Msk 0x200UL 561 #define SCB_V2_INTR_S_SET_SPI_EZ_STOP_Pos 10UL 562 #define SCB_V2_INTR_S_SET_SPI_EZ_STOP_Msk 0x400UL 563 #define SCB_V2_INTR_S_SET_SPI_BUS_ERROR_Pos 11UL 564 #define SCB_V2_INTR_S_SET_SPI_BUS_ERROR_Msk 0x800UL 565 /* SCB.INTR_S_MASK */ 566 #define SCB_V2_INTR_S_MASK_I2C_ARB_LOST_Pos 0UL 567 #define SCB_V2_INTR_S_MASK_I2C_ARB_LOST_Msk 0x1UL 568 #define SCB_V2_INTR_S_MASK_I2C_NACK_Pos 1UL 569 #define SCB_V2_INTR_S_MASK_I2C_NACK_Msk 0x2UL 570 #define SCB_V2_INTR_S_MASK_I2C_ACK_Pos 2UL 571 #define SCB_V2_INTR_S_MASK_I2C_ACK_Msk 0x4UL 572 #define SCB_V2_INTR_S_MASK_I2C_WRITE_STOP_Pos 3UL 573 #define SCB_V2_INTR_S_MASK_I2C_WRITE_STOP_Msk 0x8UL 574 #define SCB_V2_INTR_S_MASK_I2C_STOP_Pos 4UL 575 #define SCB_V2_INTR_S_MASK_I2C_STOP_Msk 0x10UL 576 #define SCB_V2_INTR_S_MASK_I2C_START_Pos 5UL 577 #define SCB_V2_INTR_S_MASK_I2C_START_Msk 0x20UL 578 #define SCB_V2_INTR_S_MASK_I2C_ADDR_MATCH_Pos 6UL 579 #define SCB_V2_INTR_S_MASK_I2C_ADDR_MATCH_Msk 0x40UL 580 #define SCB_V2_INTR_S_MASK_I2C_GENERAL_Pos 7UL 581 #define SCB_V2_INTR_S_MASK_I2C_GENERAL_Msk 0x80UL 582 #define SCB_V2_INTR_S_MASK_I2C_BUS_ERROR_Pos 8UL 583 #define SCB_V2_INTR_S_MASK_I2C_BUS_ERROR_Msk 0x100UL 584 #define SCB_V2_INTR_S_MASK_SPI_EZ_WRITE_STOP_Pos 9UL 585 #define SCB_V2_INTR_S_MASK_SPI_EZ_WRITE_STOP_Msk 0x200UL 586 #define SCB_V2_INTR_S_MASK_SPI_EZ_STOP_Pos 10UL 587 #define SCB_V2_INTR_S_MASK_SPI_EZ_STOP_Msk 0x400UL 588 #define SCB_V2_INTR_S_MASK_SPI_BUS_ERROR_Pos 11UL 589 #define SCB_V2_INTR_S_MASK_SPI_BUS_ERROR_Msk 0x800UL 590 /* SCB.INTR_S_MASKED */ 591 #define SCB_V2_INTR_S_MASKED_I2C_ARB_LOST_Pos 0UL 592 #define SCB_V2_INTR_S_MASKED_I2C_ARB_LOST_Msk 0x1UL 593 #define SCB_V2_INTR_S_MASKED_I2C_NACK_Pos 1UL 594 #define SCB_V2_INTR_S_MASKED_I2C_NACK_Msk 0x2UL 595 #define SCB_V2_INTR_S_MASKED_I2C_ACK_Pos 2UL 596 #define SCB_V2_INTR_S_MASKED_I2C_ACK_Msk 0x4UL 597 #define SCB_V2_INTR_S_MASKED_I2C_WRITE_STOP_Pos 3UL 598 #define SCB_V2_INTR_S_MASKED_I2C_WRITE_STOP_Msk 0x8UL 599 #define SCB_V2_INTR_S_MASKED_I2C_STOP_Pos 4UL 600 #define SCB_V2_INTR_S_MASKED_I2C_STOP_Msk 0x10UL 601 #define SCB_V2_INTR_S_MASKED_I2C_START_Pos 5UL 602 #define SCB_V2_INTR_S_MASKED_I2C_START_Msk 0x20UL 603 #define SCB_V2_INTR_S_MASKED_I2C_ADDR_MATCH_Pos 6UL 604 #define SCB_V2_INTR_S_MASKED_I2C_ADDR_MATCH_Msk 0x40UL 605 #define SCB_V2_INTR_S_MASKED_I2C_GENERAL_Pos 7UL 606 #define SCB_V2_INTR_S_MASKED_I2C_GENERAL_Msk 0x80UL 607 #define SCB_V2_INTR_S_MASKED_I2C_BUS_ERROR_Pos 8UL 608 #define SCB_V2_INTR_S_MASKED_I2C_BUS_ERROR_Msk 0x100UL 609 #define SCB_V2_INTR_S_MASKED_SPI_EZ_WRITE_STOP_Pos 9UL 610 #define SCB_V2_INTR_S_MASKED_SPI_EZ_WRITE_STOP_Msk 0x200UL 611 #define SCB_V2_INTR_S_MASKED_SPI_EZ_STOP_Pos 10UL 612 #define SCB_V2_INTR_S_MASKED_SPI_EZ_STOP_Msk 0x400UL 613 #define SCB_V2_INTR_S_MASKED_SPI_BUS_ERROR_Pos 11UL 614 #define SCB_V2_INTR_S_MASKED_SPI_BUS_ERROR_Msk 0x800UL 615 /* SCB.INTR_TX */ 616 #define SCB_V2_INTR_TX_TRIGGER_Pos 0UL 617 #define SCB_V2_INTR_TX_TRIGGER_Msk 0x1UL 618 #define SCB_V2_INTR_TX_NOT_FULL_Pos 1UL 619 #define SCB_V2_INTR_TX_NOT_FULL_Msk 0x2UL 620 #define SCB_V2_INTR_TX_EMPTY_Pos 4UL 621 #define SCB_V2_INTR_TX_EMPTY_Msk 0x10UL 622 #define SCB_V2_INTR_TX_OVERFLOW_Pos 5UL 623 #define SCB_V2_INTR_TX_OVERFLOW_Msk 0x20UL 624 #define SCB_V2_INTR_TX_UNDERFLOW_Pos 6UL 625 #define SCB_V2_INTR_TX_UNDERFLOW_Msk 0x40UL 626 #define SCB_V2_INTR_TX_BLOCKED_Pos 7UL 627 #define SCB_V2_INTR_TX_BLOCKED_Msk 0x80UL 628 #define SCB_V2_INTR_TX_UART_NACK_Pos 8UL 629 #define SCB_V2_INTR_TX_UART_NACK_Msk 0x100UL 630 #define SCB_V2_INTR_TX_UART_DONE_Pos 9UL 631 #define SCB_V2_INTR_TX_UART_DONE_Msk 0x200UL 632 #define SCB_V2_INTR_TX_UART_ARB_LOST_Pos 10UL 633 #define SCB_V2_INTR_TX_UART_ARB_LOST_Msk 0x400UL 634 /* SCB.INTR_TX_SET */ 635 #define SCB_V2_INTR_TX_SET_TRIGGER_Pos 0UL 636 #define SCB_V2_INTR_TX_SET_TRIGGER_Msk 0x1UL 637 #define SCB_V2_INTR_TX_SET_NOT_FULL_Pos 1UL 638 #define SCB_V2_INTR_TX_SET_NOT_FULL_Msk 0x2UL 639 #define SCB_V2_INTR_TX_SET_EMPTY_Pos 4UL 640 #define SCB_V2_INTR_TX_SET_EMPTY_Msk 0x10UL 641 #define SCB_V2_INTR_TX_SET_OVERFLOW_Pos 5UL 642 #define SCB_V2_INTR_TX_SET_OVERFLOW_Msk 0x20UL 643 #define SCB_V2_INTR_TX_SET_UNDERFLOW_Pos 6UL 644 #define SCB_V2_INTR_TX_SET_UNDERFLOW_Msk 0x40UL 645 #define SCB_V2_INTR_TX_SET_BLOCKED_Pos 7UL 646 #define SCB_V2_INTR_TX_SET_BLOCKED_Msk 0x80UL 647 #define SCB_V2_INTR_TX_SET_UART_NACK_Pos 8UL 648 #define SCB_V2_INTR_TX_SET_UART_NACK_Msk 0x100UL 649 #define SCB_V2_INTR_TX_SET_UART_DONE_Pos 9UL 650 #define SCB_V2_INTR_TX_SET_UART_DONE_Msk 0x200UL 651 #define SCB_V2_INTR_TX_SET_UART_ARB_LOST_Pos 10UL 652 #define SCB_V2_INTR_TX_SET_UART_ARB_LOST_Msk 0x400UL 653 /* SCB.INTR_TX_MASK */ 654 #define SCB_V2_INTR_TX_MASK_TRIGGER_Pos 0UL 655 #define SCB_V2_INTR_TX_MASK_TRIGGER_Msk 0x1UL 656 #define SCB_V2_INTR_TX_MASK_NOT_FULL_Pos 1UL 657 #define SCB_V2_INTR_TX_MASK_NOT_FULL_Msk 0x2UL 658 #define SCB_V2_INTR_TX_MASK_EMPTY_Pos 4UL 659 #define SCB_V2_INTR_TX_MASK_EMPTY_Msk 0x10UL 660 #define SCB_V2_INTR_TX_MASK_OVERFLOW_Pos 5UL 661 #define SCB_V2_INTR_TX_MASK_OVERFLOW_Msk 0x20UL 662 #define SCB_V2_INTR_TX_MASK_UNDERFLOW_Pos 6UL 663 #define SCB_V2_INTR_TX_MASK_UNDERFLOW_Msk 0x40UL 664 #define SCB_V2_INTR_TX_MASK_BLOCKED_Pos 7UL 665 #define SCB_V2_INTR_TX_MASK_BLOCKED_Msk 0x80UL 666 #define SCB_V2_INTR_TX_MASK_UART_NACK_Pos 8UL 667 #define SCB_V2_INTR_TX_MASK_UART_NACK_Msk 0x100UL 668 #define SCB_V2_INTR_TX_MASK_UART_DONE_Pos 9UL 669 #define SCB_V2_INTR_TX_MASK_UART_DONE_Msk 0x200UL 670 #define SCB_V2_INTR_TX_MASK_UART_ARB_LOST_Pos 10UL 671 #define SCB_V2_INTR_TX_MASK_UART_ARB_LOST_Msk 0x400UL 672 /* SCB.INTR_TX_MASKED */ 673 #define SCB_V2_INTR_TX_MASKED_TRIGGER_Pos 0UL 674 #define SCB_V2_INTR_TX_MASKED_TRIGGER_Msk 0x1UL 675 #define SCB_V2_INTR_TX_MASKED_NOT_FULL_Pos 1UL 676 #define SCB_V2_INTR_TX_MASKED_NOT_FULL_Msk 0x2UL 677 #define SCB_V2_INTR_TX_MASKED_EMPTY_Pos 4UL 678 #define SCB_V2_INTR_TX_MASKED_EMPTY_Msk 0x10UL 679 #define SCB_V2_INTR_TX_MASKED_OVERFLOW_Pos 5UL 680 #define SCB_V2_INTR_TX_MASKED_OVERFLOW_Msk 0x20UL 681 #define SCB_V2_INTR_TX_MASKED_UNDERFLOW_Pos 6UL 682 #define SCB_V2_INTR_TX_MASKED_UNDERFLOW_Msk 0x40UL 683 #define SCB_V2_INTR_TX_MASKED_BLOCKED_Pos 7UL 684 #define SCB_V2_INTR_TX_MASKED_BLOCKED_Msk 0x80UL 685 #define SCB_V2_INTR_TX_MASKED_UART_NACK_Pos 8UL 686 #define SCB_V2_INTR_TX_MASKED_UART_NACK_Msk 0x100UL 687 #define SCB_V2_INTR_TX_MASKED_UART_DONE_Pos 9UL 688 #define SCB_V2_INTR_TX_MASKED_UART_DONE_Msk 0x200UL 689 #define SCB_V2_INTR_TX_MASKED_UART_ARB_LOST_Pos 10UL 690 #define SCB_V2_INTR_TX_MASKED_UART_ARB_LOST_Msk 0x400UL 691 /* SCB.INTR_RX */ 692 #define SCB_V2_INTR_RX_TRIGGER_Pos 0UL 693 #define SCB_V2_INTR_RX_TRIGGER_Msk 0x1UL 694 #define SCB_V2_INTR_RX_NOT_EMPTY_Pos 2UL 695 #define SCB_V2_INTR_RX_NOT_EMPTY_Msk 0x4UL 696 #define SCB_V2_INTR_RX_FULL_Pos 3UL 697 #define SCB_V2_INTR_RX_FULL_Msk 0x8UL 698 #define SCB_V2_INTR_RX_OVERFLOW_Pos 5UL 699 #define SCB_V2_INTR_RX_OVERFLOW_Msk 0x20UL 700 #define SCB_V2_INTR_RX_UNDERFLOW_Pos 6UL 701 #define SCB_V2_INTR_RX_UNDERFLOW_Msk 0x40UL 702 #define SCB_V2_INTR_RX_BLOCKED_Pos 7UL 703 #define SCB_V2_INTR_RX_BLOCKED_Msk 0x80UL 704 #define SCB_V2_INTR_RX_FRAME_ERROR_Pos 8UL 705 #define SCB_V2_INTR_RX_FRAME_ERROR_Msk 0x100UL 706 #define SCB_V2_INTR_RX_PARITY_ERROR_Pos 9UL 707 #define SCB_V2_INTR_RX_PARITY_ERROR_Msk 0x200UL 708 #define SCB_V2_INTR_RX_BAUD_DETECT_Pos 10UL 709 #define SCB_V2_INTR_RX_BAUD_DETECT_Msk 0x400UL 710 #define SCB_V2_INTR_RX_BREAK_DETECT_Pos 11UL 711 #define SCB_V2_INTR_RX_BREAK_DETECT_Msk 0x800UL 712 /* SCB.INTR_RX_SET */ 713 #define SCB_V2_INTR_RX_SET_TRIGGER_Pos 0UL 714 #define SCB_V2_INTR_RX_SET_TRIGGER_Msk 0x1UL 715 #define SCB_V2_INTR_RX_SET_NOT_EMPTY_Pos 2UL 716 #define SCB_V2_INTR_RX_SET_NOT_EMPTY_Msk 0x4UL 717 #define SCB_V2_INTR_RX_SET_FULL_Pos 3UL 718 #define SCB_V2_INTR_RX_SET_FULL_Msk 0x8UL 719 #define SCB_V2_INTR_RX_SET_OVERFLOW_Pos 5UL 720 #define SCB_V2_INTR_RX_SET_OVERFLOW_Msk 0x20UL 721 #define SCB_V2_INTR_RX_SET_UNDERFLOW_Pos 6UL 722 #define SCB_V2_INTR_RX_SET_UNDERFLOW_Msk 0x40UL 723 #define SCB_V2_INTR_RX_SET_BLOCKED_Pos 7UL 724 #define SCB_V2_INTR_RX_SET_BLOCKED_Msk 0x80UL 725 #define SCB_V2_INTR_RX_SET_FRAME_ERROR_Pos 8UL 726 #define SCB_V2_INTR_RX_SET_FRAME_ERROR_Msk 0x100UL 727 #define SCB_V2_INTR_RX_SET_PARITY_ERROR_Pos 9UL 728 #define SCB_V2_INTR_RX_SET_PARITY_ERROR_Msk 0x200UL 729 #define SCB_V2_INTR_RX_SET_BAUD_DETECT_Pos 10UL 730 #define SCB_V2_INTR_RX_SET_BAUD_DETECT_Msk 0x400UL 731 #define SCB_V2_INTR_RX_SET_BREAK_DETECT_Pos 11UL 732 #define SCB_V2_INTR_RX_SET_BREAK_DETECT_Msk 0x800UL 733 /* SCB.INTR_RX_MASK */ 734 #define SCB_V2_INTR_RX_MASK_TRIGGER_Pos 0UL 735 #define SCB_V2_INTR_RX_MASK_TRIGGER_Msk 0x1UL 736 #define SCB_V2_INTR_RX_MASK_NOT_EMPTY_Pos 2UL 737 #define SCB_V2_INTR_RX_MASK_NOT_EMPTY_Msk 0x4UL 738 #define SCB_V2_INTR_RX_MASK_FULL_Pos 3UL 739 #define SCB_V2_INTR_RX_MASK_FULL_Msk 0x8UL 740 #define SCB_V2_INTR_RX_MASK_OVERFLOW_Pos 5UL 741 #define SCB_V2_INTR_RX_MASK_OVERFLOW_Msk 0x20UL 742 #define SCB_V2_INTR_RX_MASK_UNDERFLOW_Pos 6UL 743 #define SCB_V2_INTR_RX_MASK_UNDERFLOW_Msk 0x40UL 744 #define SCB_V2_INTR_RX_MASK_BLOCKED_Pos 7UL 745 #define SCB_V2_INTR_RX_MASK_BLOCKED_Msk 0x80UL 746 #define SCB_V2_INTR_RX_MASK_FRAME_ERROR_Pos 8UL 747 #define SCB_V2_INTR_RX_MASK_FRAME_ERROR_Msk 0x100UL 748 #define SCB_V2_INTR_RX_MASK_PARITY_ERROR_Pos 9UL 749 #define SCB_V2_INTR_RX_MASK_PARITY_ERROR_Msk 0x200UL 750 #define SCB_V2_INTR_RX_MASK_BAUD_DETECT_Pos 10UL 751 #define SCB_V2_INTR_RX_MASK_BAUD_DETECT_Msk 0x400UL 752 #define SCB_V2_INTR_RX_MASK_BREAK_DETECT_Pos 11UL 753 #define SCB_V2_INTR_RX_MASK_BREAK_DETECT_Msk 0x800UL 754 /* SCB.INTR_RX_MASKED */ 755 #define SCB_V2_INTR_RX_MASKED_TRIGGER_Pos 0UL 756 #define SCB_V2_INTR_RX_MASKED_TRIGGER_Msk 0x1UL 757 #define SCB_V2_INTR_RX_MASKED_NOT_EMPTY_Pos 2UL 758 #define SCB_V2_INTR_RX_MASKED_NOT_EMPTY_Msk 0x4UL 759 #define SCB_V2_INTR_RX_MASKED_FULL_Pos 3UL 760 #define SCB_V2_INTR_RX_MASKED_FULL_Msk 0x8UL 761 #define SCB_V2_INTR_RX_MASKED_OVERFLOW_Pos 5UL 762 #define SCB_V2_INTR_RX_MASKED_OVERFLOW_Msk 0x20UL 763 #define SCB_V2_INTR_RX_MASKED_UNDERFLOW_Pos 6UL 764 #define SCB_V2_INTR_RX_MASKED_UNDERFLOW_Msk 0x40UL 765 #define SCB_V2_INTR_RX_MASKED_BLOCKED_Pos 7UL 766 #define SCB_V2_INTR_RX_MASKED_BLOCKED_Msk 0x80UL 767 #define SCB_V2_INTR_RX_MASKED_FRAME_ERROR_Pos 8UL 768 #define SCB_V2_INTR_RX_MASKED_FRAME_ERROR_Msk 0x100UL 769 #define SCB_V2_INTR_RX_MASKED_PARITY_ERROR_Pos 9UL 770 #define SCB_V2_INTR_RX_MASKED_PARITY_ERROR_Msk 0x200UL 771 #define SCB_V2_INTR_RX_MASKED_BAUD_DETECT_Pos 10UL 772 #define SCB_V2_INTR_RX_MASKED_BAUD_DETECT_Msk 0x400UL 773 #define SCB_V2_INTR_RX_MASKED_BREAK_DETECT_Pos 11UL 774 #define SCB_V2_INTR_RX_MASKED_BREAK_DETECT_Msk 0x800UL 775 776 777 #endif /* _CYIP_SCB_V2_H_ */ 778 779 780 /* [] END OF FILE */ 781
