1 /***************************************************************************//** 2 * \file cyip_scb_v4.h 3 * 4 * \brief 5 * SCB IP definitions 6 * 7 ******************************************************************************** 8 * \copyright 9 * (c) (2016-2024), Cypress Semiconductor Corporation (an Infineon company) or 10 * an affiliate of Cypress Semiconductor Corporation. 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 *******************************************************************************/ 26 27 #ifndef _CYIP_SCB_V4_H_ 28 #define _CYIP_SCB_V4_H_ 29 30 #include "cyip_headers.h" 31 32 /******************************************************************************* 33 * SCB 34 *******************************************************************************/ 35 36 #define SCB_SECTION_SIZE 0x00010000UL 37 38 /** 39 * \brief Serial Communications Block (SPI/UART/I2C) (CySCB) 40 */ 41 typedef struct { 42 __IOM uint32_t CTRL; /*!< 0x00000000 Generic control */ 43 __IM uint32_t STATUS; /*!< 0x00000004 Generic status */ 44 __IOM uint32_t CMD_RESP_CTRL; /*!< 0x00000008 Command/response control */ 45 __IM uint32_t CMD_RESP_STATUS; /*!< 0x0000000C Command/response status */ 46 __IM uint32_t RESERVED[4]; 47 __IOM uint32_t SPI_CTRL; /*!< 0x00000020 SPI control */ 48 __IM uint32_t SPI_STATUS; /*!< 0x00000024 SPI status */ 49 __IOM uint32_t SPI_TX_CTRL; /*!< 0x00000028 SPI transmitter control */ 50 __IOM uint32_t SPI_RX_CTRL; /*!< 0x0000002C SPI receiver control */ 51 __IM uint32_t RESERVED1[4]; 52 __IOM uint32_t UART_CTRL; /*!< 0x00000040 UART control */ 53 __IOM uint32_t UART_TX_CTRL; /*!< 0x00000044 UART transmitter control */ 54 __IOM uint32_t UART_RX_CTRL; /*!< 0x00000048 UART receiver control */ 55 __IM uint32_t UART_RX_STATUS; /*!< 0x0000004C UART receiver status */ 56 __IOM uint32_t UART_FLOW_CTRL; /*!< 0x00000050 UART flow control */ 57 __IM uint32_t RESERVED2[3]; 58 __IOM uint32_t I2C_CTRL; /*!< 0x00000060 I2C control */ 59 __IM uint32_t I2C_STATUS; /*!< 0x00000064 I2C status */ 60 __IOM uint32_t I2C_M_CMD; /*!< 0x00000068 I2C master command */ 61 __IOM uint32_t I2C_S_CMD; /*!< 0x0000006C I2C slave command */ 62 __IOM uint32_t I2C_CFG; /*!< 0x00000070 I2C configuration */ 63 __IOM uint32_t I2C_STRETCH_CTRL; /*!< 0x00000074 I2C stretch control */ 64 __IM uint32_t I2C_STRETCH_STATUS; /*!< 0x00000078 I2C stretch status */ 65 __IM uint32_t RESERVED3; 66 __IOM uint32_t I2C_CTRL_HS; /*!< 0x00000080 I2C control for High-Speed mode */ 67 __IM uint32_t RESERVED4[95]; 68 __IOM uint32_t TX_CTRL; /*!< 0x00000200 Transmitter control */ 69 __IOM uint32_t TX_FIFO_CTRL; /*!< 0x00000204 Transmitter FIFO control */ 70 __IM uint32_t TX_FIFO_STATUS; /*!< 0x00000208 Transmitter FIFO status */ 71 __IM uint32_t RESERVED5[13]; 72 __OM uint32_t TX_FIFO_WR; /*!< 0x00000240 Transmitter FIFO write */ 73 __IM uint32_t RESERVED6[47]; 74 __IOM uint32_t RX_CTRL; /*!< 0x00000300 Receiver control */ 75 __IOM uint32_t RX_FIFO_CTRL; /*!< 0x00000304 Receiver FIFO control */ 76 __IM uint32_t RX_FIFO_STATUS; /*!< 0x00000308 Receiver FIFO status */ 77 __IM uint32_t RESERVED7; 78 __IOM uint32_t RX_MATCH; /*!< 0x00000310 Slave address and mask */ 79 __IM uint32_t RESERVED8[11]; 80 __IM uint32_t RX_FIFO_RD; /*!< 0x00000340 Receiver FIFO read */ 81 __IM uint32_t RX_FIFO_RD_SILENT; /*!< 0x00000344 Receiver FIFO read silent */ 82 __IM uint32_t RESERVED9[46]; 83 __IOM uint32_t EZ_DATA[512]; /*!< 0x00000400 Memory buffer */ 84 __IM uint32_t RESERVED10[128]; 85 __IM uint32_t INTR_CAUSE; /*!< 0x00000E00 Active clocked interrupt signal */ 86 __IM uint32_t RESERVED11[31]; 87 __IOM uint32_t INTR_I2C_EC; /*!< 0x00000E80 Externally clocked I2C interrupt request */ 88 __IM uint32_t RESERVED12; 89 __IOM uint32_t INTR_I2C_EC_MASK; /*!< 0x00000E88 Externally clocked I2C interrupt mask */ 90 __IM uint32_t INTR_I2C_EC_MASKED; /*!< 0x00000E8C Externally clocked I2C interrupt masked */ 91 __IM uint32_t RESERVED13[12]; 92 __IOM uint32_t INTR_SPI_EC; /*!< 0x00000EC0 Externally clocked SPI interrupt request */ 93 __IM uint32_t RESERVED14; 94 __IOM uint32_t INTR_SPI_EC_MASK; /*!< 0x00000EC8 Externally clocked SPI interrupt mask */ 95 __IM uint32_t INTR_SPI_EC_MASKED; /*!< 0x00000ECC Externally clocked SPI interrupt masked */ 96 __IM uint32_t RESERVED15[12]; 97 __IOM uint32_t INTR_M; /*!< 0x00000F00 Master interrupt request */ 98 __IOM uint32_t INTR_M_SET; /*!< 0x00000F04 Master interrupt set request */ 99 __IOM uint32_t INTR_M_MASK; /*!< 0x00000F08 Master interrupt mask */ 100 __IM uint32_t INTR_M_MASKED; /*!< 0x00000F0C Master interrupt masked request */ 101 __IM uint32_t RESERVED16[12]; 102 __IOM uint32_t INTR_S; /*!< 0x00000F40 Slave interrupt request */ 103 __IOM uint32_t INTR_S_SET; /*!< 0x00000F44 Slave interrupt set request */ 104 __IOM uint32_t INTR_S_MASK; /*!< 0x00000F48 Slave interrupt mask */ 105 __IM uint32_t INTR_S_MASKED; /*!< 0x00000F4C Slave interrupt masked request */ 106 __IM uint32_t RESERVED17[12]; 107 __IOM uint32_t INTR_TX; /*!< 0x00000F80 Transmitter interrupt request */ 108 __IOM uint32_t INTR_TX_SET; /*!< 0x00000F84 Transmitter interrupt set request */ 109 __IOM uint32_t INTR_TX_MASK; /*!< 0x00000F88 Transmitter interrupt mask */ 110 __IM uint32_t INTR_TX_MASKED; /*!< 0x00000F8C Transmitter interrupt masked request */ 111 __IM uint32_t RESERVED18[12]; 112 __IOM uint32_t INTR_RX; /*!< 0x00000FC0 Receiver interrupt request */ 113 __IOM uint32_t INTR_RX_SET; /*!< 0x00000FC4 Receiver interrupt set request */ 114 __IOM uint32_t INTR_RX_MASK; /*!< 0x00000FC8 Receiver interrupt mask */ 115 __IM uint32_t INTR_RX_MASKED; /*!< 0x00000FCC Receiver interrupt masked request */ 116 } CySCB_Type; /*!< Size = 4048 (0xFD0) */ 117 118 119 /* SCB.CTRL */ 120 #define SCB_CTRL_OVS_Pos 0UL 121 #define SCB_CTRL_OVS_Msk 0xFUL 122 #define SCB_CTRL_EC_AM_MODE_Pos 8UL 123 #define SCB_CTRL_EC_AM_MODE_Msk 0x100UL 124 #define SCB_CTRL_EC_OP_MODE_Pos 9UL 125 #define SCB_CTRL_EC_OP_MODE_Msk 0x200UL 126 #define SCB_CTRL_EZ_MODE_Pos 10UL 127 #define SCB_CTRL_EZ_MODE_Msk 0x400UL 128 #define SCB_CTRL_CMD_RESP_MODE_Pos 12UL 129 #define SCB_CTRL_CMD_RESP_MODE_Msk 0x1000UL 130 #define SCB_CTRL_MEM_WIDTH_Pos 14UL 131 #define SCB_CTRL_MEM_WIDTH_Msk 0xC000UL 132 #define SCB_CTRL_ADDR_ACCEPT_Pos 16UL 133 #define SCB_CTRL_ADDR_ACCEPT_Msk 0x10000UL 134 #define SCB_CTRL_BLOCK_Pos 17UL 135 #define SCB_CTRL_BLOCK_Msk 0x20000UL 136 #define SCB_CTRL_MODE_Pos 24UL 137 #define SCB_CTRL_MODE_Msk 0x3000000UL 138 #define SCB_CTRL_EC_ACCESS_Pos 28UL 139 #define SCB_CTRL_EC_ACCESS_Msk 0x10000000UL 140 #define SCB_CTRL_ENABLED_Pos 31UL 141 #define SCB_CTRL_ENABLED_Msk 0x80000000UL 142 /* SCB.STATUS */ 143 #define SCB_STATUS_EC_BUSY_Pos 0UL 144 #define SCB_STATUS_EC_BUSY_Msk 0x1UL 145 /* SCB.CMD_RESP_CTRL */ 146 #define SCB_CMD_RESP_CTRL_BASE_RD_ADDR_Pos 0UL 147 #define SCB_CMD_RESP_CTRL_BASE_RD_ADDR_Msk 0x1FFUL 148 #define SCB_CMD_RESP_CTRL_BASE_WR_ADDR_Pos 16UL 149 #define SCB_CMD_RESP_CTRL_BASE_WR_ADDR_Msk 0x1FF0000UL 150 /* SCB.CMD_RESP_STATUS */ 151 #define SCB_CMD_RESP_STATUS_CURR_RD_ADDR_Pos 0UL 152 #define SCB_CMD_RESP_STATUS_CURR_RD_ADDR_Msk 0x1FFUL 153 #define SCB_CMD_RESP_STATUS_CURR_WR_ADDR_Pos 16UL 154 #define SCB_CMD_RESP_STATUS_CURR_WR_ADDR_Msk 0x1FF0000UL 155 #define SCB_CMD_RESP_STATUS_CMD_RESP_EC_BUS_BUSY_Pos 30UL 156 #define SCB_CMD_RESP_STATUS_CMD_RESP_EC_BUS_BUSY_Msk 0x40000000UL 157 #define SCB_CMD_RESP_STATUS_CMD_RESP_EC_BUSY_Pos 31UL 158 #define SCB_CMD_RESP_STATUS_CMD_RESP_EC_BUSY_Msk 0x80000000UL 159 /* SCB.SPI_CTRL */ 160 #define SCB_SPI_CTRL_SSEL_CONTINUOUS_Pos 0UL 161 #define SCB_SPI_CTRL_SSEL_CONTINUOUS_Msk 0x1UL 162 #define SCB_SPI_CTRL_SELECT_PRECEDE_Pos 1UL 163 #define SCB_SPI_CTRL_SELECT_PRECEDE_Msk 0x2UL 164 #define SCB_SPI_CTRL_CPHA_Pos 2UL 165 #define SCB_SPI_CTRL_CPHA_Msk 0x4UL 166 #define SCB_SPI_CTRL_CPOL_Pos 3UL 167 #define SCB_SPI_CTRL_CPOL_Msk 0x8UL 168 #define SCB_SPI_CTRL_LATE_SAMPLE_Pos 4UL 169 #define SCB_SPI_CTRL_LATE_SAMPLE_Msk 0x10UL 170 #define SCB_SPI_CTRL_SCLK_CONTINUOUS_Pos 5UL 171 #define SCB_SPI_CTRL_SCLK_CONTINUOUS_Msk 0x20UL 172 #define SCB_SPI_CTRL_SSEL_POLARITY0_Pos 8UL 173 #define SCB_SPI_CTRL_SSEL_POLARITY0_Msk 0x100UL 174 #define SCB_SPI_CTRL_SSEL_POLARITY1_Pos 9UL 175 #define SCB_SPI_CTRL_SSEL_POLARITY1_Msk 0x200UL 176 #define SCB_SPI_CTRL_SSEL_POLARITY2_Pos 10UL 177 #define SCB_SPI_CTRL_SSEL_POLARITY2_Msk 0x400UL 178 #define SCB_SPI_CTRL_SSEL_POLARITY3_Pos 11UL 179 #define SCB_SPI_CTRL_SSEL_POLARITY3_Msk 0x800UL 180 #define SCB_SPI_CTRL_SSEL_SETUP_DEL_Pos 12UL 181 #define SCB_SPI_CTRL_SSEL_SETUP_DEL_Msk 0x1000UL 182 #define SCB_SPI_CTRL_SSEL_HOLD_DEL_Pos 13UL 183 #define SCB_SPI_CTRL_SSEL_HOLD_DEL_Msk 0x2000UL 184 #define SCB_SPI_CTRL_SSEL_INTER_FRAME_DEL_Pos 14UL 185 #define SCB_SPI_CTRL_SSEL_INTER_FRAME_DEL_Msk 0x4000UL 186 #define SCB_SPI_CTRL_LOOPBACK_Pos 16UL 187 #define SCB_SPI_CTRL_LOOPBACK_Msk 0x10000UL 188 #define SCB_SPI_CTRL_MODE_Pos 24UL 189 #define SCB_SPI_CTRL_MODE_Msk 0x3000000UL 190 #define SCB_SPI_CTRL_SSEL_Pos 26UL 191 #define SCB_SPI_CTRL_SSEL_Msk 0xC000000UL 192 #define SCB_SPI_CTRL_MASTER_MODE_Pos 31UL 193 #define SCB_SPI_CTRL_MASTER_MODE_Msk 0x80000000UL 194 /* SCB.SPI_STATUS */ 195 #define SCB_SPI_STATUS_BUS_BUSY_Pos 0UL 196 #define SCB_SPI_STATUS_BUS_BUSY_Msk 0x1UL 197 #define SCB_SPI_STATUS_SPI_EC_BUSY_Pos 1UL 198 #define SCB_SPI_STATUS_SPI_EC_BUSY_Msk 0x2UL 199 #define SCB_SPI_STATUS_CURR_EZ_ADDR_Pos 8UL 200 #define SCB_SPI_STATUS_CURR_EZ_ADDR_Msk 0xFF00UL 201 #define SCB_SPI_STATUS_BASE_EZ_ADDR_Pos 16UL 202 #define SCB_SPI_STATUS_BASE_EZ_ADDR_Msk 0xFF0000UL 203 /* SCB.SPI_TX_CTRL */ 204 #define SCB_SPI_TX_CTRL_PARITY_Pos 4UL 205 #define SCB_SPI_TX_CTRL_PARITY_Msk 0x10UL 206 #define SCB_SPI_TX_CTRL_PARITY_ENABLED_Pos 5UL 207 #define SCB_SPI_TX_CTRL_PARITY_ENABLED_Msk 0x20UL 208 #define SCB_SPI_TX_CTRL_MOSI_IDLE_HIGH_Pos 16UL 209 #define SCB_SPI_TX_CTRL_MOSI_IDLE_HIGH_Msk 0x10000UL 210 /* SCB.SPI_RX_CTRL */ 211 #define SCB_SPI_RX_CTRL_PARITY_Pos 4UL 212 #define SCB_SPI_RX_CTRL_PARITY_Msk 0x10UL 213 #define SCB_SPI_RX_CTRL_PARITY_ENABLED_Pos 5UL 214 #define SCB_SPI_RX_CTRL_PARITY_ENABLED_Msk 0x20UL 215 #define SCB_SPI_RX_CTRL_DROP_ON_PARITY_ERROR_Pos 8UL 216 #define SCB_SPI_RX_CTRL_DROP_ON_PARITY_ERROR_Msk 0x100UL 217 /* SCB.UART_CTRL */ 218 #define SCB_UART_CTRL_LOOPBACK_Pos 16UL 219 #define SCB_UART_CTRL_LOOPBACK_Msk 0x10000UL 220 #define SCB_UART_CTRL_MODE_Pos 24UL 221 #define SCB_UART_CTRL_MODE_Msk 0x3000000UL 222 /* SCB.UART_TX_CTRL */ 223 #define SCB_UART_TX_CTRL_STOP_BITS_Pos 0UL 224 #define SCB_UART_TX_CTRL_STOP_BITS_Msk 0x7UL 225 #define SCB_UART_TX_CTRL_PARITY_Pos 4UL 226 #define SCB_UART_TX_CTRL_PARITY_Msk 0x10UL 227 #define SCB_UART_TX_CTRL_PARITY_ENABLED_Pos 5UL 228 #define SCB_UART_TX_CTRL_PARITY_ENABLED_Msk 0x20UL 229 #define SCB_UART_TX_CTRL_RETRY_ON_NACK_Pos 8UL 230 #define SCB_UART_TX_CTRL_RETRY_ON_NACK_Msk 0x100UL 231 /* SCB.UART_RX_CTRL */ 232 #define SCB_UART_RX_CTRL_STOP_BITS_Pos 0UL 233 #define SCB_UART_RX_CTRL_STOP_BITS_Msk 0x7UL 234 #define SCB_UART_RX_CTRL_PARITY_Pos 4UL 235 #define SCB_UART_RX_CTRL_PARITY_Msk 0x10UL 236 #define SCB_UART_RX_CTRL_PARITY_ENABLED_Pos 5UL 237 #define SCB_UART_RX_CTRL_PARITY_ENABLED_Msk 0x20UL 238 #define SCB_UART_RX_CTRL_POLARITY_Pos 6UL 239 #define SCB_UART_RX_CTRL_POLARITY_Msk 0x40UL 240 #define SCB_UART_RX_CTRL_DROP_ON_PARITY_ERROR_Pos 8UL 241 #define SCB_UART_RX_CTRL_DROP_ON_PARITY_ERROR_Msk 0x100UL 242 #define SCB_UART_RX_CTRL_DROP_ON_FRAME_ERROR_Pos 9UL 243 #define SCB_UART_RX_CTRL_DROP_ON_FRAME_ERROR_Msk 0x200UL 244 #define SCB_UART_RX_CTRL_MP_MODE_Pos 10UL 245 #define SCB_UART_RX_CTRL_MP_MODE_Msk 0x400UL 246 #define SCB_UART_RX_CTRL_LIN_MODE_Pos 12UL 247 #define SCB_UART_RX_CTRL_LIN_MODE_Msk 0x1000UL 248 #define SCB_UART_RX_CTRL_SKIP_START_Pos 13UL 249 #define SCB_UART_RX_CTRL_SKIP_START_Msk 0x2000UL 250 #define SCB_UART_RX_CTRL_HDRXEN_Pos 14UL 251 #define SCB_UART_RX_CTRL_HDRXEN_Msk 0x4000UL 252 #define SCB_UART_RX_CTRL_BREAK_WIDTH_Pos 16UL 253 #define SCB_UART_RX_CTRL_BREAK_WIDTH_Msk 0xF0000UL 254 #define SCB_UART_RX_CTRL_BREAK_LEVEL_Pos 24UL 255 #define SCB_UART_RX_CTRL_BREAK_LEVEL_Msk 0x1000000UL 256 /* SCB.UART_RX_STATUS */ 257 #define SCB_UART_RX_STATUS_BR_COUNTER_Pos 0UL 258 #define SCB_UART_RX_STATUS_BR_COUNTER_Msk 0xFFFUL 259 /* SCB.UART_FLOW_CTRL */ 260 #define SCB_UART_FLOW_CTRL_TRIGGER_LEVEL_Pos 0UL 261 #define SCB_UART_FLOW_CTRL_TRIGGER_LEVEL_Msk 0xFFUL 262 #define SCB_UART_FLOW_CTRL_RTS_POLARITY_Pos 16UL 263 #define SCB_UART_FLOW_CTRL_RTS_POLARITY_Msk 0x10000UL 264 #define SCB_UART_FLOW_CTRL_CTS_POLARITY_Pos 24UL 265 #define SCB_UART_FLOW_CTRL_CTS_POLARITY_Msk 0x1000000UL 266 #define SCB_UART_FLOW_CTRL_CTS_ENABLED_Pos 25UL 267 #define SCB_UART_FLOW_CTRL_CTS_ENABLED_Msk 0x2000000UL 268 /* SCB.I2C_CTRL */ 269 #define SCB_I2C_CTRL_HIGH_PHASE_OVS_Pos 0UL 270 #define SCB_I2C_CTRL_HIGH_PHASE_OVS_Msk 0xFUL 271 #define SCB_I2C_CTRL_LOW_PHASE_OVS_Pos 4UL 272 #define SCB_I2C_CTRL_LOW_PHASE_OVS_Msk 0xF0UL 273 #define SCB_I2C_CTRL_M_READY_DATA_ACK_Pos 8UL 274 #define SCB_I2C_CTRL_M_READY_DATA_ACK_Msk 0x100UL 275 #define SCB_I2C_CTRL_M_NOT_READY_DATA_NACK_Pos 9UL 276 #define SCB_I2C_CTRL_M_NOT_READY_DATA_NACK_Msk 0x200UL 277 #define SCB_I2C_CTRL_S_GENERAL_IGNORE_Pos 11UL 278 #define SCB_I2C_CTRL_S_GENERAL_IGNORE_Msk 0x800UL 279 #define SCB_I2C_CTRL_S_READY_ADDR_ACK_Pos 12UL 280 #define SCB_I2C_CTRL_S_READY_ADDR_ACK_Msk 0x1000UL 281 #define SCB_I2C_CTRL_S_READY_DATA_ACK_Pos 13UL 282 #define SCB_I2C_CTRL_S_READY_DATA_ACK_Msk 0x2000UL 283 #define SCB_I2C_CTRL_S_NOT_READY_ADDR_NACK_Pos 14UL 284 #define SCB_I2C_CTRL_S_NOT_READY_ADDR_NACK_Msk 0x4000UL 285 #define SCB_I2C_CTRL_S_NOT_READY_DATA_NACK_Pos 15UL 286 #define SCB_I2C_CTRL_S_NOT_READY_DATA_NACK_Msk 0x8000UL 287 #define SCB_I2C_CTRL_LOOPBACK_Pos 16UL 288 #define SCB_I2C_CTRL_LOOPBACK_Msk 0x10000UL 289 #define SCB_I2C_CTRL_SLAVE_MODE_Pos 30UL 290 #define SCB_I2C_CTRL_SLAVE_MODE_Msk 0x40000000UL 291 #define SCB_I2C_CTRL_MASTER_MODE_Pos 31UL 292 #define SCB_I2C_CTRL_MASTER_MODE_Msk 0x80000000UL 293 /* SCB.I2C_STATUS */ 294 #define SCB_I2C_STATUS_BUS_BUSY_Pos 0UL 295 #define SCB_I2C_STATUS_BUS_BUSY_Msk 0x1UL 296 #define SCB_I2C_STATUS_I2C_EC_BUSY_Pos 1UL 297 #define SCB_I2C_STATUS_I2C_EC_BUSY_Msk 0x2UL 298 #define SCB_I2C_STATUS_I2CS_IC_BUSY_Pos 2UL 299 #define SCB_I2C_STATUS_I2CS_IC_BUSY_Msk 0x4UL 300 #define SCB_I2C_STATUS_S_READ_Pos 4UL 301 #define SCB_I2C_STATUS_S_READ_Msk 0x10UL 302 #define SCB_I2C_STATUS_M_READ_Pos 5UL 303 #define SCB_I2C_STATUS_M_READ_Msk 0x20UL 304 #define SCB_I2C_STATUS_CURR_EZ_ADDR_Pos 8UL 305 #define SCB_I2C_STATUS_CURR_EZ_ADDR_Msk 0xFF00UL 306 #define SCB_I2C_STATUS_BASE_EZ_ADDR_Pos 16UL 307 #define SCB_I2C_STATUS_BASE_EZ_ADDR_Msk 0xFF0000UL 308 #define SCB_I2C_STATUS_HS_MODE_Pos 24UL 309 #define SCB_I2C_STATUS_HS_MODE_Msk 0x1000000UL 310 /* SCB.I2C_M_CMD */ 311 #define SCB_I2C_M_CMD_M_START_Pos 0UL 312 #define SCB_I2C_M_CMD_M_START_Msk 0x1UL 313 #define SCB_I2C_M_CMD_M_START_ON_IDLE_Pos 1UL 314 #define SCB_I2C_M_CMD_M_START_ON_IDLE_Msk 0x2UL 315 #define SCB_I2C_M_CMD_M_ACK_Pos 2UL 316 #define SCB_I2C_M_CMD_M_ACK_Msk 0x4UL 317 #define SCB_I2C_M_CMD_M_NACK_Pos 3UL 318 #define SCB_I2C_M_CMD_M_NACK_Msk 0x8UL 319 #define SCB_I2C_M_CMD_M_STOP_Pos 4UL 320 #define SCB_I2C_M_CMD_M_STOP_Msk 0x10UL 321 /* SCB.I2C_S_CMD */ 322 #define SCB_I2C_S_CMD_S_ACK_Pos 0UL 323 #define SCB_I2C_S_CMD_S_ACK_Msk 0x1UL 324 #define SCB_I2C_S_CMD_S_NACK_Pos 1UL 325 #define SCB_I2C_S_CMD_S_NACK_Msk 0x2UL 326 #define SCB_I2C_S_CMD_S_TX_ONES_ON_EMPTY_Pos 2UL 327 #define SCB_I2C_S_CMD_S_TX_ONES_ON_EMPTY_Msk 0x4UL 328 #define SCB_I2C_S_CMD_S_STRETCH_HS_Pos 8UL 329 #define SCB_I2C_S_CMD_S_STRETCH_HS_Msk 0x100UL 330 /* SCB.I2C_CFG */ 331 #define SCB_I2C_CFG_SDA_IN_FILT_TRIM_Pos 0UL 332 #define SCB_I2C_CFG_SDA_IN_FILT_TRIM_Msk 0x3UL 333 #define SCB_I2C_CFG_SDA_IN_FILT_SEL_Pos 4UL 334 #define SCB_I2C_CFG_SDA_IN_FILT_SEL_Msk 0x10UL 335 #define SCB_I2C_CFG_SCL_IN_FILT_TRIM_Pos 8UL 336 #define SCB_I2C_CFG_SCL_IN_FILT_TRIM_Msk 0x300UL 337 #define SCB_I2C_CFG_SCL_IN_FILT_SEL_Pos 12UL 338 #define SCB_I2C_CFG_SCL_IN_FILT_SEL_Msk 0x1000UL 339 #define SCB_I2C_CFG_SDA_OUT_FILT0_TRIM_Pos 16UL 340 #define SCB_I2C_CFG_SDA_OUT_FILT0_TRIM_Msk 0x30000UL 341 #define SCB_I2C_CFG_SDA_OUT_FILT1_TRIM_Pos 18UL 342 #define SCB_I2C_CFG_SDA_OUT_FILT1_TRIM_Msk 0xC0000UL 343 #define SCB_I2C_CFG_SDA_OUT_FILT2_TRIM_Pos 20UL 344 #define SCB_I2C_CFG_SDA_OUT_FILT2_TRIM_Msk 0x300000UL 345 #define SCB_I2C_CFG_SDA_OUT_FILT_SEL_Pos 28UL 346 #define SCB_I2C_CFG_SDA_OUT_FILT_SEL_Msk 0x30000000UL 347 /* SCB.I2C_STRETCH_CTRL */ 348 #define SCB_I2C_STRETCH_CTRL_STRETCH_THRESHOLD_Pos 0UL 349 #define SCB_I2C_STRETCH_CTRL_STRETCH_THRESHOLD_Msk 0xFUL 350 /* SCB.I2C_STRETCH_STATUS */ 351 #define SCB_I2C_STRETCH_STATUS_STRETCH_COUNT_Pos 0UL 352 #define SCB_I2C_STRETCH_STATUS_STRETCH_COUNT_Msk 0xFUL 353 #define SCB_I2C_STRETCH_STATUS_STRETCH_DETECTED_Pos 4UL 354 #define SCB_I2C_STRETCH_STATUS_STRETCH_DETECTED_Msk 0x10UL 355 #define SCB_I2C_STRETCH_STATUS_SYNC_DETECTED_Pos 5UL 356 #define SCB_I2C_STRETCH_STATUS_SYNC_DETECTED_Msk 0x20UL 357 #define SCB_I2C_STRETCH_STATUS_STRETCHING_Pos 8UL 358 #define SCB_I2C_STRETCH_STATUS_STRETCHING_Msk 0x100UL 359 /* SCB.I2C_CTRL_HS */ 360 #define SCB_I2C_CTRL_HS_HOVS_HS_Pos 0UL 361 #define SCB_I2C_CTRL_HS_HOVS_HS_Msk 0xFUL 362 #define SCB_I2C_CTRL_HS_LOVS_HS_Pos 4UL 363 #define SCB_I2C_CTRL_HS_LOVS_HS_Msk 0xF0UL 364 #define SCB_I2C_CTRL_HS_HS_ENABLED_Pos 31UL 365 #define SCB_I2C_CTRL_HS_HS_ENABLED_Msk 0x80000000UL 366 /* SCB.TX_CTRL */ 367 #define SCB_TX_CTRL_DATA_WIDTH_Pos 0UL 368 #define SCB_TX_CTRL_DATA_WIDTH_Msk 0x1FUL 369 #define SCB_TX_CTRL_MSB_FIRST_Pos 8UL 370 #define SCB_TX_CTRL_MSB_FIRST_Msk 0x100UL 371 #define SCB_TX_CTRL_OPEN_DRAIN_Pos 16UL 372 #define SCB_TX_CTRL_OPEN_DRAIN_Msk 0x10000UL 373 #define SCB_TX_CTRL_OPEN_DRAIN_SCL_Pos 17UL 374 #define SCB_TX_CTRL_OPEN_DRAIN_SCL_Msk 0x20000UL 375 /* SCB.TX_FIFO_CTRL */ 376 #define SCB_TX_FIFO_CTRL_TRIGGER_LEVEL_Pos 0UL 377 #define SCB_TX_FIFO_CTRL_TRIGGER_LEVEL_Msk 0xFFUL 378 #define SCB_TX_FIFO_CTRL_CLEAR_Pos 16UL 379 #define SCB_TX_FIFO_CTRL_CLEAR_Msk 0x10000UL 380 #define SCB_TX_FIFO_CTRL_FREEZE_Pos 17UL 381 #define SCB_TX_FIFO_CTRL_FREEZE_Msk 0x20000UL 382 /* SCB.TX_FIFO_STATUS */ 383 #define SCB_TX_FIFO_STATUS_USED_Pos 0UL 384 #define SCB_TX_FIFO_STATUS_USED_Msk 0x1FFUL 385 #define SCB_TX_FIFO_STATUS_SR_VALID_Pos 15UL 386 #define SCB_TX_FIFO_STATUS_SR_VALID_Msk 0x8000UL 387 #define SCB_TX_FIFO_STATUS_RD_PTR_Pos 16UL 388 #define SCB_TX_FIFO_STATUS_RD_PTR_Msk 0xFF0000UL 389 #define SCB_TX_FIFO_STATUS_WR_PTR_Pos 24UL 390 #define SCB_TX_FIFO_STATUS_WR_PTR_Msk 0xFF000000UL 391 /* SCB.TX_FIFO_WR */ 392 #define SCB_TX_FIFO_WR_DATA_Pos 0UL 393 #define SCB_TX_FIFO_WR_DATA_Msk 0xFFFFFFFFUL 394 /* SCB.RX_CTRL */ 395 #define SCB_RX_CTRL_DATA_WIDTH_Pos 0UL 396 #define SCB_RX_CTRL_DATA_WIDTH_Msk 0x1FUL 397 #define SCB_RX_CTRL_MSB_FIRST_Pos 8UL 398 #define SCB_RX_CTRL_MSB_FIRST_Msk 0x100UL 399 #define SCB_RX_CTRL_MEDIAN_Pos 9UL 400 #define SCB_RX_CTRL_MEDIAN_Msk 0x200UL 401 /* SCB.RX_FIFO_CTRL */ 402 #define SCB_RX_FIFO_CTRL_TRIGGER_LEVEL_Pos 0UL 403 #define SCB_RX_FIFO_CTRL_TRIGGER_LEVEL_Msk 0xFFUL 404 #define SCB_RX_FIFO_CTRL_CLEAR_Pos 16UL 405 #define SCB_RX_FIFO_CTRL_CLEAR_Msk 0x10000UL 406 #define SCB_RX_FIFO_CTRL_FREEZE_Pos 17UL 407 #define SCB_RX_FIFO_CTRL_FREEZE_Msk 0x20000UL 408 /* SCB.RX_FIFO_STATUS */ 409 #define SCB_RX_FIFO_STATUS_USED_Pos 0UL 410 #define SCB_RX_FIFO_STATUS_USED_Msk 0x1FFUL 411 #define SCB_RX_FIFO_STATUS_SR_VALID_Pos 15UL 412 #define SCB_RX_FIFO_STATUS_SR_VALID_Msk 0x8000UL 413 #define SCB_RX_FIFO_STATUS_RD_PTR_Pos 16UL 414 #define SCB_RX_FIFO_STATUS_RD_PTR_Msk 0xFF0000UL 415 #define SCB_RX_FIFO_STATUS_WR_PTR_Pos 24UL 416 #define SCB_RX_FIFO_STATUS_WR_PTR_Msk 0xFF000000UL 417 /* SCB.RX_MATCH */ 418 #define SCB_RX_MATCH_ADDR_Pos 0UL 419 #define SCB_RX_MATCH_ADDR_Msk 0xFFUL 420 #define SCB_RX_MATCH_MASK_Pos 16UL 421 #define SCB_RX_MATCH_MASK_Msk 0xFF0000UL 422 /* SCB.RX_FIFO_RD */ 423 #define SCB_RX_FIFO_RD_DATA_Pos 0UL 424 #define SCB_RX_FIFO_RD_DATA_Msk 0xFFFFFFFFUL 425 /* SCB.RX_FIFO_RD_SILENT */ 426 #define SCB_RX_FIFO_RD_SILENT_DATA_Pos 0UL 427 #define SCB_RX_FIFO_RD_SILENT_DATA_Msk 0xFFFFFFFFUL 428 /* SCB.EZ_DATA */ 429 #define SCB_EZ_DATA_EZ_DATA_Pos 0UL 430 #define SCB_EZ_DATA_EZ_DATA_Msk 0xFFUL 431 /* SCB.INTR_CAUSE */ 432 #define SCB_INTR_CAUSE_M_Pos 0UL 433 #define SCB_INTR_CAUSE_M_Msk 0x1UL 434 #define SCB_INTR_CAUSE_S_Pos 1UL 435 #define SCB_INTR_CAUSE_S_Msk 0x2UL 436 #define SCB_INTR_CAUSE_TX_Pos 2UL 437 #define SCB_INTR_CAUSE_TX_Msk 0x4UL 438 #define SCB_INTR_CAUSE_RX_Pos 3UL 439 #define SCB_INTR_CAUSE_RX_Msk 0x8UL 440 #define SCB_INTR_CAUSE_I2C_EC_Pos 4UL 441 #define SCB_INTR_CAUSE_I2C_EC_Msk 0x10UL 442 #define SCB_INTR_CAUSE_SPI_EC_Pos 5UL 443 #define SCB_INTR_CAUSE_SPI_EC_Msk 0x20UL 444 /* SCB.INTR_I2C_EC */ 445 #define SCB_INTR_I2C_EC_WAKE_UP_Pos 0UL 446 #define SCB_INTR_I2C_EC_WAKE_UP_Msk 0x1UL 447 #define SCB_INTR_I2C_EC_EZ_STOP_Pos 1UL 448 #define SCB_INTR_I2C_EC_EZ_STOP_Msk 0x2UL 449 #define SCB_INTR_I2C_EC_EZ_WRITE_STOP_Pos 2UL 450 #define SCB_INTR_I2C_EC_EZ_WRITE_STOP_Msk 0x4UL 451 #define SCB_INTR_I2C_EC_EZ_READ_STOP_Pos 3UL 452 #define SCB_INTR_I2C_EC_EZ_READ_STOP_Msk 0x8UL 453 /* SCB.INTR_I2C_EC_MASK */ 454 #define SCB_INTR_I2C_EC_MASK_WAKE_UP_Pos 0UL 455 #define SCB_INTR_I2C_EC_MASK_WAKE_UP_Msk 0x1UL 456 #define SCB_INTR_I2C_EC_MASK_EZ_STOP_Pos 1UL 457 #define SCB_INTR_I2C_EC_MASK_EZ_STOP_Msk 0x2UL 458 #define SCB_INTR_I2C_EC_MASK_EZ_WRITE_STOP_Pos 2UL 459 #define SCB_INTR_I2C_EC_MASK_EZ_WRITE_STOP_Msk 0x4UL 460 #define SCB_INTR_I2C_EC_MASK_EZ_READ_STOP_Pos 3UL 461 #define SCB_INTR_I2C_EC_MASK_EZ_READ_STOP_Msk 0x8UL 462 /* SCB.INTR_I2C_EC_MASKED */ 463 #define SCB_INTR_I2C_EC_MASKED_WAKE_UP_Pos 0UL 464 #define SCB_INTR_I2C_EC_MASKED_WAKE_UP_Msk 0x1UL 465 #define SCB_INTR_I2C_EC_MASKED_EZ_STOP_Pos 1UL 466 #define SCB_INTR_I2C_EC_MASKED_EZ_STOP_Msk 0x2UL 467 #define SCB_INTR_I2C_EC_MASKED_EZ_WRITE_STOP_Pos 2UL 468 #define SCB_INTR_I2C_EC_MASKED_EZ_WRITE_STOP_Msk 0x4UL 469 #define SCB_INTR_I2C_EC_MASKED_EZ_READ_STOP_Pos 3UL 470 #define SCB_INTR_I2C_EC_MASKED_EZ_READ_STOP_Msk 0x8UL 471 /* SCB.INTR_SPI_EC */ 472 #define SCB_INTR_SPI_EC_WAKE_UP_Pos 0UL 473 #define SCB_INTR_SPI_EC_WAKE_UP_Msk 0x1UL 474 #define SCB_INTR_SPI_EC_EZ_STOP_Pos 1UL 475 #define SCB_INTR_SPI_EC_EZ_STOP_Msk 0x2UL 476 #define SCB_INTR_SPI_EC_EZ_WRITE_STOP_Pos 2UL 477 #define SCB_INTR_SPI_EC_EZ_WRITE_STOP_Msk 0x4UL 478 #define SCB_INTR_SPI_EC_EZ_READ_STOP_Pos 3UL 479 #define SCB_INTR_SPI_EC_EZ_READ_STOP_Msk 0x8UL 480 /* SCB.INTR_SPI_EC_MASK */ 481 #define SCB_INTR_SPI_EC_MASK_WAKE_UP_Pos 0UL 482 #define SCB_INTR_SPI_EC_MASK_WAKE_UP_Msk 0x1UL 483 #define SCB_INTR_SPI_EC_MASK_EZ_STOP_Pos 1UL 484 #define SCB_INTR_SPI_EC_MASK_EZ_STOP_Msk 0x2UL 485 #define SCB_INTR_SPI_EC_MASK_EZ_WRITE_STOP_Pos 2UL 486 #define SCB_INTR_SPI_EC_MASK_EZ_WRITE_STOP_Msk 0x4UL 487 #define SCB_INTR_SPI_EC_MASK_EZ_READ_STOP_Pos 3UL 488 #define SCB_INTR_SPI_EC_MASK_EZ_READ_STOP_Msk 0x8UL 489 /* SCB.INTR_SPI_EC_MASKED */ 490 #define SCB_INTR_SPI_EC_MASKED_WAKE_UP_Pos 0UL 491 #define SCB_INTR_SPI_EC_MASKED_WAKE_UP_Msk 0x1UL 492 #define SCB_INTR_SPI_EC_MASKED_EZ_STOP_Pos 1UL 493 #define SCB_INTR_SPI_EC_MASKED_EZ_STOP_Msk 0x2UL 494 #define SCB_INTR_SPI_EC_MASKED_EZ_WRITE_STOP_Pos 2UL 495 #define SCB_INTR_SPI_EC_MASKED_EZ_WRITE_STOP_Msk 0x4UL 496 #define SCB_INTR_SPI_EC_MASKED_EZ_READ_STOP_Pos 3UL 497 #define SCB_INTR_SPI_EC_MASKED_EZ_READ_STOP_Msk 0x8UL 498 /* SCB.INTR_M */ 499 #define SCB_INTR_M_I2C_ARB_LOST_Pos 0UL 500 #define SCB_INTR_M_I2C_ARB_LOST_Msk 0x1UL 501 #define SCB_INTR_M_I2C_NACK_Pos 1UL 502 #define SCB_INTR_M_I2C_NACK_Msk 0x2UL 503 #define SCB_INTR_M_I2C_ACK_Pos 2UL 504 #define SCB_INTR_M_I2C_ACK_Msk 0x4UL 505 #define SCB_INTR_M_I2C_STOP_Pos 4UL 506 #define SCB_INTR_M_I2C_STOP_Msk 0x10UL 507 #define SCB_INTR_M_I2C_BUS_ERROR_Pos 8UL 508 #define SCB_INTR_M_I2C_BUS_ERROR_Msk 0x100UL 509 #define SCB_INTR_M_SPI_DONE_Pos 9UL 510 #define SCB_INTR_M_SPI_DONE_Msk 0x200UL 511 #define SCB_INTR_M_I2C_HS_ENTER_Pos 24UL 512 #define SCB_INTR_M_I2C_HS_ENTER_Msk 0x1000000UL 513 #define SCB_INTR_M_I2C_HS_EXIT_Pos 25UL 514 #define SCB_INTR_M_I2C_HS_EXIT_Msk 0x2000000UL 515 /* SCB.INTR_M_SET */ 516 #define SCB_INTR_M_SET_I2C_ARB_LOST_Pos 0UL 517 #define SCB_INTR_M_SET_I2C_ARB_LOST_Msk 0x1UL 518 #define SCB_INTR_M_SET_I2C_NACK_Pos 1UL 519 #define SCB_INTR_M_SET_I2C_NACK_Msk 0x2UL 520 #define SCB_INTR_M_SET_I2C_ACK_Pos 2UL 521 #define SCB_INTR_M_SET_I2C_ACK_Msk 0x4UL 522 #define SCB_INTR_M_SET_I2C_STOP_Pos 4UL 523 #define SCB_INTR_M_SET_I2C_STOP_Msk 0x10UL 524 #define SCB_INTR_M_SET_I2C_BUS_ERROR_Pos 8UL 525 #define SCB_INTR_M_SET_I2C_BUS_ERROR_Msk 0x100UL 526 #define SCB_INTR_M_SET_SPI_DONE_Pos 9UL 527 #define SCB_INTR_M_SET_SPI_DONE_Msk 0x200UL 528 #define SCB_INTR_M_SET_I2C_HS_ENTER_Pos 24UL 529 #define SCB_INTR_M_SET_I2C_HS_ENTER_Msk 0x1000000UL 530 #define SCB_INTR_M_SET_I2C_HS_EXIT_Pos 25UL 531 #define SCB_INTR_M_SET_I2C_HS_EXIT_Msk 0x2000000UL 532 /* SCB.INTR_M_MASK */ 533 #define SCB_INTR_M_MASK_I2C_ARB_LOST_Pos 0UL 534 #define SCB_INTR_M_MASK_I2C_ARB_LOST_Msk 0x1UL 535 #define SCB_INTR_M_MASK_I2C_NACK_Pos 1UL 536 #define SCB_INTR_M_MASK_I2C_NACK_Msk 0x2UL 537 #define SCB_INTR_M_MASK_I2C_ACK_Pos 2UL 538 #define SCB_INTR_M_MASK_I2C_ACK_Msk 0x4UL 539 #define SCB_INTR_M_MASK_I2C_STOP_Pos 4UL 540 #define SCB_INTR_M_MASK_I2C_STOP_Msk 0x10UL 541 #define SCB_INTR_M_MASK_I2C_BUS_ERROR_Pos 8UL 542 #define SCB_INTR_M_MASK_I2C_BUS_ERROR_Msk 0x100UL 543 #define SCB_INTR_M_MASK_SPI_DONE_Pos 9UL 544 #define SCB_INTR_M_MASK_SPI_DONE_Msk 0x200UL 545 #define SCB_INTR_M_MASK_I2C_HS_ENTER_Pos 24UL 546 #define SCB_INTR_M_MASK_I2C_HS_ENTER_Msk 0x1000000UL 547 #define SCB_INTR_M_MASK_I2C_HS_EXIT_Pos 25UL 548 #define SCB_INTR_M_MASK_I2C_HS_EXIT_Msk 0x2000000UL 549 /* SCB.INTR_M_MASKED */ 550 #define SCB_INTR_M_MASKED_I2C_ARB_LOST_Pos 0UL 551 #define SCB_INTR_M_MASKED_I2C_ARB_LOST_Msk 0x1UL 552 #define SCB_INTR_M_MASKED_I2C_NACK_Pos 1UL 553 #define SCB_INTR_M_MASKED_I2C_NACK_Msk 0x2UL 554 #define SCB_INTR_M_MASKED_I2C_ACK_Pos 2UL 555 #define SCB_INTR_M_MASKED_I2C_ACK_Msk 0x4UL 556 #define SCB_INTR_M_MASKED_I2C_STOP_Pos 4UL 557 #define SCB_INTR_M_MASKED_I2C_STOP_Msk 0x10UL 558 #define SCB_INTR_M_MASKED_I2C_BUS_ERROR_Pos 8UL 559 #define SCB_INTR_M_MASKED_I2C_BUS_ERROR_Msk 0x100UL 560 #define SCB_INTR_M_MASKED_SPI_DONE_Pos 9UL 561 #define SCB_INTR_M_MASKED_SPI_DONE_Msk 0x200UL 562 #define SCB_INTR_M_MASKED_I2C_HS_ENTER_Pos 24UL 563 #define SCB_INTR_M_MASKED_I2C_HS_ENTER_Msk 0x1000000UL 564 #define SCB_INTR_M_MASKED_I2C_HS_EXIT_Pos 25UL 565 #define SCB_INTR_M_MASKED_I2C_HS_EXIT_Msk 0x2000000UL 566 /* SCB.INTR_S */ 567 #define SCB_INTR_S_I2C_ARB_LOST_Pos 0UL 568 #define SCB_INTR_S_I2C_ARB_LOST_Msk 0x1UL 569 #define SCB_INTR_S_I2C_NACK_Pos 1UL 570 #define SCB_INTR_S_I2C_NACK_Msk 0x2UL 571 #define SCB_INTR_S_I2C_ACK_Pos 2UL 572 #define SCB_INTR_S_I2C_ACK_Msk 0x4UL 573 #define SCB_INTR_S_I2C_WRITE_STOP_Pos 3UL 574 #define SCB_INTR_S_I2C_WRITE_STOP_Msk 0x8UL 575 #define SCB_INTR_S_I2C_STOP_Pos 4UL 576 #define SCB_INTR_S_I2C_STOP_Msk 0x10UL 577 #define SCB_INTR_S_I2C_START_Pos 5UL 578 #define SCB_INTR_S_I2C_START_Msk 0x20UL 579 #define SCB_INTR_S_I2C_ADDR_MATCH_Pos 6UL 580 #define SCB_INTR_S_I2C_ADDR_MATCH_Msk 0x40UL 581 #define SCB_INTR_S_I2C_GENERAL_Pos 7UL 582 #define SCB_INTR_S_I2C_GENERAL_Msk 0x80UL 583 #define SCB_INTR_S_I2C_BUS_ERROR_Pos 8UL 584 #define SCB_INTR_S_I2C_BUS_ERROR_Msk 0x100UL 585 #define SCB_INTR_S_SPI_EZ_WRITE_STOP_Pos 9UL 586 #define SCB_INTR_S_SPI_EZ_WRITE_STOP_Msk 0x200UL 587 #define SCB_INTR_S_SPI_EZ_STOP_Pos 10UL 588 #define SCB_INTR_S_SPI_EZ_STOP_Msk 0x400UL 589 #define SCB_INTR_S_SPI_BUS_ERROR_Pos 11UL 590 #define SCB_INTR_S_SPI_BUS_ERROR_Msk 0x800UL 591 #define SCB_INTR_S_I2C_RESTART_Pos 16UL 592 #define SCB_INTR_S_I2C_RESTART_Msk 0x10000UL 593 #define SCB_INTR_S_I2C_HS_ENTER_Pos 24UL 594 #define SCB_INTR_S_I2C_HS_ENTER_Msk 0x1000000UL 595 #define SCB_INTR_S_I2C_HS_EXIT_Pos 25UL 596 #define SCB_INTR_S_I2C_HS_EXIT_Msk 0x2000000UL 597 /* SCB.INTR_S_SET */ 598 #define SCB_INTR_S_SET_I2C_ARB_LOST_Pos 0UL 599 #define SCB_INTR_S_SET_I2C_ARB_LOST_Msk 0x1UL 600 #define SCB_INTR_S_SET_I2C_NACK_Pos 1UL 601 #define SCB_INTR_S_SET_I2C_NACK_Msk 0x2UL 602 #define SCB_INTR_S_SET_I2C_ACK_Pos 2UL 603 #define SCB_INTR_S_SET_I2C_ACK_Msk 0x4UL 604 #define SCB_INTR_S_SET_I2C_WRITE_STOP_Pos 3UL 605 #define SCB_INTR_S_SET_I2C_WRITE_STOP_Msk 0x8UL 606 #define SCB_INTR_S_SET_I2C_STOP_Pos 4UL 607 #define SCB_INTR_S_SET_I2C_STOP_Msk 0x10UL 608 #define SCB_INTR_S_SET_I2C_START_Pos 5UL 609 #define SCB_INTR_S_SET_I2C_START_Msk 0x20UL 610 #define SCB_INTR_S_SET_I2C_ADDR_MATCH_Pos 6UL 611 #define SCB_INTR_S_SET_I2C_ADDR_MATCH_Msk 0x40UL 612 #define SCB_INTR_S_SET_I2C_GENERAL_Pos 7UL 613 #define SCB_INTR_S_SET_I2C_GENERAL_Msk 0x80UL 614 #define SCB_INTR_S_SET_I2C_BUS_ERROR_Pos 8UL 615 #define SCB_INTR_S_SET_I2C_BUS_ERROR_Msk 0x100UL 616 #define SCB_INTR_S_SET_SPI_EZ_WRITE_STOP_Pos 9UL 617 #define SCB_INTR_S_SET_SPI_EZ_WRITE_STOP_Msk 0x200UL 618 #define SCB_INTR_S_SET_SPI_EZ_STOP_Pos 10UL 619 #define SCB_INTR_S_SET_SPI_EZ_STOP_Msk 0x400UL 620 #define SCB_INTR_S_SET_SPI_BUS_ERROR_Pos 11UL 621 #define SCB_INTR_S_SET_SPI_BUS_ERROR_Msk 0x800UL 622 #define SCB_INTR_S_SET_I2C_RESTART_Pos 16UL 623 #define SCB_INTR_S_SET_I2C_RESTART_Msk 0x10000UL 624 #define SCB_INTR_S_SET_I2C_HS_ENTER_Pos 24UL 625 #define SCB_INTR_S_SET_I2C_HS_ENTER_Msk 0x1000000UL 626 #define SCB_INTR_S_SET_I2C_HS_EXIT_Pos 25UL 627 #define SCB_INTR_S_SET_I2C_HS_EXIT_Msk 0x2000000UL 628 /* SCB.INTR_S_MASK */ 629 #define SCB_INTR_S_MASK_I2C_ARB_LOST_Pos 0UL 630 #define SCB_INTR_S_MASK_I2C_ARB_LOST_Msk 0x1UL 631 #define SCB_INTR_S_MASK_I2C_NACK_Pos 1UL 632 #define SCB_INTR_S_MASK_I2C_NACK_Msk 0x2UL 633 #define SCB_INTR_S_MASK_I2C_ACK_Pos 2UL 634 #define SCB_INTR_S_MASK_I2C_ACK_Msk 0x4UL 635 #define SCB_INTR_S_MASK_I2C_WRITE_STOP_Pos 3UL 636 #define SCB_INTR_S_MASK_I2C_WRITE_STOP_Msk 0x8UL 637 #define SCB_INTR_S_MASK_I2C_STOP_Pos 4UL 638 #define SCB_INTR_S_MASK_I2C_STOP_Msk 0x10UL 639 #define SCB_INTR_S_MASK_I2C_START_Pos 5UL 640 #define SCB_INTR_S_MASK_I2C_START_Msk 0x20UL 641 #define SCB_INTR_S_MASK_I2C_ADDR_MATCH_Pos 6UL 642 #define SCB_INTR_S_MASK_I2C_ADDR_MATCH_Msk 0x40UL 643 #define SCB_INTR_S_MASK_I2C_GENERAL_Pos 7UL 644 #define SCB_INTR_S_MASK_I2C_GENERAL_Msk 0x80UL 645 #define SCB_INTR_S_MASK_I2C_BUS_ERROR_Pos 8UL 646 #define SCB_INTR_S_MASK_I2C_BUS_ERROR_Msk 0x100UL 647 #define SCB_INTR_S_MASK_SPI_EZ_WRITE_STOP_Pos 9UL 648 #define SCB_INTR_S_MASK_SPI_EZ_WRITE_STOP_Msk 0x200UL 649 #define SCB_INTR_S_MASK_SPI_EZ_STOP_Pos 10UL 650 #define SCB_INTR_S_MASK_SPI_EZ_STOP_Msk 0x400UL 651 #define SCB_INTR_S_MASK_SPI_BUS_ERROR_Pos 11UL 652 #define SCB_INTR_S_MASK_SPI_BUS_ERROR_Msk 0x800UL 653 #define SCB_INTR_S_MASK_I2C_RESTART_Pos 16UL 654 #define SCB_INTR_S_MASK_I2C_RESTART_Msk 0x10000UL 655 #define SCB_INTR_S_MASK_I2C_HS_ENTER_Pos 24UL 656 #define SCB_INTR_S_MASK_I2C_HS_ENTER_Msk 0x1000000UL 657 #define SCB_INTR_S_MASK_I2C_HS_EXIT_Pos 25UL 658 #define SCB_INTR_S_MASK_I2C_HS_EXIT_Msk 0x2000000UL 659 /* SCB.INTR_S_MASKED */ 660 #define SCB_INTR_S_MASKED_I2C_ARB_LOST_Pos 0UL 661 #define SCB_INTR_S_MASKED_I2C_ARB_LOST_Msk 0x1UL 662 #define SCB_INTR_S_MASKED_I2C_NACK_Pos 1UL 663 #define SCB_INTR_S_MASKED_I2C_NACK_Msk 0x2UL 664 #define SCB_INTR_S_MASKED_I2C_ACK_Pos 2UL 665 #define SCB_INTR_S_MASKED_I2C_ACK_Msk 0x4UL 666 #define SCB_INTR_S_MASKED_I2C_WRITE_STOP_Pos 3UL 667 #define SCB_INTR_S_MASKED_I2C_WRITE_STOP_Msk 0x8UL 668 #define SCB_INTR_S_MASKED_I2C_STOP_Pos 4UL 669 #define SCB_INTR_S_MASKED_I2C_STOP_Msk 0x10UL 670 #define SCB_INTR_S_MASKED_I2C_START_Pos 5UL 671 #define SCB_INTR_S_MASKED_I2C_START_Msk 0x20UL 672 #define SCB_INTR_S_MASKED_I2C_ADDR_MATCH_Pos 6UL 673 #define SCB_INTR_S_MASKED_I2C_ADDR_MATCH_Msk 0x40UL 674 #define SCB_INTR_S_MASKED_I2C_GENERAL_Pos 7UL 675 #define SCB_INTR_S_MASKED_I2C_GENERAL_Msk 0x80UL 676 #define SCB_INTR_S_MASKED_I2C_BUS_ERROR_Pos 8UL 677 #define SCB_INTR_S_MASKED_I2C_BUS_ERROR_Msk 0x100UL 678 #define SCB_INTR_S_MASKED_SPI_EZ_WRITE_STOP_Pos 9UL 679 #define SCB_INTR_S_MASKED_SPI_EZ_WRITE_STOP_Msk 0x200UL 680 #define SCB_INTR_S_MASKED_SPI_EZ_STOP_Pos 10UL 681 #define SCB_INTR_S_MASKED_SPI_EZ_STOP_Msk 0x400UL 682 #define SCB_INTR_S_MASKED_SPI_BUS_ERROR_Pos 11UL 683 #define SCB_INTR_S_MASKED_SPI_BUS_ERROR_Msk 0x800UL 684 #define SCB_INTR_S_MASKED_I2C_RESTART_Pos 16UL 685 #define SCB_INTR_S_MASKED_I2C_RESTART_Msk 0x10000UL 686 #define SCB_INTR_S_MASKED_I2C_HS_ENTER_Pos 24UL 687 #define SCB_INTR_S_MASKED_I2C_HS_ENTER_Msk 0x1000000UL 688 #define SCB_INTR_S_MASKED_I2C_HS_EXIT_Pos 25UL 689 #define SCB_INTR_S_MASKED_I2C_HS_EXIT_Msk 0x2000000UL 690 /* SCB.INTR_TX */ 691 #define SCB_INTR_TX_TRIGGER_Pos 0UL 692 #define SCB_INTR_TX_TRIGGER_Msk 0x1UL 693 #define SCB_INTR_TX_NOT_FULL_Pos 1UL 694 #define SCB_INTR_TX_NOT_FULL_Msk 0x2UL 695 #define SCB_INTR_TX_EMPTY_Pos 4UL 696 #define SCB_INTR_TX_EMPTY_Msk 0x10UL 697 #define SCB_INTR_TX_OVERFLOW_Pos 5UL 698 #define SCB_INTR_TX_OVERFLOW_Msk 0x20UL 699 #define SCB_INTR_TX_UNDERFLOW_Pos 6UL 700 #define SCB_INTR_TX_UNDERFLOW_Msk 0x40UL 701 #define SCB_INTR_TX_BLOCKED_Pos 7UL 702 #define SCB_INTR_TX_BLOCKED_Msk 0x80UL 703 #define SCB_INTR_TX_UART_NACK_Pos 8UL 704 #define SCB_INTR_TX_UART_NACK_Msk 0x100UL 705 #define SCB_INTR_TX_UART_DONE_Pos 9UL 706 #define SCB_INTR_TX_UART_DONE_Msk 0x200UL 707 #define SCB_INTR_TX_UART_ARB_LOST_Pos 10UL 708 #define SCB_INTR_TX_UART_ARB_LOST_Msk 0x400UL 709 /* SCB.INTR_TX_SET */ 710 #define SCB_INTR_TX_SET_TRIGGER_Pos 0UL 711 #define SCB_INTR_TX_SET_TRIGGER_Msk 0x1UL 712 #define SCB_INTR_TX_SET_NOT_FULL_Pos 1UL 713 #define SCB_INTR_TX_SET_NOT_FULL_Msk 0x2UL 714 #define SCB_INTR_TX_SET_EMPTY_Pos 4UL 715 #define SCB_INTR_TX_SET_EMPTY_Msk 0x10UL 716 #define SCB_INTR_TX_SET_OVERFLOW_Pos 5UL 717 #define SCB_INTR_TX_SET_OVERFLOW_Msk 0x20UL 718 #define SCB_INTR_TX_SET_UNDERFLOW_Pos 6UL 719 #define SCB_INTR_TX_SET_UNDERFLOW_Msk 0x40UL 720 #define SCB_INTR_TX_SET_BLOCKED_Pos 7UL 721 #define SCB_INTR_TX_SET_BLOCKED_Msk 0x80UL 722 #define SCB_INTR_TX_SET_UART_NACK_Pos 8UL 723 #define SCB_INTR_TX_SET_UART_NACK_Msk 0x100UL 724 #define SCB_INTR_TX_SET_UART_DONE_Pos 9UL 725 #define SCB_INTR_TX_SET_UART_DONE_Msk 0x200UL 726 #define SCB_INTR_TX_SET_UART_ARB_LOST_Pos 10UL 727 #define SCB_INTR_TX_SET_UART_ARB_LOST_Msk 0x400UL 728 /* SCB.INTR_TX_MASK */ 729 #define SCB_INTR_TX_MASK_TRIGGER_Pos 0UL 730 #define SCB_INTR_TX_MASK_TRIGGER_Msk 0x1UL 731 #define SCB_INTR_TX_MASK_NOT_FULL_Pos 1UL 732 #define SCB_INTR_TX_MASK_NOT_FULL_Msk 0x2UL 733 #define SCB_INTR_TX_MASK_EMPTY_Pos 4UL 734 #define SCB_INTR_TX_MASK_EMPTY_Msk 0x10UL 735 #define SCB_INTR_TX_MASK_OVERFLOW_Pos 5UL 736 #define SCB_INTR_TX_MASK_OVERFLOW_Msk 0x20UL 737 #define SCB_INTR_TX_MASK_UNDERFLOW_Pos 6UL 738 #define SCB_INTR_TX_MASK_UNDERFLOW_Msk 0x40UL 739 #define SCB_INTR_TX_MASK_BLOCKED_Pos 7UL 740 #define SCB_INTR_TX_MASK_BLOCKED_Msk 0x80UL 741 #define SCB_INTR_TX_MASK_UART_NACK_Pos 8UL 742 #define SCB_INTR_TX_MASK_UART_NACK_Msk 0x100UL 743 #define SCB_INTR_TX_MASK_UART_DONE_Pos 9UL 744 #define SCB_INTR_TX_MASK_UART_DONE_Msk 0x200UL 745 #define SCB_INTR_TX_MASK_UART_ARB_LOST_Pos 10UL 746 #define SCB_INTR_TX_MASK_UART_ARB_LOST_Msk 0x400UL 747 /* SCB.INTR_TX_MASKED */ 748 #define SCB_INTR_TX_MASKED_TRIGGER_Pos 0UL 749 #define SCB_INTR_TX_MASKED_TRIGGER_Msk 0x1UL 750 #define SCB_INTR_TX_MASKED_NOT_FULL_Pos 1UL 751 #define SCB_INTR_TX_MASKED_NOT_FULL_Msk 0x2UL 752 #define SCB_INTR_TX_MASKED_EMPTY_Pos 4UL 753 #define SCB_INTR_TX_MASKED_EMPTY_Msk 0x10UL 754 #define SCB_INTR_TX_MASKED_OVERFLOW_Pos 5UL 755 #define SCB_INTR_TX_MASKED_OVERFLOW_Msk 0x20UL 756 #define SCB_INTR_TX_MASKED_UNDERFLOW_Pos 6UL 757 #define SCB_INTR_TX_MASKED_UNDERFLOW_Msk 0x40UL 758 #define SCB_INTR_TX_MASKED_BLOCKED_Pos 7UL 759 #define SCB_INTR_TX_MASKED_BLOCKED_Msk 0x80UL 760 #define SCB_INTR_TX_MASKED_UART_NACK_Pos 8UL 761 #define SCB_INTR_TX_MASKED_UART_NACK_Msk 0x100UL 762 #define SCB_INTR_TX_MASKED_UART_DONE_Pos 9UL 763 #define SCB_INTR_TX_MASKED_UART_DONE_Msk 0x200UL 764 #define SCB_INTR_TX_MASKED_UART_ARB_LOST_Pos 10UL 765 #define SCB_INTR_TX_MASKED_UART_ARB_LOST_Msk 0x400UL 766 /* SCB.INTR_RX */ 767 #define SCB_INTR_RX_TRIGGER_Pos 0UL 768 #define SCB_INTR_RX_TRIGGER_Msk 0x1UL 769 #define SCB_INTR_RX_NOT_EMPTY_Pos 2UL 770 #define SCB_INTR_RX_NOT_EMPTY_Msk 0x4UL 771 #define SCB_INTR_RX_FULL_Pos 3UL 772 #define SCB_INTR_RX_FULL_Msk 0x8UL 773 #define SCB_INTR_RX_OVERFLOW_Pos 5UL 774 #define SCB_INTR_RX_OVERFLOW_Msk 0x20UL 775 #define SCB_INTR_RX_UNDERFLOW_Pos 6UL 776 #define SCB_INTR_RX_UNDERFLOW_Msk 0x40UL 777 #define SCB_INTR_RX_BLOCKED_Pos 7UL 778 #define SCB_INTR_RX_BLOCKED_Msk 0x80UL 779 #define SCB_INTR_RX_FRAME_ERROR_Pos 8UL 780 #define SCB_INTR_RX_FRAME_ERROR_Msk 0x100UL 781 #define SCB_INTR_RX_PARITY_ERROR_Pos 9UL 782 #define SCB_INTR_RX_PARITY_ERROR_Msk 0x200UL 783 #define SCB_INTR_RX_BAUD_DETECT_Pos 10UL 784 #define SCB_INTR_RX_BAUD_DETECT_Msk 0x400UL 785 #define SCB_INTR_RX_BREAK_DETECT_Pos 11UL 786 #define SCB_INTR_RX_BREAK_DETECT_Msk 0x800UL 787 /* SCB.INTR_RX_SET */ 788 #define SCB_INTR_RX_SET_TRIGGER_Pos 0UL 789 #define SCB_INTR_RX_SET_TRIGGER_Msk 0x1UL 790 #define SCB_INTR_RX_SET_NOT_EMPTY_Pos 2UL 791 #define SCB_INTR_RX_SET_NOT_EMPTY_Msk 0x4UL 792 #define SCB_INTR_RX_SET_FULL_Pos 3UL 793 #define SCB_INTR_RX_SET_FULL_Msk 0x8UL 794 #define SCB_INTR_RX_SET_OVERFLOW_Pos 5UL 795 #define SCB_INTR_RX_SET_OVERFLOW_Msk 0x20UL 796 #define SCB_INTR_RX_SET_UNDERFLOW_Pos 6UL 797 #define SCB_INTR_RX_SET_UNDERFLOW_Msk 0x40UL 798 #define SCB_INTR_RX_SET_BLOCKED_Pos 7UL 799 #define SCB_INTR_RX_SET_BLOCKED_Msk 0x80UL 800 #define SCB_INTR_RX_SET_FRAME_ERROR_Pos 8UL 801 #define SCB_INTR_RX_SET_FRAME_ERROR_Msk 0x100UL 802 #define SCB_INTR_RX_SET_PARITY_ERROR_Pos 9UL 803 #define SCB_INTR_RX_SET_PARITY_ERROR_Msk 0x200UL 804 #define SCB_INTR_RX_SET_BAUD_DETECT_Pos 10UL 805 #define SCB_INTR_RX_SET_BAUD_DETECT_Msk 0x400UL 806 #define SCB_INTR_RX_SET_BREAK_DETECT_Pos 11UL 807 #define SCB_INTR_RX_SET_BREAK_DETECT_Msk 0x800UL 808 /* SCB.INTR_RX_MASK */ 809 #define SCB_INTR_RX_MASK_TRIGGER_Pos 0UL 810 #define SCB_INTR_RX_MASK_TRIGGER_Msk 0x1UL 811 #define SCB_INTR_RX_MASK_NOT_EMPTY_Pos 2UL 812 #define SCB_INTR_RX_MASK_NOT_EMPTY_Msk 0x4UL 813 #define SCB_INTR_RX_MASK_FULL_Pos 3UL 814 #define SCB_INTR_RX_MASK_FULL_Msk 0x8UL 815 #define SCB_INTR_RX_MASK_OVERFLOW_Pos 5UL 816 #define SCB_INTR_RX_MASK_OVERFLOW_Msk 0x20UL 817 #define SCB_INTR_RX_MASK_UNDERFLOW_Pos 6UL 818 #define SCB_INTR_RX_MASK_UNDERFLOW_Msk 0x40UL 819 #define SCB_INTR_RX_MASK_BLOCKED_Pos 7UL 820 #define SCB_INTR_RX_MASK_BLOCKED_Msk 0x80UL 821 #define SCB_INTR_RX_MASK_FRAME_ERROR_Pos 8UL 822 #define SCB_INTR_RX_MASK_FRAME_ERROR_Msk 0x100UL 823 #define SCB_INTR_RX_MASK_PARITY_ERROR_Pos 9UL 824 #define SCB_INTR_RX_MASK_PARITY_ERROR_Msk 0x200UL 825 #define SCB_INTR_RX_MASK_BAUD_DETECT_Pos 10UL 826 #define SCB_INTR_RX_MASK_BAUD_DETECT_Msk 0x400UL 827 #define SCB_INTR_RX_MASK_BREAK_DETECT_Pos 11UL 828 #define SCB_INTR_RX_MASK_BREAK_DETECT_Msk 0x800UL 829 /* SCB.INTR_RX_MASKED */ 830 #define SCB_INTR_RX_MASKED_TRIGGER_Pos 0UL 831 #define SCB_INTR_RX_MASKED_TRIGGER_Msk 0x1UL 832 #define SCB_INTR_RX_MASKED_NOT_EMPTY_Pos 2UL 833 #define SCB_INTR_RX_MASKED_NOT_EMPTY_Msk 0x4UL 834 #define SCB_INTR_RX_MASKED_FULL_Pos 3UL 835 #define SCB_INTR_RX_MASKED_FULL_Msk 0x8UL 836 #define SCB_INTR_RX_MASKED_OVERFLOW_Pos 5UL 837 #define SCB_INTR_RX_MASKED_OVERFLOW_Msk 0x20UL 838 #define SCB_INTR_RX_MASKED_UNDERFLOW_Pos 6UL 839 #define SCB_INTR_RX_MASKED_UNDERFLOW_Msk 0x40UL 840 #define SCB_INTR_RX_MASKED_BLOCKED_Pos 7UL 841 #define SCB_INTR_RX_MASKED_BLOCKED_Msk 0x80UL 842 #define SCB_INTR_RX_MASKED_FRAME_ERROR_Pos 8UL 843 #define SCB_INTR_RX_MASKED_FRAME_ERROR_Msk 0x100UL 844 #define SCB_INTR_RX_MASKED_PARITY_ERROR_Pos 9UL 845 #define SCB_INTR_RX_MASKED_PARITY_ERROR_Msk 0x200UL 846 #define SCB_INTR_RX_MASKED_BAUD_DETECT_Pos 10UL 847 #define SCB_INTR_RX_MASKED_BAUD_DETECT_Msk 0x400UL 848 #define SCB_INTR_RX_MASKED_BREAK_DETECT_Pos 11UL 849 #define SCB_INTR_RX_MASKED_BREAK_DETECT_Msk 0x800UL 850 851 852 #endif /* _CYIP_SCB_V4_H_ */ 853 854 855 /* [] END OF FILE */ 856
