1 /** 2 ****************************************************************************** 3 * @file stm32h5xx_hal.h 4 * @author MCD Application Team 5 * @brief This file contains all the functions prototypes for the HAL 6 * module driver. 7 ****************************************************************************** 8 * @attention 9 * 10 * Copyright (c) 2023 STMicroelectronics. 11 * All rights reserved. 12 * 13 * This software is licensed under terms that can be found in the LICENSE file 14 * in the root directory of this software component. 15 * If no LICENSE file comes with this software, it is provided AS-IS. 16 * 17 ****************************************************************************** 18 */ 19 20 /* Define to prevent recursive inclusion -------------------------------------*/ 21 #ifndef __STM32H5xx_HAL_H 22 #define __STM32H5xx_HAL_H 23 24 #ifdef __cplusplus 25 extern "C" { 26 #endif /* __cplusplus */ 27 28 /* Includes ------------------------------------------------------------------*/ 29 #include "stm32h5xx_hal_conf.h" 30 31 /** @addtogroup STM32H5xx_HAL_Driver 32 * @{ 33 */ 34 35 /** @addtogroup HAL 36 * @{ 37 */ 38 39 /* Exported types ------------------------------------------------------------*/ 40 /** @defgroup HAL_Exported_Types HAL Exported Types 41 * @{ 42 */ 43 44 /** @defgroup HAL_TICK_FREQ Tick Frequency 45 * @{ 46 */ 47 typedef enum 48 { 49 HAL_TICK_FREQ_10HZ = 100U, 50 HAL_TICK_FREQ_100HZ = 10U, 51 HAL_TICK_FREQ_1KHZ = 1U, 52 HAL_TICK_FREQ_DEFAULT = HAL_TICK_FREQ_1KHZ 53 } HAL_TickFreqTypeDef; 54 /** 55 * @} 56 */ 57 58 /** 59 * @} 60 */ 61 62 /* Exported variables --------------------------------------------------------*/ 63 /** @defgroup HAL_Exported_Variables HAL Exported Variables 64 * @{ 65 */ 66 extern __IO uint32_t uwTick; 67 extern uint32_t uwTickPrio; 68 extern HAL_TickFreqTypeDef uwTickFreq; 69 /** 70 * @} 71 */ 72 73 /* Exported constants --------------------------------------------------------*/ 74 /** @defgroup SBS_Exported_Constants SBS Exported Constants 75 * @{ 76 */ 77 78 /** @defgroup SBS_FPU_Interrupts FPU Interrupts 79 * @{ 80 */ 81 #define SBS_IT_FPU_IOC SBS_FPUIMR_FPU_IE_0 /*!< Floating Point Unit Invalid operation Interrupt */ 82 #define SBS_IT_FPU_DZC SBS_FPUIMR_FPU_IE_1 /*!< Floating Point Unit Divide-by-zero Interrupt */ 83 #define SBS_IT_FPU_UFC SBS_FPUIMR_FPU_IE_2 /*!< Floating Point Unit Underflow Interrupt */ 84 #define SBS_IT_FPU_OFC SBS_FPUIMR_FPU_IE_3 /*!< Floating Point Unit Overflow Interrupt */ 85 #define SBS_IT_FPU_IDC SBS_FPUIMR_FPU_IE_4 /*!< Floating Point Unit Input denormal Interrupt */ 86 #define SBS_IT_FPU_IXC SBS_FPUIMR_FPU_IE_5 /*!< Floating Point Unit Inexact Interrupt */ 87 88 /** 89 * @} 90 */ 91 92 /** @defgroup SBS_BREAK_CONFIG SBS Break Config 93 * @{ 94 */ 95 #define SBS_BREAK_FLASH_ECC SBS_CFGR2_ECCL /*!< Enable and lock the FLASH ECC double error with TIM1/8/15/16/17 96 Break inputs.*/ 97 #define SBS_BREAK_PVD SBS_CFGR2_PVDL /*!< Enable and lock the PVD connection with TIM1/8/15/16/17 98 Break inputs. */ 99 #define SBS_BREAK_SRAM_ECC SBS_CFGR2_SEL /*!< Enable and lock the SRAM ECC double error signal with 100 TIM1/8/15/16/17 Break inputs.*/ 101 #define SBS_BREAK_LOCKUP SBS_CFGR2_CLL /*!< Enable and lock the connection of Cortex-M33 LOCKUP (hardfault) 102 output to TIM1/8/15/16/17 Break inputs.*/ 103 104 /** 105 * @} 106 */ 107 108 #if defined(VREFBUF) 109 /** @defgroup VREFBUF_VoltageScale VREFBUF Voltage Scale 110 * @{ 111 */ 112 #define VREFBUF_VOLTAGE_SCALE0 ((uint32_t)0x00000000) /*!< Voltage reference scale 0 (VREF_OUT1) */ 113 #define VREFBUF_VOLTAGE_SCALE1 VREFBUF_CSR_VRS_0 /*!< Voltage reference scale 1 (VREF_OUT2) */ 114 #define VREFBUF_VOLTAGE_SCALE2 VREFBUF_CSR_VRS_1 /*!< Voltage reference scale 2 (VREF_OUT3) */ 115 #define VREFBUF_VOLTAGE_SCALE3 (VREFBUF_CSR_VRS_0 | VREFBUF_CSR_VRS_1) /*!< Voltage reference scale 3 (VREF_OUT4) */ 116 117 /** 118 * @} 119 */ 120 121 /** @defgroup VREFBUF_HighImpedance VREFBUF High Impedance 122 * @{ 123 */ 124 #define VREFBUF_HIGH_IMPEDANCE_DISABLE ((uint32_t)0x00000000) /*!< VREF_plus pin is internally connected to 125 Voltage reference buffer output */ 126 #define VREFBUF_HIGH_IMPEDANCE_ENABLE VREFBUF_CSR_HIZ /*!< VREF_plus pin is high impedance */ 127 128 /** 129 * @} 130 */ 131 #endif /* VREFBUF */ 132 133 /** @defgroup SBS_FastModePlus_GPIO Fast-mode Plus on GPIO 134 * @{ 135 */ 136 137 /** @brief Fast-mode Plus driving capability on a specific GPIO 138 */ 139 #define SBS_FASTMODEPLUS_PB6 SBS_PMCR_PB6_FMP /*!< Enable Fast-mode Plus on PB6 */ 140 #define SBS_FASTMODEPLUS_PB7 SBS_PMCR_PB7_FMP /*!< Enable Fast-mode Plus on PB7 */ 141 #define SBS_FASTMODEPLUS_PB8 SBS_PMCR_PB8_FMP /*!< Enable Fast-mode Plus on PB8 */ 142 #if defined(SBS_PMCR_PB9_FMP) 143 #define SBS_FASTMODEPLUS_PB9 SBS_PMCR_PB9_FMP /*!< Enable Fast-mode Plus on PB9 */ 144 #endif /* SBS_PMCR_PB9_FMP */ 145 146 /** 147 * @} 148 */ 149 150 #if defined(SBS_PMCR_ETH_SEL_PHY) 151 /** @defgroup SBS_Ethernet_Config Ethernet Config 152 * @{ 153 */ 154 #define SBS_ETH_MII ((uint32_t)0x00000000) /*!< Select the Media Independent Interface (MII) or GMII */ 155 #define SBS_ETH_RMII SBS_PMCR_ETH_SEL_PHY_2 /*!< Select the Reduced Media Independent Interface (RMII) */ 156 157 #define IS_SBS_ETHERNET_CONFIG(CONFIG) (((CONFIG) == SBS_ETH_MII) || \ 158 ((CONFIG) == SBS_ETH_RMII)) 159 160 /** 161 * @} 162 */ 163 #endif /* SBS_PMCR_ETH_SEL_PHY */ 164 165 /** @defgroup SBS_Memories_Erase_Flag_Status Memory Erase Flags Status 166 * @{ 167 */ 168 #define SBS_MEMORIES_ERASE_FLAG_IPMEE SBS_MESR_IPMEE /*!< Select the Status of End Of Erase for ICACHE 169 and PKA RAMs */ 170 #define SBS_MEMORIES_ERASE_FLAG_MCLR SBS_MESR_MCLR /*!< Select the Status of Erase after Power-on Reset 171 (SRAM2, BKPRAM, ICACHE, DCACHE, PKA rams) */ 172 173 #define IS_SBS_MEMORIES_ERASE_FLAG(FLAG) (((FLAG) == SBS_MEMORIES_ERASE_FLAG_IPMEE) || \ 174 ((FLAG) == SBS_MEMORIES_ERASE_FLAG_MCLR)) 175 176 /** 177 * @} 178 */ 179 180 /** @defgroup SBS_IOCompenstionCell_Config IOCompenstionCell Config 181 * @{ 182 */ 183 #define SBS_VDD_CELL_CODE ((uint32_t)0x00000000) /*!< Select Code from the cell */ 184 #define SBS_VDD_REGISTER_CODE SBS_CCCSR_CS1 /*!< Code from the SBS compensation cell code register */ 185 186 #define IS_SBS_VDD_CODE_SELECT(SELECT) (((SELECT) == SBS_VDD_CELL_CODE)|| \ 187 ((SELECT) == SBS_VDD_REGISTER_CODE)) 188 189 #define SBS_VDDIO_CELL_CODE ((uint32_t)0x00000000) /*!< Select Code from the cell */ 190 #define SBS_VDDIO_REGISTER_CODE SBS_CCCSR_CS2 /*!< Code from the SBS compensation cell code register */ 191 192 #define IS_SBS_VDDIO_CODE_SELECT(SELECT) (((SELECT) == SBS_VDDIO_CELL_CODE)|| \ 193 ((SELECT) == SBS_VDDIO_REGISTER_CODE)) 194 195 #define IS_SBS_CODE_CONFIG(CONFIG) ((CONFIG) < (0x10UL)) 196 197 /** 198 * @} 199 */ 200 201 #if defined(SBS_EPOCHSELCR_EPOCH_SEL) 202 /** @defgroup SBS_EPOCH_Selection EPOCH Selection 203 * @{ 204 */ 205 #define SBS_EPOCH_SEL_SECURE 0x0UL /*!< EPOCH secure selected */ 206 #define SBS_EPOCH_SEL_NONSECURE SBS_EPOCHSELCR_EPOCH_SEL_0 /*!< EPOCH non secure selected */ 207 #define SBS_EPOCH_SEL_PUFCHECK SBS_EPOCHSELCR_EPOCH_SEL_1 /*!< EPOCH all zeros for PUF integrity check */ 208 209 #define IS_SBS_EPOCH_SELECTION(SELECT) (((SELECT) == SBS_EPOCH_SEL_SECURE) || \ 210 ((SELECT) == SBS_EPOCH_SEL_NONSECURE) || \ 211 ((SELECT) == SBS_EPOCH_SEL_PUFCHECK)) 212 /** 213 * @} 214 */ 215 #endif /* SBS_EPOCHSELCR_EPOCH_SEL */ 216 217 #if defined(SBS_NEXTHDPLCR_NEXTHDPL) 218 /** @defgroup SBS_NextHDPL_Selection Next HDPL Selection 219 * @{ 220 */ 221 #define SBS_OBKHDPL_INCR_0 0x00U /*!< Index to add to the current HDPL to point (through OBK-HDPL) to the next secure storage areas */ 222 #define SBS_OBKHDPL_INCR_1 SBS_NEXTHDPLCR_NEXTHDPL_0 /*!< Index to add to the current HDPL to point (through OBK-HDPL) to the next secure storage areas */ 223 #define SBS_OBKHDPL_INCR_2 SBS_NEXTHDPLCR_NEXTHDPL_1 /*!< Index to add to the current HDPL to point (through OBK-HDPL) to the next secure storage areas */ 224 #define SBS_OBKHDPL_INCR_3 SBS_NEXTHDPLCR_NEXTHDPL /*!< Index to add to the current HDPL to point (through OBK-HDPL) to the next secure storage areas */ 225 /** 226 * @} 227 */ 228 #endif /* SBS_NEXTHDPLCR_NEXTHDPL */ 229 230 /** @defgroup SBS_HDPL_Value HDPL Value 231 * @{ 232 */ 233 #define SBS_HDPL_VALUE_0 0x000000B4U /*!< Hide protection level 0 */ 234 #define SBS_HDPL_VALUE_1 0x00000051U /*!< Hide protection level 0 */ 235 #define SBS_HDPL_VALUE_2 0x0000008AU /*!< Hide protection level 0 */ 236 #define SBS_HDPL_VALUE_3 0x0000006FU /*!< Hide protection level 0 */ 237 /** 238 * @} 239 */ 240 241 #if defined(SBS_DBGCR_DBG_AUTH_SEC) 242 /** @defgroup SBS_DEBUG_SEC_Value Debug sec Value 243 * @{ 244 */ 245 #define SBS_DEBUG_SEC_NSEC 0x000000B4U /*!< Debug opening for secure and non-secure */ 246 #define SBS_DEBUG_NSEC 0x0000003CU /*!< Debug opening for non-secure only */ 247 /** 248 * @} 249 */ 250 #endif /* SBS_DBGCR_DBG_AUTH_SEC */ 251 252 /** @defgroup SBS_Lock_items SBS Lock items 253 * @brief SBS items to set lock on 254 * @{ 255 */ 256 #define SBS_MPU_NSEC SBS_CNSLCKR_LOCKNSMPU /*!< Non-secure MPU lock (privileged secure or 257 non-secure only) */ 258 #define SBS_VTOR_NSEC SBS_CNSLCKR_LOCKNSVTOR /*!< Non-secure VTOR lock (privileged secure or 259 non-secure only) */ 260 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 261 #define SBS_SAU (SBS_CSLCKR_LOCKSAU << 16U) /*!< SAU lock (privileged secure code only) */ 262 #define SBS_MPU_SEC (SBS_CSLCKR_LOCKSMPU << 16U) /*!< Secure MPU lock (privileged secure code only) 263 */ 264 #define SBS_VTOR_AIRCR_SEC (SBS_CSLCKR_LOCKSVTAIRCR << 16U) /*!< VTOR_S and AIRCR lock (privileged secure 265 code only) */ 266 #define SBS_LOCK_ALL (SBS_MPU_NSEC|SBS_VTOR_NSEC|SBS_SAU|SBS_MPU_SEC|SBS_VTOR_AIRCR_SEC) /*!< All */ 267 #else 268 #define SBS_LOCK_ALL (SBS_MPU_NSEC|SBS_VTOR_NSEC) /*!< All (privileged secure or non-secure only) */ 269 #endif /* __ARM_FEATURE_CMSE */ 270 /** 271 * @} 272 */ 273 274 /** @defgroup SBS_Attributes_items SBS Attributes items 275 * @brief SBS items to configure secure or non-secure attributes on 276 * @{ 277 */ 278 #define SBS_CLK SBS_SECCFGR_SBSSEC /*!< SBS clock control */ 279 #define SBS_CLASSB SBS_SECCFGR_CLASSBSEC /*!< Class B */ 280 #define SBS_FPU SBS_SECCFGR_FPUSEC /*!< FPU */ 281 #define SBS_SMPS SBS_SECCFGR_SDCE_SEC_EN /*!< SMPS */ 282 #define SBS_ALL (SBS_CLK | SBS_CLASSB | SBS_FPU | SBS_SMPS) /*!< All */ 283 /** 284 * @} 285 */ 286 287 /** @defgroup SBS_attributes SBS attributes 288 * @brief SBS secure or non-secure attributes 289 * @{ 290 */ 291 #define SBS_SEC 0x00000001U /*!< Secure attribute */ 292 #define SBS_NSEC 0x00000000U /*!< Non-secure attribute */ 293 /** 294 * @} 295 */ 296 297 /** 298 * @} 299 */ 300 301 /* Exported macros -----------------------------------------------------------*/ 302 303 /** @defgroup DBGMCU_Exported_Macros DBGMCU Exported Macros 304 * @{ 305 */ 306 307 /** @brief Freeze/Unfreeze Peripherals in Debug mode 308 */ 309 #if defined(DBGMCU_APB1FZR1_DBG_TIM2_STOP) 310 #define __HAL_DBGMCU_FREEZE_TIM2() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM2_STOP) 311 #define __HAL_DBGMCU_UNFREEZE_TIM2() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM2_STOP) 312 #endif /* DBGMCU_APB1FZR1_DBG_TIM2_STOP */ 313 314 #if defined(DBGMCU_APB1FZR1_DBG_TIM3_STOP) 315 #define __HAL_DBGMCU_FREEZE_TIM3() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM3_STOP) 316 #define __HAL_DBGMCU_UNFREEZE_TIM3() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM3_STOP) 317 #endif /* DBGMCU_APB1FZR1_DBG_TIM3_STOP */ 318 319 #if defined(DBGMCU_APB1FZR1_DBG_TIM4_STOP) 320 #define __HAL_DBGMCU_FREEZE_TIM4() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM4_STOP) 321 #define __HAL_DBGMCU_UNFREEZE_TIM4() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM4_STOP) 322 #endif /* DBGMCU_APB1FZR1_DBG_TIM4_STOP */ 323 324 #if defined(DBGMCU_APB1FZR1_DBG_TIM4_STOP) 325 #define __HAL_DBGMCU_FREEZE_TIM5() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM5_STOP) 326 #define __HAL_DBGMCU_UNFREEZE_TIM5() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM5_STOP) 327 #endif /* DBGMCU_APB1FZR1_DBG_TIM4_STOP */ 328 329 #if defined(DBGMCU_APB1FZR1_DBG_TIM6_STOP) 330 #define __HAL_DBGMCU_FREEZE_TIM6() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM6_STOP) 331 #define __HAL_DBGMCU_UNFREEZE_TIM6() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM6_STOP) 332 #endif /* DBGMCU_APB1FZR1_DBG_TIM6_STOP */ 333 334 #if defined(DBGMCU_APB1FZR1_DBG_TIM7_STOP) 335 #define __HAL_DBGMCU_FREEZE_TIM7() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM7_STOP) 336 #define __HAL_DBGMCU_UNFREEZE_TIM7() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM7_STOP) 337 #endif /* DBGMCU_APB1FZR1_DBG_TIM7_STOP */ 338 339 #if defined(DBGMCU_APB1FZR1_DBG_TIM12_STOP) 340 #define __HAL_DBGMCU_FREEZE_TIM12() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM12_STOP) 341 #define __HAL_DBGMCU_UNFREEZE_TIM12() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM12_STOP) 342 #endif /* DBGMCU_APB1FZR1_DBG_TIM12_STOP */ 343 344 #if defined(DBGMCU_APB1FZR1_DBG_TIM13_STOP) 345 #define __HAL_DBGMCU_FREEZE_TIM13() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM13_STOP) 346 #define __HAL_DBGMCU_UNFREEZE_TIM13() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM13_STOP) 347 #endif /* DBGMCU_APB1FZR1_DBG_TIM13_STOP */ 348 349 #if defined(DBGMCU_APB1FZR1_DBG_TIM14_STOP) 350 #define __HAL_DBGMCU_FREEZE_TIM14() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM14_STOP) 351 #define __HAL_DBGMCU_UNFREEZE_TIM14() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM14_STOP) 352 #endif /* DBGMCU_APB1FZR1_DBG_TIM14_STOP */ 353 354 #if defined(DBGMCU_APB1FZR1_DBG_WWDG_STOP) 355 #define __HAL_DBGMCU_FREEZE_WWDG() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_WWDG_STOP) 356 #define __HAL_DBGMCU_UNFREEZE_WWDG() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_WWDG_STOP) 357 #endif /* DBGMCU_APB1FZR1_DBG_WWDG_STOP */ 358 359 #if defined(DBGMCU_APB1FZR1_DBG_IWDG_STOP) 360 #define __HAL_DBGMCU_FREEZE_IWDG() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_IWDG_STOP) 361 #define __HAL_DBGMCU_UNFREEZE_IWDG() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_IWDG_STOP) 362 #endif /* DBGMCU_APB1FZR1_DBG_IWDG_STOP */ 363 364 #if defined(DBGMCU_APB1FZR1_DBG_I2C1_STOP) 365 #define __HAL_DBGMCU_FREEZE_I2C1() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C1_STOP) 366 #define __HAL_DBGMCU_UNFREEZE_I2C1() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C1_STOP) 367 #endif /* DBGMCU_APB1FZR1_DBG_I2C1_STOP */ 368 369 #if defined(DBGMCU_APB1FZR1_DBG_I2C2_STOP) 370 #define __HAL_DBGMCU_FREEZE_I2C2() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C2_STOP) 371 #define __HAL_DBGMCU_UNFREEZE_I2C2() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C2_STOP) 372 #endif /* DBGMCU_APB1FZR1_DBG_I2C2_STOP */ 373 374 #if defined(DBGMCU_APB1FZR1_DBG_I3C1_STOP) 375 #define __HAL_DBGMCU_FREEZE_I3C1() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I3C1_STOP) 376 #define __HAL_DBGMCU_UNFREEZE_I3C1() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I3C1_STOP) 377 #endif /* DBGMCU_APB1FZR1_DBG_I3C1_STOP */ 378 379 #if defined(DBGMCU_APB1FZR2_DBG_LPTIM2_STOP) 380 #define __HAL_DBGMCU_FREEZE_LPTIM2() SET_BIT(DBGMCU->APB1FZR2, DBGMCU_APB1FZR2_DBG_LPTIM2_STOP) 381 #define __HAL_DBGMCU_UNFREEZE_LPTIM2() CLEAR_BIT(DBGMCU->APB1FZR2, DBGMCU_APB1FZR2_DBG_LPTIM2_STOP) 382 #endif /* DBGMCU_APB1FZR2_DBG_LPTIM2_STOP */ 383 384 #if defined(DBGMCU_APB2FZR_DBG_TIM1_STOP) 385 #define __HAL_DBGMCU_FREEZE_TIM1() SET_BIT(DBGMCU->APB2FZR, DBGMCU_APB2FZR_DBG_TIM1_STOP) 386 #define __HAL_DBGMCU_UNFREEZE_TIM1() CLEAR_BIT(DBGMCU->APB2FZR, DBGMCU_APB2FZR_DBG_TIM1_STOP) 387 #endif /* DBGMCU_APB2FZR_DBG_TIM1_STOP */ 388 389 #if defined(DBGMCU_APB2FZR_DBG_TIM8_STOP) 390 #define __HAL_DBGMCU_FREEZE_TIM8() SET_BIT(DBGMCU->APB2FZR, DBGMCU_APB2FZR_DBG_TIM8_STOP) 391 #define __HAL_DBGMCU_UNFREEZE_TIM8() CLEAR_BIT(DBGMCU->APB2FZR, DBGMCU_APB2FZR_DBG_TIM8_STOP) 392 #endif /* DBGMCU_APB2FZR_DBG_TIM8_STOP */ 393 394 #if defined(DBGMCU_APB2FZR_DBG_TIM15_STOP) 395 #define __HAL_DBGMCU_FREEZE_TIM15() SET_BIT(DBGMCU->APB2FZR, DBGMCU_APB2FZR_DBG_TIM15_STOP) 396 #define __HAL_DBGMCU_UNFREEZE_TIM15() CLEAR_BIT(DBGMCU->APB2FZR, DBGMCU_APB2FZR_DBG_TIM15_STOP) 397 #endif /* DBGMCU_APB2FZR_DBG_TIM15_STOP */ 398 399 #if defined(DBGMCU_APB2FZR_DBG_TIM16_STOP) 400 #define __HAL_DBGMCU_FREEZE_TIM16() SET_BIT(DBGMCU->APB2FZR, DBGMCU_APB2FZR_DBG_TIM16_STOP) 401 #define __HAL_DBGMCU_UNFREEZE_TIM16() CLEAR_BIT(DBGMCU->APB2FZR, DBGMCU_APB2FZR_DBG_TIM16_STOP) 402 #endif /* DBGMCU_APB2FZR_DBG_TIM16_STOP */ 403 404 #if defined(DBGMCU_APB2FZR_DBG_TIM17_STOP) 405 #define __HAL_DBGMCU_FREEZE_TIM17() SET_BIT(DBGMCU->APB2FZR, DBGMCU_APB2FZR_DBG_TIM17_STOP) 406 #define __HAL_DBGMCU_UNFREEZE_TIM17() CLEAR_BIT(DBGMCU->APB2FZR, DBGMCU_APB2FZR_DBG_TIM17_STOP) 407 #endif /* DBGMCU_APB2FZR_DBG_TIM17_STOP */ 408 409 #if defined(DBGMCU_APB3FZR_DBG_I2C3_STOP) 410 #define __HAL_DBGMCU_FREEZE_I2C3() SET_BIT(DBGMCU->APB3FZR, DBGMCU_APB3FZR_DBG_I2C3_STOP) 411 #define __HAL_DBGMCU_UNFREEZE_I2C3() CLEAR_BIT(DBGMCU->APB3FZR, DBGMCU_APB3FZR_DBG_I2C3_STOP) 412 #endif /* DBGMCU_APB3FZR_DBG_I2C3_STOP */ 413 414 #if defined(DBGMCU_APB3FZR_DBG_I2C4_STOP) 415 #define __HAL_DBGMCU_FREEZE_I2C4() SET_BIT(DBGMCU->APB3FZR, DBGMCU_APB3FZR_DBG_I2C4_STOP) 416 #define __HAL_DBGMCU_UNFREEZE_I2C4() CLEAR_BIT(DBGMCU->APB3FZR, DBGMCU_APB3FZR_DBG_I2C4_STOP) 417 #endif /* DBGMCU_APB3FZR_DBG_I2C4_STOP */ 418 419 #if defined(DBGMCU_APB3FZR_DBG_I3C2_STOP) 420 #define __HAL_DBGMCU_FREEZE_I3C2() SET_BIT(DBGMCU->APB3FZR, DBGMCU_APB3FZR_DBG_I3C2_STOP) 421 #define __HAL_DBGMCU_UNFREEZE_I3C2() CLEAR_BIT(DBGMCU->APB3FZR, DBGMCU_APB3FZR_DBG_I3C2_STOP) 422 #endif /* DBGMCU_APB3FZR_DBG_I3C2_STOP */ 423 424 #if defined(DBGMCU_APB3FZR_DBG_LPTIM1_STOP) 425 #define __HAL_DBGMCU_FREEZE_LPTIM1() SET_BIT(DBGMCU->APB3FZR, DBGMCU_APB3FZR_DBG_LPTIM1_STOP) 426 #define __HAL_DBGMCU_UNFREEZE_LPTIM1() CLEAR_BIT(DBGMCU->APB3FZR, DBGMCU_APB3FZR_DBG_LPTIM1_STOP) 427 #endif /* DBGMCU_APB3FZR_DBG_LPTIM1_STOP */ 428 429 #if defined(DBGMCU_APB3FZR_DBG_LPTIM3_STOP) 430 #define __HAL_DBGMCU_FREEZE_LPTIM3() SET_BIT(DBGMCU->APB3FZR, DBGMCU_APB3FZR_DBG_LPTIM3_STOP) 431 #define __HAL_DBGMCU_UNFREEZE_LPTIM3() CLEAR_BIT(DBGMCU->APB3FZR, DBGMCU_APB3FZR_DBG_LPTIM3_STOP) 432 #endif /* DBGMCU_APB3FZR_DBG_LPTIM3_STOP */ 433 434 #if defined(DBGMCU_APB3FZR_DBG_LPTIM4_STOP) 435 #define __HAL_DBGMCU_FREEZE_LPTIM4() SET_BIT(DBGMCU->APB3FZR, DBGMCU_APB3FZR_DBG_LPTIM4_STOP) 436 #define __HAL_DBGMCU_UNFREEZE_LPTIM4() CLEAR_BIT(DBGMCU->APB3FZR, DBGMCU_APB3FZR_DBG_LPTIM4_STOP) 437 #endif /* DBGMCU_APB3FZR_DBG_LPTIM4_STOP */ 438 439 #if defined(DBGMCU_APB3FZR_DBG_LPTIM5_STOP) 440 #define __HAL_DBGMCU_FREEZE_LPTIM5() SET_BIT(DBGMCU->APB3FZR, DBGMCU_APB3FZR_DBG_LPTIM5_STOP) 441 #define __HAL_DBGMCU_UNFREEZE_LPTIM5() CLEAR_BIT(DBGMCU->APB3FZR, DBGMCU_APB3FZR_DBG_LPTIM5_STOP) 442 #endif /* DBGMCU_APB3FZR_DBG_LPTIM5_STOP */ 443 444 #if defined(DBGMCU_APB3FZR_DBG_LPTIM6_STOP) 445 #define __HAL_DBGMCU_FREEZE_LPTIM6() SET_BIT(DBGMCU->APB3FZR, DBGMCU_APB3FZR_DBG_LPTIM6_STOP) 446 #define __HAL_DBGMCU_UNFREEZE_LPTIM6() CLEAR_BIT(DBGMCU->APB3FZR, DBGMCU_APB3FZR_DBG_LPTIM6_STOP) 447 #endif /* DBGMCU_APB3FZR_DBG_LPTIM6_STOP */ 448 449 #if defined(DBGMCU_APB3FZR_DBG_RTC_STOP) 450 #define __HAL_DBGMCU_FREEZE_RTC() SET_BIT(DBGMCU->APB3FZR, DBGMCU_APB3FZR_DBG_RTC_STOP) 451 #define __HAL_DBGMCU_UNFREEZE_RTC() CLEAR_BIT(DBGMCU->APB3FZR, DBGMCU_APB3FZR_DBG_RTC_STOP) 452 #endif /* DBGMCU_APB3FZR_DBG_RTC_STOP */ 453 454 #if defined(DBGMCU_AHB1FZR_DBG_GPDMA1_CH0_STOP) 455 #define __HAL_DBGMCU_FREEZE_GPDMA1_0() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA1_CH0_STOP) 456 #define __HAL_DBGMCU_UNFREEZE_GPDMA1_0() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA1_CH0_STOP) 457 #endif /* DBGMCU_AHB1FZR_DBG_GPDMA1_CH0_STOP */ 458 459 #if defined(DBGMCU_AHB1FZR_DBG_GPDMA1_CH1_STOP) 460 #define __HAL_DBGMCU_FREEZE_GPDMA1_1() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA1_CH1_STOP) 461 #define __HAL_DBGMCU_UNFREEZE_GPDMA1_1() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA1_CH1_STOP) 462 #endif /* DBGMCU_AHB1FZR_DBG_GPDMA1_CH1_STOP */ 463 464 #if defined(DBGMCU_AHB1FZR_DBG_GPDMA1_CH2_STOP) 465 #define __HAL_DBGMCU_FREEZE_GPDMA1_2() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA1_CH2_STOP) 466 #define __HAL_DBGMCU_UNFREEZE_GPDMA1_2() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA1_CH2_STOP) 467 #endif /* DBGMCU_AHB1FZR_DBG_GPDMA1_CH2_STOP */ 468 469 #if defined(DBGMCU_AHB1FZR_DBG_GPDMA1_CH3_STOP) 470 #define __HAL_DBGMCU_FREEZE_GPDMA1_3() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA1_CH3_STOP) 471 #define __HAL_DBGMCU_UNFREEZE_GPDMA1_3() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA1_CH3_STOP) 472 #endif /* DBGMCU_AHB1FZR_DBG_GPDMA1_CH3_STOP */ 473 474 #if defined(DBGMCU_AHB1FZR_DBG_GPDMA1_CH4_STOP) 475 #define __HAL_DBGMCU_FREEZE_GPDMA1_4() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA1_CH4_STOP) 476 #define __HAL_DBGMCU_UNFREEZE_GPDMA1_4() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA1_CH4_STOP) 477 #endif /* DBGMCU_AHB1FZR_DBG_GPDMA1_CH4_STOP */ 478 479 #if defined(DBGMCU_AHB1FZR_DBG_GPDMA1_CH5_STOP) 480 #define __HAL_DBGMCU_FREEZE_GPDMA1_5() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA1_CH5_STOP) 481 #define __HAL_DBGMCU_UNFREEZE_GPDMA1_5() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA1_CH5_STOP) 482 #endif /* DBGMCU_AHB1FZR_DBG_GPDMA1_CH5_STOP */ 483 484 #if defined(DBGMCU_AHB1FZR_DBG_GPDMA1_CH6_STOP) 485 #define __HAL_DBGMCU_FREEZE_GPDMA1_6() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA1_CH6_STOP) 486 #define __HAL_DBGMCU_UNFREEZE_GPDMA1_6() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA1_CH6_STOP) 487 #endif /* DBGMCU_AHB1FZR_DBG_GPDMA1_CH6_STOP */ 488 489 #if defined(DBGMCU_AHB1FZR_DBG_GPDMA1_CH7_STOP) 490 #define __HAL_DBGMCU_FREEZE_GPDMA1_7() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA1_CH7_STOP) 491 #define __HAL_DBGMCU_UNFREEZE_GPDMA1_7() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA1_CH7_STOP) 492 #endif /* DBGMCU_AHB1FZR_DBG_GPDMA1_CH7_STOP */ 493 494 #if defined(DBGMCU_AHB1FZR_DBG_GPDMA2_CH0_STOP) 495 #define __HAL_DBGMCU_FREEZE_GPDMA2_0() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA2_CH0_STOP) 496 #define __HAL_DBGMCU_UNFREEZE_GPDMA2_0() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA2_CH0_STOP) 497 #endif /* DBGMCU_AHB1FZR_DBG_GPDMA2_CH0_STOP */ 498 499 #if defined(DBGMCU_AHB1FZR_DBG_GPDMA2_CH1_STOP) 500 #define __HAL_DBGMCU_FREEZE_GPDMA2_1() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA2_CH1_STOP) 501 #define __HAL_DBGMCU_UNFREEZE_GPDMA2_1() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA2_CH1_STOP) 502 #endif /* DBGMCU_AHB1FZR_DBG_GPDMA2_CH1_STOP */ 503 504 #if defined(DBGMCU_AHB1FZR_DBG_GPDMA2_CH2_STOP) 505 #define __HAL_DBGMCU_FREEZE_GPDMA2_2() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA2_CH2_STOP) 506 #define __HAL_DBGMCU_UNFREEZE_GPDMA2_2() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA2_CH2_STOP) 507 #endif /* DBGMCU_AHB1FZR_DBG_GPDMA2_CH2_STOP */ 508 509 #if defined(DBGMCU_AHB1FZR_DBG_GPDMA2_CH3_STOP) 510 #define __HAL_DBGMCU_FREEZE_GPDMA2_3() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA2_CH3_STOP) 511 #define __HAL_DBGMCU_UNFREEZE_GPDMA2_3() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA2_CH3_STOP) 512 #endif /* DBGMCU_AHB1FZR_DBG_GPDMA2_CH3_STOP */ 513 514 #if defined(DBGMCU_AHB1FZR_DBG_GPDMA2_CH4_STOP) 515 #define __HAL_DBGMCU_FREEZE_GPDMA2_4() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA2_CH4_STOP) 516 #define __HAL_DBGMCU_UNFREEZE_GPDMA2_4() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA2_CH4_STOP) 517 #endif /* DBGMCU_AHB1FZR_DBG_GPDMA2_CH4_STOP */ 518 519 #if defined(DBGMCU_AHB1FZR_DBG_GPDMA2_CH5_STOP) 520 #define __HAL_DBGMCU_FREEZE_GPDMA2_5() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA2_CH5_STOP) 521 #define __HAL_DBGMCU_UNFREEZE_GPDMA2_5() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA2_CH5_STOP) 522 #endif /* DBGMCU_AHB1FZR_DBG_GPDMA2_CH5_STOP */ 523 524 #if defined(DBGMCU_AHB1FZR_DBG_GPDMA2_CH6_STOP) 525 #define __HAL_DBGMCU_FREEZE_GPDMA2_6() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA2_CH6_STOP) 526 #define __HAL_DBGMCU_UNFREEZE_GPDMA2_6() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA2_CH6_STOP) 527 #endif /* DBGMCU_AHB1FZR_DBG_GPDMA2_CH6_STOP */ 528 529 #if defined(DBGMCU_AHB1FZR_DBG_GPDMA2_CH7_STOP) 530 #define __HAL_DBGMCU_FREEZE_GPDMA2_7() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA2_CH7_STOP) 531 #define __HAL_DBGMCU_UNFREEZE_GPDMA2_7() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA2_CH7_STOP) 532 #endif /* DBGMCU_AHB1FZR_DBG_GPDMA2_CH7_STOP */ 533 534 /** 535 * @} 536 */ 537 538 /** @defgroup SBS_Exported_Macros SBS Exported Macros 539 * @{ 540 */ 541 542 /** @brief Floating Point Unit interrupt enable/disable macros 543 * @param __INTERRUPT__: This parameter can be a value of @ref SBS_FPU_Interrupts 544 */ 545 #define __HAL_SBS_FPU_INTERRUPT_ENABLE(__INTERRUPT__) do {assert_param(IS_SBS_FPU_INTERRUPT((__INTERRUPT__)));\ 546 SET_BIT(SBS->FPUIMR, (__INTERRUPT__));\ 547 }while(0) 548 549 #define __HAL_SBS_FPU_INTERRUPT_DISABLE(__INTERRUPT__) do {assert_param(IS_SBS_FPU_INTERRUPT((__INTERRUPT__)));\ 550 CLEAR_BIT(SBS->FPUIMR, (__INTERRUPT__));\ 551 }while(0) 552 553 /** @brief SBS Break ECC lock. 554 * Enable and lock the connection of Flash ECC error connection to TIM1/8/15/16/17 Break input. 555 * @note The selected configuration is locked and can be unlocked only by system reset. 556 */ 557 #define __HAL_SBS_BREAK_ECC_LOCK() SET_BIT(SBS->CFGR2, SBS_CFGR2_ECCL) 558 559 /** @brief SBS Break Cortex-M33 Lockup lock. 560 * Enable and lock the connection of Cortex-M33 LOCKUP (Hardfault) output to TIM1/8/15/16/17 Break input. 561 * @note The selected configuration is locked and can be unlocked only by system reset. 562 */ 563 #define __HAL_SBS_BREAK_LOCKUP_LOCK() SET_BIT(SBS->CFGR2, SBS_CFGR2_CLL) 564 565 /** @brief SBS Break PVD lock. 566 * Enable and lock the PVD connection to Timer1/8/15/16/17 Break input, as well as the PVDE and PLS[2:0] 567 * in the PWR_CR2 register. 568 * @note The selected configuration is locked and can be unlocked only by system reset. 569 */ 570 #define __HAL_SBS_BREAK_PVD_LOCK() SET_BIT(SBS->CFGR2, SBS_CFGR2_PVDL) 571 572 /** @brief SBS Break SRAM double ECC lock. 573 * Enable and lock the connection of SRAM double ECC error to TIM1/8/15/16/17 Break input. 574 * @note The selected configuration is locked and can be unlocked only by system reset. 575 */ 576 #define __HAL_SBS_BREAK_SRAM_ECC_LOCK() SET_BIT(SBS->CFGR2, SBS_CFGR2_SEL) 577 578 /** @brief Fast-mode Plus driving capability enable/disable macros 579 * @param __FASTMODEPLUS__: This parameter can be a value of : 580 * @arg @ref SBS_FASTMODEPLUS_PB6 Fast-mode Plus driving capability activation on PB6 581 * @arg @ref SBS_FASTMODEPLUS_PB7 Fast-mode Plus driving capability activation on PB7 582 * @arg @ref SBS_FASTMODEPLUS_PB8 Fast-mode Plus driving capability activation on PB8 583 * @arg @ref SBS_FASTMODEPLUS_PB9 Fast-mode Plus driving capability activation on PB9 584 */ 585 #define __HAL_SBS_FASTMODEPLUS_ENABLE(__FASTMODEPLUS__) do {assert_param(IS_SBS_FASTMODEPLUS((__FASTMODEPLUS__)));\ 586 SET_BIT(SBS->PMCR, (__FASTMODEPLUS__));\ 587 }while(0) 588 589 #define __HAL_SBS_FASTMODEPLUS_DISABLE(__FASTMODEPLUS__) do {assert_param(IS_SBS_FASTMODEPLUS((__FASTMODEPLUS__)));\ 590 CLEAR_BIT(SBS->PMCR, (__FASTMODEPLUS__));\ 591 }while(0) 592 593 /** @brief Check SBS Memories Erase Status Flags. 594 * @param __FLAG__: specifies the flag to check. 595 * This parameter can be one of the following values: 596 * @arg @ref SBS_MEMORIES_ERASE_FLAG_IPMEE Status of End Of Erase for ICACHE and PKA RAMs 597 * @arg @ref SBS_MEMORIES_ERASE_FLAG_MCLR Status of Erase after Power-on Reset ((SRAM2, BKPRAM, 598 * ICACHE, DCACHE, PKA RAMs) 599 * @retval The new state of __FLAG__ (TRUE or FALSE). 600 */ 601 #define __HAL_SBS_GET_MEMORIES_ERASE_STATUS(__FLAG__) ((((SBS->MESR) & (__FLAG__))!= 0) ? 1 : 0) 602 603 /** @brief Clear SBS Memories Erase Status Flags. 604 * @param __FLAG__: specifies the flag to clear. 605 * This parameter can be one of the following values: 606 * @arg @ref SBS_MEMORIES_ERASE_FLAG_IPMEE Status of End Of Erase for ICACHE and PKA RAMs 607 * @arg @ref SBS_MEMORIES_ERASE_FLAG_MCLR Status of Erase after Power-on Reset ((SRAM2, BKPRAM, 608 * ICACHE, DCACHE, PKA RAMs) 609 */ 610 #define __HAL_SBS_CLEAR_MEMORIES_ERASE_STATUS(__FLAG__) do {assert_param(IS_SBS_MEMORIES_ERASE_FLAG((__FLAG__)));\ 611 WRITE_REG(SBS->MESR, (__FLAG__));\ 612 }while(0) 613 614 /** 615 * @} 616 */ 617 618 /* Private macros ------------------------------------------------------------*/ 619 620 /** @defgroup SBS_Private_Macros SBS Private Macros 621 * @{ 622 */ 623 624 #define IS_SBS_FPU_INTERRUPT(__INTERRUPT__) ((((__INTERRUPT__) & SBS_IT_FPU_IOC) == SBS_IT_FPU_IOC) || \ 625 (((__INTERRUPT__) & SBS_IT_FPU_DZC) == SBS_IT_FPU_DZC) || \ 626 (((__INTERRUPT__) & SBS_IT_FPU_UFC) == SBS_IT_FPU_UFC) || \ 627 (((__INTERRUPT__) & SBS_IT_FPU_OFC) == SBS_IT_FPU_OFC) || \ 628 (((__INTERRUPT__) & SBS_IT_FPU_IDC) == SBS_IT_FPU_IDC) || \ 629 (((__INTERRUPT__) & SBS_IT_FPU_IXC) == SBS_IT_FPU_IXC)) 630 631 #define IS_SBS_BREAK_CONFIG(__CONFIG__) (((__CONFIG__) == SBS_BREAK_FLASH_ECC) || \ 632 ((__CONFIG__) == SBS_BREAK_PVD) || \ 633 ((__CONFIG__) == SBS_BREAK_SRAM_ECC) || \ 634 ((__CONFIG__) == SBS_BREAK_LOCKUP)) 635 636 #if defined(VREFBUF) 637 #define IS_VREFBUF_VOLTAGE_SCALE(__SCALE__) (((__SCALE__) == VREFBUF_VOLTAGE_SCALE0) || \ 638 ((__SCALE__) == VREFBUF_VOLTAGE_SCALE1) || \ 639 ((__SCALE__) == VREFBUF_VOLTAGE_SCALE2) || \ 640 ((__SCALE__) == VREFBUF_VOLTAGE_SCALE3)) 641 642 #define IS_VREFBUF_HIGH_IMPEDANCE(__VALUE__) (((__VALUE__) == VREFBUF_HIGH_IMPEDANCE_DISABLE) || \ 643 ((__VALUE__) == VREFBUF_HIGH_IMPEDANCE_ENABLE)) 644 645 #define IS_VREFBUF_TRIMMING(__VALUE__) (((__VALUE__) > 0U) && ((__VALUE__) <= VREFBUF_CCR_TRIM)) 646 #endif /* VREFBUF*/ 647 648 #if defined(SBS_FASTMODEPLUS_PB9) 649 #define IS_SBS_FASTMODEPLUS(__PIN__) ((((__PIN__) & SBS_FASTMODEPLUS_PB6) == SBS_FASTMODEPLUS_PB6) || \ 650 (((__PIN__) & SBS_FASTMODEPLUS_PB7) == SBS_FASTMODEPLUS_PB7) || \ 651 (((__PIN__) & SBS_FASTMODEPLUS_PB8) == SBS_FASTMODEPLUS_PB8) || \ 652 (((__PIN__) & SBS_FASTMODEPLUS_PB9) == SBS_FASTMODEPLUS_PB9)) 653 #else 654 #define IS_SBS_FASTMODEPLUS(__PIN__) ((((__PIN__) & SBS_FASTMODEPLUS_PB6) == SBS_FASTMODEPLUS_PB6) || \ 655 (((__PIN__) & SBS_FASTMODEPLUS_PB7) == SBS_FASTMODEPLUS_PB7) || \ 656 (((__PIN__) & SBS_FASTMODEPLUS_PB8) == SBS_FASTMODEPLUS_PB8)) 657 #endif /* SBS_FASTMODEPLUS_PB9 */ 658 659 #define IS_SBS_HDPL(__LEVEL__) (((__LEVEL__) == SBS_HDPL_VALUE_0) || ((__LEVEL__) == SBS_HDPL_VALUE_1) || \ 660 ((__LEVEL__) == SBS_HDPL_VALUE_2) || ((__LEVEL__) == SBS_HDPL_VALUE_3)) 661 662 #define IS_SBS_OBKHDPL_SELECTION(__SELECT__) (((__SELECT__) == SBS_OBKHDPL_INCR_0) || \ 663 ((__SELECT__) == SBS_OBKHDPL_INCR_1) || \ 664 ((__SELECT__) == SBS_OBKHDPL_INCR_2) || \ 665 ((__SELECT__) == SBS_OBKHDPL_INCR_3)) 666 667 #define IS_SBS_ITEMS_ATTRIBUTES(__ITEM__) ((((__ITEM__) & SBS_CLK) == SBS_CLK) || \ 668 (((__ITEM__) & SBS_CLASSB) == SBS_CLASSB) || \ 669 (((__ITEM__) & SBS_FPU) == SBS_FPU) || \ 670 (((__ITEM__) & SBS_SMPS) == SBS_SMPS) || \ 671 (((__ITEM__) & ~(SBS_ALL)) == 0U)) 672 673 #define IS_SBS_ATTRIBUTES(__ATTRIBUTES__) (((__ATTRIBUTES__) == SBS_SEC) ||\ 674 ((__ATTRIBUTES__) == SBS_NSEC)) 675 676 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 677 678 #define IS_SBS_LOCK_ITEMS(__ITEM__) ((((__ITEM__) & SBS_MPU_NSEC) == SBS_MPU_NSEC) || \ 679 (((__ITEM__) & SBS_VTOR_NSEC) == SBS_VTOR_NSEC) || \ 680 (((__ITEM__) & SBS_SAU) == SBS_SAU) || \ 681 (((__ITEM__) & SBS_MPU_SEC) == SBS_MPU_SEC) || \ 682 (((__ITEM__) & SBS_VTOR_AIRCR_SEC) == SBS_VTOR_AIRCR_SEC) || \ 683 (((__ITEM__) & ~(SBS_LOCK_ALL)) == 0U)) 684 685 #else 686 687 #define IS_SBS_LOCK_ITEMS(__ITEM__) ((((__ITEM__) & SBS_MPU_NSEC) == SBS_MPU_NSEC) || \ 688 (((__ITEM__) & SBS_VTOR_NSEC) == SBS_VTOR_NSEC) || \ 689 (((__ITEM__) & ~(SBS_LOCK_ALL)) == 0U)) 690 691 692 #endif /* __ARM_FEATURE_CMSE */ 693 /** 694 * @} 695 */ 696 697 /** @defgroup HAL_Private_Macros HAL Private Macros 698 * @{ 699 */ 700 #define IS_TICKFREQ(FREQ) (((FREQ) == HAL_TICK_FREQ_10HZ) || \ 701 ((FREQ) == HAL_TICK_FREQ_100HZ) || \ 702 ((FREQ) == HAL_TICK_FREQ_1KHZ)) 703 /** 704 * @} 705 */ 706 /* Exported functions --------------------------------------------------------*/ 707 708 /** @addtogroup HAL_Exported_Functions 709 * @{ 710 */ 711 712 /** @addtogroup HAL_Exported_Functions_Group1 713 * @{ 714 */ 715 716 /* Initialization and de-initialization functions ******************************/ 717 HAL_StatusTypeDef HAL_Init(void); 718 HAL_StatusTypeDef HAL_DeInit(void); 719 void HAL_MspInit(void); 720 void HAL_MspDeInit(void); 721 HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority); 722 723 /** 724 * @} 725 */ 726 727 /** @addtogroup HAL_Exported_Functions_Group2 728 * @{ 729 */ 730 731 /* Peripheral Control functions ************************************************/ 732 void HAL_IncTick(void); 733 void HAL_Delay(uint32_t Delay); 734 uint32_t HAL_GetTick(void); 735 uint32_t HAL_GetTickPrio(void); 736 HAL_StatusTypeDef HAL_SetTickFreq(HAL_TickFreqTypeDef Freq); 737 HAL_TickFreqTypeDef HAL_GetTickFreq(void); 738 void HAL_SuspendTick(void); 739 void HAL_ResumeTick(void); 740 uint32_t HAL_GetHalVersion(void); 741 uint32_t HAL_GetREVID(void); 742 uint32_t HAL_GetDEVID(void); 743 uint32_t HAL_GetUIDw0(void); 744 uint32_t HAL_GetUIDw1(void); 745 uint32_t HAL_GetUIDw2(void); 746 747 /** 748 * @} 749 */ 750 751 /** @addtogroup HAL_Exported_Functions_Group3 752 * @{ 753 */ 754 755 /* DBGMCU Peripheral Control functions *****************************************/ 756 void HAL_DBGMCU_EnableDBGStopMode(void); 757 void HAL_DBGMCU_DisableDBGStopMode(void); 758 void HAL_DBGMCU_EnableDBGStandbyMode(void); 759 void HAL_DBGMCU_DisableDBGStandbyMode(void); 760 761 /** 762 * @} 763 */ 764 765 /** @addtogroup HAL_Exported_Functions_Group4 766 * @{ 767 */ 768 769 /* VREFBUF Control functions ****************************************************/ 770 #if defined(VREFBUF) 771 void HAL_VREFBUF_VoltageScalingConfig(uint32_t VoltageScaling); 772 void HAL_VREFBUF_HighImpedanceConfig(uint32_t Mode); 773 void HAL_VREFBUF_TrimmingConfig(uint32_t TrimmingValue); 774 HAL_StatusTypeDef HAL_EnableVREFBUF(void); 775 void HAL_DisableVREFBUF(void); 776 #endif /* VREFBUF */ 777 778 /** 779 * @} 780 */ 781 782 /** @addtogroup HAL_Exported_Functions_Group5 783 * @{ 784 */ 785 786 /* SBS System Configuration functions *******************************************/ 787 void HAL_SBS_ETHInterfaceSelect(uint32_t SBS_ETHInterface); 788 void HAL_SBS_EnableVddIO1CompensationCell(void); 789 void HAL_SBS_DisableVddIO1CompensationCell(void); 790 void HAL_SBS_EnableVddIO2CompensationCell(void); 791 void HAL_SBS_DisableVddIO2CompensationCell(void); 792 void HAL_SBS_VDDCompensationCodeSelect(uint32_t SBS_CompCode); 793 void HAL_SBS_VDDIOCompensationCodeSelect(uint32_t SBS_CompCode); 794 uint32_t HAL_SBS_GetVddIO1CompensationCellReadyFlag(void); 795 uint32_t HAL_SBS_GetVddIO2CompensationCellReadyFlag(void); 796 void HAL_SBS_VDDCompensationCodeConfig(uint32_t SBS_PMOSCode, uint32_t SBS_NMOSCode); 797 void HAL_SBS_VDDIOCompensationCodeConfig(uint32_t SBS_PMOSCode, uint32_t SBS_NMOSCode); 798 uint32_t HAL_SBS_GetNMOSVddCompensationValue(void); 799 uint32_t HAL_SBS_GetPMOSVddCompensationValue(void); 800 uint32_t HAL_SBS_GetNMOSVddIO2CompensationValue(void); 801 uint32_t HAL_SBS_GetPMOSVddIO2CompensationValue(void); 802 void HAL_SBS_FLASH_EnableECCNMI(void); 803 void HAL_SBS_FLASH_DisableECCNMI(void); 804 uint32_t HAL_SBS_FLASH_ECCNMI_IsDisabled(void); 805 806 /** 807 * @} 808 */ 809 810 /** @addtogroup HAL_Exported_Functions_Group6 811 * @{ 812 */ 813 814 /* SBS Boot control functions ***************************************************/ 815 void HAL_SBS_IncrementHDPLValue(void); 816 uint32_t HAL_SBS_GetHDPLValue(void); 817 818 /** 819 * @} 820 */ 821 822 /** @addtogroup HAL_Exported_Functions_Group7 823 * @{ 824 */ 825 826 /* SBS Hardware secure storage control functions ********************************/ 827 void HAL_SBS_EPOCHSelection(uint32_t Epoch_Selection); 828 uint32_t HAL_SBS_GetEPOCHSelection(void); 829 void HAL_SBS_SetOBKHDPL(uint32_t OBKHDPL_Value); 830 uint32_t HAL_SBS_GetOBKHDPL(void); 831 832 /** 833 * @} 834 */ 835 836 /** @addtogroup HAL_Exported_Functions_Group8 837 * @{ 838 */ 839 840 /* SBS Debug control functions ***************************************************/ 841 void HAL_SBS_OpenAccessPort(void); 842 void HAL_SBS_OpenDebug(void); 843 HAL_StatusTypeDef HAL_SBS_ConfigDebugLevel(uint32_t Level); 844 uint32_t HAL_SBS_GetDebugLevel(void); 845 void HAL_SBS_LockDebugConfig(void); 846 void HAL_SBS_ConfigDebugSecurity(uint32_t Security); 847 uint32_t HAL_SBS_GetDebugSecurity(void); 848 849 /** 850 * @} 851 */ 852 853 854 /** @addtogroup HAL_Exported_Functions_Group9 855 * @{ 856 */ 857 858 /* SBS Lock functions ********************************************/ 859 void HAL_SBS_Lock(uint32_t Item); 860 HAL_StatusTypeDef HAL_SBS_GetLock(uint32_t *pItem); 861 862 /** 863 * @} 864 */ 865 866 /** @addtogroup HAL_Exported_Functions_Group10 867 * @{ 868 */ 869 870 /* SBS Attributes functions ********************************************/ 871 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 872 void HAL_SBS_ConfigAttributes(uint32_t Item, uint32_t Attributes); 873 HAL_StatusTypeDef HAL_SBS_GetConfigAttributes(uint32_t Item, uint32_t *pAttributes); 874 #endif /* __ARM_FEATURE_CMSE */ 875 876 /** 877 * @} 878 */ 879 880 /** 881 * @} 882 */ 883 884 /** 885 * @} 886 */ 887 888 /** 889 * @} 890 */ 891 892 #ifdef __cplusplus 893 } 894 #endif /* __cplusplus */ 895 896 #endif /* __STM32H5xx_HAL_H */ 897
