1 /*
2  * Copyright (c) 2023, Arm Limited. All rights reserved.
3  *
4  * Licensed under the Apache License, Version 2.0 (the "License");
5  * you may not use this file except in compliance with the License.
6  * You may obtain a copy of the License at
7  *
8  *     http://www.apache.org/licenses/LICENSE-2.0
9  *
10  * Unless required by applicable law or agreed to in writing, software
11  * distributed under the License is distributed on an "AS IS" BASIS,
12  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13  * See the License for the specific language governing permissions and
14  * limitations under the License.
15  */
16 
17 #include "device_definition.h"
18 
NMI_Handler(void)19 void NMI_Handler(void)
20 {
21     sam_handle_event(&SAM_DEV_S);
22 }
23 
SAM_Critical_Sec_Fault_S_Handler(void)24 void SAM_Critical_Sec_Fault_S_Handler(void)
25 {
26     sam_handle_event(&SAM_DEV_S);
27 }
28 
SAM_Sec_Fault_S_Handler(void)29 void SAM_Sec_Fault_S_Handler(void)
30 {
31     sam_handle_event(&SAM_DEV_S);
32 }
33 
SRAM_TRAM_ECC_Err_S_Handler(void)34 void SRAM_TRAM_ECC_Err_S_Handler(void)
35 {
36     sam_handle_single_ecc_error(&SAM_DEV_S);
37 }
38 
SRAM_ECC_Partial_Write_S_Handler(void)39 void SRAM_ECC_Partial_Write_S_Handler(void)
40 {
41     sam_handle_partial_write(&SAM_DEV_S);
42 }
43