1 /*
2 * Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6 
7 /**********************************************************************************************************************
8  * File Name    : sysc_iobitmask.h
9  * Version      : 1.00
10  * Description  : IO bit mask file for sysc.
11  *********************************************************************************************************************/
12 #ifndef SYSC_IOBITMASK_H
13 #define SYSC_IOBITMASK_H
14 
15 #define R_SYSC_SYS_MSTACCCTL0_DMAC0_AWPU_Msk                    (0x00000001UL)
16 #define R_SYSC_SYS_MSTACCCTL0_DMAC0_AWPU_Pos                    (0UL)
17 #define R_SYSC_SYS_MSTACCCTL0_DMAC0_AWNS_Msk                    (0x00000002UL)
18 #define R_SYSC_SYS_MSTACCCTL0_DMAC0_AWNS_Pos                    (1UL)
19 #define R_SYSC_SYS_MSTACCCTL0_DMAC0_AWSEL_Msk                   (0x00000008UL)
20 #define R_SYSC_SYS_MSTACCCTL0_DMAC0_AWSEL_Pos                   (3UL)
21 #define R_SYSC_SYS_MSTACCCTL0_DMAC0_ARPU_Msk                    (0x00000010UL)
22 #define R_SYSC_SYS_MSTACCCTL0_DMAC0_ARPU_Pos                    (4UL)
23 #define R_SYSC_SYS_MSTACCCTL0_DMAC0_ARNS_Msk                    (0x00000020UL)
24 #define R_SYSC_SYS_MSTACCCTL0_DMAC0_ARNS_Pos                    (5UL)
25 #define R_SYSC_SYS_MSTACCCTL0_DMAC0_ARSEL_Msk                   (0x00000080UL)
26 #define R_SYSC_SYS_MSTACCCTL0_DMAC0_ARSEL_Pos                   (7UL)
27 #define R_SYSC_SYS_MSTACCCTL0_DMAC1_AWPU_Msk                    (0x00000100UL)
28 #define R_SYSC_SYS_MSTACCCTL0_DMAC1_AWPU_Pos                    (8UL)
29 #define R_SYSC_SYS_MSTACCCTL0_DMAC1_AWNS_Msk                    (0x00000200UL)
30 #define R_SYSC_SYS_MSTACCCTL0_DMAC1_AWNS_Pos                    (9UL)
31 #define R_SYSC_SYS_MSTACCCTL0_DMAC1_AWSEL_Msk                   (0x00000800UL)
32 #define R_SYSC_SYS_MSTACCCTL0_DMAC1_AWSEL_Pos                   (11UL)
33 #define R_SYSC_SYS_MSTACCCTL0_DMAC1_ARPU_Msk                    (0x00001000UL)
34 #define R_SYSC_SYS_MSTACCCTL0_DMAC1_ARPU_Pos                    (12UL)
35 #define R_SYSC_SYS_MSTACCCTL0_DMAC1_ARNS_Msk                    (0x00002000UL)
36 #define R_SYSC_SYS_MSTACCCTL0_DMAC1_ARNS_Pos                    (13UL)
37 #define R_SYSC_SYS_MSTACCCTL0_DMAC1_ARSEL_Msk                   (0x00008000UL)
38 #define R_SYSC_SYS_MSTACCCTL0_DMAC1_ARSEL_Pos                   (15UL)
39 #define R_SYSC_SYS_MSTACCCTL1_SDHI0_AWPU_Msk                    (0x00000001UL)
40 #define R_SYSC_SYS_MSTACCCTL1_SDHI0_AWPU_Pos                    (0UL)
41 #define R_SYSC_SYS_MSTACCCTL1_SDHI0_AWNS_Msk                    (0x00000002UL)
42 #define R_SYSC_SYS_MSTACCCTL1_SDHI0_AWNS_Pos                    (1UL)
43 #define R_SYSC_SYS_MSTACCCTL1_SDHI0_AWSEL_Msk                   (0x00000008UL)
44 #define R_SYSC_SYS_MSTACCCTL1_SDHI0_AWSEL_Pos                   (3UL)
45 #define R_SYSC_SYS_MSTACCCTL1_SDHI0_ARPU_Msk                    (0x00000010UL)
46 #define R_SYSC_SYS_MSTACCCTL1_SDHI0_ARPU_Pos                    (4UL)
47 #define R_SYSC_SYS_MSTACCCTL1_SDHI0_ARNS_Msk                    (0x00000020UL)
48 #define R_SYSC_SYS_MSTACCCTL1_SDHI0_ARNS_Pos                    (5UL)
49 #define R_SYSC_SYS_MSTACCCTL1_SDHI0_ARSEL_Msk                   (0x00000080UL)
50 #define R_SYSC_SYS_MSTACCCTL1_SDHI0_ARSEL_Pos                   (7UL)
51 #define R_SYSC_SYS_MSTACCCTL1_SDHI1_AWPU_Msk                    (0x00000100UL)
52 #define R_SYSC_SYS_MSTACCCTL1_SDHI1_AWPU_Pos                    (8UL)
53 #define R_SYSC_SYS_MSTACCCTL1_SDHI1_AWNS_Msk                    (0x00000200UL)
54 #define R_SYSC_SYS_MSTACCCTL1_SDHI1_AWNS_Pos                    (9UL)
55 #define R_SYSC_SYS_MSTACCCTL1_SDHI1_AWSEL_Msk                   (0x00000800UL)
56 #define R_SYSC_SYS_MSTACCCTL1_SDHI1_AWSEL_Pos                   (11UL)
57 #define R_SYSC_SYS_MSTACCCTL1_SDHI1_ARPU_Msk                    (0x00001000UL)
58 #define R_SYSC_SYS_MSTACCCTL1_SDHI1_ARPU_Pos                    (12UL)
59 #define R_SYSC_SYS_MSTACCCTL1_SDHI1_ARNS_Msk                    (0x00002000UL)
60 #define R_SYSC_SYS_MSTACCCTL1_SDHI1_ARNS_Pos                    (13UL)
61 #define R_SYSC_SYS_MSTACCCTL1_SDHI1_ARSEL_Msk                   (0x00008000UL)
62 #define R_SYSC_SYS_MSTACCCTL1_SDHI1_ARSEL_Pos                   (15UL)
63 #define R_SYSC_SYS_MSTACCCTL1_GEther0_AWPU_Msk                  (0x00010000UL)
64 #define R_SYSC_SYS_MSTACCCTL1_GEther0_AWPU_Pos                  (16UL)
65 #define R_SYSC_SYS_MSTACCCTL1_GEther0_AWNS_Msk                  (0x00020000UL)
66 #define R_SYSC_SYS_MSTACCCTL1_GEther0_AWNS_Pos                  (17UL)
67 #define R_SYSC_SYS_MSTACCCTL1_GEther0_AWSEL_Msk                 (0x00080000UL)
68 #define R_SYSC_SYS_MSTACCCTL1_GEther0_AWSEL_Pos                 (19UL)
69 #define R_SYSC_SYS_MSTACCCTL1_GEther0_ARPU_Msk                  (0x00100000UL)
70 #define R_SYSC_SYS_MSTACCCTL1_GEther0_ARPU_Pos                  (20UL)
71 #define R_SYSC_SYS_MSTACCCTL1_GEther0_ARNS_Msk                  (0x00200000UL)
72 #define R_SYSC_SYS_MSTACCCTL1_GEther0_ARNS_Pos                  (21UL)
73 #define R_SYSC_SYS_MSTACCCTL1_GEther0_ARSEL_Msk                 (0x00800000UL)
74 #define R_SYSC_SYS_MSTACCCTL1_GEther0_ARSEL_Pos                 (23UL)
75 #define R_SYSC_SYS_MSTACCCTL1_GEther1_AWPU_Msk                  (0x01000000UL)
76 #define R_SYSC_SYS_MSTACCCTL1_GEther1_AWPU_Pos                  (24UL)
77 #define R_SYSC_SYS_MSTACCCTL1_GEther1_AWNS_Msk                  (0x02000000UL)
78 #define R_SYSC_SYS_MSTACCCTL1_GEther1_AWNS_Pos                  (25UL)
79 #define R_SYSC_SYS_MSTACCCTL1_GEther1_AWSEL_Msk                 (0x08000000UL)
80 #define R_SYSC_SYS_MSTACCCTL1_GEther1_AWSEL_Pos                 (27UL)
81 #define R_SYSC_SYS_MSTACCCTL1_GEther1_ARPU_Msk                  (0x10000000UL)
82 #define R_SYSC_SYS_MSTACCCTL1_GEther1_ARPU_Pos                  (28UL)
83 #define R_SYSC_SYS_MSTACCCTL1_GEther1_ARNS_Msk                  (0x20000000UL)
84 #define R_SYSC_SYS_MSTACCCTL1_GEther1_ARNS_Pos                  (29UL)
85 #define R_SYSC_SYS_MSTACCCTL1_GEther1_ARSEL_Msk                 (0x80000000UL)
86 #define R_SYSC_SYS_MSTACCCTL1_GEther1_ARSEL_Pos                 (31UL)
87 #define R_SYSC_SYS_MSTACCCTL2_USB20H_AWPU_Msk                   (0x00000001UL)
88 #define R_SYSC_SYS_MSTACCCTL2_USB20H_AWPU_Pos                   (0UL)
89 #define R_SYSC_SYS_MSTACCCTL2_USB20H_AWNS_Msk                   (0x00000002UL)
90 #define R_SYSC_SYS_MSTACCCTL2_USB20H_AWNS_Pos                   (1UL)
91 #define R_SYSC_SYS_MSTACCCTL2_USB20H_AWSEL_Msk                  (0x00000008UL)
92 #define R_SYSC_SYS_MSTACCCTL2_USB20H_AWSEL_Pos                  (3UL)
93 #define R_SYSC_SYS_MSTACCCTL2_USB20H_ARPU_Msk                   (0x00000010UL)
94 #define R_SYSC_SYS_MSTACCCTL2_USB20H_ARPU_Pos                   (4UL)
95 #define R_SYSC_SYS_MSTACCCTL2_USB20H_ARNS_Msk                   (0x00000020UL)
96 #define R_SYSC_SYS_MSTACCCTL2_USB20H_ARNS_Pos                   (5UL)
97 #define R_SYSC_SYS_MSTACCCTL2_USB20H_ARSEL_Msk                  (0x00000080UL)
98 #define R_SYSC_SYS_MSTACCCTL2_USB20H_ARSEL_Pos                  (7UL)
99 #define R_SYSC_SYS_MSTACCCTL2_USB20D_AWPU_Msk                   (0x00000100UL)
100 #define R_SYSC_SYS_MSTACCCTL2_USB20D_AWPU_Pos                   (8UL)
101 #define R_SYSC_SYS_MSTACCCTL2_USB20D_AWNS_Msk                   (0x00000200UL)
102 #define R_SYSC_SYS_MSTACCCTL2_USB20D_AWNS_Pos                   (9UL)
103 #define R_SYSC_SYS_MSTACCCTL2_USB20D_AWSEL_Msk                  (0x00000800UL)
104 #define R_SYSC_SYS_MSTACCCTL2_USB20D_AWSEL_Pos                  (11UL)
105 #define R_SYSC_SYS_MSTACCCTL2_USB20D_ARPU_Msk                   (0x00001000UL)
106 #define R_SYSC_SYS_MSTACCCTL2_USB20D_ARPU_Pos                   (12UL)
107 #define R_SYSC_SYS_MSTACCCTL2_USB20D_ARNS_Msk                   (0x00002000UL)
108 #define R_SYSC_SYS_MSTACCCTL2_USB20D_ARNS_Pos                   (13UL)
109 #define R_SYSC_SYS_MSTACCCTL2_USB20D_ARSEL_Msk                  (0x00008000UL)
110 #define R_SYSC_SYS_MSTACCCTL2_USB20D_ARSEL_Pos                  (15UL)
111 #define R_SYSC_SYS_MSTACCCTL2_USB21H_AWPU_Msk                   (0x00010000UL)
112 #define R_SYSC_SYS_MSTACCCTL2_USB21H_AWPU_Pos                   (16UL)
113 #define R_SYSC_SYS_MSTACCCTL2_USB21H_AWNS_Msk                   (0x00020000UL)
114 #define R_SYSC_SYS_MSTACCCTL2_USB21H_AWNS_Pos                   (17UL)
115 #define R_SYSC_SYS_MSTACCCTL2_USB21H_AWSEL_Msk                  (0x00080000UL)
116 #define R_SYSC_SYS_MSTACCCTL2_USB21H_AWSEL_Pos                  (19UL)
117 #define R_SYSC_SYS_MSTACCCTL2_USB21H_ARPU_Msk                   (0x00100000UL)
118 #define R_SYSC_SYS_MSTACCCTL2_USB21H_ARPU_Pos                   (20UL)
119 #define R_SYSC_SYS_MSTACCCTL2_USB21H_ARNS_Msk                   (0x00200000UL)
120 #define R_SYSC_SYS_MSTACCCTL2_USB21H_ARNS_Pos                   (21UL)
121 #define R_SYSC_SYS_MSTACCCTL2_USB21H_ARSEL_Msk                  (0x00800000UL)
122 #define R_SYSC_SYS_MSTACCCTL2_USB21H_ARSEL_Pos                  (23UL)
123 #define R_SYSC_SYS_MSTACCCTL6_SDHI2_AWPU_Msk                    (0x00000001UL)
124 #define R_SYSC_SYS_MSTACCCTL6_SDHI2_AWPU_Pos                    (0UL)
125 #define R_SYSC_SYS_MSTACCCTL6_SDHI2_AWNS_Msk                    (0x00000002UL)
126 #define R_SYSC_SYS_MSTACCCTL6_SDHI2_AWNS_Pos                    (1UL)
127 #define R_SYSC_SYS_MSTACCCTL6_SDHI2_AWSEL_Msk                   (0x00000008UL)
128 #define R_SYSC_SYS_MSTACCCTL6_SDHI2_AWSEL_Pos                   (3UL)
129 #define R_SYSC_SYS_MSTACCCTL6_SDHI2_ARPU_Msk                    (0x00000010UL)
130 #define R_SYSC_SYS_MSTACCCTL6_SDHI2_ARPU_Pos                    (4UL)
131 #define R_SYSC_SYS_MSTACCCTL6_SDHI2_ARNS_Msk                    (0x00000020UL)
132 #define R_SYSC_SYS_MSTACCCTL6_SDHI2_ARNS_Pos                    (5UL)
133 #define R_SYSC_SYS_MSTACCCTL6_SDHI2_ARSEL_Msk                   (0x00000080UL)
134 #define R_SYSC_SYS_MSTACCCTL6_SDHI2_ARSEL_Pos                   (7UL)
135 #define R_SYSC_SYS_MSTACCCTL6_PCIE_AWPU_Msk                     (0x00000100UL)
136 #define R_SYSC_SYS_MSTACCCTL6_PCIE_AWPU_Pos                     (8UL)
137 #define R_SYSC_SYS_MSTACCCTL6_PCIE_AWNS_Msk                     (0x00000200UL)
138 #define R_SYSC_SYS_MSTACCCTL6_PCIE_AWNS_Pos                     (9UL)
139 #define R_SYSC_SYS_MSTACCCTL6_PCIE_AWSEL_Msk                    (0x00000800UL)
140 #define R_SYSC_SYS_MSTACCCTL6_PCIE_AWSEL_Pos                    (11UL)
141 #define R_SYSC_SYS_MSTACCCTL6_PCIE_ARPU_Msk                     (0x00001000UL)
142 #define R_SYSC_SYS_MSTACCCTL6_PCIE_ARPU_Pos                     (12UL)
143 #define R_SYSC_SYS_MSTACCCTL6_PCIE_ARNS_Msk                     (0x00002000UL)
144 #define R_SYSC_SYS_MSTACCCTL6_PCIE_ARNS_Pos                     (13UL)
145 #define R_SYSC_SYS_MSTACCCTL6_PCIE_ARSEL_Msk                    (0x00008000UL)
146 #define R_SYSC_SYS_MSTACCCTL6_PCIE_ARSEL_Pos                    (15UL)
147 #define R_SYSC_SYS_SLVACCCTL0_SRAM0_SL_Msk                      (0x00000003UL)
148 #define R_SYSC_SYS_SLVACCCTL0_SRAM0_SL_Pos                      (0UL)
149 #define R_SYSC_SYS_SLVACCCTL0_SRAM1_SL_Msk                      (0x0000000CUL)
150 #define R_SYSC_SYS_SLVACCCTL0_SRAM1_SL_Pos                      (2UL)
151 #define R_SYSC_SYS_SLVACCCTL0_SRAM2_SL_Msk                      (0x00000030UL)
152 #define R_SYSC_SYS_SLVACCCTL0_SRAM2_SL_Pos                      (4UL)
153 #define R_SYSC_SYS_SLVACCCTL0_SRAM3_SL_Msk                      (0x000000C0UL)
154 #define R_SYSC_SYS_SLVACCCTL0_SRAM3_SL_Pos                      (6UL)
155 #define R_SYSC_SYS_SLVACCCTL2_TZC0_SL_Msk                       (0x00000003UL)
156 #define R_SYSC_SYS_SLVACCCTL2_TZC0_SL_Pos                       (0UL)
157 #define R_SYSC_SYS_SLVACCCTL2_TZC1_SL_Msk                       (0x0000000CUL)
158 #define R_SYSC_SYS_SLVACCCTL2_TZC1_SL_Pos                       (2UL)
159 #define R_SYSC_SYS_SLVACCCTL2_TZC2_SL_Msk                       (0x00000030UL)
160 #define R_SYSC_SYS_SLVACCCTL2_TZC2_SL_Pos                       (4UL)
161 #define R_SYSC_SYS_SLVACCCTL2_TZC3_SL_Msk                       (0x000000C0UL)
162 #define R_SYSC_SYS_SLVACCCTL2_TZC3_SL_Pos                       (6UL)
163 #define R_SYSC_SYS_SLVACCCTL2_TZC5_SL_Msk                       (0x00000C00UL)
164 #define R_SYSC_SYS_SLVACCCTL2_TZC5_SL_Pos                       (10UL)
165 #define R_SYSC_SYS_SLVACCCTL2_TZC6_SL_Msk                       (0x00003000UL)
166 #define R_SYSC_SYS_SLVACCCTL2_TZC6_SL_Pos                       (12UL)
167 #define R_SYSC_SYS_SLVACCCTL3_CST_SL_Msk                        (0x00000003UL)
168 #define R_SYSC_SYS_SLVACCCTL3_CST_SL_Pos                        (0UL)
169 #define R_SYSC_SYS_SLVACCCTL3_CPG_SL_Msk                        (0x0000000CUL)
170 #define R_SYSC_SYS_SLVACCCTL3_CPG_SL_Pos                        (2UL)
171 #define R_SYSC_SYS_SLVACCCTL3_SYSC_SL_Msk                       (0x00000030UL)
172 #define R_SYSC_SYS_SLVACCCTL3_SYSC_SL_Pos                       (4UL)
173 #define R_SYSC_SYS_SLVACCCTL3_SYC_SL_Msk                        (0x000000C0UL)
174 #define R_SYSC_SYS_SLVACCCTL3_SYC_SL_Pos                        (6UL)
175 #define R_SYSC_SYS_SLVACCCTL3_GIC_SL_Msk                        (0x00000300UL)
176 #define R_SYSC_SYS_SLVACCCTL3_GIC_SL_Pos                        (8UL)
177 #define R_SYSC_SYS_SLVACCCTL3_IA55IM33_SL_Msk                   (0x00000C00UL)
178 #define R_SYSC_SYS_SLVACCCTL3_IA55IM33_SL_Pos                   (10UL)
179 #define R_SYSC_SYS_SLVACCCTL3_GPIO_SL_Msk                       (0x00003000UL)
180 #define R_SYSC_SYS_SLVACCCTL3_GPIO_SL_Pos                       (12UL)
181 #define R_SYSC_SYS_SLVACCCTL3_MHU_SL_Msk                        (0x0000C000UL)
182 #define R_SYSC_SYS_SLVACCCTL3_MHU_SL_Pos                        (14UL)
183 #define R_SYSC_SYS_SLVACCCTL4_DMAC0_SL_Msk                      (0x00000003UL)
184 #define R_SYSC_SYS_SLVACCCTL4_DMAC0_SL_Pos                      (0UL)
185 #define R_SYSC_SYS_SLVACCCTL4_DMAC1_SL_Msk                      (0x0000000CUL)
186 #define R_SYSC_SYS_SLVACCCTL4_DMAC1_SL_Pos                      (2UL)
187 #define R_SYSC_SYS_SLVACCCTL4_OSTM0_SL_Msk                      (0x00000030UL)
188 #define R_SYSC_SYS_SLVACCCTL4_OSTM0_SL_Pos                      (4UL)
189 #define R_SYSC_SYS_SLVACCCTL4_OSTM1_SL_Msk                      (0x000000C0UL)
190 #define R_SYSC_SYS_SLVACCCTL4_OSTM1_SL_Pos                      (6UL)
191 #define R_SYSC_SYS_SLVACCCTL4_OSTM2_SL_Msk                      (0x00000300UL)
192 #define R_SYSC_SYS_SLVACCCTL4_OSTM2_SL_Pos                      (8UL)
193 #define R_SYSC_SYS_SLVACCCTL4_OSTM3_SL_Msk                      (0x00000C00UL)
194 #define R_SYSC_SYS_SLVACCCTL4_OSTM3_SL_Pos                      (10UL)
195 #define R_SYSC_SYS_SLVACCCTL4_OSTM4_SL_Msk                      (0x00003000UL)
196 #define R_SYSC_SYS_SLVACCCTL4_OSTM4_SL_Pos                      (12UL)
197 #define R_SYSC_SYS_SLVACCCTL4_OSTM5_SL_Msk                      (0x0000C000UL)
198 #define R_SYSC_SYS_SLVACCCTL4_OSTM5_SL_Pos                      (14UL)
199 #define R_SYSC_SYS_SLVACCCTL4_OSTM6_SL_Msk                      (0x00030000UL)
200 #define R_SYSC_SYS_SLVACCCTL4_OSTM6_SL_Pos                      (16UL)
201 #define R_SYSC_SYS_SLVACCCTL4_OSTM7_SL_Msk                      (0x000C0000UL)
202 #define R_SYSC_SYS_SLVACCCTL4_OSTM7_SL_Pos                      (18UL)
203 #define R_SYSC_SYS_SLVACCCTL4_WDT0_SL_Msk                       (0x00300000UL)
204 #define R_SYSC_SYS_SLVACCCTL4_WDT0_SL_Pos                       (20UL)
205 #define R_SYSC_SYS_SLVACCCTL4_WDT1_SL_Msk                       (0x00C00000UL)
206 #define R_SYSC_SYS_SLVACCCTL4_WDT1_SL_Pos                       (22UL)
207 #define R_SYSC_SYS_SLVACCCTL4_WDT2_SL_Msk                       (0x03000000UL)
208 #define R_SYSC_SYS_SLVACCCTL4_WDT2_SL_Pos                       (24UL)
209 #define R_SYSC_SYS_SLVACCCTL4_RTC_SL_Msk                        (0x30000000UL)
210 #define R_SYSC_SYS_SLVACCCTL4_RTC_SL_Pos                        (28UL)
211 #define R_SYSC_SYS_SLVACCCTL5_MTU3A_SL_Msk                      (0x00000003UL)
212 #define R_SYSC_SYS_SLVACCCTL5_MTU3A_SL_Pos                      (0UL)
213 #define R_SYSC_SYS_SLVACCCTL5_POE3_SL_Msk                       (0x0000000CUL)
214 #define R_SYSC_SYS_SLVACCCTL5_POE3_SL_Pos                       (2UL)
215 #define R_SYSC_SYS_SLVACCCTL5_GPT_SL_Msk                        (0x00000030UL)
216 #define R_SYSC_SYS_SLVACCCTL5_GPT_SL_Pos                        (4UL)
217 #define R_SYSC_SYS_SLVACCCTL5_POEG_SL_Msk                       (0x000000C0UL)
218 #define R_SYSC_SYS_SLVACCCTL5_POEG_SL_Pos                       (6UL)
219 #define R_SYSC_SYS_SLVACCCTL5_DDR_SL_Msk                        (0x00000300UL)
220 #define R_SYSC_SYS_SLVACCCTL5_DDR_SL_Pos                        (8UL)
221 #define R_SYSC_SYS_SLVACCCTL5_XSPI_SL_Msk                       (0x00000C00UL)
222 #define R_SYSC_SYS_SLVACCCTL5_XSPI_SL_Pos                       (10UL)
223 #define R_SYSC_SYS_SLVACCCTL5_OCTA_SL_Msk                       (0x00003000UL)
224 #define R_SYSC_SYS_SLVACCCTL5_OCTA_SL_Pos                       (12UL)
225 #define R_SYSC_SYS_SLVACCCTL6_USBT_SL_Msk                       (0x00000003UL)
226 #define R_SYSC_SYS_SLVACCCTL6_USBT_SL_Pos                       (0UL)
227 #define R_SYSC_SYS_SLVACCCTL6_USBT20_SL_Msk                     (0x0000000CUL)
228 #define R_SYSC_SYS_SLVACCCTL6_USBT20_SL_Pos                     (2UL)
229 #define R_SYSC_SYS_SLVACCCTL6_USBT21_SL_Msk                     (0x00000030UL)
230 #define R_SYSC_SYS_SLVACCCTL6_USBT21_SL_Pos                     (4UL)
231 #define R_SYSC_SYS_SLVACCCTL6_SDHI0_SL_Msk                      (0x000000C0UL)
232 #define R_SYSC_SYS_SLVACCCTL6_SDHI0_SL_Pos                      (6UL)
233 #define R_SYSC_SYS_SLVACCCTL6_SDHI1_SL_Msk                      (0x00000300UL)
234 #define R_SYSC_SYS_SLVACCCTL6_SDHI1_SL_Pos                      (8UL)
235 #define R_SYSC_SYS_SLVACCCTL6_SDHI2_SL_Msk                      (0x00000C00UL)
236 #define R_SYSC_SYS_SLVACCCTL6_SDHI2_SL_Pos                      (10UL)
237 #define R_SYSC_SYS_SLVACCCTL6_ETH0_SL_Msk                       (0x00003000UL)
238 #define R_SYSC_SYS_SLVACCCTL6_ETH0_SL_Pos                       (12UL)
239 #define R_SYSC_SYS_SLVACCCTL6_ETH1_SL_Msk                       (0x0000C000UL)
240 #define R_SYSC_SYS_SLVACCCTL6_ETH1_SL_Pos                       (14UL)
241 #define R_SYSC_SYS_SLVACCCTL6_PCIE_SL_Msk                       (0x00030000UL)
242 #define R_SYSC_SYS_SLVACCCTL6_PCIE_SL_Pos                       (16UL)
243 #define R_SYSC_SYS_SLVACCCTL7_I2C0_SL_Msk                       (0x00000003UL)
244 #define R_SYSC_SYS_SLVACCCTL7_I2C0_SL_Pos                       (0UL)
245 #define R_SYSC_SYS_SLVACCCTL7_I2C1_SL_Msk                       (0x0000000CUL)
246 #define R_SYSC_SYS_SLVACCCTL7_I2C1_SL_Pos                       (2UL)
247 #define R_SYSC_SYS_SLVACCCTL7_I2C2_SL_Msk                       (0x00000030UL)
248 #define R_SYSC_SYS_SLVACCCTL7_I2C2_SL_Pos                       (4UL)
249 #define R_SYSC_SYS_SLVACCCTL7_I2C3_SL_Msk                       (0x000000C0UL)
250 #define R_SYSC_SYS_SLVACCCTL7_I2C3_SL_Pos                       (6UL)
251 #define R_SYSC_SYS_SLVACCCTL7_I3C_SL_Msk                        (0x00000300UL)
252 #define R_SYSC_SYS_SLVACCCTL7_I3C_SL_Pos                        (8UL)
253 #define R_SYSC_SYS_SLVACCCTL7_CANFD_SL_Msk                      (0x00000C00UL)
254 #define R_SYSC_SYS_SLVACCCTL7_CANFD_SL_Pos                      (10UL)
255 #define R_SYSC_SYS_SLVACCCTL7_RSPI0_SL_Msk                      (0x00003000UL)
256 #define R_SYSC_SYS_SLVACCCTL7_RSPI0_SL_Pos                      (12UL)
257 #define R_SYSC_SYS_SLVACCCTL7_RSPI1_SL_Msk                      (0x0000C000UL)
258 #define R_SYSC_SYS_SLVACCCTL7_RSPI1_SL_Pos                      (14UL)
259 #define R_SYSC_SYS_SLVACCCTL7_RSPI2_SL_Msk                      (0x00030000UL)
260 #define R_SYSC_SYS_SLVACCCTL7_RSPI2_SL_Pos                      (16UL)
261 #define R_SYSC_SYS_SLVACCCTL7_RSPI3_SL_Msk                      (0x000C0000UL)
262 #define R_SYSC_SYS_SLVACCCTL7_RSPI3_SL_Pos                      (18UL)
263 #define R_SYSC_SYS_SLVACCCTL7_RSPI4_SL_Msk                      (0x00300000UL)
264 #define R_SYSC_SYS_SLVACCCTL7_RSPI4_SL_Pos                      (20UL)
265 #define R_SYSC_SYS_SLVACCCTL8_SCIF0_SL_Msk                      (0x00000003UL)
266 #define R_SYSC_SYS_SLVACCCTL8_SCIF0_SL_Pos                      (0UL)
267 #define R_SYSC_SYS_SLVACCCTL8_SCIF1_SL_Msk                      (0x0000000CUL)
268 #define R_SYSC_SYS_SLVACCCTL8_SCIF1_SL_Pos                      (2UL)
269 #define R_SYSC_SYS_SLVACCCTL8_SCIF2_SL_Msk                      (0x00000030UL)
270 #define R_SYSC_SYS_SLVACCCTL8_SCIF2_SL_Pos                      (4UL)
271 #define R_SYSC_SYS_SLVACCCTL8_SCIF3_SL_Msk                      (0x000000C0UL)
272 #define R_SYSC_SYS_SLVACCCTL8_SCIF3_SL_Pos                      (6UL)
273 #define R_SYSC_SYS_SLVACCCTL8_SCIF4_SL_Msk                      (0x00000300UL)
274 #define R_SYSC_SYS_SLVACCCTL8_SCIF4_SL_Pos                      (8UL)
275 #define R_SYSC_SYS_SLVACCCTL8_SCIF5_SL_Msk                      (0x00000C00UL)
276 #define R_SYSC_SYS_SLVACCCTL8_SCIF5_SL_Pos                      (10UL)
277 #define R_SYSC_SYS_SLVACCCTL8_SCI0_SL_Msk                       (0x00003000UL)
278 #define R_SYSC_SYS_SLVACCCTL8_SCI0_SL_Pos                       (12UL)
279 #define R_SYSC_SYS_SLVACCCTL8_SCI1_SL_Msk                       (0x0000C000UL)
280 #define R_SYSC_SYS_SLVACCCTL8_SCI1_SL_Pos                       (14UL)
281 #define R_SYSC_SYS_SLVACCCTL8_IRDA_SL_Msk                       (0x00030000UL)
282 #define R_SYSC_SYS_SLVACCCTL8_IRDA_SL_Pos                       (16UL)
283 #define R_SYSC_SYS_SLVACCCTL9_SSIF0_SL_Msk                      (0x00000003UL)
284 #define R_SYSC_SYS_SLVACCCTL9_SSIF0_SL_Pos                      (0UL)
285 #define R_SYSC_SYS_SLVACCCTL9_SSIF1_SL_Msk                      (0x0000000CUL)
286 #define R_SYSC_SYS_SLVACCCTL9_SSIF1_SL_Pos                      (2UL)
287 #define R_SYSC_SYS_SLVACCCTL9_SSIF2_SL_Msk                      (0x00000030UL)
288 #define R_SYSC_SYS_SLVACCCTL9_SSIF2_SL_Pos                      (4UL)
289 #define R_SYSC_SYS_SLVACCCTL9_SSIF3_SL_Msk                      (0x000000C0UL)
290 #define R_SYSC_SYS_SLVACCCTL9_SSIF3_SL_Pos                      (6UL)
291 #define R_SYSC_SYS_SLVACCCTL9_SRC_SL_Msk                        (0x00000300UL)
292 #define R_SYSC_SYS_SLVACCCTL9_SRC_SL_Pos                        (8UL)
293 #define R_SYSC_SYS_SLVACCCTL9_SPDIF_SL_Msk                      (0x00000C00UL)
294 #define R_SYSC_SYS_SLVACCCTL9_SPDIF_SL_Pos                      (10UL)
295 #define R_SYSC_SYS_SLVACCCTL9_PDM_SL_Msk                        (0x00003000UL)
296 #define R_SYSC_SYS_SLVACCCTL9_PDM_SL_Pos                        (12UL)
297 #define R_SYSC_SYS_SLVACCCTL10_ADC_SL_Msk                       (0x00000003UL)
298 #define R_SYSC_SYS_SLVACCCTL10_ADC_SL_Pos                       (0UL)
299 #define R_SYSC_SYS_SLVACCCTL10_TSU_SL_Msk                       (0x0000000CUL)
300 #define R_SYSC_SYS_SLVACCCTL10_TSU_SL_Pos                       (2UL)
301 #define R_SYSC_SYS_SLVACCCTL11_OTP_SL_Msk                       (0x0000000CUL)
302 #define R_SYSC_SYS_SLVACCCTL11_OTP_SL_Pos                       (2UL)
303 #define R_SYSC_SYS_SLVACCCTL11_VBATT_SL_Msk                     (0x00000C00UL)
304 #define R_SYSC_SYS_SLVACCCTL11_VBATT_SL_Pos                     (10UL)
305 #define R_SYSC_SYS_SLVACCCTL12_CA55_SL_Msk                      (0x00000003UL)
306 #define R_SYSC_SYS_SLVACCCTL12_CA55_SL_Pos                      (0UL)
307 #define R_SYSC_SYS_SLVACCCTL12_CM33_SL_Msk                      (0x0000000CUL)
308 #define R_SYSC_SYS_SLVACCCTL12_CM33_SL_Pos                      (2UL)
309 #define R_SYSC_SYS_SLVACCCTL12_CM33FPU_SL_Msk                   (0x00000030UL)
310 #define R_SYSC_SYS_SLVACCCTL12_CM33FPU_SL_Pos                   (4UL)
311 #define R_SYSC_SYS_SLVACCCTL14_LSI_SL_Msk                       (0x00000003UL)
312 #define R_SYSC_SYS_SLVACCCTL14_LSI_SL_Pos                       (0UL)
313 #define R_SYSC_SYS_SLVACCCTL16_AOF_SL_Msk                       (0x00000003UL)
314 #define R_SYSC_SYS_SLVACCCTL16_AOF_SL_Pos                       (0UL)
315 #define R_SYSC_SYS_SLVACCCTL17_LP_SL_Msk                        (0x00000003UL)
316 #define R_SYSC_SYS_SLVACCCTL17_LP_SL_Pos                        (0UL)
317 #define R_SYSC_SYS_SLVACCCTL18_GPREG_SL_Msk                     (0x00000003UL)
318 #define R_SYSC_SYS_SLVACCCTL18_GPREG_SL_Pos                     (0UL)
319 #define R_SYSC_SYS_SLVACCCTL20_IPCONT_SL_Msk                    (0x00000003UL)
320 #define R_SYSC_SYS_SLVACCCTL20_IPCONT_SL_Pos                    (0UL)
321 #define R_SYSC_SYS_RAM0_ECC_VECCEN_Msk                          (0x00000001UL)
322 #define R_SYSC_SYS_RAM0_ECC_VECCEN_Pos                          (0UL)
323 #define R_SYSC_SYS_RAM0_EN_VCEN_Msk                             (0x00000001UL)
324 #define R_SYSC_SYS_RAM0_EN_VCEN_Pos                             (0UL)
325 #define R_SYSC_SYS_RAM0_EN_VLWEN_Msk                            (0x00000002UL)
326 #define R_SYSC_SYS_RAM0_EN_VLWEN_Pos                            (1UL)
327 #define R_SYSC_SYS_RAM1_ECC_VECCEN_Msk                          (0x00000001UL)
328 #define R_SYSC_SYS_RAM1_ECC_VECCEN_Pos                          (0UL)
329 #define R_SYSC_SYS_RAM1_EN_VCEN_Msk                             (0x00000001UL)
330 #define R_SYSC_SYS_RAM1_EN_VCEN_Pos                             (0UL)
331 #define R_SYSC_SYS_RAM1_EN_VLWEN_Msk                            (0x00000002UL)
332 #define R_SYSC_SYS_RAM1_EN_VLWEN_Pos                            (1UL)
333 #define R_SYSC_SYS_RAM2_ECC_VECCEN_Msk                          (0x00000001UL)
334 #define R_SYSC_SYS_RAM2_ECC_VECCEN_Pos                          (0UL)
335 #define R_SYSC_SYS_RAM2_EN_VCEN_Msk                             (0x00000001UL)
336 #define R_SYSC_SYS_RAM2_EN_VCEN_Pos                             (0UL)
337 #define R_SYSC_SYS_RAM2_EN_VLWEN_Msk                            (0x00000002UL)
338 #define R_SYSC_SYS_RAM2_EN_VLWEN_Pos                            (1UL)
339 #define R_SYSC_SYS_RAM3_ECC_VECCEN_Msk                          (0x00000001UL)
340 #define R_SYSC_SYS_RAM3_ECC_VECCEN_Pos                          (0UL)
341 #define R_SYSC_SYS_RAM3_EN_VCEN_Msk                             (0x00000001UL)
342 #define R_SYSC_SYS_RAM3_EN_VCEN_Pos                             (0UL)
343 #define R_SYSC_SYS_RAM3_EN_VLWEN_Msk                            (0x00000002UL)
344 #define R_SYSC_SYS_RAM3_EN_VLWEN_Pos                            (1UL)
345 #define R_SYSC_SYS_WDT0_CTRL_WDTSTOP_Msk                        (0x00000001UL)
346 #define R_SYSC_SYS_WDT0_CTRL_WDTSTOP_Pos                        (0UL)
347 #define R_SYSC_SYS_WDT0_CTRL_WDTSTOPMASK_Msk                    (0x00010000UL)
348 #define R_SYSC_SYS_WDT0_CTRL_WDTSTOPMASK_Pos                    (16UL)
349 #define R_SYSC_SYS_WDT1_CTRL_WDTSTOP_Msk                        (0x00000001UL)
350 #define R_SYSC_SYS_WDT1_CTRL_WDTSTOP_Pos                        (0UL)
351 #define R_SYSC_SYS_WDT1_CTRL_WDTSTOPMASK_Msk                    (0x00010000UL)
352 #define R_SYSC_SYS_WDT1_CTRL_WDTSTOPMASK_Pos                    (16UL)
353 #define R_SYSC_SYS_WDT2_CTRL_WDTSTOP_Msk                        (0x00000001UL)
354 #define R_SYSC_SYS_WDT2_CTRL_WDTSTOP_Pos                        (0UL)
355 #define R_SYSC_SYS_WDT2_CTRL_WDTSTOPMASK_Msk                    (0x00010000UL)
356 #define R_SYSC_SYS_WDT2_CTRL_WDTSTOPMASK_Pos                    (16UL)
357 #define R_SYSC_SYS_DDR_MCAR_CTRL_MCAR_CTRL_Msk                  (0x00010000UL)
358 #define R_SYSC_SYS_DDR_MCAR_CTRL_MCAR_CTRL_Pos                  (16UL)
359 #define R_SYSC_SYS_XSPI_MAP_STAADD_CS0_MAP_STAADD_CS0_Msk       (0xFFFFFFFFUL)
360 #define R_SYSC_SYS_XSPI_MAP_STAADD_CS0_MAP_STAADD_CS0_Pos       (0UL)
361 #define R_SYSC_SYS_XSPI_MAP_ENDADD_CS0_MAP_ENDADD_CS0_Msk       (0xFFFFFFFFUL)
362 #define R_SYSC_SYS_XSPI_MAP_ENDADD_CS0_MAP_ENDADD_CS0_Pos       (0UL)
363 #define R_SYSC_SYS_XSPI_MAP_STAADD_CS1_MAP_STAADD_CS0_Msk       (0x00000001UL)
364 #define R_SYSC_SYS_XSPI_MAP_STAADD_CS1_MAP_STAADD_CS0_Pos       (0UL)
365 #define R_SYSC_SYS_XSPI_MAP_STAADD_CS1_MAP_STAADD_CS1_Msk       (0xFFFFFFFEUL)
366 #define R_SYSC_SYS_XSPI_MAP_STAADD_CS1_MAP_STAADD_CS1_Pos       (1UL)
367 #define R_SYSC_SYS_XSPI_MAP_ENDADD_CS1_MAP_ENDADD_CS0_Msk       (0x00000001UL)
368 #define R_SYSC_SYS_XSPI_MAP_ENDADD_CS1_MAP_ENDADD_CS0_Pos       (0UL)
369 #define R_SYSC_SYS_XSPI_MAP_ENDADD_CS1_MAP_ENDADD_CS1_Msk       (0xFFFFFFFEUL)
370 #define R_SYSC_SYS_XSPI_MAP_ENDADD_CS1_MAP_ENDADD_CS1_Pos       (1UL)
371 #define R_SYSC_SYS_GETH0_CFG_FEC_GIGA_ENABLE_Msk                (0x01000000UL)
372 #define R_SYSC_SYS_GETH0_CFG_FEC_GIGA_ENABLE_Pos                (24UL)
373 #define R_SYSC_SYS_GETH1_CFG_FEC_GIGA_ENABLE_Msk                (0x01000000UL)
374 #define R_SYSC_SYS_GETH1_CFG_FEC_GIGA_ENABLE_Pos                (24UL)
375 #define R_SYSC_SYS_PCIE_CFG_ALLOW_ENTER_L1_Msk                  (0x00000100UL)
376 #define R_SYSC_SYS_PCIE_CFG_ALLOW_ENTER_L1_Pos                  (8UL)
377 #define R_SYSC_SYS_PCIE_MON_PMU_POWEROFF_Msk                    (0x00000001UL)
378 #define R_SYSC_SYS_PCIE_MON_PMU_POWEROFF_Pos                    (0UL)
379 #define R_SYSC_SYS_PCIE_MON_CLKL1PM_REQ_Msk                     (0x00000002UL)
380 #define R_SYSC_SYS_PCIE_MON_CLKL1PM_REQ_Pos                     (1UL)
381 #define R_SYSC_SYS_PCIE_MON_D_STATE_OUT_F0_Msk                  (0x00000030UL)
382 #define R_SYSC_SYS_PCIE_MON_D_STATE_OUT_F0_Pos                  (4UL)
383 #define R_SYSC_SYS_PCIE_ERR_MON_ERR_COR_DETECTED_F0_Msk         (0x00000001UL)
384 #define R_SYSC_SYS_PCIE_ERR_MON_ERR_COR_DETECTED_F0_Pos         (0UL)
385 #define R_SYSC_SYS_PCIE_ERR_MON_ERR_NONFATAL_DETECTED_F0_Msk    (0x00000002UL)
386 #define R_SYSC_SYS_PCIE_ERR_MON_ERR_NONFATAL_DETECTED_F0_Pos    (1UL)
387 #define R_SYSC_SYS_PCIE_ERR_MON_ERR_FATAL_DETECTED_F0_Msk       (0x00000004UL)
388 #define R_SYSC_SYS_PCIE_ERR_MON_ERR_FATAL_DETECTED_F0_Pos       (2UL)
389 #define R_SYSC_SYS_PCIE_PHY_MODE_RXTERMINATION_Msk              (0x00000001UL)
390 #define R_SYSC_SYS_PCIE_PHY_MODE_RXTERMINATION_Pos              (0UL)
391 #define R_SYSC_SYS_I2C0_CFG_af_bypass_Msk                       (0x00000001UL)
392 #define R_SYSC_SYS_I2C0_CFG_af_bypass_Pos                       (0UL)
393 #define R_SYSC_SYS_I2C1_CFG_af_bypass_Msk                       (0x00000001UL)
394 #define R_SYSC_SYS_I2C1_CFG_af_bypass_Pos                       (0UL)
395 #define R_SYSC_SYS_I2C2_CFG_af_bypass_Msk                       (0x00000001UL)
396 #define R_SYSC_SYS_I2C2_CFG_af_bypass_Pos                       (0UL)
397 #define R_SYSC_SYS_I2C3_CFG_af_bypass_Msk                       (0x00000001UL)
398 #define R_SYSC_SYS_I2C3_CFG_af_bypass_Pos                       (0UL)
399 #define R_SYSC_SYS_I3C_CFG_af_bypass_Msk                        (0x00000001UL)
400 #define R_SYSC_SYS_I3C_CFG_af_bypass_Pos                        (0UL)
401 #define R_SYSC_SYS_CA55_CFG_RVAL0_RVBARADDRL0_Msk               (0xFFFFFFFCUL)
402 #define R_SYSC_SYS_CA55_CFG_RVAL0_RVBARADDRL0_Pos               (2UL)
403 #define R_SYSC_SYS_CA55_CFG_RVAH0_RVBARADDRH0_Msk               (0x000000FFUL)
404 #define R_SYSC_SYS_CA55_CFG_RVAH0_RVBARADDRH0_Pos               (0UL)
405 #define R_SYSC_SYS_CM33_CFG0_CONFIGSSYSTICK_Msk                 (0x03FFFFFFUL)
406 #define R_SYSC_SYS_CM33_CFG0_CONFIGSSYSTICK_Pos                 (0UL)
407 #define R_SYSC_SYS_CM33_CFG1_CONFIGNSSYSTICK_Msk                (0x03FFFFFFUL)
408 #define R_SYSC_SYS_CM33_CFG1_CONFIGNSSYSTICK_Pos                (0UL)
409 #define R_SYSC_SYS_CM33_CFG2_INITSVTOR_Msk                      (0xFFFFFF80UL)
410 #define R_SYSC_SYS_CM33_CFG2_INITSVTOR_Pos                      (7UL)
411 #define R_SYSC_SYS_CM33_CFG3_INITNSVTOR_Msk                     (0xFFFFFF80UL)
412 #define R_SYSC_SYS_CM33_CFG3_INITNSVTOR_Pos                     (7UL)
413 #define R_SYSC_SYS_CM33_LOCK_LOCKSVTAIRCR_Msk                   (0x00000001UL)
414 #define R_SYSC_SYS_CM33_LOCK_LOCKSVTAIRCR_Pos                   (0UL)
415 #define R_SYSC_SYS_CM33_LOCK_LOCKNSVTOR_Msk                     (0x00000002UL)
416 #define R_SYSC_SYS_CM33_LOCK_LOCKNSVTOR_Pos                     (1UL)
417 #define R_SYSC_SYS_CM33FPU_CFG0_CONFIGSSYSTICK_Msk              (0x03FFFFFFUL)
418 #define R_SYSC_SYS_CM33FPU_CFG0_CONFIGSSYSTICK_Pos              (0UL)
419 #define R_SYSC_SYS_CM33FPU_CFG1_CONFIGNSSYSTICK_Msk             (0x03FFFFFFUL)
420 #define R_SYSC_SYS_CM33FPU_CFG1_CONFIGNSSYSTICK_Pos             (0UL)
421 #define R_SYSC_SYS_CM33FPU_CFG2_INITSVTOR_Msk                   (0xFFFFFFC0UL)
422 #define R_SYSC_SYS_CM33FPU_CFG2_INITSVTOR_Pos                   (6UL)
423 #define R_SYSC_SYS_CM33FPU_CFG3_INITNSVTOR_Msk                  (0xFFFFFFC0UL)
424 #define R_SYSC_SYS_CM33FPU_CFG3_INITNSVTOR_Pos                  (6UL)
425 #define R_SYSC_SYS_CM33FPU_LOCK_LOCKSVTAIRCR_Msk                (0x00000001UL)
426 #define R_SYSC_SYS_CM33FPU_LOCK_LOCKSVTAIRCR_Pos                (0UL)
427 #define R_SYSC_SYS_CM33FPU_LOCK_LOCKNSVTOR_Msk                  (0x00000002UL)
428 #define R_SYSC_SYS_CM33FPU_LOCK_LOCKNSVTOR_Pos                  (1UL)
429 #define R_SYSC_SYS_LSI_MODE_STAT_BOOTCPUSEL_Msk                 (0x00000001UL)
430 #define R_SYSC_SYS_LSI_MODE_STAT_BOOTCPUSEL_Pos                 (0UL)
431 #define R_SYSC_SYS_LSI_MODE_STAT_MD_BOOT_Msk                    (0x00000070UL)
432 #define R_SYSC_SYS_LSI_MODE_STAT_MD_BOOT_Pos                    (4UL)
433 #define R_SYSC_SYS_LSI_MODE_STAT_DEBUGEN_Msk                    (0x00000200UL)
434 #define R_SYSC_SYS_LSI_MODE_STAT_DEBUGEN_Pos                    (9UL)
435 #define R_SYSC_SYS_LSI_MODE_STAT_MD_CLKS_Msk                    (0x00001000UL)
436 #define R_SYSC_SYS_LSI_MODE_STAT_MD_CLKS_Pos                    (12UL)
437 #define R_SYSC_SYS_LSI_MODE_STAT_MD_BYPASS_Msk                  (0x00002000UL)
438 #define R_SYSC_SYS_LSI_MODE_STAT_MD_BYPASS_Pos                  (13UL)
439 #define R_SYSC_SYS_LSI_MODE_STAT_SEC_EN_Msk                     (0x00010000UL)
440 #define R_SYSC_SYS_LSI_MODE_STAT_SEC_EN_Pos                     (16UL)
441 #define R_SYSC_SYS_AOF0_OFS00_SXSDHI_0_Msk                      (0x0000000FUL)
442 #define R_SYSC_SYS_AOF0_OFS00_SXSDHI_0_Pos                      (0UL)
443 #define R_SYSC_SYS_AOF0_OFS01_SXSDHI_0_Msk                      (0x000000F0UL)
444 #define R_SYSC_SYS_AOF0_OFS01_SXSDHI_0_Pos                      (4UL)
445 #define R_SYSC_SYS_AOF0_OFS10_SXSDHI_0_Msk                      (0x00000F00UL)
446 #define R_SYSC_SYS_AOF0_OFS10_SXSDHI_0_Pos                      (8UL)
447 #define R_SYSC_SYS_AOF0_OFS11_SXSDHI_0_Msk                      (0x0000F000UL)
448 #define R_SYSC_SYS_AOF0_OFS11_SXSDHI_0_Pos                      (12UL)
449 #define R_SYSC_SYS_AOF0_OFS00_SXSDHI_1_Msk                      (0x000F0000UL)
450 #define R_SYSC_SYS_AOF0_OFS00_SXSDHI_1_Pos                      (16UL)
451 #define R_SYSC_SYS_AOF0_OFS01_SXSDHI_1_Msk                      (0x00F00000UL)
452 #define R_SYSC_SYS_AOF0_OFS01_SXSDHI_1_Pos                      (20UL)
453 #define R_SYSC_SYS_AOF0_OFS10_SXSDHI_1_Msk                      (0x0F000000UL)
454 #define R_SYSC_SYS_AOF0_OFS10_SXSDHI_1_Pos                      (24UL)
455 #define R_SYSC_SYS_AOF0_OFS11_SXSDHI_1_Msk                      (0xF0000000UL)
456 #define R_SYSC_SYS_AOF0_OFS11_SXSDHI_1_Pos                      (28UL)
457 #define R_SYSC_SYS_AOF1_OFS00_SXGIGE_0_Msk                      (0x0000000FUL)
458 #define R_SYSC_SYS_AOF1_OFS00_SXGIGE_0_Pos                      (0UL)
459 #define R_SYSC_SYS_AOF1_OFS01_SXGIGE_0_Msk                      (0x000000F0UL)
460 #define R_SYSC_SYS_AOF1_OFS01_SXGIGE_0_Pos                      (4UL)
461 #define R_SYSC_SYS_AOF1_OFS10_SXGIGE_0_Msk                      (0x00000F00UL)
462 #define R_SYSC_SYS_AOF1_OFS10_SXGIGE_0_Pos                      (8UL)
463 #define R_SYSC_SYS_AOF1_OFS11_SXGIGE_0_Msk                      (0x0000F000UL)
464 #define R_SYSC_SYS_AOF1_OFS11_SXGIGE_0_Pos                      (12UL)
465 #define R_SYSC_SYS_AOF1_OFS00_SXGIGE_1_Msk                      (0x000F0000UL)
466 #define R_SYSC_SYS_AOF1_OFS00_SXGIGE_1_Pos                      (16UL)
467 #define R_SYSC_SYS_AOF1_OFS01_SXGIGE_1_Msk                      (0x00F00000UL)
468 #define R_SYSC_SYS_AOF1_OFS01_SXGIGE_1_Pos                      (20UL)
469 #define R_SYSC_SYS_AOF1_OFS10_SXGIGE_1_Msk                      (0x0F000000UL)
470 #define R_SYSC_SYS_AOF1_OFS10_SXGIGE_1_Pos                      (24UL)
471 #define R_SYSC_SYS_AOF1_OFS11_SXGIGE_1_Msk                      (0xF0000000UL)
472 #define R_SYSC_SYS_AOF1_OFS11_SXGIGE_1_Pos                      (28UL)
473 #define R_SYSC_SYS_AOF2_OFS00_SXUSB2_0_H_Msk                    (0x0000000FUL)
474 #define R_SYSC_SYS_AOF2_OFS00_SXUSB2_0_H_Pos                    (0UL)
475 #define R_SYSC_SYS_AOF2_OFS01_SXUSB2_0_H_Msk                    (0x000000F0UL)
476 #define R_SYSC_SYS_AOF2_OFS01_SXUSB2_0_H_Pos                    (4UL)
477 #define R_SYSC_SYS_AOF2_OFS10_SXUSB2_0_H_Msk                    (0x00000F00UL)
478 #define R_SYSC_SYS_AOF2_OFS10_SXUSB2_0_H_Pos                    (8UL)
479 #define R_SYSC_SYS_AOF2_OFS11_SXUSB2_0_H_Msk                    (0x0000F000UL)
480 #define R_SYSC_SYS_AOF2_OFS11_SXUSB2_0_H_Pos                    (12UL)
481 #define R_SYSC_SYS_AOF2_OFS00_SXUSB2_1_Msk                      (0x000F0000UL)
482 #define R_SYSC_SYS_AOF2_OFS00_SXUSB2_1_Pos                      (16UL)
483 #define R_SYSC_SYS_AOF2_OFS01_SXUSB2_1_Msk                      (0x00F00000UL)
484 #define R_SYSC_SYS_AOF2_OFS01_SXUSB2_1_Pos                      (20UL)
485 #define R_SYSC_SYS_AOF2_OFS10_SXUSB2_1_Msk                      (0x0F000000UL)
486 #define R_SYSC_SYS_AOF2_OFS10_SXUSB2_1_Pos                      (24UL)
487 #define R_SYSC_SYS_AOF2_OFS11_SXUSB2_1_Msk                      (0xF0000000UL)
488 #define R_SYSC_SYS_AOF2_OFS11_SXUSB2_1_Pos                      (28UL)
489 #define R_SYSC_SYS_AOF3_OFS00_SXUSB2_0_F_Msk                    (0x0000000FUL)
490 #define R_SYSC_SYS_AOF3_OFS00_SXUSB2_0_F_Pos                    (0UL)
491 #define R_SYSC_SYS_AOF3_OFS01_SXUSB2_0_F_Msk                    (0x000000F0UL)
492 #define R_SYSC_SYS_AOF3_OFS01_SXUSB2_0_F_Pos                    (4UL)
493 #define R_SYSC_SYS_AOF3_OFS10_SXUSB2_0_F_Msk                    (0x00000F00UL)
494 #define R_SYSC_SYS_AOF3_OFS10_SXUSB2_0_F_Pos                    (8UL)
495 #define R_SYSC_SYS_AOF3_OFS11_SXUSB2_0_F_Msk                    (0x0000F000UL)
496 #define R_SYSC_SYS_AOF3_OFS11_SXUSB2_0_F_Pos                    (12UL)
497 #define R_SYSC_SYS_AOF6_OFS00_SXDMAC_S_Msk                      (0x0000000FUL)
498 #define R_SYSC_SYS_AOF6_OFS00_SXDMAC_S_Pos                      (0UL)
499 #define R_SYSC_SYS_AOF6_OFS01_SXDMAC_S_Msk                      (0x000000F0UL)
500 #define R_SYSC_SYS_AOF6_OFS01_SXDMAC_S_Pos                      (4UL)
501 #define R_SYSC_SYS_AOF6_OFS10_SXDMAC_S_Msk                      (0x00000F00UL)
502 #define R_SYSC_SYS_AOF6_OFS10_SXDMAC_S_Pos                      (8UL)
503 #define R_SYSC_SYS_AOF6_OFS11_SXDMAC_S_Msk                      (0x0000F000UL)
504 #define R_SYSC_SYS_AOF6_OFS11_SXDMAC_S_Pos                      (12UL)
505 #define R_SYSC_SYS_AOF6_OFS00_SXDMAC_NS_Msk                     (0x000F0000UL)
506 #define R_SYSC_SYS_AOF6_OFS00_SXDMAC_NS_Pos                     (16UL)
507 #define R_SYSC_SYS_AOF6_OFS01_SXDMAC_NS_Msk                     (0x00F00000UL)
508 #define R_SYSC_SYS_AOF6_OFS01_SXDMAC_NS_Pos                     (20UL)
509 #define R_SYSC_SYS_AOF6_OFS10_SXDMAC_NS_Msk                     (0x0F000000UL)
510 #define R_SYSC_SYS_AOF6_OFS10_SXDMAC_NS_Pos                     (24UL)
511 #define R_SYSC_SYS_AOF6_OFS11_SXDMAC_NS_Msk                     (0xF0000000UL)
512 #define R_SYSC_SYS_AOF6_OFS11_SXDMAC_NS_Pos                     (28UL)
513 #define R_SYSC_SYS_AOF9_OFS00_SXSDHI_2_Msk                      (0x0000000FUL)
514 #define R_SYSC_SYS_AOF9_OFS00_SXSDHI_2_Pos                      (0UL)
515 #define R_SYSC_SYS_AOF9_OFS01_SXDMAC_S_Msk                      (0x000000F0UL)
516 #define R_SYSC_SYS_AOF9_OFS01_SXDMAC_S_Pos                      (4UL)
517 #define R_SYSC_SYS_AOF9_OFS10_SXDMAC_S_Msk                      (0x00000F00UL)
518 #define R_SYSC_SYS_AOF9_OFS10_SXDMAC_S_Pos                      (8UL)
519 #define R_SYSC_SYS_AOF9_OFS11_SXDMAC_S_Msk                      (0x0000F000UL)
520 #define R_SYSC_SYS_AOF9_OFS11_SXDMAC_S_Pos                      (12UL)
521 #define R_SYSC_SYS_LP_CTL1_CA55SLEEP_REQ_Msk                    (0x00000100UL)
522 #define R_SYSC_SYS_LP_CTL1_CA55SLEEP_REQ_Pos                    (8UL)
523 #define R_SYSC_SYS_LP_CTL1_CM33SLEEP_REQ_Msk                    (0x00001000UL)
524 #define R_SYSC_SYS_LP_CTL1_CM33SLEEP_REQ_Pos                    (12UL)
525 #define R_SYSC_SYS_LP_CTL1_CM33FPUSLEEP_REQ_Msk                 (0x00002000UL)
526 #define R_SYSC_SYS_LP_CTL1_CM33FPUSLEEP_REQ_Pos                 (13UL)
527 #define R_SYSC_SYS_LP_CTL1_CA55SLEEP_ACK_Msk                    (0x01000000UL)
528 #define R_SYSC_SYS_LP_CTL1_CA55SLEEP_ACK_Pos                    (24UL)
529 #define R_SYSC_SYS_LP_CTL1_CM33SLEEP_ACK_Msk                    (0x10000000UL)
530 #define R_SYSC_SYS_LP_CTL1_CM33SLEEP_ACK_Pos                    (28UL)
531 #define R_SYSC_SYS_LP_CTL1_CM33FPUSLEEP_ACK_Msk                 (0x20000000UL)
532 #define R_SYSC_SYS_LP_CTL1_CM33FPUSLEEP_ACK_Pos                 (29UL)
533 #define R_SYSC_SYS_LP_CTL2_CA55_STBYCTL_Msk                     (0x00000001UL)
534 #define R_SYSC_SYS_LP_CTL2_CA55_STBYCTL_Pos                     (0UL)
535 #define R_SYSC_SYS_LP_CTL5_ASCLKQDENY_F_Msk                     (0x00000002UL)
536 #define R_SYSC_SYS_LP_CTL5_ASCLKQDENY_F_Pos                     (1UL)
537 #define R_SYSC_SYS_LP_CTL5_AMCLKQDENY_F_Msk                     (0x00000004UL)
538 #define R_SYSC_SYS_LP_CTL5_AMCLKQDENY_F_Pos                     (2UL)
539 #define R_SYSC_SYS_LP_CTL5_CA55SLEEP0_F_Msk                     (0x00000100UL)
540 #define R_SYSC_SYS_LP_CTL5_CA55SLEEP0_F_Pos                     (8UL)
541 #define R_SYSC_SYS_LP_CTL5_CM33SLEEP_F_Msk                      (0x00000400UL)
542 #define R_SYSC_SYS_LP_CTL5_CM33SLEEP_F_Pos                      (10UL)
543 #define R_SYSC_SYS_LP_CTL5_CM33FPUSLEEP_F_Msk                   (0x00000800UL)
544 #define R_SYSC_SYS_LP_CTL5_CM33FPUSLEEP_F_Pos                   (11UL)
545 #define R_SYSC_SYS_LP_CTL6_ASCLKQDENY_E_Msk                     (0x00000002UL)
546 #define R_SYSC_SYS_LP_CTL6_ASCLKQDENY_E_Pos                     (1UL)
547 #define R_SYSC_SYS_LP_CTL6_AMCLKQDENY_E_Msk                     (0x00000004UL)
548 #define R_SYSC_SYS_LP_CTL6_AMCLKQDENY_E_Pos                     (2UL)
549 #define R_SYSC_SYS_LP_CTL6_CA55SLEEP0_E_Msk                     (0x00000100UL)
550 #define R_SYSC_SYS_LP_CTL6_CA55SLEEP0_E_Pos                     (8UL)
551 #define R_SYSC_SYS_LP_CTL6_CM33SLEEP_E_Msk                      (0x00000400UL)
552 #define R_SYSC_SYS_LP_CTL6_CM33SLEEP_E_Pos                      (10UL)
553 #define R_SYSC_SYS_LP_CTL6_CM33FPUSLEEP_E_Msk                   (0x00000800UL)
554 #define R_SYSC_SYS_LP_CTL6_CM33FPUSLEEP_E_Pos                   (11UL)
555 #define R_SYSC_SYS_LP_CTL7_IM33_MASK_Msk                        (0x00000001UL)
556 #define R_SYSC_SYS_LP_CTL7_IM33_MASK_Pos                        (0UL)
557 #define R_SYSC_SYS_LP_CTL7_IM33FPU_MASK_Msk                     (0x00000002UL)
558 #define R_SYSC_SYS_LP_CTL7_IM33FPU_MASK_Pos                     (1UL)
559 #define R_SYSC_SYS_LP_CM33CTL0_SLEEPMODE_Msk                    (0x00000001UL)
560 #define R_SYSC_SYS_LP_CM33CTL0_SLEEPMODE_Pos                    (0UL)
561 #define R_SYSC_SYS_LP_CM33CTL0_SLEEPDEEP_Msk                    (0x00000010UL)
562 #define R_SYSC_SYS_LP_CM33CTL0_SLEEPDEEP_Pos                    (4UL)
563 #define R_SYSC_SYS_LP_CM33CTL0_SYSRESETREQ_Msk                  (0x00000200UL)
564 #define R_SYSC_SYS_LP_CM33CTL0_SYSRESETREQ_Pos                  (9UL)
565 #define R_SYSC_SYS_LP_CA55CK_CTL1_ASCLKQACTIVE_Msk              (0x00000002UL)
566 #define R_SYSC_SYS_LP_CA55CK_CTL1_ASCLKQACTIVE_Pos              (1UL)
567 #define R_SYSC_SYS_LP_CA55CK_CTL1_AMCLKQACTIVE_Msk              (0x00000004UL)
568 #define R_SYSC_SYS_LP_CA55CK_CTL1_AMCLKQACTIVE_Pos              (2UL)
569 #define R_SYSC_SYS_LP_CA55CK_CTL1_PCLKQACTIVE_Msk               (0x00000100UL)
570 #define R_SYSC_SYS_LP_CA55CK_CTL1_PCLKQACTIVE_Pos               (8UL)
571 #define R_SYSC_SYS_LP_CA55CK_CTL1_ATCLKQACTIVE_Msk              (0x00000200UL)
572 #define R_SYSC_SYS_LP_CA55CK_CTL1_ATCLKQACTIVE_Pos              (9UL)
573 #define R_SYSC_SYS_LP_CA55CK_CTL1_GICCLKQACTIVE_Msk             (0x00000400UL)
574 #define R_SYSC_SYS_LP_CA55CK_CTL1_GICCLKQACTIVE_Pos             (10UL)
575 #define R_SYSC_SYS_LP_CA55CK_CTL1_PDBGCLKQACTIVE_Msk            (0x00000800UL)
576 #define R_SYSC_SYS_LP_CA55CK_CTL1_PDBGCLKQACTIVE_Pos            (11UL)
577 #define R_SYSC_SYS_LP_CA55CK_CTL2_ASCLKQREQn_Msk                (0x00000002UL)
578 #define R_SYSC_SYS_LP_CA55CK_CTL2_ASCLKQREQn_Pos                (1UL)
579 #define R_SYSC_SYS_LP_CA55CK_CTL2_AMCLKQREQn_Msk                (0x00000004UL)
580 #define R_SYSC_SYS_LP_CA55CK_CTL2_AMCLKQREQn_Pos                (2UL)
581 #define R_SYSC_SYS_LP_CA55CK_CTL2_PCLKQREQn_Msk                 (0x00000100UL)
582 #define R_SYSC_SYS_LP_CA55CK_CTL2_PCLKQREQn_Pos                 (8UL)
583 #define R_SYSC_SYS_LP_CA55CK_CTL2_ATCLKQREQn_Msk                (0x00000200UL)
584 #define R_SYSC_SYS_LP_CA55CK_CTL2_ATCLKQREQn_Pos                (9UL)
585 #define R_SYSC_SYS_LP_CA55CK_CTL2_GICCLKQAREQn_Msk              (0x00000400UL)
586 #define R_SYSC_SYS_LP_CA55CK_CTL2_GICCLKQAREQn_Pos              (10UL)
587 #define R_SYSC_SYS_LP_CA55CK_CTL2_PDBGCLKQREQn_Msk              (0x00000800UL)
588 #define R_SYSC_SYS_LP_CA55CK_CTL2_PDBGCLKQREQn_Pos              (11UL)
589 #define R_SYSC_SYS_LP_CA55CK_CTL3_CA55_COREINSTRRUN0_Msk        (0x00000001UL)
590 #define R_SYSC_SYS_LP_CA55CK_CTL3_CA55_COREINSTRRUN0_Pos        (0UL)
591 #define R_SYSC_SYS_LP_CA55CK_CTL3_ASCLKQACCEPTn_Msk             (0x00000002UL)
592 #define R_SYSC_SYS_LP_CA55CK_CTL3_ASCLKQACCEPTn_Pos             (1UL)
593 #define R_SYSC_SYS_LP_CA55CK_CTL3_AMCLKQACCEPTn_Msk             (0x00000004UL)
594 #define R_SYSC_SYS_LP_CA55CK_CTL3_AMCLKQACCEPTn_Pos             (2UL)
595 #define R_SYSC_SYS_LP_CA55CK_CTL3_PCLKQACCEPTn_Msk              (0x00000100UL)
596 #define R_SYSC_SYS_LP_CA55CK_CTL3_PCLKQACCEPTn_Pos              (8UL)
597 #define R_SYSC_SYS_LP_CA55CK_CTL3_ATCLKQACCEPTn_Msk             (0x00000200UL)
598 #define R_SYSC_SYS_LP_CA55CK_CTL3_ATCLKQACCEPTn_Pos             (9UL)
599 #define R_SYSC_SYS_LP_CA55CK_CTL3_GICCLKQACCEPTn_Msk            (0x00000400UL)
600 #define R_SYSC_SYS_LP_CA55CK_CTL3_GICCLKQACCEPTn_Pos            (10UL)
601 #define R_SYSC_SYS_LP_CA55CK_CTL3_PDBGCLKQACCEPTn_Msk           (0x00000800UL)
602 #define R_SYSC_SYS_LP_CA55CK_CTL3_PDBGCLKQACCEPTn_Pos           (11UL)
603 #define R_SYSC_SYS_LP_CA55CK_CTL3_ASCLKQDENY_Msk                (0x00020000UL)
604 #define R_SYSC_SYS_LP_CA55CK_CTL3_ASCLKQDENY_Pos                (17UL)
605 #define R_SYSC_SYS_LP_CA55CK_CTL3_AMCLKQDENY_Msk                (0x00040000UL)
606 #define R_SYSC_SYS_LP_CA55CK_CTL3_AMCLKQDENY_Pos                (18UL)
607 #define R_SYSC_SYS_LP_CA55CK_CTL3_PCLKQDENY_Msk                 (0x01000000UL)
608 #define R_SYSC_SYS_LP_CA55CK_CTL3_PCLKQDENY_Pos                 (24UL)
609 #define R_SYSC_SYS_LP_CA55CK_CTL3_ATCLKQDENY_Msk                (0x02000000UL)
610 #define R_SYSC_SYS_LP_CA55CK_CTL3_ATCLKQDENY_Pos                (25UL)
611 #define R_SYSC_SYS_LP_CA55CK_CTL3_GICCLKQDENY_Msk               (0x04000000UL)
612 #define R_SYSC_SYS_LP_CA55CK_CTL3_GICCLKQDENY_Pos               (26UL)
613 #define R_SYSC_SYS_LP_CA55CK_CTL3_PDBGCLKQDENY_Msk              (0x08000000UL)
614 #define R_SYSC_SYS_LP_CA55CK_CTL3_PDBGCLKQDENY_Pos              (27UL)
615 #define R_SYSC_SYS_LP_CM33FPUCTL0_SLEEPMODE_Msk                 (0x00000001UL)
616 #define R_SYSC_SYS_LP_CM33FPUCTL0_SLEEPMODE_Pos                 (0UL)
617 #define R_SYSC_SYS_LP_CM33FPUCTL0_SLEEPDEEP_Msk                 (0x00000010UL)
618 #define R_SYSC_SYS_LP_CM33FPUCTL0_SLEEPDEEP_Pos                 (4UL)
619 #define R_SYSC_SYS_LP_CM33FPUCTL0_SYSRESETREQ_Msk               (0x00000200UL)
620 #define R_SYSC_SYS_LP_CM33FPUCTL0_SYSRESETREQ_Pos               (9UL)
621 #define R_SYSC_SYS_PD_ISO_CTRL_PD_ISOVCC_ISOEN_Msk              (0x00000001UL)
622 #define R_SYSC_SYS_PD_ISO_CTRL_PD_ISOVCC_ISOEN_Pos              (0UL)
623 #define R_SYSC_PWRDN_DDRPHY_CTRL_DDRPHY_CTRL1_EN_Msk            (0x00000001UL)
624 #define R_SYSC_PWRDN_DDRPHY_CTRL_DDRPHY_CTRL1_EN_Pos            (0UL)
625 #define R_SYSC_PWRDN_DDRPHY_CTRL_DDRPHY_CTRL1_Msk               (0x00000002UL)
626 #define R_SYSC_PWRDN_DDRPHY_CTRL_DDRPHY_CTRL1_Pos               (1UL)
627 #define R_SYSC_PWRDN_DDRPHY_CTRL_DDRPHY_CTRL2_EN_Msk            (0x00000010UL)
628 #define R_SYSC_PWRDN_DDRPHY_CTRL_DDRPHY_CTRL2_EN_Pos            (4UL)
629 #define R_SYSC_PWRDN_DDRPHY_CTRL_DDRPHY_CTRL2_Msk               (0x00000020UL)
630 #define R_SYSC_PWRDN_DDRPHY_CTRL_DDRPHY_CTRL2_Pos               (5UL)
631 #define R_SYSC_PWRDN_DDRPHY_CTRL_DDRPHY_CTRL3_EN_Msk            (0x00000100UL)
632 #define R_SYSC_PWRDN_DDRPHY_CTRL_DDRPHY_CTRL3_EN_Pos            (8UL)
633 #define R_SYSC_PWRDN_DDRPHY_CTRL_DDRPHY_CTRL3_Msk               (0x00000200UL)
634 #define R_SYSC_PWRDN_DDRPHY_CTRL_DDRPHY_CTRL3_Pos               (9UL)
635 #define R_SYSC_ISO_IOBUF_SE18_CTRL_ISO_IOBUF_SE18_Msk           (0x00000001UL)
636 #define R_SYSC_ISO_IOBUF_SE18_CTRL_ISO_IOBUF_SE18_Pos           (0UL)
637 #define R_SYSC_SYS_USB_PWRRDY_PWRRDY_N_Msk                      (0x00000001UL)
638 #define R_SYSC_SYS_USB_PWRRDY_PWRRDY_N_Pos                      (0UL)
639 #define R_SYSC_SYS_PCIE_RST_RSM_B_PCIE_RST_RSM_B_Msk            (0x00000001UL)
640 #define R_SYSC_SYS_PCIE_RST_RSM_B_PCIE_RST_RSM_B_Pos            (0UL)
641 #define R_SYSC_SYS_GPREG_0_GPREG0_Msk                           (0xFFFFFFFFUL)
642 #define R_SYSC_SYS_GPREG_0_GPREG0_Pos                           (0UL)
643 #define R_SYSC_SYS_GPREG_1_GPREG1_Msk                           (0xFFFFFFFFUL)
644 #define R_SYSC_SYS_GPREG_1_GPREG1_Pos                           (0UL)
645 #define R_SYSC_SYS_GPREG_2_GPREG2_Msk                           (0xFFFFFFFFUL)
646 #define R_SYSC_SYS_GPREG_2_GPREG2_Pos                           (0UL)
647 #define R_SYSC_SYS_GPREG_3_GPREG3_Msk                           (0xFFFFFFFFUL)
648 #define R_SYSC_SYS_GPREG_3_GPREG3_Pos                           (0UL)
649 #define R_SYSC_SYS_IPCONT_SEL_SPI_OCTA_SEL_SPI_OCTA_Msk         (0x00000001UL)
650 #define R_SYSC_SYS_IPCONT_SEL_SPI_OCTA_SEL_SPI_OCTA_Pos         (0UL)
651 #define R_SYSC_SYS_IPCONT_IDAUZERONS_IDAUZERONS_Msk             (0x00000001UL)
652 #define R_SYSC_SYS_IPCONT_IDAUZERONS_IDAUZERONS_Pos             (0UL)
653 #define R_SYSC_SYS_IPCONT_IDAUZERONS_FPU_IDAUZERONS_FPU_Msk     (0x00000001UL)
654 #define R_SYSC_SYS_IPCONT_IDAUZERONS_FPU_IDAUZERONS_FPU_Pos     (0UL)
655 
656 #endif
657