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Searched defs:R_SPI0_SPCR_SPE_Msk (Results 1 – 20 of 20) sorted by relevance

/hal_renesas-latest/drivers/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/
DR7FA2L1AB.h16897 …#define R_SPI0_SPCR_SPE_Msk (0x40UL) /*!< SPE (Bitfield-Mask: 0x01) … macro
DR7FA4E10D.h17912 …#define R_SPI0_SPCR_SPE_Msk (0x40UL) /*!< SPE (Bitfield-Mask: 0x01) … macro
DR7FA2A1AB.h18213 …#define R_SPI0_SPCR_SPE_Msk (0x40UL) /*!< SPE (Bitfield-Mask: 0x01) … macro
DR7FA4W1AD.h18218 …#define R_SPI0_SPCR_SPE_Msk (0x40UL) /*!< SPE (Bitfield-Mask: 0x01) … macro
DR7FA6E10F.h19932 …#define R_SPI0_SPCR_SPE_Msk (0x40UL) /*!< SPE (Bitfield-Mask: 0x01) … macro
DR7FA4M1AB.h18369 …#define R_SPI0_SPCR_SPE_Msk (0x40UL) /*!< SPE (Bitfield-Mask: 0x01) … macro
DR7FA4M2AD.h19298 …#define R_SPI0_SPCR_SPE_Msk (0x40UL) /*!< SPE (Bitfield-Mask: 0x01) … macro
DR7FA4M3AF.h19403 …#define R_SPI0_SPCR_SPE_Msk (0x40UL) /*!< SPE (Bitfield-Mask: 0x01) … macro
DR7FA4E2B9.h21054 …#define R_SPI0_SPCR_SPE_Msk (0x40UL) /*!< SPE (Bitfield-Mask: 0x01) … macro
DR7FA6E2BB.h21342 …#define R_SPI0_SPCR_SPE_Msk (0x40UL) /*!< SPE (Bitfield-Mask: 0x01) … macro
DR7FA6M1AD.h20116 …#define R_SPI0_SPCR_SPE_Msk (0x40UL) /*!< SPE (Bitfield-Mask: 0x01) … macro
DR7FA6M4AF.h21793 …#define R_SPI0_SPCR_SPE_Msk (0x40UL) /*!< SPE (Bitfield-Mask: 0x01) … macro
DR7FA4L1BD.h23923 …#define R_SPI0_SPCR_SPE_Msk (0x40UL) /*!< SPE (Bitfield-Mask: 0x01) … macro
DR7FA6M2AF.h23100 …#define R_SPI0_SPCR_SPE_Msk (0x40UL) /*!< SPE (Bitfield-Mask: 0x01) … macro
DR7FA6M3AH.h26735 …#define R_SPI0_SPCR_SPE_Msk (0x40UL) /*!< SPE (Bitfield-Mask: 0x01) … macro
DR7FA6M5BH.h25603 …#define R_SPI0_SPCR_SPE_Msk (0x40UL) /*!< SPE (Bitfield-Mask: 0x01) … macro
DR7FA8T1AH.h26170 …#define R_SPI0_SPCR_SPE_Msk (0x40UL) /*!< SPE (Bitfield-Mask: 0x01) … macro
DR7FA8M1AH.h28158 …#define R_SPI0_SPCR_SPE_Msk (0x40UL) /*!< SPE (Bitfield-Mask: 0x01) … macro
DR7FA8D1BH.h36712 …#define R_SPI0_SPCR_SPE_Msk (0x40UL) /*!< SPE (Bitfield-Mask: 0x01) … macro
/hal_renesas-latest/drivers/rz/fsp/src/rzn/bsp/cmsis/Device/RENESAS/Include/
DR9A07G084.h33154 …#define R_SPI0_SPCR_SPE_Msk (0x1UL) /*!< SPE (Bitfield-Mask: 0x01) … macro