1 /* 2 * Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 /********************************************************************************************************************** 8 * File Name : scifa_iobitmask.h 9 * Version : 1.00 10 * Description : IO bit mask file for scifa. 11 *********************************************************************************************************************/ 12 13 #ifndef SCIFA_IOBITMASK_H 14 #define SCIFA_IOBITMASK_H 15 16 #define R_SCIFA0_SMR_CKS_Msk (0x0003UL) 17 #define R_SCIFA0_SMR_CKS_Pos (0UL) 18 #define R_SCIFA0_SMR_STOP_Msk (0x0008UL) 19 #define R_SCIFA0_SMR_STOP_Pos (3UL) 20 #define R_SCIFA0_SMR_PM_Msk (0x0010UL) 21 #define R_SCIFA0_SMR_PM_Pos (4UL) 22 #define R_SCIFA0_SMR_PE_Msk (0x0020UL) 23 #define R_SCIFA0_SMR_PE_Pos (5UL) 24 #define R_SCIFA0_SMR_CHR_Msk (0x0040UL) 25 #define R_SCIFA0_SMR_CHR_Pos (6UL) 26 #define R_SCIFA0_SMR_CM_Msk (0x0080UL) 27 #define R_SCIFA0_SMR_CM_Pos (7UL) 28 #define R_SCIFA0_MDDR_MDDR_Msk (0xFFUL) 29 #define R_SCIFA0_MDDR_MDDR_Pos (0UL) 30 #define R_SCIFA0_BRR_BRR_Msk (0xFFUL) 31 #define R_SCIFA0_BRR_BRR_Pos (0UL) 32 #define R_SCIFA0_SCR_CKE_Msk (0x0003UL) 33 #define R_SCIFA0_SCR_CKE_Pos (0UL) 34 #define R_SCIFA0_SCR_TEIE_Msk (0x0004UL) 35 #define R_SCIFA0_SCR_TEIE_Pos (2UL) 36 #define R_SCIFA0_SCR_REIE_Msk (0x0008UL) 37 #define R_SCIFA0_SCR_REIE_Pos (3UL) 38 #define R_SCIFA0_SCR_RE_Msk (0x0010UL) 39 #define R_SCIFA0_SCR_RE_Pos (4UL) 40 #define R_SCIFA0_SCR_TE_Msk (0x0020UL) 41 #define R_SCIFA0_SCR_TE_Pos (5UL) 42 #define R_SCIFA0_SCR_RIE_Msk (0x0040UL) 43 #define R_SCIFA0_SCR_RIE_Pos (6UL) 44 #define R_SCIFA0_SCR_TIE_Msk (0x0080UL) 45 #define R_SCIFA0_SCR_TIE_Pos (7UL) 46 #define R_SCIFA0_FTDR_FTDR_Msk (0xFFUL) 47 #define R_SCIFA0_FTDR_FTDR_Pos (0UL) 48 #define R_SCIFA0_FSR_DR_Msk (0x0001UL) 49 #define R_SCIFA0_FSR_DR_Pos (0UL) 50 #define R_SCIFA0_FSR_RDF_Msk (0x0002UL) 51 #define R_SCIFA0_FSR_RDF_Pos (1UL) 52 #define R_SCIFA0_FSR_PER_Msk (0x0004UL) 53 #define R_SCIFA0_FSR_PER_Pos (2UL) 54 #define R_SCIFA0_FSR_FER_Msk (0x0008UL) 55 #define R_SCIFA0_FSR_FER_Pos (3UL) 56 #define R_SCIFA0_FSR_BRK_Msk (0x0010UL) 57 #define R_SCIFA0_FSR_BRK_Pos (4UL) 58 #define R_SCIFA0_FSR_TDFE_Msk (0x0020UL) 59 #define R_SCIFA0_FSR_TDFE_Pos (5UL) 60 #define R_SCIFA0_FSR_TEND_Msk (0x0040UL) 61 #define R_SCIFA0_FSR_TEND_Pos (6UL) 62 #define R_SCIFA0_FSR_ER_Msk (0x0080UL) 63 #define R_SCIFA0_FSR_ER_Pos (7UL) 64 #define R_SCIFA0_FRDR_FRDR_Msk (0xFFUL) 65 #define R_SCIFA0_FRDR_FRDR_Pos (0UL) 66 #define R_SCIFA0_FCR_LOOP_Msk (0x0001UL) 67 #define R_SCIFA0_FCR_LOOP_Pos (0UL) 68 #define R_SCIFA0_FCR_RFRST_Msk (0x0002UL) 69 #define R_SCIFA0_FCR_RFRST_Pos (1UL) 70 #define R_SCIFA0_FCR_TFRST_Msk (0x0004UL) 71 #define R_SCIFA0_FCR_TFRST_Pos (2UL) 72 #define R_SCIFA0_FCR_MCE_Msk (0x0008UL) 73 #define R_SCIFA0_FCR_MCE_Pos (3UL) 74 #define R_SCIFA0_FCR_TTRG_Msk (0x0030UL) 75 #define R_SCIFA0_FCR_TTRG_Pos (4UL) 76 #define R_SCIFA0_FCR_RTRG_Msk (0x00C0UL) 77 #define R_SCIFA0_FCR_RTRG_Pos (6UL) 78 #define R_SCIFA0_FCR_RSTRG_Msk (0x0700UL) 79 #define R_SCIFA0_FCR_RSTRG_Pos (8UL) 80 #define R_SCIFA0_FDR_R_Msk (0x001FUL) 81 #define R_SCIFA0_FDR_R_Pos (0UL) 82 #define R_SCIFA0_FDR_T_Msk (0x1F00UL) 83 #define R_SCIFA0_FDR_T_Pos (8UL) 84 #define R_SCIFA0_SPTR_SPB2DT_Msk (0x0001UL) 85 #define R_SCIFA0_SPTR_SPB2DT_Pos (0UL) 86 #define R_SCIFA0_SPTR_SPB2IO_Msk (0x0002UL) 87 #define R_SCIFA0_SPTR_SPB2IO_Pos (1UL) 88 #define R_SCIFA0_SPTR_SCKDT_Msk (0x0004UL) 89 #define R_SCIFA0_SPTR_SCKDT_Pos (2UL) 90 #define R_SCIFA0_SPTR_SCKIO_Msk (0x0008UL) 91 #define R_SCIFA0_SPTR_SCKIO_Pos (3UL) 92 #define R_SCIFA0_SPTR_CTS2DT_Msk (0x0010UL) 93 #define R_SCIFA0_SPTR_CTS2DT_Pos (4UL) 94 #define R_SCIFA0_SPTR_CTS2IO_Msk (0x0020UL) 95 #define R_SCIFA0_SPTR_CTS2IO_Pos (5UL) 96 #define R_SCIFA0_SPTR_RTS2DT_Msk (0x0040UL) 97 #define R_SCIFA0_SPTR_RTS2DT_Pos (6UL) 98 #define R_SCIFA0_SPTR_RTS2IO_Msk (0x0080UL) 99 #define R_SCIFA0_SPTR_RTS2IO_Pos (7UL) 100 #define R_SCIFA0_LSR_ORER_Msk (0x0001UL) 101 #define R_SCIFA0_LSR_ORER_Pos (0UL) 102 #define R_SCIFA0_LSR_FER_Msk (0x003CUL) 103 #define R_SCIFA0_LSR_FER_Pos (2UL) 104 #define R_SCIFA0_LSR_PER_Msk (0x0F00UL) 105 #define R_SCIFA0_LSR_PER_Pos (8UL) 106 #define R_SCIFA0_SEMR_ABCS0_Msk (0x01UL) 107 #define R_SCIFA0_SEMR_ABCS0_Pos (0UL) 108 #define R_SCIFA0_SEMR_NFEN_Msk (0x04UL) 109 #define R_SCIFA0_SEMR_NFEN_Pos (2UL) 110 #define R_SCIFA0_SEMR_DIR_Msk (0x08UL) 111 #define R_SCIFA0_SEMR_DIR_Pos (3UL) 112 #define R_SCIFA0_SEMR_MDDRS_Msk (0x10UL) 113 #define R_SCIFA0_SEMR_MDDRS_Pos (4UL) 114 #define R_SCIFA0_SEMR_BRME_Msk (0x20UL) 115 #define R_SCIFA0_SEMR_BRME_Pos (5UL) 116 #define R_SCIFA0_SEMR_BGDM_Msk (0x80UL) 117 #define R_SCIFA0_SEMR_BGDM_Pos (7UL) 118 #define R_SCIFA0_FTCR_TFTC_Msk (0x001FUL) 119 #define R_SCIFA0_FTCR_TFTC_Pos (0UL) 120 #define R_SCIFA0_FTCR_TTRGS_Msk (0x0080UL) 121 #define R_SCIFA0_FTCR_TTRGS_Pos (7UL) 122 #define R_SCIFA0_FTCR_RFTC_Msk (0x1F00UL) 123 #define R_SCIFA0_FTCR_RFTC_Pos (8UL) 124 #define R_SCIFA0_FTCR_RTRGS_Msk (0x8000UL) 125 #define R_SCIFA0_FTCR_RTRGS_Pos (15UL) 126 127 #endif /* SCIFA_IOBITMASK_H */ 128
