1 /*
2 * Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6 
7 /**********************************************************************************************************************
8  * File Name    : rspi_iobitmask.h
9  * Version      : 1.00
10  * Description  : IO bit mask file for rspi.
11  *********************************************************************************************************************/
12 
13 #ifndef RSPI_IOBITMASK_H
14 #define RSPI_IOBITMASK_H
15 
16 #define R_RSPI0_SPCR_MODFEN_Msk      (0x04UL)
17 #define R_RSPI0_SPCR_MODFEN_Pos      (2UL)
18 #define R_RSPI0_SPCR_MSTR_Msk        (0x08UL)
19 #define R_RSPI0_SPCR_MSTR_Pos        (3UL)
20 #define R_RSPI0_SPCR_SPEIE_Msk       (0x10UL)
21 #define R_RSPI0_SPCR_SPEIE_Pos       (4UL)
22 #define R_RSPI0_SPCR_SPTIE_Msk       (0x20UL)
23 #define R_RSPI0_SPCR_SPTIE_Pos       (5UL)
24 #define R_RSPI0_SPCR_SPE_Msk         (0x40UL)
25 #define R_RSPI0_SPCR_SPE_Pos         (6UL)
26 #define R_RSPI0_SPCR_SPRIE_Msk       (0x80UL)
27 #define R_RSPI0_SPCR_SPRIE_Pos       (7UL)
28 #define R_RSPI0_SSLP_SSL0P_Msk       (0x01UL)
29 #define R_RSPI0_SSLP_SSL0P_Pos       (0UL)
30 #define R_RSPI0_SPPCR_SPLP_Msk       (0x01UL)
31 #define R_RSPI0_SPPCR_SPLP_Pos       (0UL)
32 #define R_RSPI0_SPPCR_MOIFV_Msk      (0x10UL)
33 #define R_RSPI0_SPPCR_MOIFV_Pos      (4UL)
34 #define R_RSPI0_SPPCR_MOIFE_Msk      (0x20UL)
35 #define R_RSPI0_SPPCR_MOIFE_Pos      (5UL)
36 #define R_RSPI0_SPSR_OVRF_Msk        (0x01UL)
37 #define R_RSPI0_SPSR_OVRF_Pos        (0UL)
38 #define R_RSPI0_SPSR_MODF_Msk        (0x04UL)
39 #define R_RSPI0_SPSR_MODF_Pos        (2UL)
40 #define R_RSPI0_SPSR_SPTEF_Msk       (0x20UL)
41 #define R_RSPI0_SPSR_SPTEF_Pos       (5UL)
42 #define R_RSPI0_SPSR_TEND_Msk        (0x40UL)
43 #define R_RSPI0_SPSR_TEND_Pos        (6UL)
44 #define R_RSPI0_SPSR_SPRF_Msk        (0x80UL)
45 #define R_RSPI0_SPSR_SPRF_Pos        (7UL)
46 #define R_RSPI0_SPDR_SPD_Msk         (0xFFFFFFFFUL)
47 #define R_RSPI0_SPDR_SPD_Pos         (0UL)
48 #define R_RSPI0_SPSCR_SPSLN_Msk      (0x03UL)
49 #define R_RSPI0_SPSCR_SPSLN_Pos      (0UL)
50 #define R_RSPI0_SPSSR_SPCP_Msk       (0x03UL)
51 #define R_RSPI0_SPSSR_SPCP_Pos       (0UL)
52 #define R_RSPI0_SPBR_SPR_Msk         (0xFFUL)
53 #define R_RSPI0_SPBR_SPR_Pos         (0UL)
54 #define R_RSPI0_SPDCR_SPLW_Msk       (0x60UL)
55 #define R_RSPI0_SPDCR_SPLW_Pos       (5UL)
56 #define R_RSPI0_SPDCR_TXDMY_Msk      (0x80UL)
57 #define R_RSPI0_SPDCR_TXDMY_Pos      (7UL)
58 #define R_RSPI0_SPCKD_SCKDL_Msk      (0x07UL)
59 #define R_RSPI0_SPCKD_SCKDL_Pos      (0UL)
60 #define R_RSPI0_SSLND_SLNDL_Msk      (0x07UL)
61 #define R_RSPI0_SSLND_SLNDL_Pos      (0UL)
62 #define R_RSPI0_SPND_SPNDL_Msk       (0x07UL)
63 #define R_RSPI0_SPND_SPNDL_Pos       (0UL)
64 #define R_RSPI0_SPCMD0_CPHA_Msk      (0x0001UL)
65 #define R_RSPI0_SPCMD0_CPHA_Pos      (0UL)
66 #define R_RSPI0_SPCMD0_CPOL_Msk      (0x0002UL)
67 #define R_RSPI0_SPCMD0_CPOL_Pos      (1UL)
68 #define R_RSPI0_SPCMD0_BRDV_Msk      (0x000CUL)
69 #define R_RSPI0_SPCMD0_BRDV_Pos      (2UL)
70 #define R_RSPI0_SPCMD0_SSLKP_Msk     (0x0080UL)
71 #define R_RSPI0_SPCMD0_SSLKP_Pos     (7UL)
72 #define R_RSPI0_SPCMD0_SPB_Msk       (0x0F00UL)
73 #define R_RSPI0_SPCMD0_SPB_Pos       (8UL)
74 #define R_RSPI0_SPCMD0_LSBF_Msk      (0x1000UL)
75 #define R_RSPI0_SPCMD0_LSBF_Pos      (12UL)
76 #define R_RSPI0_SPCMD0_SPNDEN_Msk    (0x2000UL)
77 #define R_RSPI0_SPCMD0_SPNDEN_Pos    (13UL)
78 #define R_RSPI0_SPCMD0_SLNDEN_Msk    (0x4000UL)
79 #define R_RSPI0_SPCMD0_SLNDEN_Pos    (14UL)
80 #define R_RSPI0_SPCMD0_SCKDEN_Msk    (0x8000UL)
81 #define R_RSPI0_SPCMD0_SCKDEN_Pos    (15UL)
82 #define R_RSPI0_SPCMD1_CPHA_Msk      (0x0001UL)
83 #define R_RSPI0_SPCMD1_CPHA_Pos      (0UL)
84 #define R_RSPI0_SPCMD1_CPOL_Msk      (0x0002UL)
85 #define R_RSPI0_SPCMD1_CPOL_Pos      (1UL)
86 #define R_RSPI0_SPCMD1_BRDV_Msk      (0x000CUL)
87 #define R_RSPI0_SPCMD1_BRDV_Pos      (2UL)
88 #define R_RSPI0_SPCMD1_SSLKP_Msk     (0x0080UL)
89 #define R_RSPI0_SPCMD1_SSLKP_Pos     (7UL)
90 #define R_RSPI0_SPCMD1_SPB_Msk       (0x0F00UL)
91 #define R_RSPI0_SPCMD1_SPB_Pos       (8UL)
92 #define R_RSPI0_SPCMD1_LSBF_Msk      (0x1000UL)
93 #define R_RSPI0_SPCMD1_LSBF_Pos      (12UL)
94 #define R_RSPI0_SPCMD1_SPNDEN_Msk    (0x2000UL)
95 #define R_RSPI0_SPCMD1_SPNDEN_Pos    (13UL)
96 #define R_RSPI0_SPCMD1_SLNDEN_Msk    (0x4000UL)
97 #define R_RSPI0_SPCMD1_SLNDEN_Pos    (14UL)
98 #define R_RSPI0_SPCMD1_SCKDEN_Msk    (0x8000UL)
99 #define R_RSPI0_SPCMD1_SCKDEN_Pos    (15UL)
100 #define R_RSPI0_SPCMD2_CPHA_Msk      (0x0001UL)
101 #define R_RSPI0_SPCMD2_CPHA_Pos      (0UL)
102 #define R_RSPI0_SPCMD2_CPOL_Msk      (0x0002UL)
103 #define R_RSPI0_SPCMD2_CPOL_Pos      (1UL)
104 #define R_RSPI0_SPCMD2_BRDV_Msk      (0x000CUL)
105 #define R_RSPI0_SPCMD2_BRDV_Pos      (2UL)
106 #define R_RSPI0_SPCMD2_SSLKP_Msk     (0x0080UL)
107 #define R_RSPI0_SPCMD2_SSLKP_Pos     (7UL)
108 #define R_RSPI0_SPCMD2_SPB_Msk       (0x0F00UL)
109 #define R_RSPI0_SPCMD2_SPB_Pos       (8UL)
110 #define R_RSPI0_SPCMD2_LSBF_Msk      (0x1000UL)
111 #define R_RSPI0_SPCMD2_LSBF_Pos      (12UL)
112 #define R_RSPI0_SPCMD2_SPNDEN_Msk    (0x2000UL)
113 #define R_RSPI0_SPCMD2_SPNDEN_Pos    (13UL)
114 #define R_RSPI0_SPCMD2_SLNDEN_Msk    (0x4000UL)
115 #define R_RSPI0_SPCMD2_SLNDEN_Pos    (14UL)
116 #define R_RSPI0_SPCMD2_SCKDEN_Msk    (0x8000UL)
117 #define R_RSPI0_SPCMD2_SCKDEN_Pos    (15UL)
118 #define R_RSPI0_SPCMD3_CPHA_Msk      (0x0001UL)
119 #define R_RSPI0_SPCMD3_CPHA_Pos      (0UL)
120 #define R_RSPI0_SPCMD3_CPOL_Msk      (0x0002UL)
121 #define R_RSPI0_SPCMD3_CPOL_Pos      (1UL)
122 #define R_RSPI0_SPCMD3_BRDV_Msk      (0x000CUL)
123 #define R_RSPI0_SPCMD3_BRDV_Pos      (2UL)
124 #define R_RSPI0_SPCMD3_SSLKP_Msk     (0x0080UL)
125 #define R_RSPI0_SPCMD3_SSLKP_Pos     (7UL)
126 #define R_RSPI0_SPCMD3_SPB_Msk       (0x0F00UL)
127 #define R_RSPI0_SPCMD3_SPB_Pos       (8UL)
128 #define R_RSPI0_SPCMD3_LSBF_Msk      (0x1000UL)
129 #define R_RSPI0_SPCMD3_LSBF_Pos      (12UL)
130 #define R_RSPI0_SPCMD3_SPNDEN_Msk    (0x2000UL)
131 #define R_RSPI0_SPCMD3_SPNDEN_Pos    (13UL)
132 #define R_RSPI0_SPCMD3_SLNDEN_Msk    (0x4000UL)
133 #define R_RSPI0_SPCMD3_SLNDEN_Pos    (14UL)
134 #define R_RSPI0_SPCMD3_SCKDEN_Msk    (0x8000UL)
135 #define R_RSPI0_SPCMD3_SCKDEN_Pos    (15UL)
136 #define R_RSPI0_SPBFCR_RXTRG_Msk     (0x07UL)
137 #define R_RSPI0_SPBFCR_RXTRG_Pos     (0UL)
138 #define R_RSPI0_SPBFCR_TXTRG_Msk     (0x30UL)
139 #define R_RSPI0_SPBFCR_TXTRG_Pos     (4UL)
140 #define R_RSPI0_SPBFCR_RXRST_Msk     (0x40UL)
141 #define R_RSPI0_SPBFCR_RXRST_Pos     (6UL)
142 #define R_RSPI0_SPBFCR_TXRST_Msk     (0x80UL)
143 #define R_RSPI0_SPBFCR_TXRST_Pos     (7UL)
144 #define R_RSPI0_SPBFDR_R_Msk         (0x003FUL)
145 #define R_RSPI0_SPBFDR_R_Pos         (0UL)
146 #define R_RSPI0_SPBFDR_T_Msk         (0x0F00UL)
147 #define R_RSPI0_SPBFDR_T_Pos         (8UL)
148 
149 #endif                                 /* RSPI_IOBITMASK_H */
150