1 /*
2 * Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 /***********************************************************************************************************************
8 * Includes
9 **********************************************************************************************************************/
10 #include "r_riic_master.h"
11 #if RIIC_MASTER_CFG_DMAC_ENABLE
12 #include "r_dmac_b.h"
13 #endif
14
15 /***********************************************************************************************************************
16 * Macro definitions
17 **********************************************************************************************************************/
18
19 /* "IIC" in ASCII, used to determine if channel is open. */
20 #define IIC_MASTER_OPEN (0x52494943U)
21
22 #define I2C_CODE_READ (0x01U)
23 #define I2C_CODE_10BIT (0xF0U)
24
25 /* The timeout interrupt enable bit */
26 #define IIC_MASTER_TMO_EN_BIT (0x01)
27
28 /* The arbitration loss detection interrupt enable bit */
29 #define IIC_MASTER_ALD_EN_BIT (0x02)
30
31 /* The start condition detection interrupt enable bit */
32 #define IIC_MASTER_STR_EN_BIT (0x04)
33
34 /* The stop condition detection interrupt enable bit */
35 #define IIC_MASTER_STP_EN_BIT (0x08)
36
37 /* The NAK reception interrupt enable bit */
38 #define IIC_MASTER_NAK_EN_BIT (0x10)
39
40 /* The receive data full interrupt enable bit */
41 #define IIC_MASTER_RXI_EN_BIT (0x20)
42
43 /* The transmit end interrupt enable bit */
44 #define IIC_MASTER_TEI_EN_BIT (0x40)
45
46 /* The transmit data empty interrupt enable bit */
47 #define IIC_MASTER_TXI_EN_BIT (0x80)
48
49 /* Bit position for STOP condition flag in ICSR2 */
50 #define IIC_MASTER_ICSR2_STOP_BIT (0x08U)
51
52 #define IIC_MASTER_BUS_RATE_REG_RESERVED_BITS (0xE0U)
53 #define IIC_MASTER_INTERNAL_REF_CLOCK_SELECT_MAX (0x07U)
54
55 #define IIC_MASTER_SLAVE_10_BIT_ADDR_LEN_ADJUST (2U)
56
57 #define IIC_MASTER_FUNCTION_ENABLE_REG_VAL (0x02U)
58 #define IIC_MASTER_INTERRUPT_ENABLE_INIT_MASK (0xB3U)
59 #define IIC_MASTER_FUNCTION_ENABLE_INIT_SETTINGS (0x77U)
60 #define IIC_MASTER_BUS_MODE_REGISTER_1_MASK (0x08U)
61 #define IIC_MASTER_BUS_MODE_REGISTER_2_MASK (0x06U)
62 #define IIC_MASTER_PRV_SCL_SDA_NOT_DRIVEN (0x1FU)
63 #define IIC_MASTER_ICCR1_ICE_BIT_MASK (0x80)
64 #define IIC_MASTER_ICCR1_IICRST_BIT_MASK (0x40)
65 #define IIC_MASTER_ICCR2_SP_BIT_MASK (0x08)
66 #define IIC_MASTER_ICCR2_RS_BIT_MASK (0x04)
67 #define IIC_MASTER_ICCR2_ST_BIT_MASK (0x02)
68
69 #define IIC_MASTER_HARDWARE_REGISTER_WAIT(reg, required_value, timeout) \
70 while ((timeout)) \
71 { \
72 if ((required_value) == (reg)) \
73 { \
74 break; \
75 } \
76 (timeout)--; \
77 }
78
79 /***********************************************************************************************************************
80 * Typedef definitions
81 **********************************************************************************************************************/
82
83 /* RIIC read/write enumeration */
84 typedef enum e_iic_master_transfer_dir_option
85 {
86 IIC_MASTER_TRANSFER_DIR_WRITE = 0x0,
87 IIC_MASTER_TRANSFER_DIR_READ = 0x1
88 } iic_master_transfer_dir_t;
89
90 #if defined(__ARMCC_VERSION) || defined(__ICCARM__)
91 typedef void (BSP_CMSE_NONSECURE_CALL * iic_master_prv_ns_callback)(i2c_master_callback_args_t * p_args);
92 #elif defined(__GNUC__)
93 typedef BSP_CMSE_NONSECURE_CALL void (*volatile iic_master_prv_ns_callback)(i2c_master_callback_args_t * p_args);
94 #endif
95
96 /***********************************************************************************************************************
97 * Private function prototypes
98 **********************************************************************************************************************/
99
100 void riic_master_rxi_isr(void);
101 void riic_master_txi_isr(void);
102 void riic_master_tei_isr(void);
103 void riic_master_naki_isr(void);
104 void riic_master_sti_isr(void);
105 void riic_master_spi_isr(void);
106 void riic_master_ali_isr(void);
107 void riic_master_tmoi_isr(void);
108
109 /* Internal helper functions */
110 static void iic_master_abort_seq_master(iic_master_instance_ctrl_t * const p_ctrl, bool iic_reset);
111 static fsp_err_t iic_master_read_write(i2c_master_ctrl_t * const p_api_ctrl,
112 uint8_t * const p_buffer,
113 uint32_t const bytes,
114 iic_master_transfer_dir_t direction);
115 static void iic_master_notify(iic_master_instance_ctrl_t * const p_ctrl, i2c_master_event_t const event);
116
117 /* Interrupt handlers */
118 static void iic_master_rxi_master(iic_master_instance_ctrl_t * p_ctrl);
119 static void iic_master_txi_master(iic_master_instance_ctrl_t * p_ctrl);
120 static void iic_master_tei_master(iic_master_instance_ctrl_t * p_ctrl);
121 static void iic_master_naki_master(iic_master_instance_ctrl_t * p_ctrl);
122 static void iic_master_spi_master(iic_master_instance_ctrl_t * p_ctrl);
123 static void iic_master_sti_master(iic_master_instance_ctrl_t * p_ctrl);
124 static void iic_master_ali_master(iic_master_instance_ctrl_t * p_ctrl);
125 static void iic_master_tmoi_master(iic_master_instance_ctrl_t * p_ctrl);
126
127 /* Functions that manipulate hardware */
128 static void iic_master_open_hw_master(iic_master_instance_ctrl_t * const p_ctrl,
129 i2c_master_cfg_t const * const p_cfg);
130 static fsp_err_t iic_master_run_hw_master(iic_master_instance_ctrl_t * const p_ctrl);
131 static void iic_master_rxi_read_data(iic_master_instance_ctrl_t * const p_ctrl);
132 static void iic_master_txi_send_address(iic_master_instance_ctrl_t * const p_ctrl);
133
134 #if RIIC_MASTER_CFG_DMAC_ENABLE
135 void riic_master_rx_dmac_callback(iic_master_instance_ctrl_t * p_ctrl);
136 void riic_master_tx_dmac_callback(iic_master_instance_ctrl_t * p_ctrl);
137 static fsp_err_t iic_master_transfer_open(i2c_master_cfg_t const * const p_cfg);
138 static fsp_err_t iic_master_transfer_configure(transfer_instance_t const * p_transfer,
139 iic_master_transfer_dir_t direction);
140
141 #endif
142
143 /***********************************************************************************************************************
144 * Private global variables
145 **********************************************************************************************************************/
146
147 /***********************************************************************************************************************
148 * Global variables
149 **********************************************************************************************************************/
150
151 /* RIIC Implementation of I2C device master interface */
152 i2c_master_api_t const g_i2c_master_on_iic =
153 {
154 .open = R_RIIC_MASTER_Open,
155 .read = R_RIIC_MASTER_Read,
156 .write = R_RIIC_MASTER_Write,
157 .abort = R_RIIC_MASTER_Abort,
158 .slaveAddressSet = R_RIIC_MASTER_SlaveAddressSet,
159 .close = R_RIIC_MASTER_Close,
160 .statusGet = R_RIIC_MASTER_StatusGet,
161 .callbackSet = R_RIIC_MASTER_CallbackSet
162 };
163
164 /*******************************************************************************************************************//**
165 * @addtogroup RIIC_MASTER
166 * @{
167 **********************************************************************************************************************/
168
169 /***********************************************************************************************************************
170 * Functions
171 **********************************************************************************************************************/
172
173 /*******************************************************************************************************************//**
174 * Opens the I2C device.
175 *
176 * @retval FSP_SUCCESS Requested clock rate was set exactly.
177 * @retval FSP_ERR_ALREADY_OPEN Module is already open.
178 * @retval FSP_ERR_IP_CHANNEL_NOT_PRESENT Channel is not available on this MPU.
179 * @retval FSP_ERR_ASSERTION Parameter check failure due to one or more reasons below:
180 * 1. p_api_ctrl or p_cfg is NULL.
181 * 2. extended parameter is NULL.
182 * 3. Callback parameter is NULL.
183 * 4. Set the rate to fast mode plus on a channel which does not support it.
184 * 5. Invalid IRQ number assigned
185 **********************************************************************************************************************/
R_RIIC_MASTER_Open(i2c_master_ctrl_t * const p_api_ctrl,i2c_master_cfg_t const * const p_cfg)186 fsp_err_t R_RIIC_MASTER_Open (i2c_master_ctrl_t * const p_api_ctrl, i2c_master_cfg_t const * const p_cfg)
187 {
188 iic_master_instance_ctrl_t * p_ctrl = (iic_master_instance_ctrl_t *) p_api_ctrl;
189
190 #if RIIC_MASTER_CFG_PARAM_CHECKING_ENABLE
191 FSP_ASSERT(p_api_ctrl != NULL);
192 FSP_ASSERT(p_cfg != NULL);
193
194 riic_master_extended_cfg_t * p_extend = (riic_master_extended_cfg_t *) p_cfg->p_extend;
195 FSP_ASSERT(p_extend != NULL);
196 FSP_ASSERT(p_cfg->rxi_irq >= (IRQn_Type) 0);
197 FSP_ASSERT(p_cfg->txi_irq >= (IRQn_Type) 0);
198 FSP_ASSERT(p_cfg->tei_irq >= (IRQn_Type) 0);
199 FSP_ASSERT(p_extend->naki_irq >= (IRQn_Type) 0);
200 FSP_ASSERT(p_extend->spi_irq >= (IRQn_Type) 0);
201 FSP_ASSERT(p_extend->sti_irq >= (IRQn_Type) 0);
202 FSP_ASSERT(p_extend->ali_irq >= (IRQn_Type) 0);
203 FSP_ASSERT(p_extend->tmoi_irq >= (IRQn_Type) 0);
204 FSP_ERROR_RETURN(IIC_MASTER_OPEN != p_ctrl->open, FSP_ERR_ALREADY_OPEN);
205
206 FSP_ERROR_RETURN(BSP_FEATURE_IIC_VALID_CHANNEL_MASK & (1 << p_cfg->channel), FSP_ERR_IP_CHANNEL_NOT_PRESENT);
207 #endif
208
209 /* Save register base address. */
210 p_ctrl->p_reg =
211 (R_RIIC0_Type *) ((uint32_t) R_RIIC0 + (p_cfg->channel * ((uint32_t) R_RIIC1 - (uint32_t) R_RIIC0)));
212
213 /* Record the pointer to the configuration structure for later use */
214 p_ctrl->p_cfg = p_cfg;
215 p_ctrl->slave = p_cfg->slave;
216 p_ctrl->addr_mode = p_cfg->addr_mode;
217 p_ctrl->p_callback = p_cfg->p_callback;
218 p_ctrl->p_context = p_cfg->p_context;
219 p_ctrl->p_callback_memory = NULL;
220
221 R_BSP_MODULE_START(FSP_IP_RIIC, p_cfg->channel);
222
223 /* Open the hardware in master mode. */
224 iic_master_open_hw_master(p_ctrl, p_cfg);
225
226 #if RIIC_MASTER_CFG_DMAC_ENABLE
227 fsp_err_t err = FSP_SUCCESS;
228
229 /* Open the IIC transfer interface if available */
230 err = iic_master_transfer_open(p_cfg);
231 if (FSP_SUCCESS != err)
232 {
233 /* module stop */
234 R_BSP_MODULE_STOP(FSP_IP_RIIC, p_ctrl->p_cfg->channel);
235
236 return err;
237 }
238 #endif
239
240 p_ctrl->p_buff = NULL;
241 p_ctrl->total = 0U;
242 p_ctrl->remain = 0U;
243 p_ctrl->loaded = 0U;
244 p_ctrl->read = false;
245 p_ctrl->restart = false;
246 p_ctrl->err = false;
247 p_ctrl->restarted = false;
248 p_ctrl->open = IIC_MASTER_OPEN;
249
250 return FSP_SUCCESS;
251 }
252
253 /*******************************************************************************************************************//**
254 * Performs a read from the I2C device.
255 * The caller will be notified when the operation has completed (successfully) by an
256 * I2C_MASTER_EVENT_RX_COMPLETE in the callback.
257 *
258 * @retval FSP_SUCCESS Function executed without issue.
259 * @retval FSP_ERR_ASSERTION p_api_ctrl, p_dest or bytes is NULL.
260 * @retval FSP_ERR_IN_USE Bus busy condition. Another transfer was in progress.
261 * @retval FSP_ERR_NOT_OPEN Handle is not initialized. Call R_RIIC_MASTER_Open to initialize the control block.
262 **********************************************************************************************************************/
R_RIIC_MASTER_Read(i2c_master_ctrl_t * const p_api_ctrl,uint8_t * const p_dest,uint32_t const bytes,bool const restart)263 fsp_err_t R_RIIC_MASTER_Read (i2c_master_ctrl_t * const p_api_ctrl,
264 uint8_t * const p_dest,
265 uint32_t const bytes,
266 bool const restart)
267 {
268 #if RIIC_MASTER_CFG_PARAM_CHECKING_ENABLE
269 FSP_ASSERT(p_api_ctrl != NULL);
270 FSP_ASSERT(bytes != 0U);
271 #endif
272 fsp_err_t err = FSP_SUCCESS;
273
274 /* Record the restart information about this transfer.
275 * This is done here to keep the parameter (argument) list of iic_master_read_write to 4. */
276 ((iic_master_instance_ctrl_t *) p_api_ctrl)->restart = restart;
277
278 /* Call the common helper function to perform I2C Read operation.*/
279 err = iic_master_read_write(p_api_ctrl, p_dest, bytes, IIC_MASTER_TRANSFER_DIR_READ);
280
281 return err;
282 }
283
284 /*******************************************************************************************************************//**
285 * Performs a write to the I2C device.
286 * The caller will be notified when the operation has completed (successfully) by an
287 * I2C_MASTER_EVENT_TX_COMPLETE in the callback.
288 *
289 * @retval FSP_SUCCESS Function executed without issue.
290 * @retval FSP_ERR_ASSERTION p_api_ctrl or p_src is NULL.
291 * @retval FSP_ERR_IN_USE Bus busy condition. Another transfer was in progress.
292 * @retval FSP_ERR_NOT_OPEN Handle is not initialized. Call R_RIIC_MASTER_Open to initialize the control block.
293 **********************************************************************************************************************/
R_RIIC_MASTER_Write(i2c_master_ctrl_t * const p_api_ctrl,uint8_t * const p_src,uint32_t const bytes,bool const restart)294 fsp_err_t R_RIIC_MASTER_Write (i2c_master_ctrl_t * const p_api_ctrl,
295 uint8_t * const p_src,
296 uint32_t const bytes,
297 bool const restart)
298 {
299 #if RIIC_MASTER_CFG_PARAM_CHECKING_ENABLE
300 FSP_ASSERT(p_api_ctrl != NULL);
301 #endif
302 fsp_err_t err = FSP_SUCCESS;
303
304 /* Record the restart information about this transfer.
305 * This is done here to keep the parameter (argument) list of iic_master_read_write to 4. */
306 ((iic_master_instance_ctrl_t *) p_api_ctrl)->restart = restart;
307
308 /* Call the common helper function to perform I2C Write operation.*/
309 err = iic_master_read_write(p_api_ctrl, p_src, bytes, IIC_MASTER_TRANSFER_DIR_WRITE);
310
311 return err;
312 }
313
314 /*******************************************************************************************************************//**
315 * Safely aborts any in-progress transfer and forces the RIIC peripheral into ready state.
316 *
317 *
318 * @retval FSP_SUCCESS Channel was reset successfully.
319 * @retval FSP_ERR_ASSERTION p_api_ctrl is NULL.
320 * @retval FSP_ERR_NOT_OPEN Handle is not initialized. Call R_RIIC_MASTER_Open to initialize the control block.
321 *
322 * @note A callback will not be invoked in case an in-progress transfer gets aborted by calling this API.
323 **********************************************************************************************************************/
R_RIIC_MASTER_Abort(i2c_master_ctrl_t * const p_api_ctrl)324 fsp_err_t R_RIIC_MASTER_Abort (i2c_master_ctrl_t * const p_api_ctrl)
325 {
326 iic_master_instance_ctrl_t * p_ctrl = (iic_master_instance_ctrl_t *) p_api_ctrl;
327
328 #if RIIC_MASTER_CFG_PARAM_CHECKING_ENABLE
329 FSP_ASSERT(p_ctrl != NULL);
330 FSP_ERROR_RETURN(IIC_MASTER_OPEN == p_ctrl->open, FSP_ERR_NOT_OPEN);
331 #endif
332
333 /* Abort any transfer happening on the channel */
334 iic_master_abort_seq_master(p_ctrl, true);
335
336 return FSP_SUCCESS;
337 }
338
339 /*******************************************************************************************************************//**
340 * Sets address and addressing mode of the slave device.
341 * This function is used to set the device address and addressing mode of the slave
342 * without reconfiguring the entire bus.
343 *
344 * @retval FSP_SUCCESS Address of the slave is set correctly.
345 * @retval FSP_ERR_ASSERTION Pointer to control structure is NULL.
346 * @retval FSP_ERR_IN_USE Another transfer was in-progress.
347 * @retval FSP_ERR_NOT_OPEN Handle is not initialized. Call R_RIIC_MASTER_Open to initialize the control block.
348 **********************************************************************************************************************/
R_RIIC_MASTER_SlaveAddressSet(i2c_master_ctrl_t * const p_api_ctrl,uint32_t const slave,i2c_master_addr_mode_t const addr_mode)349 fsp_err_t R_RIIC_MASTER_SlaveAddressSet (i2c_master_ctrl_t * const p_api_ctrl,
350 uint32_t const slave,
351 i2c_master_addr_mode_t const addr_mode)
352 {
353 iic_master_instance_ctrl_t * p_ctrl = (iic_master_instance_ctrl_t *) p_api_ctrl;
354
355 fsp_err_t err = FSP_SUCCESS;
356
357 #if RIIC_MASTER_CFG_PARAM_CHECKING_ENABLE
358 FSP_ASSERT(p_ctrl != NULL);
359 FSP_ERROR_RETURN(IIC_MASTER_OPEN == p_ctrl->open, FSP_ERR_NOT_OPEN);
360
361 /* Fail if there is already a transfer in progress */
362 FSP_ERROR_RETURN(((0 == p_ctrl->remain) && (false == p_ctrl->restart)), FSP_ERR_IN_USE);
363 #endif
364
365 /* Sets the address of the slave device */
366 p_ctrl->slave = slave;
367
368 /* Sets the mode of addressing */
369 p_ctrl->addr_mode = addr_mode;
370
371 return err;
372 }
373
374 /*******************************************************************************************************************//**
375 * Updates the user callback and has option of providing memory for callback structure.
376 * Implements i2c_master_api_t::callbackSet
377 *
378 * @retval FSP_SUCCESS Callback updated successfully.
379 * @retval FSP_ERR_ASSERTION A required pointer is NULL.
380 * @retval FSP_ERR_NOT_OPEN The control block has not been opened.
381 * @retval FSP_ERR_NO_CALLBACK_MEMORY p_callback is non-secure and p_callback_memory is either secure or NULL.
382 **********************************************************************************************************************/
R_RIIC_MASTER_CallbackSet(i2c_master_ctrl_t * const p_api_ctrl,void (* p_callback)(i2c_master_callback_args_t *),void const * const p_context,i2c_master_callback_args_t * const p_callback_memory)383 fsp_err_t R_RIIC_MASTER_CallbackSet (i2c_master_ctrl_t * const p_api_ctrl,
384 void ( * p_callback)(i2c_master_callback_args_t *),
385 void const * const p_context,
386 i2c_master_callback_args_t * const p_callback_memory)
387 {
388 iic_master_instance_ctrl_t * p_ctrl = (iic_master_instance_ctrl_t *) p_api_ctrl;
389
390 #if (RIIC_MASTER_CFG_PARAM_CHECKING_ENABLE)
391 FSP_ASSERT(p_ctrl);
392 FSP_ASSERT(p_callback);
393 FSP_ERROR_RETURN(IIC_MASTER_OPEN == p_ctrl->open, FSP_ERR_NOT_OPEN);
394 #endif
395
396 #if BSP_TZ_SECURE_BUILD
397
398 /* Get security state of p_callback */
399 bool callback_is_secure =
400 (NULL == cmse_check_address_range((void *) p_callback, sizeof(void *), CMSE_AU_NONSECURE));
401
402 #if RIIC_MASTER_CFG_PARAM_CHECKING_ENABLE
403
404 /* In secure projects, p_callback_memory must be provided in non-secure space if p_callback is non-secure */
405 i2c_master_callback_args_t * const p_callback_memory_checked = cmse_check_pointed_object(p_callback_memory,
406 CMSE_AU_NONSECURE);
407 FSP_ERROR_RETURN(callback_is_secure || (NULL != p_callback_memory_checked), FSP_ERR_NO_CALLBACK_MEMORY);
408 #endif
409 #endif
410
411 /* Store callback and context */
412 #if BSP_TZ_SECURE_BUILD
413 p_ctrl->p_callback = callback_is_secure ? p_callback :
414 (void (*)(i2c_master_callback_args_t *))cmse_nsfptr_create(p_callback);
415 #else
416 p_ctrl->p_callback = p_callback;
417 #endif
418 p_ctrl->p_context = p_context;
419 p_ctrl->p_callback_memory = p_callback_memory;
420
421 return FSP_SUCCESS;
422 }
423
424 /*******************************************************************************************************************//**
425 * Provides driver status.
426 *
427 * @retval FSP_SUCCESS Status stored in p_status.
428 * @retval FSP_ERR_ASSERTION NULL pointer.
429 **********************************************************************************************************************/
R_RIIC_MASTER_StatusGet(i2c_master_ctrl_t * const p_api_ctrl,i2c_master_status_t * p_status)430 fsp_err_t R_RIIC_MASTER_StatusGet (i2c_master_ctrl_t * const p_api_ctrl, i2c_master_status_t * p_status)
431 {
432 iic_master_instance_ctrl_t * p_ctrl = (iic_master_instance_ctrl_t *) p_api_ctrl;
433
434 #if RIIC_MASTER_CFG_PARAM_CHECKING_ENABLE
435 FSP_ASSERT(p_ctrl != NULL);
436 FSP_ASSERT(p_status != NULL);
437 #endif
438
439 p_status->open = (IIC_MASTER_OPEN == p_ctrl->open);
440
441 return FSP_SUCCESS;
442 }
443
444 /*******************************************************************************************************************//**
445 * Closes the I2C device. May power down RIIC peripheral.
446 * This function will safely terminate any in-progress I2C transfers.
447 *
448 * @retval FSP_SUCCESS Device closed without issue.
449 * @retval FSP_ERR_ASSERTION p_api_ctrl is NULL.
450 * @retval FSP_ERR_NOT_OPEN Handle is not initialized. Call R_RIIC_MASTER_Open to initialize the control block.
451 *
452 * @note A callback will not be invoked in case an in-progress transfer gets aborted by calling this API.
453 **********************************************************************************************************************/
R_RIIC_MASTER_Close(i2c_master_ctrl_t * const p_api_ctrl)454 fsp_err_t R_RIIC_MASTER_Close (i2c_master_ctrl_t * const p_api_ctrl)
455 {
456 iic_master_instance_ctrl_t * p_ctrl = (iic_master_instance_ctrl_t *) p_api_ctrl;
457
458 #if RIIC_MASTER_CFG_PARAM_CHECKING_ENABLE
459 FSP_ASSERT(p_ctrl != NULL);
460 FSP_ASSERT(p_ctrl->p_cfg != NULL);
461
462 riic_master_extended_cfg_t * p_extend = (riic_master_extended_cfg_t *) p_ctrl->p_cfg->p_extend;
463 FSP_ASSERT(p_extend != NULL);
464 FSP_ERROR_RETURN(IIC_MASTER_OPEN == p_ctrl->open, FSP_ERR_NOT_OPEN);
465 #else
466 riic_master_extended_cfg_t * p_extend = (riic_master_extended_cfg_t *) p_ctrl->p_cfg->p_extend;
467 #endif
468
469 /* Abort an in-progress transfer with this device only */
470 iic_master_abort_seq_master(p_ctrl, true);
471
472 /* Disable I2C interrupts. Described in hardware manual (see section
473 * 'I2C Bus Interrupt Enable Register (ICIER)' of the user's manual). */
474 p_ctrl->p_reg->ICIER = 0x00000000UL;
475
476 /* The device is now considered closed */
477 p_ctrl->open = 0U;
478
479 #if RIIC_MASTER_CFG_DMAC_ENABLE
480
481 /* Close the handles for the transfer interfaces */
482 if (NULL != p_ctrl->p_cfg->p_transfer_rx)
483 {
484 p_ctrl->p_cfg->p_transfer_rx->p_api->close(p_ctrl->p_cfg->p_transfer_rx->p_ctrl);
485 }
486
487 if (NULL != p_ctrl->p_cfg->p_transfer_tx)
488 {
489 p_ctrl->p_cfg->p_transfer_tx->p_api->close(p_ctrl->p_cfg->p_transfer_tx->p_ctrl);
490 }
491 #endif
492
493 R_BSP_IrqDisable(p_extend->tmoi_irq);
494 R_BSP_IrqDisable(p_extend->ali_irq);
495 R_BSP_IrqDisable(p_extend->sti_irq);
496 R_BSP_IrqDisable(p_extend->spi_irq);
497 R_BSP_IrqDisable(p_extend->naki_irq);
498 R_BSP_IrqDisable(p_ctrl->p_cfg->rxi_irq);
499 R_BSP_IrqDisable(p_ctrl->p_cfg->tei_irq);
500 R_BSP_IrqDisable(p_ctrl->p_cfg->txi_irq);
501
502 /* Remove power to the channel. */
503 R_BSP_MODULE_STOP(FSP_IP_RIIC, p_ctrl->p_cfg->channel);
504
505 return FSP_SUCCESS;
506 }
507
508 /*******************************************************************************************************************//**
509 * @} (end addtogroup RIIC_MASTER)
510 **********************************************************************************************************************/
511
512 /***********************************************************************************************************************
513 * Private Functions
514 **********************************************************************************************************************/
515
516 /*******************************************************************************************************************//**
517 * Helper function for handling I2C Read or Write.
518 *
519 * @param p_api_ctrl Pointer to control block
520 * @param p_buffer Pointer to the buffer to store read/write data.
521 * @param[in] bytes Number of bytes to be read/written.
522 * @param[in] direction Read or Write
523 *
524 * @retval FSP_SUCCESS Function executed successfully.
525 * @retval FSP_ERR_ASSERTION p_api_ctrl or p_buffer is NULL.
526 * @retval FSP_ERR_IN_USE Another transfer was in progress.
527 * @retval FSP_ERR_NOT_OPEN Handle is not initialized. Call R_RIIC_MASTER_Open to initialize the control block.
528 **********************************************************************************************************************/
iic_master_read_write(i2c_master_ctrl_t * const p_api_ctrl,uint8_t * const p_buffer,uint32_t const bytes,iic_master_transfer_dir_t direction)529 static fsp_err_t iic_master_read_write (i2c_master_ctrl_t * const p_api_ctrl,
530 uint8_t * const p_buffer,
531 uint32_t const bytes,
532 iic_master_transfer_dir_t direction)
533 {
534 iic_master_instance_ctrl_t * p_ctrl = (iic_master_instance_ctrl_t *) p_api_ctrl;
535
536 #if RIIC_MASTER_CFG_PARAM_CHECKING_ENABLE
537 FSP_ASSERT(p_buffer != NULL);
538 FSP_ERROR_RETURN((p_ctrl->open == IIC_MASTER_OPEN), FSP_ERR_NOT_OPEN);
539 FSP_ASSERT(((iic_master_instance_ctrl_t *) p_api_ctrl)->p_callback != NULL);
540 #endif
541
542 fsp_err_t err = FSP_SUCCESS;
543
544 p_ctrl->p_buff = p_buffer;
545 p_ctrl->total = bytes;
546 p_ctrl->nack_before_stop = false;
547
548 /* Handle the (different) addressing mode(s) */
549 if (p_ctrl->addr_mode == I2C_MASTER_ADDR_MODE_7BIT)
550 {
551 /* Set the address bytes according to a 7-bit slave read command */
552 p_ctrl->addr_high = 0U;
553 p_ctrl->addr_low = (uint8_t) ((p_ctrl->slave << 1U) | (uint8_t) direction);
554 p_ctrl->addr_total = 1U;
555 }
556
557 #if RIIC_MASTER_CFG_ADDR_MODE_10_BIT_ENABLE
558 else
559 {
560 /* Set the address bytes according to a 10-bit slave read command */
561 p_ctrl->addr_high = (uint8_t) (((p_ctrl->slave >> 7U) | I2C_CODE_10BIT) & (uint8_t) ~(I2C_CODE_READ));
562 p_ctrl->addr_low = (uint8_t) p_ctrl->slave;
563
564 /* Addr total = 3 for Read and 2 for Write.
565 * See section "Communication Data Format" of the user's manual.
566 */
567 p_ctrl->addr_total = (uint8_t) ((uint8_t) direction + IIC_MASTER_SLAVE_10_BIT_ADDR_LEN_ADJUST);
568 }
569 #endif
570
571 p_ctrl->read = (bool) direction;
572
573 /* Kickoff the read operation as a master */
574 err = iic_master_run_hw_master(p_ctrl);
575
576 FSP_ERROR_RETURN(FSP_SUCCESS == err, err);
577
578 return FSP_SUCCESS;
579 }
580
581 /*******************************************************************************************************************//**
582 * Single point for managing the logic around notifying a transfer has finished.
583 *
584 * @param[in] p_ctrl Pointer to transfer that is ending.
585 * @param[in] event The event code to pass to the callback.
586 **********************************************************************************************************************/
iic_master_notify(iic_master_instance_ctrl_t * const p_ctrl,i2c_master_event_t const event)587 static void iic_master_notify (iic_master_instance_ctrl_t * const p_ctrl, i2c_master_event_t const event)
588 {
589 i2c_master_callback_args_t args;
590
591 /* Store callback arguments in memory provided by user if available. This allows callback arguments to be
592 * stored in non-secure memory so they can be accessed by a non-secure callback function. */
593 i2c_master_callback_args_t * p_args = p_ctrl->p_callback_memory;
594 if (NULL == p_args)
595 {
596 /* Store on stack */
597 p_args = &args;
598 }
599 else
600 {
601 /* Save current arguments on the stack in case this is a nested interrupt. */
602 args = *p_args;
603 }
604
605 p_args->p_context = p_ctrl->p_context;
606 p_args->event = event;
607
608 #if RIIC_MASTER_CFG_DMAC_ENABLE
609
610 /* Stop any DMAC assisted transfer for tx */
611 const transfer_instance_t * p_transfer_tx = p_ctrl->p_cfg->p_transfer_tx;
612 if ((NULL != p_transfer_tx) && (!p_ctrl->read))
613 {
614 p_transfer_tx->p_api->disable(p_transfer_tx->p_ctrl);
615 }
616
617 /* Stop any DMAC assisted transfer for rx */
618 const transfer_instance_t * p_transfer_rx = p_ctrl->p_cfg->p_transfer_rx;
619 if ((NULL != p_transfer_rx) && (p_ctrl->read))
620 {
621 p_transfer_rx->p_api->disable(p_transfer_rx->p_ctrl);
622 }
623 #endif
624
625 /* Now do the callback here */
626 #if BSP_TZ_SECURE_BUILD
627
628 /* p_callback can point to a secure function or a non-secure function. */
629 if (!cmse_is_nsfptr(p_ctrl->p_callback))
630 {
631 /* If p_callback is secure, then the project does not need to change security state. */
632 p_ctrl->p_callback(p_args);
633 }
634 else
635 {
636 /* If p_callback is Non-secure, then the project must change to Non-secure state in order to call the callback. */
637 iic_master_prv_ns_callback p_callback = (iic_master_prv_ns_callback) (p_ctrl->p_callback);
638 p_callback(p_args);
639 }
640
641 #else
642 p_ctrl->p_callback(p_args);
643 #endif
644
645 if (NULL != p_ctrl->p_callback_memory)
646 {
647 /* Restore callback memory in case this is a nested interrupt. */
648 *p_ctrl->p_callback_memory = args;
649 }
650
651 /* Clear the err flags */
652 p_ctrl->err = false;
653 }
654
655 /*******************************************************************************************************************//**
656 * Single point for managing the logic around aborting a transfer when operating as a master.
657 *
658 * @param[in] p_ctrl Pointer to control structure of specific device.
659 * @param[in] iic_reset Flag to enable RIIC reset
660 **********************************************************************************************************************/
iic_master_abort_seq_master(iic_master_instance_ctrl_t * const p_ctrl,bool iic_reset)661 static void iic_master_abort_seq_master (iic_master_instance_ctrl_t * const p_ctrl, bool iic_reset)
662 {
663 /* Safely stop the hardware from operating. */
664
665 /* Reset the peripheral */
666 if (true == iic_reset)
667 {
668 /* Disable channel interrupts */
669 p_ctrl->p_reg->ICIER = 0x00000000UL;
670
671 /* This helper function would do a full IIC reset
672 * followed by re-initializing the required peripheral registers. */
673 iic_master_open_hw_master(p_ctrl, p_ctrl->p_cfg);
674 }
675
676 /* Update the transfer descriptor to show no longer in-progress and an error */
677 p_ctrl->remain = 0U;
678
679 /* Update the transfer descriptor to make sure interrupts no longer process */
680 p_ctrl->addr_loaded = p_ctrl->addr_total;
681 p_ctrl->loaded = p_ctrl->total;
682 p_ctrl->restarted = false;
683 p_ctrl->restart = false;
684
685 /* Enable Interrupts: TMOIE, ALIE, NAKIE, RIE, TIE.
686 * Disable Interrupt: TEIE, STIE, SPIE
687 * (see section 'I2C Bus Interrupt Enable Register (ICIER)' of the user's manual).
688 */
689 p_ctrl->p_reg->ICIER = IIC_MASTER_INTERRUPT_ENABLE_INIT_MASK;
690 }
691
692 /*******************************************************************************************************************//**
693 * Performs the hardware initialization sequence when operating as a master.
694 * (see section 'Initial Settings' of the user's manual).
695 *
696 * @param[in] p_ctrl Pointer to RIIC specific control structure
697 * @param[in] p_cfg Pointer to RIIC specific configuration structure.
698 **********************************************************************************************************************/
iic_master_open_hw_master(iic_master_instance_ctrl_t * const p_ctrl,i2c_master_cfg_t const * const p_cfg)699 static void iic_master_open_hw_master (iic_master_instance_ctrl_t * const p_ctrl, i2c_master_cfg_t const * const p_cfg)
700 {
701 riic_master_extended_cfg_t * p_extend = (riic_master_extended_cfg_t *) p_ctrl->p_cfg->p_extend;
702
703 /* Perform RIIC reset */
704 p_ctrl->p_reg->ICCR1 = IIC_MASTER_PRV_SCL_SDA_NOT_DRIVEN;
705
706 /* Reset */
707 p_ctrl->p_reg->ICCR1 =
708 (IIC_MASTER_ICCR1_IICRST_BIT_MASK | IIC_MASTER_PRV_SCL_SDA_NOT_DRIVEN);
709
710 /* Come out of RIIC reset to internal reset */
711 p_ctrl->p_reg->ICCR1 =
712 (IIC_MASTER_ICCR1_ICE_BIT_MASK | IIC_MASTER_ICCR1_IICRST_BIT_MASK |
713 IIC_MASTER_PRV_SCL_SDA_NOT_DRIVEN);
714
715 /* Configure the clock settings. This is set in the configuration structure by the tooling. */
716 /* Set the number of counts that the clock remains low, bit 7 to 5 should be written as 1 */
717 p_ctrl->p_reg->ICBRL =
718 (IIC_MASTER_BUS_RATE_REG_RESERVED_BITS |
719 p_extend->clock_settings.brl_value);
720
721 /* Set the number of counts that the clock remains high, bit 7 to 5 should be written as 1 */
722 p_ctrl->p_reg->ICBRH = (IIC_MASTER_BUS_RATE_REG_RESERVED_BITS |
723 p_extend->clock_settings.brh_value);
724
725 /* Set the internal reference clock source for generating RIIC clock */
726 p_ctrl->p_reg->ICMR1 = (uint8_t) (IIC_MASTER_BUS_MODE_REGISTER_1_MASK |
727 (uint8_t) ((p_extend->
728 clock_settings.
729 cks_value &
730 IIC_MASTER_INTERNAL_REF_CLOCK_SELECT_MAX) << 4U));
731
732 /* Allow timeouts to be generated on the low value of SCL using either long or short mode */
733
734 /* TMOL 'Timeout L Count Control' and TMOH 'Timeout H Count Control' will be set at the time of I2C reset.
735 * This will enable time out detection for both SCLn high and low.
736 * Only Set/Clear TMOS here to select long or short mode.
737 * (see section 'I2C Bus Mode Register 2 (ICMR2)' of the user's manual).
738 */
739 p_ctrl->p_reg->ICMR2 = (uint8_t) (IIC_MASTER_BUS_MODE_REGISTER_2_MASK |
740 (uint8_t) (IIC_MASTER_TIMEOUT_MODE_SHORT == p_extend->timeout_mode) |
741 (uint8_t) (p_extend->timeout_scl_low << R_RIIC0_ICMR2_TMOL_Pos));
742
743 /* ICMR3 Register Settings:
744 * Set Noise Filter Stage Selection.
745 * (see section 'I2C Bus Mode Register 3 (ICMR3)' of the user's manual).
746 */
747 p_ctrl->p_reg->ICMR3 = (0x00UL | (uint8_t) (p_extend->noise_filter_stage - 1U));
748
749 /* ICFER Register Settings:
750 * 1. Enable timeout function.
751 * 2. Enable master arbitration loss detection.
752 * 3. Enable NACK arbitration loss detection.
753 * 4. Disable Slave arbitration loss detection.
754 * 5. Enable NACK reception transfer suspension.
755 * 6. Use the digital noise filter circuit.
756 * 7. Use the SCL synchronous circuit.
757 * 8. Enable FM+ slope circuit if fast mode plus is enabled.
758 * (see section 'I2C Bus Function Enable Register' of the user's manual).
759 */
760 p_ctrl->p_reg->ICFER =
761 ((uint8_t) ((uint8_t) (I2C_MASTER_RATE_FASTPLUS ==
762 p_ctrl->p_cfg->rate) << 7U) |
763 IIC_MASTER_FUNCTION_ENABLE_INIT_SETTINGS);
764
765 /* Ensure the HW is in master mode and does not behave as a slave to another master on the same channel. */
766 p_ctrl->p_reg->ICSER = 0x00000000UL;
767
768 /* Enable Interrupts: TMOIE, ALIE, NAKIE, RIE, TIE.
769 * Disable Interrupt: TEIE, STIE, SPIE
770 * (see section 'I2C Bus Interrupt Enable Register (ICIER)' of the user's manual).
771 */
772 p_ctrl->p_reg->ICIER = IIC_MASTER_INTERRUPT_ENABLE_INIT_MASK;
773
774 /* Set valid interrupt contexts and user provided priority. Enable the interrupts at the NVIC */
775 R_BSP_IrqCfgEnable(p_extend->tmoi_irq, p_cfg->ipl, p_ctrl);
776 R_BSP_IrqCfgEnable(p_extend->ali_irq, p_cfg->ipl, p_ctrl);
777 R_BSP_IrqCfgEnable(p_extend->spi_irq, p_cfg->ipl, p_ctrl);
778 R_BSP_IrqCfgEnable(p_extend->sti_irq, p_cfg->ipl, p_ctrl);
779 R_BSP_IrqCfgEnable(p_extend->naki_irq, p_cfg->ipl, p_ctrl);
780 R_BSP_IrqCfgEnable(p_cfg->txi_irq, p_cfg->ipl, p_ctrl);
781 R_BSP_IrqCfgEnable(p_cfg->tei_irq, p_cfg->ipl, p_ctrl);
782 R_BSP_IrqCfgEnable(p_cfg->rxi_irq, p_cfg->ipl, p_ctrl);
783
784 /* Release RIIC from internal reset */
785
786 /* Reset */
787 p_ctrl->p_reg->ICCR1 = (uint8_t) (IIC_MASTER_ICCR1_ICE_BIT_MASK | IIC_MASTER_PRV_SCL_SDA_NOT_DRIVEN);
788 }
789
790 /*******************************************************************************************************************//**
791 * Performs the data transfer described by the parameters when operating as a master.
792 * See section "Master Transmit Operation" and "Master Receive Operation"
793 * of the user's manual.
794 * @param[in] p_ctrl Pointer to control structure of specific device.
795 *
796 * @retval FSP_SUCCESS Data transfer success.
797 * @retval FSP_ERR_IN_USE If data transfer is in progress.
798 **********************************************************************************************************************/
iic_master_run_hw_master(iic_master_instance_ctrl_t * const p_ctrl)799 static fsp_err_t iic_master_run_hw_master (iic_master_instance_ctrl_t * const p_ctrl)
800 {
801 /* RIICn operates using P0CLK. The ratio I2CLK (System Clock)/(P0CLK/IIC) gives the CPU cycles for 1 ICBRL count.
802 * IIC is division ratio of internal reference clock of RIICn.
803 * The internal reference clock (IIC_CLK) is calculated as P0CLK/IIC.
804 * Since each time we loop the timeout count will be decremented by 1 this would require at least 4 CPU clocks,
805 * making the final timeout count as:
806 * Timeout = ((I2CLK/(IIC_CLK))*ICBRL)/4.
807 */
808 riic_master_extended_cfg_t * p_extend = (riic_master_extended_cfg_t *) p_ctrl->p_cfg->p_extend;
809 uint32_t i2_clk = R_FSP_SystemClockHzGet(FSP_PRIV_CLOCK_I2CLK);
810 uint32_t p0_clk = R_FSP_SystemClockHzGet(FSP_PRIV_CLOCK_P0CLK);
811 uint32_t iic_clk = p0_clk / (1U << p_ctrl->p_reg->ICMR1_b.CKS);
812 uint32_t timeout_count = (i2_clk / iic_clk * p_ctrl->p_reg->ICBRL_b.BRL) >> 2U;
813
814 /* Check if this is a new transaction or a continuation */
815 if (!p_ctrl->restarted)
816 {
817 /* BBSY clearing conditions in section 'I2C Bus Control Register 2 (ICCR2)' of the user's manual,
818 * the BBSY bit is 0 after the bus free time (ICBRL setting)
819 * if a start condition is not detected after a stop condition detection.
820 */
821 IIC_MASTER_HARDWARE_REGISTER_WAIT(p_ctrl->p_reg->ICCR2_b.BBSY, 0UL, timeout_count);
822
823 /* If bus is busy, return error */
824 FSP_ERROR_RETURN((0U != timeout_count), FSP_ERR_IN_USE);
825
826 /* This is not a restarted transaction. Enable TXI for the next transfer.
827 * This had been disabled at the end of TXI interrupt.
828 * The intention is to only enable IIC_MASTER_TXI_EN_BIT.
829 * Writing the whole mask - IIC_MASTER_INTERRUPT_ENABLE_INIT_MASK saves cycles.
830 */
831 p_ctrl->p_reg->ICIER = IIC_MASTER_INTERRUPT_ENABLE_INIT_MASK;
832 }
833
834 /* Initialize fields used during transfer */
835 p_ctrl->addr_loaded = 0U;
836 p_ctrl->loaded = 0U;
837 p_ctrl->remain = p_ctrl->total;
838 p_ctrl->addr_remain = p_ctrl->addr_total;
839 p_ctrl->err = false;
840 p_ctrl->dummy_read_completed = false;
841 p_ctrl->activation_on_rxi = false;
842 p_ctrl->activation_on_txi = false;
843 p_ctrl->address_restarted = false;
844
845 /* Allow timeouts to be generated on the low value of SCL using either short or long mode.
846 * This gets disabled in case the previous transaction issues a restart.
847 */
848
849 /* TMOL 'Timeout L Count Control' and TMOH 'Timeout H Count Control' will be set at the time of I2C reset.
850 * This will enable time out detection for both SCLn high and low.
851 * Only Set/Clear TMOS here to select long or short mode.
852 * (see section 'I2C Bus Mode Register 2 (ICMR2)' of the user's manual).
853 */
854 p_ctrl->p_reg->ICMR2 = (uint8_t) (IIC_MASTER_BUS_MODE_REGISTER_2_MASK |
855 (uint8_t) (IIC_MASTER_TIMEOUT_MODE_SHORT == p_extend->timeout_mode) |
856 (uint8_t) (p_extend->timeout_scl_low << R_RIIC0_ICMR2_TMOL_Pos));
857
858 /* Enable timeout function */
859 p_ctrl->p_reg->ICFER_b.TMOE = 1UL;
860
861 /* Enable TXI. This is treated differently to support restart functionality.
862 * In case the previous RIIC master transaction enabled restart, the queued TXI will fire a this point.
863 *
864 * The TXI had been NVIC-disabled (but Peripheral enabled) before setting the
865 * RS bit by the previous restart enabled transaction.
866 * The RS bit mimics a "stop" followed by a "start" and keeps the bus busy.
867 * As a part of the previous transaction, TXI fires at the peripheral level and is queued at the CPU.
868 *
869 * If the previous transaction was not restart enabled -
870 * NVIC-enable TXI which will fire after the start condition below.
871 */
872 NVIC_EnableIRQ(p_ctrl->p_cfg->txi_irq);
873
874 /* Enable SPIE to detect unexpected STOP condition. This is disabled between communication events as it can lead
875 * to undesired interrupts in multi-master setups. */
876 p_ctrl->p_reg->ICIER = (IIC_MASTER_INTERRUPT_ENABLE_INIT_MASK |
877 R_RIIC0_ICIER_STIE_Msk | R_RIIC0_ICIER_SPIE_Msk);
878
879 /* If previous transaction did not end with restart, send a start condition */
880 if (!p_ctrl->restarted)
881 {
882 /* Request RIIC to issue the start condition */
883 p_ctrl->p_reg->ICCR2 = IIC_MASTER_ICCR2_ST_BIT_MASK;
884 }
885 else
886 {
887 p_ctrl->restarted = false;
888 }
889
890 /*
891 * The Flowchart "Master Transmit Operation" and section "Master Receive Operation"
892 * of the user's manual is covered in the interrupts:
893 *
894 * 1. NACKF processing is handled in the NAKI interrupt.
895 * For receive, dummy reading ICDRR is not required because the NACK processing in this driver resets the RIIC peripheral.
896 * 2. Data is written to ICDRT in the transmit interrupt (TDRE is set when a transmit interrupt fires).
897 * 3. For transmit, stop is issued in the transmit end interrupt (TEND is set when a transmit end interrupt fires).
898 * 4. For transmit, ICSR2 is cleared in the transmit end interrupt.
899 * 5. For receive, remaining processing including reading ICDRR happens in the receive interrupt (RDRF is set when a receive interrupt fires).
900 */
901 return FSP_SUCCESS;
902 }
903
904 /*******************************************************************************************************************//**
905 * Handles the receive data full interrupt when operating as a master.
906 *
907 * @param[in] p_ctrl The target RIIC block's control block.
908 **********************************************************************************************************************/
iic_master_rxi_master(iic_master_instance_ctrl_t * p_ctrl)909 static void iic_master_rxi_master (iic_master_instance_ctrl_t * p_ctrl)
910 {
911 volatile uint8_t dummy_read;
912
913 /* First receive interrupt: Handle the special case of 1 or 2 byte read here */
914 if (false == p_ctrl->dummy_read_completed)
915 {
916 /* Enable WAIT for 1 or 2 byte read */
917 if (2U >= p_ctrl->total)
918 {
919 p_ctrl->p_reg->ICMR3_b.WAIT = 1UL;
920 }
921
922 /* Enable NACK for 1 byte read */
923 if (1U == p_ctrl->remain)
924 {
925 /* Writes to be done separately.
926 * See section 'I2C Bus Mode Register 3 (ICMR3)' of the user's manual.
927 */
928 p_ctrl->p_reg->ICMR3_b.ACKWP = 1UL; /* Write enable ACKBT */
929 p_ctrl->p_reg->ICMR3_b.ACKBT = 1UL;
930 }
931
932 #if RIIC_MASTER_CFG_DMAC_ENABLE
933 uint8_t volatile const * p_iic_master_rx_buffer = &(p_ctrl->p_reg->ICDRR);
934
935 /* Enable transfer support if possible */
936 if ((NULL != p_ctrl->p_cfg->p_transfer_rx) && (p_ctrl->read) && (p_ctrl->total > 3U))
937 {
938 p_ctrl->p_cfg->p_transfer_rx->p_cfg->p_info->p_src = (uint8_t *) (p_iic_master_rx_buffer);
939 p_ctrl->p_cfg->p_transfer_rx->p_cfg->p_info->p_dest = (void *) (p_ctrl->p_buff);
940 p_ctrl->p_cfg->p_transfer_rx->p_cfg->p_info->length = p_ctrl->total - 3U;
941
942 p_ctrl->p_cfg->p_transfer_rx->p_api->reconfigure(p_ctrl->p_cfg->p_transfer_rx->p_ctrl,
943 p_ctrl->p_cfg->p_transfer_rx->p_cfg->p_info);
944
945 p_ctrl->remain = 3U;
946 p_ctrl->loaded = p_ctrl->total - 3U;
947 p_ctrl->activation_on_rxi = true;
948 }
949 #endif
950
951 /* Do a dummy read to clock the data into the ICDRR. */
952 dummy_read = p_ctrl->p_reg->ICDRR_b.DRR;
953 FSP_PARAMETER_NOT_USED(dummy_read);
954
955 /* Update the counter */
956 p_ctrl->dummy_read_completed = true;
957 }
958
959 #if RIIC_MASTER_CFG_DMAC_ENABLE
960
961 /* If this is the interrupt that got fired after DMAC transfer,
962 * ignore it as the DMAC has already taken care of the data transfer */
963 else if (true == p_ctrl->activation_on_rxi)
964 {
965 p_ctrl->activation_on_rxi = false;
966 }
967 #endif
968
969 /* ICDRR contain valid received data */
970 else if (0U < p_ctrl->remain)
971 {
972 iic_master_rxi_read_data(p_ctrl);
973 }
974 else
975 {
976 /* Do nothing */
977 }
978 }
979
980 /*******************************************************************************************************************//**
981 * Handles the transmit data empty interrupt when operating as a master.
982 *
983 * @param[in] p_ctrl The target RIIC block's control block.
984 **********************************************************************************************************************/
iic_master_txi_master(iic_master_instance_ctrl_t * p_ctrl)985 static void iic_master_txi_master (iic_master_instance_ctrl_t * p_ctrl)
986 {
987 /* Check if we are issuing the slave address */
988 if (0U < p_ctrl->addr_remain)
989 {
990 iic_master_txi_send_address(p_ctrl);
991 }
992 else if (!p_ctrl->read)
993 {
994 #if RIIC_MASTER_CFG_DMAC_ENABLE
995
996 /* If this is the interrupt that got fired after DMAC transfer,
997 * ignore it as the DMAC has already taken care of the data transfer */
998 if (true == p_ctrl->activation_on_txi)
999 {
1000 p_ctrl->activation_on_txi = false;
1001 }
1002 else if (p_ctrl->remain > 0U)
1003 #else
1004 if (p_ctrl->remain > 0U)
1005 #endif
1006 {
1007 /* Write the data to ICDRT register */
1008 p_ctrl->p_reg->ICDRT_b.DRT = p_ctrl->p_buff[p_ctrl->loaded];
1009
1010 /* Update the number of bytes remaining for next pass */
1011 p_ctrl->loaded++;
1012 p_ctrl->remain--;
1013 }
1014 else
1015 {
1016 /* Do nothing */
1017 }
1018
1019 /* We are done loading ICDRT, wait for TEND to send a stop/restart */
1020 if (0U == p_ctrl->remain)
1021 {
1022 p_ctrl->p_reg->ICIER_b.TIE = 0UL;
1023
1024 /* Wait for the value to reflect at the peripheral.
1025 * See 'Caution:1' under Table "Interrupt sources" of the user's manual. */
1026 while (0UL != p_ctrl->p_reg->ICIER_b.TIE)
1027 {
1028 /* Do nothing */
1029 }
1030
1031 /* Enable the transmit end IRQ, to issue a STOP or RESTART */
1032 /* Clear any pending TEND interrupts */
1033 R_BSP_IrqStatusClear(p_ctrl->p_cfg->tei_irq);
1034 NVIC_ClearPendingIRQ(p_ctrl->p_cfg->tei_irq);
1035
1036 /* Enable the TXEND interrupt */
1037 p_ctrl->p_reg->ICIER_b.TEIE = 1UL;
1038
1039 /* No need to wait to check TEIE has actually become 1U; because if that's not the case,
1040 * no other operation can occur at this point */
1041 }
1042 }
1043 else
1044 {
1045 /* Do nothing */
1046 }
1047 }
1048
1049 /*******************************************************************************************************************//**
1050 * Handles the transmit end interrupt when operating as a master.
1051 * @note This interrupt is configured to be generated at the end of last byte of the requested transfer.
1052 *
1053 * @param[in] p_ctrl The target RIIC block's control block.
1054 **********************************************************************************************************************/
iic_master_tei_master(iic_master_instance_ctrl_t * p_ctrl)1055 static void iic_master_tei_master (iic_master_instance_ctrl_t * p_ctrl)
1056 {
1057 /* This is a 10 bit address read, issue a restart prior to the last address byte transmission */
1058 if ((p_ctrl->read) && (p_ctrl->addr_remain == 1U) && (false == p_ctrl->address_restarted))
1059 {
1060 #if RIIC_MASTER_CFG_ADDR_MODE_10_BIT_ENABLE
1061
1062 /* Enable TXI so that it fires after restart condition. */
1063 p_ctrl->p_reg->ICIER_b.TIE = 1UL;
1064
1065 /* Request IIC to issue the restart condition */
1066 p_ctrl->p_reg->ICCR2 = IIC_MASTER_ICCR2_RS_BIT_MASK;
1067 p_ctrl->address_restarted = true;
1068 #endif
1069 }
1070 /* We are done with the transfer, send STOP or RESTART */
1071 else if (0U == p_ctrl->remain)
1072 {
1073 /* Send RESTART */
1074 if (p_ctrl->restart)
1075 {
1076 /* NOTE:Only disable in NVIC, disabling in I2C would cause the
1077 * restart condition to fail because we are using the buffered
1078 * interrupt to start the next sequence */
1079 R_BSP_IrqDisable(p_ctrl->p_cfg->txi_irq);
1080 p_ctrl->p_reg->ICIER_b.TIE = 1UL;
1081
1082 /* Request RIIC to issue the restart condition. At this point we will queue a TXI at the NVIC level. */
1083 p_ctrl->p_reg->ICCR2 = IIC_MASTER_ICCR2_RS_BIT_MASK;
1084
1085 /* Disable timeout function */
1086 p_ctrl->p_reg->ICFER_b.TMOE = 0UL;
1087
1088 /* Remember that we issued a restart for the next transfer */
1089 p_ctrl->restarted = true;
1090 }
1091 /* Send STOP */
1092 else
1093 {
1094 /* Clear STOP flag and set SP.
1095 * It is ok to clear other status' as this transaction is over.
1096 */
1097 p_ctrl->p_reg->ICSR2 &= (uint8_t) ~(IIC_MASTER_ICSR2_STOP_BIT);
1098
1099 /* Request RIIC to issue the stop condition */
1100 p_ctrl->p_reg->ICCR2 = IIC_MASTER_ICCR2_SP_BIT_MASK; /* It is safe to write 0's to other bits. */
1101 }
1102 }
1103 else
1104 {
1105 /* Do nothing */
1106 }
1107
1108 /* Disable the interrupt as we are done with the transfer */
1109 p_ctrl->p_reg->ICIER_b.TEIE = 0UL;
1110
1111 /* Wait for the value to reflect at the peripheral. */
1112 while (0UL != p_ctrl->p_reg->ICIER_b.TEIE)
1113 {
1114 /* Do nothing */
1115 }
1116 }
1117
1118 /*******************************************************************************************************************//**
1119 * Handles the reception of NACK interrupt when operating as a master.
1120 *
1121 * @param[in] p_ctrl Pointer to transfer control block
1122 **********************************************************************************************************************/
iic_master_naki_master(iic_master_instance_ctrl_t * p_ctrl)1123 static void iic_master_naki_master (iic_master_instance_ctrl_t * p_ctrl)
1124 {
1125 riic_master_extended_cfg_t * p_extend = (riic_master_extended_cfg_t *) p_ctrl->p_cfg->p_extend;
1126
1127 if ((1UL != p_ctrl->p_reg->ICCR2_b.MST) && (true != p_ctrl->nack_before_stop))
1128 {
1129 p_ctrl->p_reg->ICSR2_b.NACKF = 0UL;
1130
1131 /*This is a NACK error and this device is no longer the active master on the bus.
1132 * The MST bit here can get cleared:
1133 * 1. In case of an arbitration loss error.also occurs.
1134 * 2. If the slave timeout is lesser than master timeout and the slave releases
1135 * the bus by performing an internal reset.
1136 * Refer section "I2C Bus Control Register 2 (ICCR2) - Clearing conditions for MST"
1137 * of the user's manual.
1138 */
1139 p_ctrl->err = true;
1140
1141 /* Abort an in-progress transfer with the current device */
1142 iic_master_abort_seq_master(p_ctrl, true); /* This will reset the RIIC Master driver */
1143 /* Notify anyone waiting that the transfer is Aborted due to error. */
1144 iic_master_notify(p_ctrl, I2C_MASTER_EVENT_ABORTED);
1145 }
1146 else if (true == p_ctrl->nack_before_stop)
1147 {
1148 /* This is the process that branches Reception of NACK interrupt again,
1149 * when Stop Condition was requested once in Reception of NACK interrupt,
1150 * and then ICSR2_b.STOP is not 1 .
1151 */
1152 p_ctrl->nack_before_stop = false;
1153
1154 p_ctrl->p_reg->ICSR2_b.NACKF = 0UL;
1155 }
1156 else
1157 {
1158 /* MST bit must be set to issue a stop condition.
1159 * Refer section "Issuing a Stop Condition" of the user's manual.
1160 */
1161
1162 /* Set the error flag when an error event occurred
1163 * This will be checked after the stop condition is detected from the request below. */
1164 p_ctrl->err = true;
1165
1166 /* The sequence below is to handle a NACK received from slave in the middle of a write.
1167 * See item '[4]' under figure 'Example master transmission flow' of the user's manual. */
1168
1169 /* Request RIIC to issue the stop condition */
1170 p_ctrl->p_reg->ICSR2 &= (uint8_t) ~(IIC_MASTER_ICSR2_STOP_BIT);
1171 p_ctrl->p_reg->ICCR2 = IIC_MASTER_ICCR2_SP_BIT_MASK; /* It is safe to write 0's to other bits. */
1172 /* Allow timeouts to be generated on the low value of SCL using either long or short mode */
1173 p_ctrl->p_reg->ICMR2 = ((uint8_t) 0x02UL |
1174 (uint8_t) (IIC_MASTER_TIMEOUT_MODE_SHORT ==
1175 p_extend->timeout_mode));
1176 p_ctrl->p_reg->ICFER_b.TMOE = 1UL;
1177
1178 /* NACK flag must be cleared after ICSR2_b.STOP=1. */
1179 if (1UL == p_ctrl->p_reg->ICSR2_b.STOP)
1180 {
1181 p_ctrl->p_reg->ICSR2_b.NACKF = 0UL;
1182 }
1183 else
1184 {
1185 /* If the state of ICSR2_b.STOP=1 is not reached by the above process,
1186 * the information that Stop Condition was requested in Reception of NACK interrupt is saved.
1187 */
1188 p_ctrl->nack_before_stop = true;
1189 }
1190 }
1191 }
1192
1193 /*******************************************************************************************************************//**
1194 * Handles the Detection of a stop condition interrupt when operating as a master.
1195 *
1196 * @param[in] p_ctrl Pointer to transfer control block.
1197 **********************************************************************************************************************/
iic_master_spi_master(iic_master_instance_ctrl_t * p_ctrl)1198 static void iic_master_spi_master (iic_master_instance_ctrl_t * p_ctrl)
1199 {
1200 p_ctrl->p_reg->ICSR2_b.STOP = 0UL;
1201 i2c_master_event_t event = I2C_MASTER_EVENT_ABORTED;
1202 if (false == p_ctrl->err) /* Successful transaction */
1203 {
1204 /* Get the correct event to notify the user */
1205 event = (p_ctrl->read) ? I2C_MASTER_EVENT_RX_COMPLETE : I2C_MASTER_EVENT_TX_COMPLETE;
1206
1207 /* Disable SPIE to prevent Detection of a stop condition interrupts in multi-master scenarios */
1208 p_ctrl->p_reg->ICIER_b.SPIE = 0UL;
1209 }
1210 else
1211 {
1212 /* This is the STOP condition requested due to a NACK error earlier.
1213 * Since the stop condition is successfully issued there is no need to reset the driver.
1214 */
1215 iic_master_abort_seq_master(p_ctrl, false); /* Clear the transaction flags only */
1216 }
1217
1218 /* Notify anyone waiting */
1219 iic_master_notify(p_ctrl, event);
1220 }
1221
1222 /*******************************************************************************************************************//**
1223 * Handles the Detection of a start condition interrupt when operating as a master.
1224 *
1225 * @param[in] p_ctrl Pointer to transfer control block.
1226 **********************************************************************************************************************/
iic_master_sti_master(iic_master_instance_ctrl_t * p_ctrl)1227 static void iic_master_sti_master (iic_master_instance_ctrl_t * p_ctrl)
1228 {
1229 p_ctrl->p_reg->ICSR2_b.START = 0UL;
1230 if (p_ctrl->restarted)
1231 {
1232 i2c_master_event_t event = I2C_MASTER_EVENT_ABORTED;
1233 if (false == p_ctrl->err) /* Successful transaction */
1234 {
1235 /* Get the correct event to notify the user */
1236 event = (p_ctrl->read) ? I2C_MASTER_EVENT_RX_COMPLETE : I2C_MASTER_EVENT_TX_COMPLETE;
1237
1238 /* Disable STIE to prevent Detection of a start condition interrupts in multi-master scenarios */
1239 p_ctrl->p_reg->ICIER_b.STIE = 0UL;
1240 }
1241 else
1242 {
1243 /* Do nothing */
1244 }
1245
1246 /* Notify anyone waiting */
1247 iic_master_notify(p_ctrl, event);
1248 }
1249 else
1250 {
1251 /* Do nothing */
1252 }
1253 }
1254
1255 /*******************************************************************************************************************//**
1256 * Handles the Arbitration lost interrupt when operating as a master.
1257 *
1258 * @param[in] p_ctrl Pointer to transfer control block.
1259 **********************************************************************************************************************/
iic_master_ali_master(iic_master_instance_ctrl_t * p_ctrl)1260 static void iic_master_ali_master (iic_master_instance_ctrl_t * p_ctrl)
1261 {
1262 p_ctrl->p_reg->ICSR2_b.AL = 0UL;
1263
1264 /* This is arbitration loss error during an ongoing transaction */
1265 /* Set the error flag when an error event occurred */
1266 p_ctrl->err = true;
1267
1268 /* Abort an in-progress transfer with the current device */
1269 iic_master_abort_seq_master(p_ctrl, true); /* This will reset the RIIC Master driver */
1270 /* Notify anyone waiting that the transfer is Aborted due to error. */
1271 iic_master_notify(p_ctrl, I2C_MASTER_EVENT_ABORTED);
1272 }
1273
1274 /*******************************************************************************************************************//**
1275 * Handles the Timeout interrupt when operating as a master.
1276 *
1277 * @param[in] p_ctrl Pointer to transfer control block.
1278 **********************************************************************************************************************/
iic_master_tmoi_master(iic_master_instance_ctrl_t * p_ctrl)1279 static void iic_master_tmoi_master (iic_master_instance_ctrl_t * p_ctrl)
1280 {
1281 p_ctrl->p_reg->ICSR2_b.TMOF = 0UL;
1282
1283 /* This is Timeout error during an ongoing transaction */
1284 /* Set the error flag when an error event occurred */
1285 p_ctrl->err = true;
1286
1287 /* Abort an in-progress transfer with the current device */
1288 iic_master_abort_seq_master(p_ctrl, true); /* This will reset the RIIC Master driver */
1289 /* Notify anyone waiting that the transfer is Aborted due to error. */
1290 iic_master_notify(p_ctrl, I2C_MASTER_EVENT_ABORTED);
1291 }
1292
1293 /*******************************************************************************************************************//**
1294 * Check valid receive data and set WAIT, NACK and STOP/RESTART bit in RXI handler.
1295 *
1296 * @param[in] p_ctrl Pointer to transfer control block
1297 **********************************************************************************************************************/
iic_master_rxi_read_data(iic_master_instance_ctrl_t * const p_ctrl)1298 static void iic_master_rxi_read_data (iic_master_instance_ctrl_t * const p_ctrl)
1299 {
1300 /* If next data = (final byte - 2), enable WAIT */
1301 if (3U == p_ctrl->remain)
1302 {
1303 p_ctrl->p_reg->ICMR3_b.WAIT = 1UL;
1304 }
1305 /* If next data = (final byte - 1), enable NACK */
1306 else if (2U == p_ctrl->remain)
1307 {
1308 /* Writes to be done separately.
1309 * See Note 1 in section 'I2C Bus Mode Register 3 (ICMR3)' of the user's manual.
1310 */
1311 p_ctrl->p_reg->ICMR3_b.ACKWP = 1UL; /* Write enable ACKBT */
1312 p_ctrl->p_reg->ICMR3_b.ACKBT = 1UL;
1313 }
1314 /* If next data = final byte, send STOP or RESTART */
1315 else if (1U == p_ctrl->remain)
1316 {
1317 if (p_ctrl->restart)
1318 {
1319 /* NOTE:Only disable in NVIC, disabling in I2C would cause the
1320 * restart condition to fail because we are using the buffered
1321 * interrupt to start the next sequence */
1322 R_BSP_IrqDisable(p_ctrl->p_cfg->txi_irq);
1323 p_ctrl->p_reg->ICIER_b.TIE = 1UL;
1324
1325 p_ctrl->p_reg->ICMR3_b.ACKWP = 1UL; /* Write enable ACKBT */
1326
1327 /* This bit clears to 0 automatically by issuing stop condition.
1328 * For restart condition, clear bit by software.
1329 */
1330 p_ctrl->p_reg->ICMR3_b.ACKBT = 0UL;
1331
1332 /* Request RIIC to issue the restart condition */
1333 p_ctrl->p_reg->ICCR2 = IIC_MASTER_ICCR2_RS_BIT_MASK;
1334
1335 /* Disable timeout function */
1336 p_ctrl->p_reg->ICFER_b.TMOE = 0UL;
1337
1338 /* Remember that we issued a restart when doing the next transfer */
1339 p_ctrl->restarted = true;
1340 }
1341 else
1342 {
1343 /* Clear STOP flag and set SP.
1344 * It is ok to clear other status' as this transaction is over.
1345 */
1346 p_ctrl->p_reg->ICSR2 &= (uint8_t) ~(IIC_MASTER_ICSR2_STOP_BIT);;
1347
1348 /* Request RIIC to issue the stop condition */
1349 p_ctrl->p_reg->ICCR2 = IIC_MASTER_ICCR2_SP_BIT_MASK; /* It is safe to write 0's to other bits. */
1350
1351 /* STOP flag will not be set just yet.
1352 * STOP will be set only after reading the last byte from ICDRR and clearing the WAIT.
1353 * See Point #7 under section 'Master Receive Operation' of the user's manual.
1354 */
1355 }
1356 }
1357 else
1358 {
1359 /* Do nothing */
1360 }
1361
1362 p_ctrl->p_buff[p_ctrl->loaded] = p_ctrl->p_reg->ICDRR_b.DRR;
1363
1364 /* Update the counter values */
1365 p_ctrl->loaded++;
1366 p_ctrl->remain--;
1367
1368 /* If we are done with the reception, clear the WAIT bit */
1369 if (0U == p_ctrl->remain)
1370 {
1371 p_ctrl->p_reg->ICMR3_b.WAIT = 0UL;
1372
1373 /* If this transaction does not have the restart flag set to true,
1374 * last byte has been read and WAIT has been cleared.
1375 * Callback will be issued by the SPI once the stop condition is detected
1376 * In case of restart flag set to true a callback will be issued by the STI once the start
1377 * (from restart) condition is detected
1378 */
1379 }
1380 }
1381
1382 /*******************************************************************************************************************//**
1383 * Write the address byte to the iic bus
1384 *
1385 * @param[in] p_ctrl Pointer to transfer control block
1386 **********************************************************************************************************************/
iic_master_txi_send_address(iic_master_instance_ctrl_t * const p_ctrl)1387 static void iic_master_txi_send_address (iic_master_instance_ctrl_t * const p_ctrl)
1388 {
1389 /* This is a 10 bit read and we have transmitted the low byte, next is restart */
1390 if ((3U == p_ctrl->addr_total) && (2U == p_ctrl->addr_loaded) && (false == p_ctrl->address_restarted))
1391 {
1392 #if RIIC_MASTER_CFG_ADDR_MODE_10_BIT_ENABLE
1393
1394 /* For Read operation an extra address byte needs to be sent after issuing restart.
1395 * At this point we have sent the first 2 address bytes. Disable TXI.
1396 */
1397 p_ctrl->p_reg->ICIER_b.TIE = 0UL;
1398
1399 /* Wait for the value to reflect at the peripheral.
1400 * See 'Note' under table "Interrupt sources" of the user's manual. */
1401 while (0UL != p_ctrl->p_reg->ICIER_b.TIE)
1402 {
1403 /* Do nothing */
1404 }
1405
1406 /* Enable the transmit end IRQ, so that we can generate a RESTART condition */
1407 /* Clear any pending TEND interrupts */
1408 R_BSP_IrqStatusClear(p_ctrl->p_cfg->tei_irq);
1409 NVIC_ClearPendingIRQ(p_ctrl->p_cfg->tei_irq);
1410
1411 /* Enable the TXEND interrupt */
1412 p_ctrl->p_reg->ICIER_b.TEIE = 1UL;
1413
1414 /* No need to wait to check TEIE has actually become 1U; because if that's not the case,
1415 * no other operation can occur at this point */
1416 #endif
1417 }
1418 else
1419 {
1420 /* Address low byte, this could either be a 7 bit address or low byte of 10 bit address */
1421 uint8_t address_byte = p_ctrl->addr_low;
1422 #if RIIC_MASTER_CFG_ADDR_MODE_10_BIT_ENABLE
1423
1424 /* 10 bit address, handle accordingly */
1425 if (p_ctrl->addr_total > 1U)
1426 {
1427 /* MSB transfer, send address high byte with with R/W set to 0 */
1428 if (0U == p_ctrl->addr_loaded)
1429 {
1430 address_byte = p_ctrl->addr_high;
1431 }
1432 /* MSB transfer after restart of 10 bit read, send high byte with R/W set to 1 */
1433 else if ((2U == p_ctrl->addr_loaded) && (3U == p_ctrl->addr_total))
1434 {
1435 address_byte = p_ctrl->addr_high | (uint8_t) I2C_CODE_READ;
1436 }
1437 /* Low byte transfer */
1438 else
1439 {
1440 address_byte = p_ctrl->addr_low;
1441 }
1442 }
1443 #endif
1444
1445 #if RIIC_MASTER_CFG_DMAC_ENABLE
1446 uint8_t volatile const * p_iic_master_tx_buffer = &(p_ctrl->p_reg->ICDRT);
1447
1448 /* If this is the last address byte, enable transfer */
1449 if (1U == p_ctrl->addr_remain)
1450 {
1451 if ((NULL != p_ctrl->p_cfg->p_transfer_tx) && !(p_ctrl->read) && (p_ctrl->total > 0U))
1452 {
1453 p_ctrl->p_cfg->p_transfer_tx->p_cfg->p_info->p_src = (void *) (p_ctrl->p_buff);
1454 p_ctrl->p_cfg->p_transfer_tx->p_cfg->p_info->p_dest = (uint8_t *) (p_iic_master_tx_buffer);
1455 p_ctrl->p_cfg->p_transfer_tx->p_cfg->p_info->length = p_ctrl->remain;
1456
1457 p_ctrl->p_cfg->p_transfer_tx->p_api->reconfigure(p_ctrl->p_cfg->p_transfer_tx->p_ctrl,
1458 p_ctrl->p_cfg->p_transfer_tx->p_cfg->p_info);
1459
1460 p_ctrl->remain = 0U;
1461 p_ctrl->loaded = p_ctrl->total;
1462 p_ctrl->activation_on_txi = true;
1463 }
1464 }
1465 #endif
1466
1467 /* Write the address byte */
1468 p_ctrl->p_reg->ICDRT_b.DRT = address_byte;
1469
1470 /* Update the number of address bytes loaded for next pass */
1471 p_ctrl->addr_loaded++;
1472 p_ctrl->addr_remain--;
1473 }
1474 }
1475
1476 #if RIIC_MASTER_CFG_DMAC_ENABLE
1477
1478 /*******************************************************************************************************************//**
1479 * Configures IIC related transfer drivers (if enabled).
1480 *
1481 * @param[in] p_ctrl Pointer to IIC specific control structure
1482 * @param[in] p_cfg Pointer to IIC specific configuration structure
1483 *
1484 * @retval FSP_SUCCESS Transfer interface initialized successfully.
1485 * @retval FSP_ERR_ASSERTION Pointer to transfer instance for I2C receive in p_cfg is NULL.
1486 **********************************************************************************************************************/
iic_master_transfer_open(i2c_master_cfg_t const * const p_cfg)1487 static fsp_err_t iic_master_transfer_open (i2c_master_cfg_t const * const p_cfg)
1488 {
1489 fsp_err_t err = FSP_SUCCESS;
1490
1491 if (NULL != p_cfg->p_transfer_rx)
1492 {
1493 err = iic_master_transfer_configure(p_cfg->p_transfer_rx, IIC_MASTER_TRANSFER_DIR_READ);
1494 FSP_ERROR_RETURN(FSP_SUCCESS == err, err);
1495 }
1496
1497 if (NULL != p_cfg->p_transfer_tx)
1498 {
1499 err = iic_master_transfer_configure(p_cfg->p_transfer_tx, IIC_MASTER_TRANSFER_DIR_WRITE);
1500 if (FSP_SUCCESS != err)
1501 {
1502 if (NULL != p_cfg->p_transfer_rx)
1503 {
1504 p_cfg->p_transfer_rx->p_api->close(p_cfg->p_transfer_rx->p_ctrl);
1505 }
1506
1507 return err;
1508 }
1509 }
1510
1511 return FSP_SUCCESS;
1512 }
1513
1514 /*******************************************************************************************************************//**
1515 * Configures IIC RX related transfer.
1516 * @param[in] p_ctrl Pointer to IIC specific control structure
1517 * @param[in] p_cfg Pointer to IIC specific configuration structure
1518 *
1519 * @retval FSP_SUCCESS Transfer interface is configured with valid parameters.
1520 * @retval FSP_ERR_ASSERTION Pointer to transfer instance for I2C receive in p_cfg is NULL.
1521 **********************************************************************************************************************/
iic_master_transfer_configure(transfer_instance_t const * p_transfer,iic_master_transfer_dir_t direction)1522 static fsp_err_t iic_master_transfer_configure (transfer_instance_t const * p_transfer,
1523 iic_master_transfer_dir_t direction)
1524 {
1525 fsp_err_t err;
1526 FSP_PARAMETER_NOT_USED(direction);
1527
1528 /* Set default transfer info and open receive transfer module, if enabled. */
1529 #if (IIC_MASTER_CFG_PARAM_CHECKING_ENABLE)
1530 FSP_ASSERT(NULL != p_transfer->p_api);
1531 FSP_ASSERT(NULL != p_transfer->p_ctrl);
1532 FSP_ASSERT(NULL != p_transfer->p_cfg);
1533 FSP_ASSERT(NULL != p_transfer->p_cfg->p_info);
1534 #endif
1535
1536 err = p_transfer->p_api->open(p_transfer->p_ctrl, p_transfer->p_cfg);
1537 FSP_ERROR_RETURN((FSP_SUCCESS == err), err);
1538
1539 return FSP_SUCCESS;
1540 }
1541
1542 #endif
1543
1544 /***********************************************************************************************************************
1545 * Interrupt Vectors
1546 **********************************************************************************************************************/
1547
1548 /*******************************************************************************************************************//**
1549 * Receive data full interrupt routine.
1550 *
1551 * This function implements the RIIC Receive buffer full ISR routine.
1552 *
1553 **********************************************************************************************************************/
riic_master_rxi_isr(void)1554 void riic_master_rxi_isr (void)
1555 {
1556 /* Save context if RTOS is used */
1557 FSP_CONTEXT_SAVE
1558 /* Clear the IR flag */
1559 R_BSP_IrqStatusClear(R_FSP_CurrentIrqGet());
1560
1561 IRQn_Type irq = R_FSP_CurrentIrqGet();
1562 iic_master_instance_ctrl_t * p_ctrl = (iic_master_instance_ctrl_t *) R_FSP_IsrContextGet(irq);
1563 iic_master_rxi_master(p_ctrl);
1564
1565 /* Restore context if RTOS is used */
1566 FSP_CONTEXT_RESTORE
1567 }
1568
1569 /*******************************************************************************************************************//**
1570 * Transmit data empty interrupt routine.
1571 *
1572 * This function implements the Transmit buffer empty ISR routine.
1573 *
1574 **********************************************************************************************************************/
riic_master_txi_isr(void)1575 void riic_master_txi_isr (void)
1576 {
1577 /* Save context if RTOS is used */
1578 FSP_CONTEXT_SAVE
1579 /* Clear the IR flag */
1580 R_BSP_IrqStatusClear(R_FSP_CurrentIrqGet());
1581
1582 IRQn_Type irq = R_FSP_CurrentIrqGet();
1583 iic_master_instance_ctrl_t * p_ctrl = (iic_master_instance_ctrl_t *) R_FSP_IsrContextGet(irq);
1584 iic_master_txi_master(p_ctrl);
1585
1586 /* Restore context if RTOS is used */
1587 FSP_CONTEXT_RESTORE
1588 }
1589
1590 /*******************************************************************************************************************//**
1591 * Transmit end interrupt routine.
1592 *
1593 * This function implements the RIIC Transmission End ISR routine.
1594 *
1595 **********************************************************************************************************************/
riic_master_tei_isr(void)1596 void riic_master_tei_isr (void)
1597 {
1598 /* Save context if RTOS is used */
1599 FSP_CONTEXT_SAVE
1600
1601 IRQn_Type irq = R_FSP_CurrentIrqGet();
1602 iic_master_instance_ctrl_t * p_ctrl = (iic_master_instance_ctrl_t *) R_FSP_IsrContextGet(irq);
1603 iic_master_tei_master(p_ctrl);
1604
1605 /* Clear the IR flag */
1606 R_BSP_IrqStatusClear(R_FSP_CurrentIrqGet());
1607
1608 /* Restore context if RTOS is used */
1609 FSP_CONTEXT_RESTORE
1610 }
1611
1612 /*******************************************************************************************************************//**
1613 * NACK reception interrupt routine.
1614 *
1615 * This function implements the RIIC NACK reception ISR routine.
1616 *
1617 **********************************************************************************************************************/
riic_master_naki_isr(void)1618 void riic_master_naki_isr (void)
1619 {
1620 /* Save context if RTOS is used */
1621 FSP_CONTEXT_SAVE
1622
1623 IRQn_Type irq = R_FSP_CurrentIrqGet();
1624 iic_master_instance_ctrl_t * p_ctrl = (iic_master_instance_ctrl_t *) R_FSP_IsrContextGet(irq);
1625 iic_master_naki_master(p_ctrl);
1626
1627 /* Clear the IR flag */
1628 R_BSP_IrqStatusClear(R_FSP_CurrentIrqGet());
1629
1630 /* Restore context if RTOS is used */
1631 FSP_CONTEXT_RESTORE
1632 }
1633
1634 /*******************************************************************************************************************//**
1635 * Stop condition detection interrupt routine.
1636 *
1637 * This function implements the RIIC Stop condition detection ISR routine.
1638 *
1639 **********************************************************************************************************************/
riic_master_spi_isr(void)1640 void riic_master_spi_isr (void)
1641 {
1642 /* Save context if RTOS is used */
1643 FSP_CONTEXT_SAVE
1644
1645 IRQn_Type irq = R_FSP_CurrentIrqGet();
1646 iic_master_instance_ctrl_t * p_ctrl = (iic_master_instance_ctrl_t *) R_FSP_IsrContextGet(irq);
1647 iic_master_spi_master(p_ctrl);
1648
1649 /* Clear the IR flag */
1650 R_BSP_IrqStatusClear(R_FSP_CurrentIrqGet());
1651
1652 /* Restore context if RTOS is used */
1653 FSP_CONTEXT_RESTORE
1654 }
1655
1656 /*******************************************************************************************************************//**
1657 * Start condition detection interrupt routine.
1658 *
1659 * This function implements the RIIC Start condition detection ISR routine.
1660 *
1661 **********************************************************************************************************************/
riic_master_sti_isr(void)1662 void riic_master_sti_isr (void)
1663 {
1664 /* Save context if RTOS is used */
1665 FSP_CONTEXT_SAVE
1666
1667 IRQn_Type irq = R_FSP_CurrentIrqGet();
1668 iic_master_instance_ctrl_t * p_ctrl = (iic_master_instance_ctrl_t *) R_FSP_IsrContextGet(irq);
1669 iic_master_sti_master(p_ctrl);
1670
1671 /* Clear the IR flag */
1672 R_BSP_IrqStatusClear(R_FSP_CurrentIrqGet());
1673
1674 /* Restore context if RTOS is used */
1675 FSP_CONTEXT_RESTORE
1676 }
1677
1678 /*******************************************************************************************************************//**
1679 * Arbitration-Lost interrupt routine.
1680 *
1681 * This function implements the RIIC Arbitration-Lost ISR routine.
1682 *
1683 **********************************************************************************************************************/
riic_master_ali_isr(void)1684 void riic_master_ali_isr (void)
1685 {
1686 /* Save context if RTOS is used */
1687 FSP_CONTEXT_SAVE
1688
1689 IRQn_Type irq = R_FSP_CurrentIrqGet();
1690 iic_master_instance_ctrl_t * p_ctrl = (iic_master_instance_ctrl_t *) R_FSP_IsrContextGet(irq);
1691 iic_master_ali_master(p_ctrl);
1692
1693 /* Clear the IR flag */
1694 R_BSP_IrqStatusClear(R_FSP_CurrentIrqGet());
1695
1696 /* Restore context if RTOS is used */
1697 FSP_CONTEXT_RESTORE
1698 }
1699
1700 /*******************************************************************************************************************//**
1701 * Timeout interrupt routine.
1702 *
1703 * This function implements the RIIC Timeout ISR routine.
1704 *
1705 **********************************************************************************************************************/
riic_master_tmoi_isr(void)1706 void riic_master_tmoi_isr (void)
1707 {
1708 /* Save context if RTOS is used */
1709 FSP_CONTEXT_SAVE
1710
1711 IRQn_Type irq = R_FSP_CurrentIrqGet();
1712 iic_master_instance_ctrl_t * p_ctrl = (iic_master_instance_ctrl_t *) R_FSP_IsrContextGet(irq);
1713 iic_master_tmoi_master(p_ctrl);
1714
1715 /* Clear the IR flag */
1716 R_BSP_IrqStatusClear(R_FSP_CurrentIrqGet());
1717
1718 /* Restore context if RTOS is used */
1719 FSP_CONTEXT_RESTORE
1720 }
1721
1722 #if RIIC_MASTER_CFG_DMAC_ENABLE
1723
1724 /*******************************************************************************************************************//**
1725 * End processing of IIC transmission operation after the end of dmac transfer.
1726 *
1727 * This function implements that IIC transmission interrupt is disabled and transmission end interrupt is enabled.
1728 *
1729 **********************************************************************************************************************/
riic_master_tx_dmac_callback(iic_master_instance_ctrl_t * p_ctrl)1730 void riic_master_tx_dmac_callback (iic_master_instance_ctrl_t * p_ctrl)
1731 {
1732 iic_master_txi_master(p_ctrl);
1733
1734 /* Restore context if RTOS is used */
1735 FSP_CONTEXT_RESTORE
1736 }
1737
1738 /*******************************************************************************************************************//**
1739 * End processing of IIC receive operation after the end of dmac transfer.
1740 *
1741 * This function implements that the remaining 3 bytes of data are read and a stop condition is issued.
1742 *
1743 **********************************************************************************************************************/
riic_master_rx_dmac_callback(iic_master_instance_ctrl_t * p_ctrl)1744 void riic_master_rx_dmac_callback (iic_master_instance_ctrl_t * p_ctrl)
1745 {
1746 iic_master_rxi_master(p_ctrl);
1747
1748 /* Restore context if RTOS is used */
1749 FSP_CONTEXT_RESTORE
1750 }
1751
1752 #endif
1753
