1 /* 2 * Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 /********************************************************************************************************************** 8 * File Name : gtm_iodefine.h 9 * Version : 1.00 10 * Description : IO define file for gtm. 11 *********************************************************************************************************************/ 12 13 /* ================================================================================================================= */ 14 /* ================ Device Specific Cluster Section ====== */ 15 /* ================================================================================================================= */ 16 17 /* ================================================================================================================= */ 18 /* ================ Device Specific Peripheral Section ====== */ 19 /* ================================================================================================================= */ 20 21 #ifndef GTM_IODEFINE_H 22 #define GTM_IODEFINE_H 23 24 typedef struct 25 { 26 union 27 { 28 __IOM uint32_t OSTMnCMP; 29 struct 30 { 31 __IOM uint32_t OSTMnCMP : 32; 32 } OSTMnCMP_b; 33 }; 34 35 union 36 { 37 __IM uint32_t OSTMnCNT; 38 struct 39 { 40 __IM uint32_t OSTMnCNT : 32; 41 } OSTMnCNT_b; 42 }; 43 44 __IM uint8_t RESERVED[8]; 45 union 46 { 47 __IM uint8_t OSTMnTE; 48 struct 49 { 50 __IM uint8_t OSTMnTE : 1; 51 uint8_t : 7; 52 } OSTMnTE_b; 53 }; 54 55 __IM uint8_t RESERVED1[3]; 56 union 57 { 58 __IOM uint8_t OSTMnTS; 59 struct 60 { 61 __OM uint8_t OSTMnTS : 1; 62 uint8_t : 7; 63 } OSTMnTS_b; 64 }; 65 66 __IM uint8_t RESERVED2[3]; 67 union 68 { 69 __IOM uint8_t OSTMnTT; 70 struct 71 { 72 __OM uint8_t OSTMnTT : 1; 73 uint8_t : 7; 74 } OSTMnTT_b; 75 }; 76 77 __IM uint8_t RESERVED3[7]; 78 union 79 { 80 __IOM uint8_t OSTMnCTL; 81 struct 82 { 83 __IOM uint8_t OSTMnMD0 : 1; 84 __IOM uint8_t OSTMnMD1 : 1; 85 uint8_t : 6; 86 } OSTMnCTL_b; 87 }; 88 } R_GTM0_Type; 89 90 /* ================================================================================================================= */ 91 /* ================ Device Specific Peripheral Address Map ====== */ 92 /* ================================================================================================================= */ 93 94 #define R_GTM0_BASE 0x42801000 95 #define R_GTM1_BASE 0x42801400 96 #define R_GTM2_BASE 0x42801800 97 #define R_GTM3_BASE 0x42801C00 98 #define R_GTM4_BASE 0x42802000 99 #define R_GTM5_BASE 0x42802400 100 #define R_GTM6_BASE 0x42802800 101 #define R_GTM7_BASE 0x42802C00 102 103 /* ================================================================================================================= */ 104 /* ================ Peripheral declaration ====== */ 105 /* ================================================================================================================= */ 106 107 #define R_GTM0 ((R_GTM0_Type *) R_GTM0_BASE) 108 #define R_GTM1 ((R_GTM0_Type *) R_GTM1_BASE) 109 #define R_GTM2 ((R_GTM0_Type *) R_GTM2_BASE) 110 #define R_GTM3 ((R_GTM0_Type *) R_GTM3_BASE) 111 #define R_GTM4 ((R_GTM0_Type *) R_GTM4_BASE) 112 #define R_GTM5 ((R_GTM0_Type *) R_GTM5_BASE) 113 #define R_GTM6 ((R_GTM0_Type *) R_GTM6_BASE) 114 #define R_GTM7 ((R_GTM0_Type *) R_GTM7_BASE) 115 116 #endif /* GTM_IODEFINE_H */ 117