1 /* 2 * Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 /********************************************************************************************************************** 8 * File Name : bsp_dmac.h 9 * Version : 1.00 10 * Description : bsp_dmac header 11 *********************************************************************************************************************/ 12 13 #ifndef BSP_DMAC_H 14 #define BSP_DMAC_H 15 16 /********************************************************************************************************************** 17 * Macro definitions 18 *********************************************************************************************************************/ 19 20 /********************************************************************************************************************** 21 * Typedef definitions 22 *********************************************************************************************************************/ 23 24 /********************************************************************************************************************** 25 * Exported global variables 26 *********************************************************************************************************************/ 27 28 /********************************************************************************************************************** 29 * Exported global functions (to be accessed by other files) 30 *********************************************************************************************************************/ 31 32 /********************************************************************************************************************** 33 * @addtogroup BSP_MPU_RZG3S 34 * @{ 35 *********************************************************************************************************************/ 36 37 #define ACK_MODE_LEVEL_MODE (1 << 16) 38 #define ACK_MODE_BUS_CYCLE_MODE (2 << 16) 39 #define ACK_MODE_MASK_DACK_OUTPUT (4 << 16) 40 41 #define DETECTION_RISING_EDGE (2 << 24) 42 #define DETECTION_HIGH_LEVEL (6 << 24) 43 44 #define R_BSP_DMAC_ACTIVATION_SOURCE_ENABLE(unit, channel, activation) {if (0 == (channel / 2)) { \ 45 R_DMAC_B0_EX->DMARS0 &= \ 46 ~((uint32_t) ( \ 47 R_DMAC_B0_EX_DMARS0_CH0_RID_Msk \ 48 | \ 49 R_DMAC_B0_EX_DMARS0_CH0_MID_Msk) \ 50 << (16U * (channel % 2))); \ 51 R_DMAC_B0_EX->DMARS0 |= \ 52 (uint32_t) ((activation \ 53 & ( \ 54 R_DMAC_B0_EX_DMARS0_CH0_RID_Msk \ 55 | \ 56 R_DMAC_B0_EX_DMARS0_CH0_MID_Msk)) \ 57 << \ 58 (16U * \ 59 (channel % \ 60 2))); \ 61 R_DMAC_B0->GRP[channel / \ 62 8].CH[ \ 63 channel % \ 64 8].CHCFG |= \ 65 ((((activation >> 16U) & 0x7U) << \ 66 R_DMAC_B0_GRP_CH_CHCFG_AM_Pos) | \ 67 ((( \ 68 activation \ 69 >> \ 70 24U) & 0x7U) << \ 71 R_DMAC_B0_GRP_CH_CHCFG_LOEN_Pos)); \ 72 } \ 73 else if (1 == (channel / 2)) { \ 74 R_DMAC_B0_EX->DMARS1 &= \ 75 ~((uint32_t) ( \ 76 R_DMAC_B0_EX_DMARS0_CH0_RID_Msk \ 77 | \ 78 R_DMAC_B0_EX_DMARS0_CH0_MID_Msk) \ 79 << (16U * (channel % 2))); \ 80 R_DMAC_B0_EX->DMARS1 |= \ 81 (uint32_t) ((activation \ 82 & ( \ 83 R_DMAC_B0_EX_DMARS0_CH0_RID_Msk \ 84 | \ 85 R_DMAC_B0_EX_DMARS0_CH0_MID_Msk)) \ 86 << \ 87 (16U * \ 88 (channel % \ 89 2))); \ 90 R_DMAC_B0->GRP[channel / \ 91 8].CH[ \ 92 channel % \ 93 8].CHCFG |= \ 94 ((((activation >> 16U) & 0x7U) << \ 95 R_DMAC_B0_GRP_CH_CHCFG_AM_Pos) | \ 96 ((( \ 97 activation \ 98 >> \ 99 24U) & 0x7U) << \ 100 R_DMAC_B0_GRP_CH_CHCFG_LOEN_Pos)); \ 101 } \ 102 else if (2 == (channel / 2)) { \ 103 R_DMAC_B0_EX->DMARS2 &= \ 104 ~((uint32_t) ( \ 105 R_DMAC_B0_EX_DMARS0_CH0_RID_Msk \ 106 | \ 107 R_DMAC_B0_EX_DMARS0_CH0_MID_Msk) \ 108 << (16U * (channel % 2))); \ 109 R_DMAC_B0_EX->DMARS2 |= \ 110 (uint32_t) ((activation \ 111 & ( \ 112 R_DMAC_B0_EX_DMARS0_CH0_RID_Msk \ 113 | \ 114 R_DMAC_B0_EX_DMARS0_CH0_MID_Msk)) \ 115 << \ 116 (16U * \ 117 (channel % \ 118 2))); \ 119 R_DMAC_B0->GRP[channel / \ 120 8].CH[ \ 121 channel % \ 122 8].CHCFG |= \ 123 ((((activation >> 16U) & 0x7U) << \ 124 R_DMAC_B0_GRP_CH_CHCFG_AM_Pos) | \ 125 ((( \ 126 activation \ 127 >> \ 128 24U) & 0x7U) << \ 129 R_DMAC_B0_GRP_CH_CHCFG_LOEN_Pos)); \ 130 } \ 131 else if (3 == (channel / 2)) { \ 132 R_DMAC_B0_EX->DMARS3 &= \ 133 ~((uint32_t) ( \ 134 R_DMAC_B0_EX_DMARS0_CH0_RID_Msk \ 135 | \ 136 R_DMAC_B0_EX_DMARS0_CH0_MID_Msk) \ 137 << (16U * (channel % 2))); \ 138 R_DMAC_B0_EX->DMARS3 |= \ 139 (uint32_t) ((activation \ 140 & ( \ 141 R_DMAC_B0_EX_DMARS0_CH0_RID_Msk \ 142 | \ 143 R_DMAC_B0_EX_DMARS0_CH0_MID_Msk)) \ 144 << \ 145 (16U * \ 146 (channel % \ 147 2))); \ 148 R_DMAC_B0->GRP[channel / \ 149 8].CH[ \ 150 channel % \ 151 8].CHCFG |= \ 152 ((((activation >> 16U) & 0x7U) << \ 153 R_DMAC_B0_GRP_CH_CHCFG_AM_Pos) | \ 154 ((( \ 155 activation \ 156 >> \ 157 24U) & 0x7U) << \ 158 R_DMAC_B0_GRP_CH_CHCFG_LOEN_Pos)); \ 159 } \ 160 else if (4 == (channel / 2)) { \ 161 R_DMAC_B0_EX->DMARS4 &= \ 162 ~((uint32_t) ( \ 163 R_DMAC_B0_EX_DMARS0_CH0_RID_Msk \ 164 | \ 165 R_DMAC_B0_EX_DMARS0_CH0_MID_Msk) \ 166 << (16U * (channel % 2))); \ 167 R_DMAC_B0_EX->DMARS4 |= \ 168 (uint32_t) ((activation \ 169 & ( \ 170 R_DMAC_B0_EX_DMARS0_CH0_RID_Msk \ 171 | \ 172 R_DMAC_B0_EX_DMARS0_CH0_MID_Msk)) \ 173 << \ 174 (16U * \ 175 (channel % \ 176 2))); \ 177 R_DMAC_B0->GRP[channel / \ 178 8].CH[ \ 179 channel % \ 180 8].CHCFG |= \ 181 ((((activation >> 16U) & 0x7U) << \ 182 R_DMAC_B0_GRP_CH_CHCFG_AM_Pos) | \ 183 ((( \ 184 activation \ 185 >> \ 186 24U) & 0x7U) << \ 187 R_DMAC_B0_GRP_CH_CHCFG_LOEN_Pos)); \ 188 } \ 189 else if (5 == (channel / 2)) { \ 190 R_DMAC_B0_EX->DMARS5 &= \ 191 ~((uint32_t) ( \ 192 R_DMAC_B0_EX_DMARS0_CH0_RID_Msk \ 193 | \ 194 R_DMAC_B0_EX_DMARS0_CH0_MID_Msk) \ 195 << (16U * (channel % 2))); \ 196 R_DMAC_B0_EX->DMARS5 |= \ 197 (uint32_t) ((activation \ 198 & ( \ 199 R_DMAC_B0_EX_DMARS0_CH0_RID_Msk \ 200 | \ 201 R_DMAC_B0_EX_DMARS0_CH0_MID_Msk)) \ 202 << \ 203 (16U * \ 204 (channel % \ 205 2))); \ 206 R_DMAC_B0->GRP[channel / \ 207 8].CH[ \ 208 channel % \ 209 8].CHCFG |= \ 210 ((((activation >> 16U) & 0x7U) << \ 211 R_DMAC_B0_GRP_CH_CHCFG_AM_Pos) | \ 212 ((( \ 213 activation \ 214 >> \ 215 24U) & 0x7U) << \ 216 R_DMAC_B0_GRP_CH_CHCFG_LOEN_Pos)); \ 217 } \ 218 else if (6 == (channel / 2)) { \ 219 R_DMAC_B0_EX->DMARS6 &= \ 220 ~((uint32_t) ( \ 221 R_DMAC_B0_EX_DMARS0_CH0_RID_Msk \ 222 | \ 223 R_DMAC_B0_EX_DMARS0_CH0_MID_Msk) \ 224 << (16U * (channel % 2))); \ 225 R_DMAC_B0_EX->DMARS6 |= \ 226 (uint32_t) ((activation \ 227 & ( \ 228 R_DMAC_B0_EX_DMARS0_CH0_RID_Msk \ 229 | \ 230 R_DMAC_B0_EX_DMARS0_CH0_MID_Msk)) \ 231 << \ 232 (16U * \ 233 (channel % \ 234 2))); \ 235 R_DMAC_B0->GRP[channel / \ 236 8].CH[ \ 237 channel % \ 238 8].CHCFG |= \ 239 ((((activation >> 16U) & 0x7U) << \ 240 R_DMAC_B0_GRP_CH_CHCFG_AM_Pos) | \ 241 ((( \ 242 activation \ 243 >> \ 244 24U) & 0x7U) << \ 245 R_DMAC_B0_GRP_CH_CHCFG_LOEN_Pos)); \ 246 } \ 247 else if (7 == (channel / 2)) { \ 248 R_DMAC_B0_EX->DMARS7 &= \ 249 ~((uint32_t) ( \ 250 R_DMAC_B0_EX_DMARS0_CH0_RID_Msk \ 251 | \ 252 R_DMAC_B0_EX_DMARS0_CH0_MID_Msk) \ 253 << (16U * (channel % 2))); \ 254 R_DMAC_B0_EX->DMARS7 |= \ 255 (uint32_t) ((activation \ 256 & ( \ 257 R_DMAC_B0_EX_DMARS0_CH0_RID_Msk \ 258 | \ 259 R_DMAC_B0_EX_DMARS0_CH0_MID_Msk)) \ 260 << \ 261 (16U * \ 262 (channel % \ 263 2))); \ 264 R_DMAC_B0->GRP[channel / \ 265 8].CH[ \ 266 channel % \ 267 8].CHCFG |= \ 268 ((((activation >> 16U) & 0x7U) << \ 269 R_DMAC_B0_GRP_CH_CHCFG_AM_Pos) | \ 270 ((( \ 271 activation \ 272 >> \ 273 24U) & 0x7U) << \ 274 R_DMAC_B0_GRP_CH_CHCFG_LOEN_Pos)); \ 275 } \ 276 else { /* Do nothing */} \ 277 } \ 278 279 280 #define R_BSP_DMAC_ACTIVATION_SOURCE_DISABLE(unit, channel) {if (0 == (channel / 2)) { \ 281 R_DMAC_B0_EX->DMARS0 &= \ 282 (uint32_t) ~(( \ 283 R_DMAC_B0_EX_DMARS0_CH0_RID_Msk \ 284 | \ 285 R_DMAC_B0_EX_DMARS0_CH0_MID_Msk) \ 286 << (16U * \ 287 (channel % 2))); \ 288 } \ 289 else if (1 == (channel / 2)) { \ 290 R_DMAC_B0_EX->DMARS1 &= \ 291 (uint32_t) ~(( \ 292 R_DMAC_B0_EX_DMARS0_CH0_RID_Msk \ 293 | \ 294 R_DMAC_B0_EX_DMARS0_CH0_MID_Msk) \ 295 << (16U * \ 296 (channel % 2))); \ 297 } \ 298 else if (2 == (channel / 2)) { \ 299 R_DMAC_B0_EX->DMARS2 &= \ 300 (uint32_t) ~(( \ 301 R_DMAC_B0_EX_DMARS0_CH0_RID_Msk \ 302 | \ 303 R_DMAC_B0_EX_DMARS0_CH0_MID_Msk) \ 304 << (16U * \ 305 (channel % 2))); \ 306 } \ 307 else if (3 == (channel / 2)) { \ 308 R_DMAC_B0_EX->DMARS3 &= \ 309 (uint32_t) ~(( \ 310 R_DMAC_B0_EX_DMARS0_CH0_RID_Msk \ 311 | \ 312 R_DMAC_B0_EX_DMARS0_CH0_MID_Msk) \ 313 << (16U * \ 314 (channel % 2))); \ 315 } \ 316 else if (4 == (channel / 2)) { \ 317 R_DMAC_B0_EX->DMARS4 &= \ 318 (uint32_t) ~(( \ 319 R_DMAC_B0_EX_DMARS0_CH0_RID_Msk \ 320 | \ 321 R_DMAC_B0_EX_DMARS0_CH0_MID_Msk) \ 322 << (16U * \ 323 (channel % 2))); \ 324 } \ 325 else if (5 == (channel / 2)) { \ 326 R_DMAC_B0_EX->DMARS5 &= \ 327 (uint32_t) ~(( \ 328 R_DMAC_B0_EX_DMARS0_CH0_RID_Msk \ 329 | \ 330 R_DMAC_B0_EX_DMARS0_CH0_MID_Msk) \ 331 << (16U * \ 332 (channel % 2))); \ 333 } \ 334 else if (6 == (channel / 2)) { \ 335 R_DMAC_B0_EX->DMARS6 &= \ 336 (uint32_t) ~(( \ 337 R_DMAC_B0_EX_DMARS0_CH0_RID_Msk \ 338 | \ 339 R_DMAC_B0_EX_DMARS0_CH0_MID_Msk) \ 340 << (16U * \ 341 (channel % 2))); \ 342 } \ 343 else if (7 == (channel / 2)) { \ 344 R_DMAC_B0_EX->DMARS7 &= \ 345 (uint32_t) ~(( \ 346 R_DMAC_B0_EX_DMARS0_CH0_RID_Msk \ 347 | \ 348 R_DMAC_B0_EX_DMARS0_CH0_MID_Msk) \ 349 << (16U * \ 350 (channel % 2))); \ 351 } \ 352 else { /* Do nothing */} \ 353 } \ 354 355 #define R_BSP_DMAC_DREQ_DETECT_METHOD_SELECT(detection, \ 356 activation) { /* No configuration required for this device. */; \ 357 } \ 358 359 #define R_BSP_DMAC_B_TRANSFER_END_DETECT_METHOD_SELECT(unit, channel, \ 360 dmaint_detect) { /* No configuration required for this device. */; \ 361 } \ 362 363 #define R_BSP_DMAC_DREQ_STATUS_CLEAR(activation) { /* No clearing required for this device. */; \ 364 } \ 365 366 typedef enum e_dmac_trigger_event 367 { 368 DMAC_TRIGGER_EVENT_SOFTWARE_TRIGGER = 0, 369 DMAC_TRIGGER_EVENT_GTM_OSTM0TINT = 35 | ACK_MODE_BUS_CYCLE_MODE | DETECTION_RISING_EDGE, 370 DMAC_TRIGGER_EVENT_GTM_OSTM1TINT = 39 | ACK_MODE_BUS_CYCLE_MODE | DETECTION_RISING_EDGE, 371 DMAC_TRIGGER_EVENT_GTM_OSTM2TINT = 43 | ACK_MODE_BUS_CYCLE_MODE | DETECTION_RISING_EDGE, 372 DMAC_TRIGGER_EVENT_GTM_OSTM3TINT = 47 | ACK_MODE_BUS_CYCLE_MODE | DETECTION_RISING_EDGE, 373 DMAC_TRIGGER_EVENT_GTM_OSTM4TINT = 51 | ACK_MODE_BUS_CYCLE_MODE | DETECTION_RISING_EDGE, 374 DMAC_TRIGGER_EVENT_GTM_OSTM5TINT = 55 | ACK_MODE_BUS_CYCLE_MODE | DETECTION_RISING_EDGE, 375 DMAC_TRIGGER_EVENT_GTM_OSTM6TINT = 59 | ACK_MODE_BUS_CYCLE_MODE | DETECTION_RISING_EDGE, 376 DMAC_TRIGGER_EVENT_GTM_OSTM7TINT = 63 | ACK_MODE_BUS_CYCLE_MODE | DETECTION_RISING_EDGE, 377 DMAC_TRIGGER_EVENT_MTU3_TGIA0 = 67 | ACK_MODE_LEVEL_MODE | DETECTION_RISING_EDGE, 378 DMAC_TRIGGER_EVENT_MTU3_TGIB0 = 71 | ACK_MODE_LEVEL_MODE | DETECTION_RISING_EDGE, 379 DMAC_TRIGGER_EVENT_MTU3_TGIC0 = 75 | ACK_MODE_LEVEL_MODE | DETECTION_RISING_EDGE, 380 DMAC_TRIGGER_EVENT_MTU3_TGID0 = 79 | ACK_MODE_LEVEL_MODE | DETECTION_RISING_EDGE, 381 DMAC_TRIGGER_EVENT_MTU3_TGIA1 = 83 | ACK_MODE_LEVEL_MODE | DETECTION_RISING_EDGE, 382 DMAC_TRIGGER_EVENT_MTU3_TGIB1 = 87 | ACK_MODE_LEVEL_MODE | DETECTION_RISING_EDGE, 383 DMAC_TRIGGER_EVENT_MTU3_TGIA2 = 91 | ACK_MODE_LEVEL_MODE | DETECTION_RISING_EDGE, 384 DMAC_TRIGGER_EVENT_MTU3_TGIB2 = 95 | ACK_MODE_LEVEL_MODE | DETECTION_RISING_EDGE, 385 DMAC_TRIGGER_EVENT_MTU3_TGIA3 = 99 | ACK_MODE_LEVEL_MODE | DETECTION_RISING_EDGE, 386 DMAC_TRIGGER_EVENT_MTU3_TGIB3 = 103 | ACK_MODE_LEVEL_MODE | DETECTION_RISING_EDGE, 387 DMAC_TRIGGER_EVENT_MTU3_TGIC3 = 107 | ACK_MODE_LEVEL_MODE | DETECTION_RISING_EDGE, 388 DMAC_TRIGGER_EVENT_MTU3_TGID3 = 111 | ACK_MODE_LEVEL_MODE | DETECTION_RISING_EDGE, 389 DMAC_TRIGGER_EVENT_MTU3_TGIA4 = 115 | ACK_MODE_LEVEL_MODE | DETECTION_RISING_EDGE, 390 DMAC_TRIGGER_EVENT_MTU3_TGIB4 = 119 | ACK_MODE_LEVEL_MODE | DETECTION_RISING_EDGE, 391 DMAC_TRIGGER_EVENT_MTU3_TGIC4 = 123 | ACK_MODE_LEVEL_MODE | DETECTION_RISING_EDGE, 392 DMAC_TRIGGER_EVENT_MTU3_TGID4 = 127 | ACK_MODE_LEVEL_MODE | DETECTION_RISING_EDGE, 393 DMAC_TRIGGER_EVENT_MTU3_TCIV4 = 131 | ACK_MODE_LEVEL_MODE | DETECTION_RISING_EDGE, 394 DMAC_TRIGGER_EVENT_MTU3_TGIU5 = 135 | ACK_MODE_LEVEL_MODE | DETECTION_RISING_EDGE, 395 DMAC_TRIGGER_EVENT_MTU3_TGIV5 = 139 | ACK_MODE_LEVEL_MODE | DETECTION_RISING_EDGE, 396 DMAC_TRIGGER_EVENT_MTU3_TGIW5 = 143 | ACK_MODE_LEVEL_MODE | DETECTION_RISING_EDGE, 397 DMAC_TRIGGER_EVENT_MTU3_TGIA6 = 147 | ACK_MODE_LEVEL_MODE | DETECTION_RISING_EDGE, 398 DMAC_TRIGGER_EVENT_MTU3_TGIB6 = 151 | ACK_MODE_LEVEL_MODE | DETECTION_RISING_EDGE, 399 DMAC_TRIGGER_EVENT_MTU3_TGIC6 = 155 | ACK_MODE_LEVEL_MODE | DETECTION_RISING_EDGE, 400 DMAC_TRIGGER_EVENT_MTU3_TGID6 = 159 | ACK_MODE_LEVEL_MODE | DETECTION_RISING_EDGE, 401 DMAC_TRIGGER_EVENT_MTU3_TGIA7 = 163 | ACK_MODE_LEVEL_MODE | DETECTION_RISING_EDGE, 402 DMAC_TRIGGER_EVENT_MTU3_TGIB7 = 167 | ACK_MODE_LEVEL_MODE | DETECTION_RISING_EDGE, 403 DMAC_TRIGGER_EVENT_MTU3_TGIC7 = 171 | ACK_MODE_LEVEL_MODE | DETECTION_RISING_EDGE, 404 DMAC_TRIGGER_EVENT_MTU3_TGID7 = 175 | ACK_MODE_LEVEL_MODE | DETECTION_RISING_EDGE, 405 DMAC_TRIGGER_EVENT_MTU3_TCIV7 = 179 | ACK_MODE_LEVEL_MODE | DETECTION_RISING_EDGE, 406 DMAC_TRIGGER_EVENT_MTU3_TGIA8 = 183 | ACK_MODE_LEVEL_MODE | DETECTION_RISING_EDGE, 407 DMAC_TRIGGER_EVENT_MTU3_TGIB8 = 187 | ACK_MODE_LEVEL_MODE | DETECTION_RISING_EDGE, 408 DMAC_TRIGGER_EVENT_MTU3_TGIC8 = 191 | ACK_MODE_LEVEL_MODE | DETECTION_RISING_EDGE, 409 DMAC_TRIGGER_EVENT_MTU3_TGID8 = 195 | ACK_MODE_LEVEL_MODE | DETECTION_RISING_EDGE, 410 DMAC_TRIGGER_EVENT_GPT_CCMPA0 = 199 | ACK_MODE_LEVEL_MODE | DETECTION_RISING_EDGE, 411 DMAC_TRIGGER_EVENT_GPT_CCMPB0 = 203 | ACK_MODE_LEVEL_MODE | DETECTION_RISING_EDGE, 412 DMAC_TRIGGER_EVENT_GPT_CMPC0 = 207 | ACK_MODE_LEVEL_MODE | DETECTION_RISING_EDGE, 413 DMAC_TRIGGER_EVENT_GPT_CMPD0 = 211 | ACK_MODE_LEVEL_MODE | DETECTION_RISING_EDGE, 414 DMAC_TRIGGER_EVENT_GPT_CMPE0 = 215 | ACK_MODE_LEVEL_MODE | DETECTION_RISING_EDGE, 415 DMAC_TRIGGER_EVENT_GPT_CMPF0 = 219 | ACK_MODE_LEVEL_MODE | DETECTION_RISING_EDGE, 416 DMAC_TRIGGER_EVENT_GPT_ADTRGA0 = 223 | ACK_MODE_LEVEL_MODE | DETECTION_RISING_EDGE, 417 DMAC_TRIGGER_EVENT_GPT_ADTRGB0 = 227 | ACK_MODE_LEVEL_MODE | DETECTION_RISING_EDGE, 418 DMAC_TRIGGER_EVENT_GPT_OVF0 = 231 | ACK_MODE_LEVEL_MODE | DETECTION_RISING_EDGE, 419 DMAC_TRIGGER_EVENT_GPT_UNF0 = 235 | ACK_MODE_LEVEL_MODE | DETECTION_RISING_EDGE, 420 DMAC_TRIGGER_EVENT_GPT_CCMPA1 = 251 | ACK_MODE_LEVEL_MODE | DETECTION_RISING_EDGE, 421 DMAC_TRIGGER_EVENT_GPT_CCMPB1 = 255 | ACK_MODE_LEVEL_MODE | DETECTION_RISING_EDGE, 422 DMAC_TRIGGER_EVENT_GPT_CMPC1 = 259 | ACK_MODE_LEVEL_MODE | DETECTION_RISING_EDGE, 423 DMAC_TRIGGER_EVENT_GPT_CMPD1 = 263 | ACK_MODE_LEVEL_MODE | DETECTION_RISING_EDGE, 424 DMAC_TRIGGER_EVENT_GPT_CMPE1 = 267 | ACK_MODE_LEVEL_MODE | DETECTION_RISING_EDGE, 425 DMAC_TRIGGER_EVENT_GPT_CMPF1 = 271 | ACK_MODE_LEVEL_MODE | DETECTION_RISING_EDGE, 426 DMAC_TRIGGER_EVENT_GPT_ADTRGA1 = 275 | ACK_MODE_LEVEL_MODE | DETECTION_RISING_EDGE, 427 DMAC_TRIGGER_EVENT_GPT_ADTRGB1 = 279 | ACK_MODE_LEVEL_MODE | DETECTION_RISING_EDGE, 428 DMAC_TRIGGER_EVENT_GPT_OVF1 = 283 | ACK_MODE_LEVEL_MODE | DETECTION_RISING_EDGE, 429 DMAC_TRIGGER_EVENT_GPT_UNF1 = 287 | ACK_MODE_LEVEL_MODE | DETECTION_RISING_EDGE, 430 DMAC_TRIGGER_EVENT_GPT_CCMPA2 = 303 | ACK_MODE_LEVEL_MODE | DETECTION_RISING_EDGE, 431 DMAC_TRIGGER_EVENT_GPT_CCMPB2 = 307 | ACK_MODE_LEVEL_MODE | DETECTION_RISING_EDGE, 432 DMAC_TRIGGER_EVENT_GPT_CMPC2 = 311 | ACK_MODE_LEVEL_MODE | DETECTION_RISING_EDGE, 433 DMAC_TRIGGER_EVENT_GPT_CMPD2 = 315 | ACK_MODE_LEVEL_MODE | DETECTION_RISING_EDGE, 434 DMAC_TRIGGER_EVENT_GPT_CMPE2 = 319 | ACK_MODE_LEVEL_MODE | DETECTION_RISING_EDGE, 435 DMAC_TRIGGER_EVENT_GPT_CMPF2 = 323 | ACK_MODE_LEVEL_MODE | DETECTION_RISING_EDGE, 436 DMAC_TRIGGER_EVENT_GPT_ADTRGA2 = 327 | ACK_MODE_LEVEL_MODE | DETECTION_RISING_EDGE, 437 DMAC_TRIGGER_EVENT_GPT_ADTRGB2 = 331 | ACK_MODE_LEVEL_MODE | DETECTION_RISING_EDGE, 438 DMAC_TRIGGER_EVENT_GPT_OVF2 = 335 | ACK_MODE_LEVEL_MODE | DETECTION_RISING_EDGE, 439 DMAC_TRIGGER_EVENT_GPT_UNF2 = 339 | ACK_MODE_LEVEL_MODE | DETECTION_RISING_EDGE, 440 DMAC_TRIGGER_EVENT_GPT_CCMPA3 = 355 | ACK_MODE_LEVEL_MODE | DETECTION_RISING_EDGE, 441 DMAC_TRIGGER_EVENT_GPT_CCMPB3 = 359 | ACK_MODE_LEVEL_MODE | DETECTION_RISING_EDGE, 442 DMAC_TRIGGER_EVENT_GPT_CMPC3 = 363 | ACK_MODE_LEVEL_MODE | DETECTION_RISING_EDGE, 443 DMAC_TRIGGER_EVENT_GPT_CMPD3 = 367 | ACK_MODE_LEVEL_MODE | DETECTION_RISING_EDGE, 444 DMAC_TRIGGER_EVENT_GPT_CMPE3 = 371 | ACK_MODE_LEVEL_MODE | DETECTION_RISING_EDGE, 445 DMAC_TRIGGER_EVENT_GPT_CMPF3 = 375 | ACK_MODE_LEVEL_MODE | DETECTION_RISING_EDGE, 446 DMAC_TRIGGER_EVENT_GPT_ADTRGA3 = 379 | ACK_MODE_LEVEL_MODE | DETECTION_RISING_EDGE, 447 DMAC_TRIGGER_EVENT_GPT_ADTRGB3 = 384 | ACK_MODE_LEVEL_MODE | DETECTION_RISING_EDGE, 448 DMAC_TRIGGER_EVENT_GPT_OVF3 = 387 | ACK_MODE_LEVEL_MODE | DETECTION_RISING_EDGE, 449 DMAC_TRIGGER_EVENT_GPT_UNF3 = 391 | ACK_MODE_LEVEL_MODE | DETECTION_RISING_EDGE, 450 DMAC_TRIGGER_EVENT_GPT_CCMPA4 = 407 | ACK_MODE_LEVEL_MODE | DETECTION_RISING_EDGE, 451 DMAC_TRIGGER_EVENT_GPT_CCMPB4 = 411 | ACK_MODE_LEVEL_MODE | DETECTION_RISING_EDGE, 452 DMAC_TRIGGER_EVENT_GPT_CMPC4 = 415 | ACK_MODE_LEVEL_MODE | DETECTION_RISING_EDGE, 453 DMAC_TRIGGER_EVENT_GPT_CMPD4 = 419 | ACK_MODE_LEVEL_MODE | DETECTION_RISING_EDGE, 454 DMAC_TRIGGER_EVENT_GPT_CMPE4 = 423 | ACK_MODE_LEVEL_MODE | DETECTION_RISING_EDGE, 455 DMAC_TRIGGER_EVENT_GPT_CMPF4 = 427 | ACK_MODE_LEVEL_MODE | DETECTION_RISING_EDGE, 456 DMAC_TRIGGER_EVENT_GPT_ADTRGA4 = 431 | ACK_MODE_LEVEL_MODE | DETECTION_RISING_EDGE, 457 DMAC_TRIGGER_EVENT_GPT_ADTRGB4 = 435 | ACK_MODE_LEVEL_MODE | DETECTION_RISING_EDGE, 458 DMAC_TRIGGER_EVENT_GPT_OVF4 = 439 | ACK_MODE_LEVEL_MODE | DETECTION_RISING_EDGE, 459 DMAC_TRIGGER_EVENT_GPT_UNF4 = 443 | ACK_MODE_LEVEL_MODE | DETECTION_RISING_EDGE, 460 DMAC_TRIGGER_EVENT_GPT_CCMPA5 = 459 | ACK_MODE_LEVEL_MODE | DETECTION_RISING_EDGE, 461 DMAC_TRIGGER_EVENT_GPT_CCMPB5 = 463 | ACK_MODE_LEVEL_MODE | DETECTION_RISING_EDGE, 462 DMAC_TRIGGER_EVENT_GPT_CMPC5 = 467 | ACK_MODE_LEVEL_MODE | DETECTION_RISING_EDGE, 463 DMAC_TRIGGER_EVENT_GPT_CMPD5 = 471 | ACK_MODE_LEVEL_MODE | DETECTION_RISING_EDGE, 464 DMAC_TRIGGER_EVENT_GPT_CMPE5 = 475 | ACK_MODE_LEVEL_MODE | DETECTION_RISING_EDGE, 465 DMAC_TRIGGER_EVENT_GPT_CMPF5 = 479 | ACK_MODE_LEVEL_MODE | DETECTION_RISING_EDGE, 466 DMAC_TRIGGER_EVENT_GPT_ADTRGA5 = 483 | ACK_MODE_LEVEL_MODE | DETECTION_RISING_EDGE, 467 DMAC_TRIGGER_EVENT_GPT_ADTRGB5 = 487 | ACK_MODE_LEVEL_MODE | DETECTION_RISING_EDGE, 468 DMAC_TRIGGER_EVENT_GPT_OVF5 = 491 | ACK_MODE_LEVEL_MODE | DETECTION_RISING_EDGE, 469 DMAC_TRIGGER_EVENT_GPT_UNF5 = 495 | ACK_MODE_LEVEL_MODE | DETECTION_RISING_EDGE, 470 DMAC_TRIGGER_EVENT_GPT_CCMPA6 = 511 | ACK_MODE_LEVEL_MODE | DETECTION_RISING_EDGE, 471 DMAC_TRIGGER_EVENT_GPT_CCMPB6 = 515 | ACK_MODE_LEVEL_MODE | DETECTION_RISING_EDGE, 472 DMAC_TRIGGER_EVENT_GPT_CMPC6 = 519 | ACK_MODE_LEVEL_MODE | DETECTION_RISING_EDGE, 473 DMAC_TRIGGER_EVENT_GPT_CMPD6 = 523 | ACK_MODE_LEVEL_MODE | DETECTION_RISING_EDGE, 474 DMAC_TRIGGER_EVENT_GPT_CMPE6 = 527 | ACK_MODE_LEVEL_MODE | DETECTION_RISING_EDGE, 475 DMAC_TRIGGER_EVENT_GPT_CMPF6 = 531 | ACK_MODE_LEVEL_MODE | DETECTION_RISING_EDGE, 476 DMAC_TRIGGER_EVENT_GPT_ADTRGA6 = 535 | ACK_MODE_LEVEL_MODE | DETECTION_RISING_EDGE, 477 DMAC_TRIGGER_EVENT_GPT_ADTRGB6 = 539 | ACK_MODE_LEVEL_MODE | DETECTION_RISING_EDGE, 478 DMAC_TRIGGER_EVENT_GPT_OVF6 = 543 | ACK_MODE_LEVEL_MODE | DETECTION_RISING_EDGE, 479 DMAC_TRIGGER_EVENT_GPT_UNF6 = 547 | ACK_MODE_LEVEL_MODE | DETECTION_RISING_EDGE, 480 DMAC_TRIGGER_EVENT_GPT_CCMPA7 = 563 | ACK_MODE_LEVEL_MODE | DETECTION_RISING_EDGE, 481 DMAC_TRIGGER_EVENT_GPT_CCMPB7 = 567 | ACK_MODE_LEVEL_MODE | DETECTION_RISING_EDGE, 482 DMAC_TRIGGER_EVENT_GPT_CMPC7 = 571 | ACK_MODE_LEVEL_MODE | DETECTION_RISING_EDGE, 483 DMAC_TRIGGER_EVENT_GPT_CMPD7 = 575 | ACK_MODE_LEVEL_MODE | DETECTION_RISING_EDGE, 484 DMAC_TRIGGER_EVENT_GPT_CMPE7 = 579 | ACK_MODE_LEVEL_MODE | DETECTION_RISING_EDGE, 485 DMAC_TRIGGER_EVENT_GPT_CMPF7 = 583 | ACK_MODE_LEVEL_MODE | DETECTION_RISING_EDGE, 486 DMAC_TRIGGER_EVENT_GPT_ADTRGA7 = 587 | ACK_MODE_LEVEL_MODE | DETECTION_RISING_EDGE, 487 DMAC_TRIGGER_EVENT_GPT_ADTRGB7 = 591 | ACK_MODE_LEVEL_MODE | DETECTION_RISING_EDGE, 488 DMAC_TRIGGER_EVENT_GPT_OVF7 = 595 | ACK_MODE_LEVEL_MODE | DETECTION_RISING_EDGE, 489 DMAC_TRIGGER_EVENT_GPT_UNF7 = 599 | ACK_MODE_LEVEL_MODE | DETECTION_RISING_EDGE, 490 DMAC_TRIGGER_EVENT_SSIF_DMA_RX0 = 614 | ACK_MODE_BUS_CYCLE_MODE | DETECTION_RISING_EDGE, 491 DMAC_TRIGGER_EVENT_SSIF_DMA_TX0 = 613 | ACK_MODE_BUS_CYCLE_MODE | DETECTION_RISING_EDGE, 492 DMAC_TRIGGER_EVENT_SSIF_DMA_RX1 = 618 | ACK_MODE_BUS_CYCLE_MODE | DETECTION_RISING_EDGE, 493 DMAC_TRIGGER_EVENT_SSIF_DMA_TX1 = 617 | ACK_MODE_BUS_CYCLE_MODE | DETECTION_RISING_EDGE, 494 DMAC_TRIGGER_EVENT_SSIF_DMA_RX2 = 622 | ACK_MODE_BUS_CYCLE_MODE | DETECTION_RISING_EDGE, 495 DMAC_TRIGGER_EVENT_SSIF_DMA_TX2 = 621 | ACK_MODE_BUS_CYCLE_MODE | DETECTION_RISING_EDGE, 496 DMAC_TRIGGER_EVENT_SSIF_DMA_RX3 = 626 | ACK_MODE_BUS_CYCLE_MODE | DETECTION_RISING_EDGE, 497 DMAC_TRIGGER_EVENT_SSIF_DMA_TX3 = 625 | ACK_MODE_BUS_CYCLE_MODE | DETECTION_RISING_EDGE, 498 DMAC_TRIGGER_EVENT_SRC_IDEI = 630 | ACK_MODE_BUS_CYCLE_MODE | DETECTION_RISING_EDGE, 499 DMAC_TRIGGER_EVENT_SRC_ODFI = 629 | ACK_MODE_BUS_CYCLE_MODE | DETECTION_RISING_EDGE, 500 DMAC_TRIGGER_EVENT_I2C_INTRIIC_RI0 = 650 | ACK_MODE_BUS_CYCLE_MODE | DETECTION_RISING_EDGE, 501 DMAC_TRIGGER_EVENT_I2C_INTRIIC_TI0 = 649 | ACK_MODE_BUS_CYCLE_MODE | DETECTION_RISING_EDGE, 502 DMAC_TRIGGER_EVENT_I2C_INTRIIC_RI1 = 654 | ACK_MODE_BUS_CYCLE_MODE | DETECTION_RISING_EDGE, 503 DMAC_TRIGGER_EVENT_I2C_INTRIIC_TI1 = 653 | ACK_MODE_BUS_CYCLE_MODE | DETECTION_RISING_EDGE, 504 DMAC_TRIGGER_EVENT_I2C_INTRIIC_RI2 = 658 | ACK_MODE_BUS_CYCLE_MODE | DETECTION_RISING_EDGE, 505 DMAC_TRIGGER_EVENT_I2C_INTRIIC_TI2 = 657 | ACK_MODE_BUS_CYCLE_MODE | DETECTION_RISING_EDGE, 506 DMAC_TRIGGER_EVENT_I2C_INTRIIC_RI3 = 662 | ACK_MODE_BUS_CYCLE_MODE | DETECTION_RISING_EDGE, 507 DMAC_TRIGGER_EVENT_I2C_INTRIIC_TI3 = 661 | ACK_MODE_BUS_CYCLE_MODE | DETECTION_RISING_EDGE, 508 DMAC_TRIGGER_EVENT_I3C_INTRESP = 667 | ACK_MODE_MASK_DACK_OUTPUT | DETECTION_RISING_EDGE, 509 DMAC_TRIGGER_EVENT_I3C_INTCMD = 671 | ACK_MODE_MASK_DACK_OUTPUT | DETECTION_RISING_EDGE, 510 DMAC_TRIGGER_EVENT_I3C_INTIBI = 675 | ACK_MODE_MASK_DACK_OUTPUT | DETECTION_RISING_EDGE, 511 DMAC_TRIGGER_EVENT_I3C_INTRX = 678 | ACK_MODE_MASK_DACK_OUTPUT | DETECTION_RISING_EDGE, 512 DMAC_TRIGGER_EVENT_I3C_INTTX = 677 | ACK_MODE_MASK_DACK_OUTPUT | DETECTION_RISING_EDGE, 513 DMAC_TRIGGER_EVENT_I3C_INTRCV = 683 | ACK_MODE_MASK_DACK_OUTPUT | DETECTION_RISING_EDGE, 514 DMAC_TRIGGER_EVENT_I3C_INTHRESP = 687 | ACK_MODE_MASK_DACK_OUTPUT | DETECTION_RISING_EDGE, 515 DMAC_TRIGGER_EVENT_I3C_INTHCMD = 691 | ACK_MODE_MASK_DACK_OUTPUT | DETECTION_RISING_EDGE, 516 DMAC_TRIGGER_EVENT_I3C_INTHRX = 694 | ACK_MODE_MASK_DACK_OUTPUT | DETECTION_RISING_EDGE, 517 DMAC_TRIGGER_EVENT_I3C_INTHTX = 693 | ACK_MODE_MASK_DACK_OUTPUT | DETECTION_RISING_EDGE, 518 DMAC_TRIGGER_EVENT_SCIF_RXI0 = 698 | ACK_MODE_MASK_DACK_OUTPUT | DETECTION_HIGH_LEVEL, 519 DMAC_TRIGGER_EVENT_SCIF_TXI0 = 697 | ACK_MODE_MASK_DACK_OUTPUT | DETECTION_HIGH_LEVEL, 520 DMAC_TRIGGER_EVENT_SCIF_RXI1 = 702 | ACK_MODE_MASK_DACK_OUTPUT | DETECTION_HIGH_LEVEL, 521 DMAC_TRIGGER_EVENT_SCIF_TXI1 = 701 | ACK_MODE_MASK_DACK_OUTPUT | DETECTION_HIGH_LEVEL, 522 DMAC_TRIGGER_EVENT_SCIF_RXI2 = 706 | ACK_MODE_MASK_DACK_OUTPUT | DETECTION_HIGH_LEVEL, 523 DMAC_TRIGGER_EVENT_SCIF_TXI2 = 705 | ACK_MODE_MASK_DACK_OUTPUT | DETECTION_HIGH_LEVEL, 524 DMAC_TRIGGER_EVENT_SCIF_RXI3 = 710 | ACK_MODE_MASK_DACK_OUTPUT | DETECTION_HIGH_LEVEL, 525 DMAC_TRIGGER_EVENT_SCIF_TXI3 = 709 | ACK_MODE_MASK_DACK_OUTPUT | DETECTION_HIGH_LEVEL, 526 DMAC_TRIGGER_EVENT_SCIF_RXI4 = 714 | ACK_MODE_MASK_DACK_OUTPUT | DETECTION_HIGH_LEVEL, 527 DMAC_TRIGGER_EVENT_SCIF_TXI4 = 713 | ACK_MODE_MASK_DACK_OUTPUT | DETECTION_HIGH_LEVEL, 528 DMAC_TRIGGER_EVENT_SCIF_RXI5 = 718 | ACK_MODE_MASK_DACK_OUTPUT | DETECTION_HIGH_LEVEL, 529 DMAC_TRIGGER_EVENT_SCIF_TXI5 = 717 | ACK_MODE_MASK_DACK_OUTPUT | DETECTION_HIGH_LEVEL, 530 DMAC_TRIGGER_EVENT_SCIg_RXI0 = 722 | ACK_MODE_BUS_CYCLE_MODE | DETECTION_HIGH_LEVEL, 531 DMAC_TRIGGER_EVENT_SCIg_TXI0 = 721 | ACK_MODE_BUS_CYCLE_MODE | DETECTION_HIGH_LEVEL, 532 DMAC_TRIGGER_EVENT_SCIg_RXI1 = 726 | ACK_MODE_BUS_CYCLE_MODE | DETECTION_HIGH_LEVEL, 533 DMAC_TRIGGER_EVENT_SCIg_TXI1 = 725 | ACK_MODE_BUS_CYCLE_MODE | DETECTION_HIGH_LEVEL, 534 DMAC_TRIGGER_EVENT_RSPI_SPRI0 = 730 | ACK_MODE_BUS_CYCLE_MODE | DETECTION_HIGH_LEVEL, 535 DMAC_TRIGGER_EVENT_RSPI_SPTI0 = 729 | ACK_MODE_BUS_CYCLE_MODE | DETECTION_HIGH_LEVEL, 536 DMAC_TRIGGER_EVENT_RSPI_SPRI1 = 734 | ACK_MODE_BUS_CYCLE_MODE | DETECTION_HIGH_LEVEL, 537 DMAC_TRIGGER_EVENT_RSPI_SPTI1 = 733 | ACK_MODE_BUS_CYCLE_MODE | DETECTION_HIGH_LEVEL, 538 DMAC_TRIGGER_EVENT_RSPI_SPRI2 = 738 | ACK_MODE_BUS_CYCLE_MODE | DETECTION_HIGH_LEVEL, 539 DMAC_TRIGGER_EVENT_RSPI_SPTI2 = 737 | ACK_MODE_BUS_CYCLE_MODE | DETECTION_HIGH_LEVEL, 540 DMAC_TRIGGER_EVENT_RSPI_SPRI3 = 742 | ACK_MODE_BUS_CYCLE_MODE | DETECTION_HIGH_LEVEL, 541 DMAC_TRIGGER_EVENT_RSPI_SPTI3 = 741 | ACK_MODE_BUS_CYCLE_MODE | DETECTION_HIGH_LEVEL, 542 DMAC_TRIGGER_EVENT_RSPI_SPRI4 = 746 | ACK_MODE_BUS_CYCLE_MODE | DETECTION_HIGH_LEVEL, 543 DMAC_TRIGGER_EVENT_RSPI_SPTI4 = 745 | ACK_MODE_BUS_CYCLE_MODE | DETECTION_HIGH_LEVEL, 544 DMAC_TRIGGER_EVENT_CANFD_RXF_DMA0 = 751 | ACK_MODE_LEVEL_MODE | DETECTION_RISING_EDGE, 545 DMAC_TRIGGER_EVENT_CANFD_RXF_DMA1 = 755 | ACK_MODE_LEVEL_MODE | DETECTION_RISING_EDGE, 546 DMAC_TRIGGER_EVENT_CANFD_RXF_DMA2 = 759 | ACK_MODE_LEVEL_MODE | DETECTION_RISING_EDGE, 547 DMAC_TRIGGER_EVENT_CANFD_RXF_DMA3 = 763 | ACK_MODE_LEVEL_MODE | DETECTION_RISING_EDGE, 548 DMAC_TRIGGER_EVENT_CANFD_RXF_DMA4 = 767 | ACK_MODE_LEVEL_MODE | DETECTION_RISING_EDGE, 549 DMAC_TRIGGER_EVENT_CANFD_RXF_DMA5 = 771 | ACK_MODE_LEVEL_MODE | DETECTION_RISING_EDGE, 550 DMAC_TRIGGER_EVENT_CANFD_RXF_DMA6 = 775 | ACK_MODE_LEVEL_MODE | DETECTION_RISING_EDGE, 551 DMAC_TRIGGER_EVENT_CANFD_RXF_DMA7 = 779 | ACK_MODE_LEVEL_MODE | DETECTION_RISING_EDGE, 552 DMAC_TRIGGER_EVENT_CANFD_COM_DMA0 = 783 | ACK_MODE_LEVEL_MODE | DETECTION_RISING_EDGE, 553 DMAC_TRIGGER_EVENT_CANFD_COM_DMA1 = 787 | ACK_MODE_LEVEL_MODE | DETECTION_RISING_EDGE, 554 DMAC_TRIGGER_EVENT_SPDIF_RBDMAREQN_TX = 633 | ACK_MODE_LEVEL_MODE | DETECTION_HIGH_LEVEL, 555 DMAC_TRIGGER_EVENT_SPDIF_RBDMAREQN_RX = 634 | ACK_MODE_LEVEL_MODE | DETECTION_HIGH_LEVEL, 556 DMAC_TRIGGER_EVENT_PDM_INT_PDM_DAT0 = 639 | ACK_MODE_MASK_DACK_OUTPUT | DETECTION_HIGH_LEVEL, 557 DMAC_TRIGGER_EVENT_PDM_INT_PDM_DAT1 = 643 | ACK_MODE_MASK_DACK_OUTPUT | DETECTION_HIGH_LEVEL, 558 DMAC_TRIGGER_EVENT_PDM_INT_PDM_DAT2 = 647 | ACK_MODE_MASK_DACK_OUTPUT | DETECTION_HIGH_LEVEL, 559 } dmac_trigger_event_t; 560 561 /** @} (end addtogroup BSP_MPU_RZG3S) */ 562 563 #endif /* BSP_DMAC_H */ 564
