1 /*
2 * Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 /***********************************************************************************************************************
8 * Includes <System Includes> , "Project Includes"
9 **********************************************************************************************************************/
10 #include "bsp_api.h"
11
12 /***********************************************************************************************************************
13 * Macro definitions
14 **********************************************************************************************************************/
15 #define BSP_RESET_MRCTL_BIT_SHIFT_MASK (0x0000001FU)
16 #define BSP_RESET_MRCTL_SELECT_MASK (0x001F0000U)
17 #define BSP_RESET_MRCTL_REGION_SELECT_MASK (0x00400000U)
18
19 #define BSP_RESET_RMR_RESET_REQUEST_AARCH64 (0x3)
20
21 /***********************************************************************************************************************
22 * Typedef definitions
23 **********************************************************************************************************************/
24
25 /***********************************************************************************************************************
26 * Exported global variables (to be accessed by other files)
27 **********************************************************************************************************************/
28
29 /***********************************************************************************************************************
30 * Private global variables and functions
31 **********************************************************************************************************************/
32
33 /*******************************************************************************************************************//**
34 * @addtogroup BSP_MCU
35 *
36 * @{
37 **********************************************************************************************************************/
38
39 /*******************************************************************************************************************//**
40 * Occur the system software reset.
41 **********************************************************************************************************************/
R_BSP_SystemReset(void)42 void R_BSP_SystemReset (void)
43 {
44 R_BSP_RegisterProtectDisable(BSP_REG_PROTECT_LPC_RESET);
45
46 /* System software reset. */
47 R_SYSC_S->SWRSYS = BSP_PRV_RESET_KEY;
48 }
49
50 /*******************************************************************************************************************//**
51 * Occur the CPU software reset.
52 *
53 * @param[in] cpu to be reset state.
54 *
55 * @note With Cortex-A55, you cannot use resets that are not automatically released when a software reset is executed.
56 **********************************************************************************************************************/
R_BSP_CPUReset(bsp_reset_t cpu)57 void R_BSP_CPUReset (bsp_reset_t cpu)
58 {
59 R_BSP_RegisterProtectDisable(BSP_REG_PROTECT_LPC_RESET);
60
61 if (BSP_RESET_CR52_0 == cpu)
62 {
63 /* CR52_0 software reset. */
64 R_SYSC_S->SWRCPU0 = BSP_PRV_RESET_KEY;
65
66 R_BSP_RegisterProtectEnable(BSP_REG_PROTECT_LPC_RESET);
67
68 #if defined(BSP_CFG_CORE_CR52) && (0 == BSP_CFG_CORE_CR52)
69 __asm volatile ("WFI");
70 #endif
71 }
72
73 #if (1U < BSP_FEATURE_BSP_CR52_CORE_NUM)
74 else if (BSP_RESET_CR52_1 == cpu)
75 {
76 /* CR52_1 software reset. */
77 R_SYSC_S->SWRCPU1 = BSP_PRV_RESET_KEY;
78
79 R_BSP_RegisterProtectEnable(BSP_REG_PROTECT_LPC_RESET);
80
81 #if defined(BSP_CFG_CORE_CR52) && (1 == BSP_CFG_CORE_CR52)
82 __asm volatile ("WFI");
83 #endif
84 }
85 #endif
86 #if (1U < BSP_FEATURE_BSP_CA55_CORE_NUM)
87 else if (BSP_RESET_CA55_CLUSTER == cpu)
88 {
89 /* CA55_cluster software reset. */
90 R_SYSC_S->SWR55C = BSP_PRV_RESET_KEY;
91
92 R_BSP_RegisterProtectEnable(BSP_REG_PROTECT_LPC_RESET);
93 }
94 #endif
95 else
96 {
97 R_BSP_RegisterProtectEnable(BSP_REG_PROTECT_LPC_RESET);
98 }
99 }
100
101 /*******************************************************************************************************************//**
102 * Occur the CPU software reset. When using this function, the CPU reset state is automatically released
103 * after an elapsed time corresponding to the setting value in SCKCR2.DIVSELSUB bit.
104 *
105 * @param[in] cpu to be reset state.
106 **********************************************************************************************************************/
R_BSP_CPUResetAutoRelease(bsp_reset_t cpu)107 void R_BSP_CPUResetAutoRelease (bsp_reset_t cpu)
108 {
109 R_BSP_RegisterProtectDisable(BSP_REG_PROTECT_LPC_RESET);
110
111 if (BSP_RESET_CR52_0 == cpu)
112 {
113 /* CR52_0 software reset. */
114 R_SYSC_S->SWRCPU0 = BSP_PRV_RESET_KEY_AUTO_RELEASE;
115
116 R_BSP_RegisterProtectEnable(BSP_REG_PROTECT_LPC_RESET);
117
118 #if defined(BSP_CFG_CORE_CR52) && (0 == BSP_CFG_CORE_CR52)
119 __asm volatile ("WFI");
120 #endif
121 }
122
123 #if (1U < BSP_FEATURE_BSP_CR52_CORE_NUM)
124 else if (BSP_RESET_CR52_1 == cpu)
125 {
126 /* CR52_1 software reset. */
127 R_SYSC_S->SWRCPU1 = BSP_PRV_RESET_KEY_AUTO_RELEASE;
128
129 R_BSP_RegisterProtectEnable(BSP_REG_PROTECT_LPC_RESET);
130
131 #if defined(BSP_CFG_CORE_CR52) && (1 == BSP_CFG_CORE_CR52)
132 __asm volatile ("WFI");
133 #endif
134 }
135 #endif
136 #if (1U < BSP_FEATURE_BSP_CA55_CORE_NUM)
137 else if (BSP_RESET_CA55_CLUSTER == cpu)
138 {
139 /* CA55_cluster software reset. */
140 R_SYSC_S->SWR55C = BSP_PRV_RESET_KEY_AUTO_RELEASE;
141
142 R_BSP_RegisterProtectEnable(BSP_REG_PROTECT_LPC_RESET);
143 }
144 #if defined(BSP_CFG_CORE_CA55)
145 else if (BSP_RESET_CA55_0 == cpu)
146 {
147 /* CA55_0 software reset. */
148 __asm volatile (
149 "MOV x0, %0 \n"
150 "MSR RMR_EL3, x0 \n"
151 ::"r" (BSP_RESET_RMR_RESET_REQUEST_AARCH64) : "memory");
152
153 R_BSP_RegisterProtectEnable(BSP_REG_PROTECT_LPC_RESET);
154
155 #if (0 == BSP_CFG_CORE_CA55)
156 __asm volatile ("WFI");
157 #endif
158 }
159 else if (BSP_RESET_CA55_1 == cpu)
160 {
161 /* CA55_1 software reset. */
162 __asm volatile (
163 "MOV x0, %0 \n"
164 "MSR RMR_EL3, x0 \n"
165 ::"r" (BSP_RESET_RMR_RESET_REQUEST_AARCH64) : "memory");
166
167 R_BSP_RegisterProtectEnable(BSP_REG_PROTECT_LPC_RESET);
168
169 #if (1 == BSP_CFG_CORE_CA55)
170 __asm volatile ("WFI");
171 #endif
172 }
173 else if (BSP_RESET_CA55_2 == cpu)
174 {
175 /* CA55_2 software reset. */
176 __asm volatile (
177 "MOV x0, %0 \n"
178 "MSR RMR_EL3, x0 \n"
179 ::"r" (BSP_RESET_RMR_RESET_REQUEST_AARCH64) : "memory");
180
181 R_BSP_RegisterProtectEnable(BSP_REG_PROTECT_LPC_RESET);
182
183 #if (2 == BSP_CFG_CORE_CA55)
184 __asm volatile ("WFI");
185 #endif
186 }
187 else if (BSP_RESET_CA55_3 == cpu)
188 {
189 /* CA55_3 software reset. */
190 __asm volatile (
191 "MOV x0, %0 \n"
192 "MSR RMR_EL3, x0 \n"
193 ::"r" (BSP_RESET_RMR_RESET_REQUEST_AARCH64) : "memory");
194
195 R_BSP_RegisterProtectEnable(BSP_REG_PROTECT_LPC_RESET);
196
197 #if (3 == BSP_CFG_CORE_CA55)
198 __asm volatile ("WFI");
199 #endif
200 }
201 #endif
202 #endif
203 else
204 {
205 R_BSP_RegisterProtectEnable(BSP_REG_PROTECT_LPC_RESET);
206 }
207 }
208
209 /*******************************************************************************************************************//**
210 * Release the CPU reset state.
211 *
212 * @param[in] cpu to be release reset state.
213 **********************************************************************************************************************/
R_BSP_CPUResetRelease(bsp_reset_t cpu)214 void R_BSP_CPUResetRelease (bsp_reset_t cpu)
215 {
216 R_BSP_RegisterProtectDisable(BSP_REG_PROTECT_LPC_RESET);
217
218 if (BSP_RESET_CR52_0 == cpu)
219 {
220 /* Release CR52_0 reset state. */
221 R_SYSC_S->SWRCPU0 = BSP_PRV_RESET_RELEASE_KEY;
222 }
223
224 #if (1U < BSP_FEATURE_BSP_CR52_CORE_NUM)
225 else if (BSP_RESET_CR52_1 == cpu)
226 {
227 /* Release CR52_1 reset state. */
228 R_SYSC_S->SWRCPU1 = BSP_PRV_RESET_RELEASE_KEY;
229 }
230 #endif
231 #if (1U < BSP_FEATURE_BSP_CA55_CORE_NUM)
232 else if (BSP_RESET_CA55_CLUSTER == cpu)
233 {
234 /* Release CA55_cluster software reset. */
235 R_SYSC_S->SWR55C = BSP_PRV_RESET_RELEASE_KEY;
236 }
237 else if (BSP_RESET_CA55_0 == cpu)
238 {
239 /* Release CA55_0 reset state. */
240 R_SYSC_S->SWR550 = BSP_PRV_RESET_RELEASE_KEY;
241 }
242 else if (BSP_RESET_CA55_1 == cpu)
243 {
244 /* Release CA55_1 reset state. */
245 R_SYSC_S->SWR551 = BSP_PRV_RESET_RELEASE_KEY;
246 }
247 else if (BSP_RESET_CA55_2 == cpu)
248 {
249 /* Release CA55_2 reset state. */
250 R_SYSC_S->SWR552 = BSP_PRV_RESET_RELEASE_KEY;
251 }
252 else if (BSP_RESET_CA55_3 == cpu)
253 {
254 /* Release CA55_3 reset state. */
255 R_SYSC_S->SWR553 = BSP_PRV_RESET_RELEASE_KEY;
256 }
257 #endif
258 else
259 {
260 /* Do Nothing. */
261 }
262
263 R_BSP_RegisterProtectEnable(BSP_REG_PROTECT_LPC_RESET);
264 }
265
266 #if (1U < BSP_FEATURE_BSP_CA55_CORE_NUM)
267
268 /*******************************************************************************************************************//**
269 * Controls whether the core is automatically released from reset when a CA55 cluster reset is performed.
270 *
271 * @param[in] cpu to be release reset state.
272 * @param[in] release Enable/disable automatic reset release.
273 **********************************************************************************************************************/
R_BSP_CPUClusterResetAutoReleaseControl(bsp_reset_t cpu,bsp_cluster_reset_auto_release_t release)274 void R_BSP_CPUClusterResetAutoReleaseControl (bsp_reset_t cpu, bsp_cluster_reset_auto_release_t release)
275 {
276 R_BSP_RegisterProtectDisable(BSP_REG_PROTECT_LPC_RESET);
277
278 if (BSP_RESET_CA55_0 == cpu)
279 {
280 /* Controls the automatic reset release of CA55_0. */
281 R_SYSC_S->SWR55ARC_b.ARC550 = release;
282 }
283 else if (BSP_RESET_CA55_1 == cpu)
284 {
285 /* Controls the automatic reset release of CA55_1. */
286 R_SYSC_S->SWR55ARC_b.ARC551 = release;
287 }
288 else if (BSP_RESET_CA55_2 == cpu)
289 {
290 /* Controls the automatic reset release of CA55_2. */
291 R_SYSC_S->SWR55ARC_b.ARC552 = release;
292 }
293 else if (BSP_RESET_CA55_3 == cpu)
294 {
295 /* Controls the automatic reset release of CA55_3. */
296 R_SYSC_S->SWR55ARC_b.ARC553 = release;
297 }
298 else
299 {
300 /* Do Nothing. */
301 }
302
303 R_BSP_RegisterProtectEnable(BSP_REG_PROTECT_LPC_RESET);
304 }
305
306 #endif
307
308 /*******************************************************************************************************************//**
309 * Enable module reset state.
310 *
311 * @param[in] module_to_enable Modules to enable module reset state.
312 **********************************************************************************************************************/
R_BSP_ModuleResetEnable(bsp_module_reset_t module_to_enable)313 void R_BSP_ModuleResetEnable (bsp_module_reset_t module_to_enable)
314 {
315 volatile uint32_t mrctl;
316 uint32_t * p_reg;
317
318 /** When MRCTLn register exists in the safety region,
319 * it is necessary to add an offset of safety region. */
320 p_reg = (uint32_t *) &R_SYSC_NS->MRCTLA +
321 (((module_to_enable & BSP_RESET_MRCTL_SELECT_MASK) >> 16U) +
322 (module_to_enable & BSP_RESET_MRCTL_REGION_SELECT_MASK));
323 mrctl = 1U << (module_to_enable & BSP_RESET_MRCTL_BIT_SHIFT_MASK);
324
325 /** Enable module reset state using MRCTLE register. */
326 *p_reg |= mrctl;
327
328 /** To ensure processing after module reset. */
329 mrctl = *(volatile uint32_t *) (p_reg);
330 }
331
332 /*******************************************************************************************************************//**
333 * Disable module reset state.
334 *
335 * @param[in] module_to_disable Modules to disable module reset state.
336 *
337 * @note After reset release is performed by the module control register, a dummy read is performed to allow access
338 * to other than the RTC and LCDC. This is done several times according to the RZ microprocessor manual.
339 * However, the dummy read count for the RTC and LCDC may not be met depending on the device used.
340 * In that case, please perform additional dummy read processing after API execution.
341 * For example, in the case of RZN2H, 300 dummy reads are required for RTC and
342 * 100 dummy reads are required for LCDC.
343 *
344 **********************************************************************************************************************/
R_BSP_ModuleResetDisable(bsp_module_reset_t module_to_disable)345 void R_BSP_ModuleResetDisable (bsp_module_reset_t module_to_disable)
346 {
347 volatile uint32_t mrctl;
348 uint32_t * p_reg;
349
350 /** When MRCTLn register exists in the safety region,
351 * it is necessary to add an offset of safety region. */
352 p_reg = (uint32_t *) &R_SYSC_NS->MRCTLA +
353 (((module_to_disable & BSP_RESET_MRCTL_SELECT_MASK) >> 16U) +
354 (module_to_disable & BSP_RESET_MRCTL_REGION_SELECT_MASK));
355 mrctl = 1U << (module_to_disable & BSP_RESET_MRCTL_BIT_SHIFT_MASK);
356
357 /** Disable module stop state using MRCTLn register. */
358 *p_reg &= ~mrctl;
359
360 /** In order to secure processing after release from module reset,
361 * dummy read the same register.
362 * Refer to "Notes on Module Reset Control Register Operation" of the RZ microprocessor manual. */
363 uint32_t dummy_read_cnt = BSP_FEATURE_BSP_MODULE_RESET_DUMMY_READ_COUNT;
364
365 while (dummy_read_cnt)
366 {
367 mrctl = *(volatile uint32_t *) (p_reg);
368 dummy_read_cnt--;
369 }
370 }
371
372 /** @} (end addtogroup BSP_MCU) */
373
