1 /***************************************************************************//** 2 * \file cyip_tdm.h 3 * 4 * \brief 5 * TDM IP definitions 6 * 7 ******************************************************************************** 8 * \copyright 9 * (c) (2016-2023), Cypress Semiconductor Corporation (an Infineon company) or 10 * an affiliate of Cypress Semiconductor Corporation. 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 *******************************************************************************/ 26 27 #ifndef _CYIP_TDM_H_ 28 #define _CYIP_TDM_H_ 29 30 #include "cyip_headers.h" 31 32 /******************************************************************************* 33 * TDM 34 *******************************************************************************/ 35 36 #define TDM_TDM_STRUCT_TDM_TX_STRUCT_SECTION_SIZE 0x00000100UL 37 #define TDM_TDM_STRUCT_TDM_RX_STRUCT_SECTION_SIZE 0x00000100UL 38 #define TDM_TDM_STRUCT_SECTION_SIZE 0x00000200UL 39 #define TDM_SECTION_SIZE 0x00010000UL 40 41 /** 42 * \brief TDM TX structure (TDM_TDM_STRUCT_TDM_TX_STRUCT) 43 */ 44 typedef struct { 45 __IOM uint32_t TX_CTL; /*!< 0x00000000 TX control */ 46 __IM uint32_t RESERVED[3]; 47 __IOM uint32_t TX_IF_CTL; /*!< 0x00000010 TX interface control */ 48 __IOM uint32_t TX_CH_CTL; /*!< 0x00000014 TX channel control */ 49 __IM uint32_t RESERVED1[2]; 50 __IOM uint32_t TX_TEST_CTL; /*!< 0x00000020 TX test control */ 51 __IOM uint32_t TX_ROUTE_CTL; /*!< 0x00000024 TX route control */ 52 __IM uint32_t RESERVED2[22]; 53 __IOM uint32_t TX_FIFO_CTL; /*!< 0x00000080 TX FIFO control */ 54 __IM uint32_t TX_FIFO_STATUS; /*!< 0x00000084 TX FIFO status */ 55 __OM uint32_t TX_FIFO_WR; /*!< 0x00000088 TX FIFO write */ 56 __IM uint32_t RESERVED3[13]; 57 __IOM uint32_t INTR_TX; /*!< 0x000000C0 Interrupt */ 58 __IOM uint32_t INTR_TX_SET; /*!< 0x000000C4 Interrupt set */ 59 __IOM uint32_t INTR_TX_MASK; /*!< 0x000000C8 Interrupt mask */ 60 __IM uint32_t INTR_TX_MASKED; /*!< 0x000000CC Interrupt masked */ 61 __IM uint32_t RESERVED4[12]; 62 } TDM_TDM_STRUCT_TDM_TX_STRUCT_Type; /*!< Size = 256 (0x100) */ 63 64 /** 65 * \brief TDM RX structure (TDM_TDM_STRUCT_TDM_RX_STRUCT) 66 */ 67 typedef struct { 68 __IOM uint32_t RX_CTL; /*!< 0x00000000 RX control */ 69 __IM uint32_t RESERVED[3]; 70 __IOM uint32_t RX_IF_CTL; /*!< 0x00000010 RX interface control */ 71 __IOM uint32_t RX_CH_CTL; /*!< 0x00000014 RX channel control */ 72 __IM uint32_t RESERVED1[2]; 73 __IOM uint32_t RX_TEST_CTL; /*!< 0x00000020 RX test control */ 74 __IOM uint32_t RX_ROUTE_CTL; /*!< 0x00000024 RX route control */ 75 __IM uint32_t RESERVED2[22]; 76 __IOM uint32_t RX_FIFO_CTL; /*!< 0x00000080 RX FIFO control */ 77 __IM uint32_t RX_FIFO_STATUS; /*!< 0x00000084 RX FIFO status */ 78 __IM uint32_t RX_FIFO_RD; /*!< 0x00000088 RX FIFO read */ 79 __IM uint32_t RX_FIFO_RD_SILENT; /*!< 0x0000008C RX FIFO silent read */ 80 __IM uint32_t RESERVED3[12]; 81 __IOM uint32_t INTR_RX; /*!< 0x000000C0 Interrupt */ 82 __IOM uint32_t INTR_RX_SET; /*!< 0x000000C4 Interrupt set */ 83 __IOM uint32_t INTR_RX_MASK; /*!< 0x000000C8 Interrupt mask */ 84 __IM uint32_t INTR_RX_MASKED; /*!< 0x000000CC Interrupt masked */ 85 __IM uint32_t RESERVED4[12]; 86 } TDM_TDM_STRUCT_TDM_RX_STRUCT_Type; /*!< Size = 256 (0x100) */ 87 88 /** 89 * \brief TDM structure (TDM_TDM_STRUCT) 90 */ 91 typedef struct { 92 TDM_TDM_STRUCT_TDM_TX_STRUCT_Type TDM_TX_STRUCT; /*!< 0x00000000 TDM TX structure */ 93 TDM_TDM_STRUCT_TDM_RX_STRUCT_Type TDM_RX_STRUCT; /*!< 0x00000100 TDM RX structure */ 94 } TDM_TDM_STRUCT_Type; /*!< Size = 512 (0x200) */ 95 96 /** 97 * \brief TDM (TDM) 98 */ 99 typedef struct { 100 __IM uint32_t RESERVED[8192]; 101 TDM_TDM_STRUCT_Type TDM_STRUCT[4]; /*!< 0x00008000 TDM structure */ 102 } TDM_Type; /*!< Size = 34816 (0x8800) */ 103 104 105 /* TDM_TDM_STRUCT_TDM_TX_STRUCT.TX_CTL */ 106 #define TDM_TDM_STRUCT_TDM_TX_STRUCT_TX_CTL_WORD_SIZE_Pos 0UL 107 #define TDM_TDM_STRUCT_TDM_TX_STRUCT_TX_CTL_WORD_SIZE_Msk 0xFUL 108 #define TDM_TDM_STRUCT_TDM_TX_STRUCT_TX_CTL_FORMAT_Pos 12UL 109 #define TDM_TDM_STRUCT_TDM_TX_STRUCT_TX_CTL_FORMAT_Msk 0x3000UL 110 #define TDM_TDM_STRUCT_TDM_TX_STRUCT_TX_CTL_MS_Pos 16UL 111 #define TDM_TDM_STRUCT_TDM_TX_STRUCT_TX_CTL_MS_Msk 0x10000UL 112 #define TDM_TDM_STRUCT_TDM_TX_STRUCT_TX_CTL_ENABLED_Pos 31UL 113 #define TDM_TDM_STRUCT_TDM_TX_STRUCT_TX_CTL_ENABLED_Msk 0x80000000UL 114 /* TDM_TDM_STRUCT_TDM_TX_STRUCT.TX_IF_CTL */ 115 #define TDM_TDM_STRUCT_TDM_TX_STRUCT_TX_IF_CTL_CLOCK_DIV_Pos 0UL 116 #define TDM_TDM_STRUCT_TDM_TX_STRUCT_TX_IF_CTL_CLOCK_DIV_Msk 0xFFUL 117 #define TDM_TDM_STRUCT_TDM_TX_STRUCT_TX_IF_CTL_CLOCK_SEL_Pos 8UL 118 #define TDM_TDM_STRUCT_TDM_TX_STRUCT_TX_IF_CTL_CLOCK_SEL_Msk 0x700UL 119 #define TDM_TDM_STRUCT_TDM_TX_STRUCT_TX_IF_CTL_SCK_POLARITY_Pos 12UL 120 #define TDM_TDM_STRUCT_TDM_TX_STRUCT_TX_IF_CTL_SCK_POLARITY_Msk 0x1000UL 121 #define TDM_TDM_STRUCT_TDM_TX_STRUCT_TX_IF_CTL_FSYNC_POLARITY_Pos 13UL 122 #define TDM_TDM_STRUCT_TDM_TX_STRUCT_TX_IF_CTL_FSYNC_POLARITY_Msk 0x2000UL 123 #define TDM_TDM_STRUCT_TDM_TX_STRUCT_TX_IF_CTL_FSYNC_FORMAT_Pos 15UL 124 #define TDM_TDM_STRUCT_TDM_TX_STRUCT_TX_IF_CTL_FSYNC_FORMAT_Msk 0x8000UL 125 #define TDM_TDM_STRUCT_TDM_TX_STRUCT_TX_IF_CTL_CH_NR_Pos 16UL 126 #define TDM_TDM_STRUCT_TDM_TX_STRUCT_TX_IF_CTL_CH_NR_Msk 0x1F0000UL 127 #define TDM_TDM_STRUCT_TDM_TX_STRUCT_TX_IF_CTL_CH_SIZE_Pos 24UL 128 #define TDM_TDM_STRUCT_TDM_TX_STRUCT_TX_IF_CTL_CH_SIZE_Msk 0x1F000000UL 129 #define TDM_TDM_STRUCT_TDM_TX_STRUCT_TX_IF_CTL_I2S_MODE_Pos 31UL 130 #define TDM_TDM_STRUCT_TDM_TX_STRUCT_TX_IF_CTL_I2S_MODE_Msk 0x80000000UL 131 /* TDM_TDM_STRUCT_TDM_TX_STRUCT.TX_CH_CTL */ 132 #define TDM_TDM_STRUCT_TDM_TX_STRUCT_TX_CH_CTL_CH_EN_Pos 0UL 133 #define TDM_TDM_STRUCT_TDM_TX_STRUCT_TX_CH_CTL_CH_EN_Msk 0xFFFFFFFFUL 134 /* TDM_TDM_STRUCT_TDM_TX_STRUCT.TX_TEST_CTL */ 135 #define TDM_TDM_STRUCT_TDM_TX_STRUCT_TX_TEST_CTL_ENABLED_Pos 31UL 136 #define TDM_TDM_STRUCT_TDM_TX_STRUCT_TX_TEST_CTL_ENABLED_Msk 0x80000000UL 137 /* TDM_TDM_STRUCT_TDM_TX_STRUCT.TX_ROUTE_CTL */ 138 #define TDM_TDM_STRUCT_TDM_TX_STRUCT_TX_ROUTE_CTL_MODE_Pos 0UL 139 #define TDM_TDM_STRUCT_TDM_TX_STRUCT_TX_ROUTE_CTL_MODE_Msk 0x3UL 140 /* TDM_TDM_STRUCT_TDM_TX_STRUCT.TX_FIFO_CTL */ 141 #define TDM_TDM_STRUCT_TDM_TX_STRUCT_TX_FIFO_CTL_TRIGGER_LEVEL_Pos 0UL 142 #define TDM_TDM_STRUCT_TDM_TX_STRUCT_TX_FIFO_CTL_TRIGGER_LEVEL_Msk 0x7FUL 143 #define TDM_TDM_STRUCT_TDM_TX_STRUCT_TX_FIFO_CTL_MUTE_Pos 16UL 144 #define TDM_TDM_STRUCT_TDM_TX_STRUCT_TX_FIFO_CTL_MUTE_Msk 0x10000UL 145 #define TDM_TDM_STRUCT_TDM_TX_STRUCT_TX_FIFO_CTL_FREEZE_Pos 17UL 146 #define TDM_TDM_STRUCT_TDM_TX_STRUCT_TX_FIFO_CTL_FREEZE_Msk 0x20000UL 147 #define TDM_TDM_STRUCT_TDM_TX_STRUCT_TX_FIFO_CTL_ACTIVE_Pos 18UL 148 #define TDM_TDM_STRUCT_TDM_TX_STRUCT_TX_FIFO_CTL_ACTIVE_Msk 0x40000UL 149 #define TDM_TDM_STRUCT_TDM_TX_STRUCT_TX_FIFO_CTL_REPLAY_Pos 19UL 150 #define TDM_TDM_STRUCT_TDM_TX_STRUCT_TX_FIFO_CTL_REPLAY_Msk 0x80000UL 151 /* TDM_TDM_STRUCT_TDM_TX_STRUCT.TX_FIFO_STATUS */ 152 #define TDM_TDM_STRUCT_TDM_TX_STRUCT_TX_FIFO_STATUS_USED_Pos 0UL 153 #define TDM_TDM_STRUCT_TDM_TX_STRUCT_TX_FIFO_STATUS_USED_Msk 0xFFUL 154 #define TDM_TDM_STRUCT_TDM_TX_STRUCT_TX_FIFO_STATUS_RD_PTR_Pos 16UL 155 #define TDM_TDM_STRUCT_TDM_TX_STRUCT_TX_FIFO_STATUS_RD_PTR_Msk 0x7F0000UL 156 #define TDM_TDM_STRUCT_TDM_TX_STRUCT_TX_FIFO_STATUS_WR_PTR_Pos 24UL 157 #define TDM_TDM_STRUCT_TDM_TX_STRUCT_TX_FIFO_STATUS_WR_PTR_Msk 0x7F000000UL 158 /* TDM_TDM_STRUCT_TDM_TX_STRUCT.TX_FIFO_WR */ 159 #define TDM_TDM_STRUCT_TDM_TX_STRUCT_TX_FIFO_WR_DATA_Pos 0UL 160 #define TDM_TDM_STRUCT_TDM_TX_STRUCT_TX_FIFO_WR_DATA_Msk 0xFFFFFFFFUL 161 /* TDM_TDM_STRUCT_TDM_TX_STRUCT.INTR_TX */ 162 #define TDM_TDM_STRUCT_TDM_TX_STRUCT_INTR_TX_FIFO_TRIGGER_Pos 0UL 163 #define TDM_TDM_STRUCT_TDM_TX_STRUCT_INTR_TX_FIFO_TRIGGER_Msk 0x1UL 164 #define TDM_TDM_STRUCT_TDM_TX_STRUCT_INTR_TX_FIFO_OVERFLOW_Pos 1UL 165 #define TDM_TDM_STRUCT_TDM_TX_STRUCT_INTR_TX_FIFO_OVERFLOW_Msk 0x2UL 166 #define TDM_TDM_STRUCT_TDM_TX_STRUCT_INTR_TX_FIFO_UNDERFLOW_Pos 2UL 167 #define TDM_TDM_STRUCT_TDM_TX_STRUCT_INTR_TX_FIFO_UNDERFLOW_Msk 0x4UL 168 #define TDM_TDM_STRUCT_TDM_TX_STRUCT_INTR_TX_IF_UNDERFLOW_Pos 8UL 169 #define TDM_TDM_STRUCT_TDM_TX_STRUCT_INTR_TX_IF_UNDERFLOW_Msk 0x100UL 170 /* TDM_TDM_STRUCT_TDM_TX_STRUCT.INTR_TX_SET */ 171 #define TDM_TDM_STRUCT_TDM_TX_STRUCT_INTR_TX_SET_FIFO_TRIGGER_Pos 0UL 172 #define TDM_TDM_STRUCT_TDM_TX_STRUCT_INTR_TX_SET_FIFO_TRIGGER_Msk 0x1UL 173 #define TDM_TDM_STRUCT_TDM_TX_STRUCT_INTR_TX_SET_FIFO_OVERFLOW_Pos 1UL 174 #define TDM_TDM_STRUCT_TDM_TX_STRUCT_INTR_TX_SET_FIFO_OVERFLOW_Msk 0x2UL 175 #define TDM_TDM_STRUCT_TDM_TX_STRUCT_INTR_TX_SET_FIFO_UNDERFLOW_Pos 2UL 176 #define TDM_TDM_STRUCT_TDM_TX_STRUCT_INTR_TX_SET_FIFO_UNDERFLOW_Msk 0x4UL 177 #define TDM_TDM_STRUCT_TDM_TX_STRUCT_INTR_TX_SET_IF_UNDERFLOW_Pos 8UL 178 #define TDM_TDM_STRUCT_TDM_TX_STRUCT_INTR_TX_SET_IF_UNDERFLOW_Msk 0x100UL 179 /* TDM_TDM_STRUCT_TDM_TX_STRUCT.INTR_TX_MASK */ 180 #define TDM_TDM_STRUCT_TDM_TX_STRUCT_INTR_TX_MASK_FIFO_TRIGGER_Pos 0UL 181 #define TDM_TDM_STRUCT_TDM_TX_STRUCT_INTR_TX_MASK_FIFO_TRIGGER_Msk 0x1UL 182 #define TDM_TDM_STRUCT_TDM_TX_STRUCT_INTR_TX_MASK_FIFO_OVERFLOW_Pos 1UL 183 #define TDM_TDM_STRUCT_TDM_TX_STRUCT_INTR_TX_MASK_FIFO_OVERFLOW_Msk 0x2UL 184 #define TDM_TDM_STRUCT_TDM_TX_STRUCT_INTR_TX_MASK_FIFO_UNDERFLOW_Pos 2UL 185 #define TDM_TDM_STRUCT_TDM_TX_STRUCT_INTR_TX_MASK_FIFO_UNDERFLOW_Msk 0x4UL 186 #define TDM_TDM_STRUCT_TDM_TX_STRUCT_INTR_TX_MASK_IF_UNDERFLOW_Pos 8UL 187 #define TDM_TDM_STRUCT_TDM_TX_STRUCT_INTR_TX_MASK_IF_UNDERFLOW_Msk 0x100UL 188 /* TDM_TDM_STRUCT_TDM_TX_STRUCT.INTR_TX_MASKED */ 189 #define TDM_TDM_STRUCT_TDM_TX_STRUCT_INTR_TX_MASKED_FIFO_TRIGGER_Pos 0UL 190 #define TDM_TDM_STRUCT_TDM_TX_STRUCT_INTR_TX_MASKED_FIFO_TRIGGER_Msk 0x1UL 191 #define TDM_TDM_STRUCT_TDM_TX_STRUCT_INTR_TX_MASKED_FIFO_OVERFLOW_Pos 1UL 192 #define TDM_TDM_STRUCT_TDM_TX_STRUCT_INTR_TX_MASKED_FIFO_OVERFLOW_Msk 0x2UL 193 #define TDM_TDM_STRUCT_TDM_TX_STRUCT_INTR_TX_MASKED_FIFO_UNDERFLOW_Pos 2UL 194 #define TDM_TDM_STRUCT_TDM_TX_STRUCT_INTR_TX_MASKED_FIFO_UNDERFLOW_Msk 0x4UL 195 #define TDM_TDM_STRUCT_TDM_TX_STRUCT_INTR_TX_MASKED_IF_UNDERFLOW_Pos 8UL 196 #define TDM_TDM_STRUCT_TDM_TX_STRUCT_INTR_TX_MASKED_IF_UNDERFLOW_Msk 0x100UL 197 198 199 /* TDM_TDM_STRUCT_TDM_RX_STRUCT.RX_CTL */ 200 #define TDM_TDM_STRUCT_TDM_RX_STRUCT_RX_CTL_WORD_SIZE_Pos 0UL 201 #define TDM_TDM_STRUCT_TDM_RX_STRUCT_RX_CTL_WORD_SIZE_Msk 0xFUL 202 #define TDM_TDM_STRUCT_TDM_RX_STRUCT_RX_CTL_WORD_SIGN_EXTEND_Pos 8UL 203 #define TDM_TDM_STRUCT_TDM_RX_STRUCT_RX_CTL_WORD_SIGN_EXTEND_Msk 0x100UL 204 #define TDM_TDM_STRUCT_TDM_RX_STRUCT_RX_CTL_FORMAT_Pos 12UL 205 #define TDM_TDM_STRUCT_TDM_RX_STRUCT_RX_CTL_FORMAT_Msk 0x3000UL 206 #define TDM_TDM_STRUCT_TDM_RX_STRUCT_RX_CTL_MS_Pos 16UL 207 #define TDM_TDM_STRUCT_TDM_RX_STRUCT_RX_CTL_MS_Msk 0x10000UL 208 #define TDM_TDM_STRUCT_TDM_RX_STRUCT_RX_CTL_ENABLED_Pos 31UL 209 #define TDM_TDM_STRUCT_TDM_RX_STRUCT_RX_CTL_ENABLED_Msk 0x80000000UL 210 /* TDM_TDM_STRUCT_TDM_RX_STRUCT.RX_IF_CTL */ 211 #define TDM_TDM_STRUCT_TDM_RX_STRUCT_RX_IF_CTL_CLOCK_DIV_Pos 0UL 212 #define TDM_TDM_STRUCT_TDM_RX_STRUCT_RX_IF_CTL_CLOCK_DIV_Msk 0xFFUL 213 #define TDM_TDM_STRUCT_TDM_RX_STRUCT_RX_IF_CTL_CLOCK_SEL_Pos 8UL 214 #define TDM_TDM_STRUCT_TDM_RX_STRUCT_RX_IF_CTL_CLOCK_SEL_Msk 0x700UL 215 #define TDM_TDM_STRUCT_TDM_RX_STRUCT_RX_IF_CTL_SCK_POLARITY_Pos 12UL 216 #define TDM_TDM_STRUCT_TDM_RX_STRUCT_RX_IF_CTL_SCK_POLARITY_Msk 0x1000UL 217 #define TDM_TDM_STRUCT_TDM_RX_STRUCT_RX_IF_CTL_FSYNC_POLARITY_Pos 13UL 218 #define TDM_TDM_STRUCT_TDM_RX_STRUCT_RX_IF_CTL_FSYNC_POLARITY_Msk 0x2000UL 219 #define TDM_TDM_STRUCT_TDM_RX_STRUCT_RX_IF_CTL_LATE_SAMPLE_Pos 14UL 220 #define TDM_TDM_STRUCT_TDM_RX_STRUCT_RX_IF_CTL_LATE_SAMPLE_Msk 0x4000UL 221 #define TDM_TDM_STRUCT_TDM_RX_STRUCT_RX_IF_CTL_FSYNC_FORMAT_Pos 15UL 222 #define TDM_TDM_STRUCT_TDM_RX_STRUCT_RX_IF_CTL_FSYNC_FORMAT_Msk 0x8000UL 223 #define TDM_TDM_STRUCT_TDM_RX_STRUCT_RX_IF_CTL_CH_NR_Pos 16UL 224 #define TDM_TDM_STRUCT_TDM_RX_STRUCT_RX_IF_CTL_CH_NR_Msk 0x1F0000UL 225 #define TDM_TDM_STRUCT_TDM_RX_STRUCT_RX_IF_CTL_CH_SIZE_Pos 24UL 226 #define TDM_TDM_STRUCT_TDM_RX_STRUCT_RX_IF_CTL_CH_SIZE_Msk 0x1F000000UL 227 #define TDM_TDM_STRUCT_TDM_RX_STRUCT_RX_IF_CTL_LATE_CAPTURE_Pos 29UL 228 #define TDM_TDM_STRUCT_TDM_RX_STRUCT_RX_IF_CTL_LATE_CAPTURE_Msk 0x60000000UL 229 #define TDM_TDM_STRUCT_TDM_RX_STRUCT_RX_IF_CTL_I2S_MODE_Pos 31UL 230 #define TDM_TDM_STRUCT_TDM_RX_STRUCT_RX_IF_CTL_I2S_MODE_Msk 0x80000000UL 231 /* TDM_TDM_STRUCT_TDM_RX_STRUCT.RX_CH_CTL */ 232 #define TDM_TDM_STRUCT_TDM_RX_STRUCT_RX_CH_CTL_CH_EN_Pos 0UL 233 #define TDM_TDM_STRUCT_TDM_RX_STRUCT_RX_CH_CTL_CH_EN_Msk 0xFFFFFFFFUL 234 /* TDM_TDM_STRUCT_TDM_RX_STRUCT.RX_TEST_CTL */ 235 #define TDM_TDM_STRUCT_TDM_RX_STRUCT_RX_TEST_CTL_ENABLED_Pos 31UL 236 #define TDM_TDM_STRUCT_TDM_RX_STRUCT_RX_TEST_CTL_ENABLED_Msk 0x80000000UL 237 /* TDM_TDM_STRUCT_TDM_RX_STRUCT.RX_ROUTE_CTL */ 238 #define TDM_TDM_STRUCT_TDM_RX_STRUCT_RX_ROUTE_CTL_MODE_Pos 0UL 239 #define TDM_TDM_STRUCT_TDM_RX_STRUCT_RX_ROUTE_CTL_MODE_Msk 0x3UL 240 /* TDM_TDM_STRUCT_TDM_RX_STRUCT.RX_FIFO_CTL */ 241 #define TDM_TDM_STRUCT_TDM_RX_STRUCT_RX_FIFO_CTL_TRIGGER_LEVEL_Pos 0UL 242 #define TDM_TDM_STRUCT_TDM_RX_STRUCT_RX_FIFO_CTL_TRIGGER_LEVEL_Msk 0x7FUL 243 #define TDM_TDM_STRUCT_TDM_RX_STRUCT_RX_FIFO_CTL_FREEZE_Pos 17UL 244 #define TDM_TDM_STRUCT_TDM_RX_STRUCT_RX_FIFO_CTL_FREEZE_Msk 0x20000UL 245 #define TDM_TDM_STRUCT_TDM_RX_STRUCT_RX_FIFO_CTL_ACTIVE_Pos 18UL 246 #define TDM_TDM_STRUCT_TDM_RX_STRUCT_RX_FIFO_CTL_ACTIVE_Msk 0x40000UL 247 /* TDM_TDM_STRUCT_TDM_RX_STRUCT.RX_FIFO_STATUS */ 248 #define TDM_TDM_STRUCT_TDM_RX_STRUCT_RX_FIFO_STATUS_USED_Pos 0UL 249 #define TDM_TDM_STRUCT_TDM_RX_STRUCT_RX_FIFO_STATUS_USED_Msk 0xFFUL 250 #define TDM_TDM_STRUCT_TDM_RX_STRUCT_RX_FIFO_STATUS_RD_PTR_Pos 16UL 251 #define TDM_TDM_STRUCT_TDM_RX_STRUCT_RX_FIFO_STATUS_RD_PTR_Msk 0x7F0000UL 252 #define TDM_TDM_STRUCT_TDM_RX_STRUCT_RX_FIFO_STATUS_WR_PTR_Pos 24UL 253 #define TDM_TDM_STRUCT_TDM_RX_STRUCT_RX_FIFO_STATUS_WR_PTR_Msk 0x7F000000UL 254 /* TDM_TDM_STRUCT_TDM_RX_STRUCT.RX_FIFO_RD */ 255 #define TDM_TDM_STRUCT_TDM_RX_STRUCT_RX_FIFO_RD_DATA_Pos 0UL 256 #define TDM_TDM_STRUCT_TDM_RX_STRUCT_RX_FIFO_RD_DATA_Msk 0xFFFFFFFFUL 257 /* TDM_TDM_STRUCT_TDM_RX_STRUCT.RX_FIFO_RD_SILENT */ 258 #define TDM_TDM_STRUCT_TDM_RX_STRUCT_RX_FIFO_RD_SILENT_DATA_Pos 0UL 259 #define TDM_TDM_STRUCT_TDM_RX_STRUCT_RX_FIFO_RD_SILENT_DATA_Msk 0xFFFFFFFFUL 260 /* TDM_TDM_STRUCT_TDM_RX_STRUCT.INTR_RX */ 261 #define TDM_TDM_STRUCT_TDM_RX_STRUCT_INTR_RX_FIFO_TRIGGER_Pos 0UL 262 #define TDM_TDM_STRUCT_TDM_RX_STRUCT_INTR_RX_FIFO_TRIGGER_Msk 0x1UL 263 #define TDM_TDM_STRUCT_TDM_RX_STRUCT_INTR_RX_FIFO_OVERFLOW_Pos 1UL 264 #define TDM_TDM_STRUCT_TDM_RX_STRUCT_INTR_RX_FIFO_OVERFLOW_Msk 0x2UL 265 #define TDM_TDM_STRUCT_TDM_RX_STRUCT_INTR_RX_FIFO_UNDERFLOW_Pos 2UL 266 #define TDM_TDM_STRUCT_TDM_RX_STRUCT_INTR_RX_FIFO_UNDERFLOW_Msk 0x4UL 267 #define TDM_TDM_STRUCT_TDM_RX_STRUCT_INTR_RX_IF_OVERFLOW_Pos 8UL 268 #define TDM_TDM_STRUCT_TDM_RX_STRUCT_INTR_RX_IF_OVERFLOW_Msk 0x100UL 269 /* TDM_TDM_STRUCT_TDM_RX_STRUCT.INTR_RX_SET */ 270 #define TDM_TDM_STRUCT_TDM_RX_STRUCT_INTR_RX_SET_FIFO_TRIGGER_Pos 0UL 271 #define TDM_TDM_STRUCT_TDM_RX_STRUCT_INTR_RX_SET_FIFO_TRIGGER_Msk 0x1UL 272 #define TDM_TDM_STRUCT_TDM_RX_STRUCT_INTR_RX_SET_FIFO_OVERFLOW_Pos 1UL 273 #define TDM_TDM_STRUCT_TDM_RX_STRUCT_INTR_RX_SET_FIFO_OVERFLOW_Msk 0x2UL 274 #define TDM_TDM_STRUCT_TDM_RX_STRUCT_INTR_RX_SET_FIFO_UNDERFLOW_Pos 2UL 275 #define TDM_TDM_STRUCT_TDM_RX_STRUCT_INTR_RX_SET_FIFO_UNDERFLOW_Msk 0x4UL 276 #define TDM_TDM_STRUCT_TDM_RX_STRUCT_INTR_RX_SET_IF_OVERFLOW_Pos 8UL 277 #define TDM_TDM_STRUCT_TDM_RX_STRUCT_INTR_RX_SET_IF_OVERFLOW_Msk 0x100UL 278 /* TDM_TDM_STRUCT_TDM_RX_STRUCT.INTR_RX_MASK */ 279 #define TDM_TDM_STRUCT_TDM_RX_STRUCT_INTR_RX_MASK_FIFO_TRIGGER_Pos 0UL 280 #define TDM_TDM_STRUCT_TDM_RX_STRUCT_INTR_RX_MASK_FIFO_TRIGGER_Msk 0x1UL 281 #define TDM_TDM_STRUCT_TDM_RX_STRUCT_INTR_RX_MASK_FIFO_OVERFLOW_Pos 1UL 282 #define TDM_TDM_STRUCT_TDM_RX_STRUCT_INTR_RX_MASK_FIFO_OVERFLOW_Msk 0x2UL 283 #define TDM_TDM_STRUCT_TDM_RX_STRUCT_INTR_RX_MASK_FIFO_UNDERFLOW_Pos 2UL 284 #define TDM_TDM_STRUCT_TDM_RX_STRUCT_INTR_RX_MASK_FIFO_UNDERFLOW_Msk 0x4UL 285 #define TDM_TDM_STRUCT_TDM_RX_STRUCT_INTR_RX_MASK_IF_OVERFLOW_Pos 8UL 286 #define TDM_TDM_STRUCT_TDM_RX_STRUCT_INTR_RX_MASK_IF_OVERFLOW_Msk 0x100UL 287 /* TDM_TDM_STRUCT_TDM_RX_STRUCT.INTR_RX_MASKED */ 288 #define TDM_TDM_STRUCT_TDM_RX_STRUCT_INTR_RX_MASKED_FIFO_TRIGGER_Pos 0UL 289 #define TDM_TDM_STRUCT_TDM_RX_STRUCT_INTR_RX_MASKED_FIFO_TRIGGER_Msk 0x1UL 290 #define TDM_TDM_STRUCT_TDM_RX_STRUCT_INTR_RX_MASKED_FIFO_OVERFLOW_Pos 1UL 291 #define TDM_TDM_STRUCT_TDM_RX_STRUCT_INTR_RX_MASKED_FIFO_OVERFLOW_Msk 0x2UL 292 #define TDM_TDM_STRUCT_TDM_RX_STRUCT_INTR_RX_MASKED_FIFO_UNDERFLOW_Pos 2UL 293 #define TDM_TDM_STRUCT_TDM_RX_STRUCT_INTR_RX_MASKED_FIFO_UNDERFLOW_Msk 0x4UL 294 #define TDM_TDM_STRUCT_TDM_RX_STRUCT_INTR_RX_MASKED_IF_OVERFLOW_Pos 8UL 295 #define TDM_TDM_STRUCT_TDM_RX_STRUCT_INTR_RX_MASKED_IF_OVERFLOW_Msk 0x100UL 296 297 298 #endif /* _CYIP_TDM_H_ */ 299 300 301 /* [] END OF FILE */ 302
