1 /* 2 * Copyright 2014-2016 Freescale Semiconductor, Inc. 3 * Copyright 2016-2018 NXP 4 * All rights reserved. 5 * 6 * SPDX-License-Identifier: BSD-3-Clause 7 * 8 */ 9 10 #ifndef __FSL_DEVICE_REGISTERS_H__ 11 #define __FSL_DEVICE_REGISTERS_H__ 12 13 /* 14 * Include the cpu specific register header files. 15 * 16 * The CPU macro should be declared in the project or makefile. 17 */ 18 #if defined(CPU_RV32M1_cm0plus) 19 20 #define RV32M1_cm0plus_SERIES 21 22 /* CMSIS-style register definitions */ 23 #include "RV32M1_cm0plus.h" 24 /* CPU specific feature definitions */ 25 #include "RV32M1_cm0plus_features.h" 26 27 #elif defined(CPU_RV32M1_cm4) 28 29 #define RV32M1_cm4_SERIES 30 31 /* CMSIS-style register definitions */ 32 #include "RV32M1_cm4.h" 33 /* CPU specific feature definitions */ 34 #include "RV32M1_cm4_features.h" 35 36 #elif defined(CPU_RV32M1_zero_riscy) 37 38 #define RV32M1_zero_riscy_SERIES 39 40 /* CMSIS-style register definitions */ 41 #include "RV32M1_zero_riscy.h" 42 /* CPU specific feature definitions */ 43 #include "RV32M1_zero_riscy_features.h" 44 45 #elif defined(CPU_RV32M1_ri5cy) 46 47 #define RV32M1_ri5cy_SERIES 48 49 /* CMSIS-style register definitions */ 50 #include "RV32M1_ri5cy.h" 51 /* CPU specific feature definitions */ 52 #include "RV32M1_ri5cy_features.h" 53 54 #else 55 #error "No valid CPU defined!" 56 #endif 57 58 #endif /* __FSL_DEVICE_REGISTERS_H__ */ 59 60 /******************************************************************************* 61 * EOF 62 ******************************************************************************/ 63
