1 /* ----------------------------------------------------------------------------- 2 * SPDX-License-Identifier: Zlib 3 * Copyright (c) 2013-2016 ARM Ltd. 4 * 5 * This software is provided 'as-is', without any express or implied warranty. 6 * In no event will the authors be held liable for any damages arising from 7 * the use of this software. Permission is granted to anyone to use this 8 * software for any purpose, including commercial applications, and to alter 9 * it and redistribute it freely, subject to the following restrictions: 10 * 11 * 1. The origin of this software must not be misrepresented; you must not 12 * claim that you wrote the original software. If you use this software in 13 * a product, an acknowledgement in the product documentation would be 14 * appreciated but is not required. 15 * 16 * 2. Altered source versions must be plainly marked as such, and must not be 17 * misrepresented as being the original software. 18 * 19 * 3. This notice may not be removed or altered from any source distribution. 20 * 21 * $Date: 1. December 2016 22 * $Revision: V2.4.4 23 * 24 * Project: RTE Device Configuration for Si91x 25 * -------------------------------------------------------------------------- */ 26 27 //-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- 28 29 #ifndef __RTE_DEVICE_H 30 #define __RTE_DEVICE_H 31 #include "rsi_ccp_user_config.h" 32 33 // <e> USART0 [Driver_USART0] 34 // <i> Configuration settings for Driver_USART0 in component ::CMSIS Driver:USART 35 #define RTE_ENABLE_FIFO 1 36 37 #define RTE_USART0 1 38 39 #define RTE_USART0_CLK_SRC USART_INTFPLLCLK 40 #define RTE_USART0_CLK_DIV_FACT 1 41 #define RTE_USART0_FRAC_DIV_SEL USART_FRACTIONAL_DIVIDER 42 43 #define RTE_USART_MODE 0 //!Usart mode macros 44 #define RTE_CONTINUOUS_CLOCK_MODE 0 45 46 #define RTE_USART0_LOOPBACK 0 47 #define RTE_USART0_DTR_EANBLE 0 48 49 #define RTE_USART0_DMA_MODE1_EN 0 //!dma mode 50 51 #define RTE_USART0_TX_FIFO_THRESHOLD USART_TRIGGER_TX_EMPTY 52 #define RTE_USART0_RX_FIFO_THRESHOLD USART_TRIGGER_RX_AEMPTY 53 54 #define RTE_USART0_DMA_TX_LEN_PER_DES 1024 55 #define RTE_USART0_DMA_RX_LEN_PER_DES 1024 56 57 #define RTE_USART0_CHNL_UDMA_TX_EN 0 58 #define RTE_USART0_CHNL_UDMA_TX_CH 25 59 60 #define RTE_USART0_CHNL_UDMA_RX_EN 0 61 #define RTE_USART0_CHNL_UDMA_RX_CH 24 62 63 64 // <o> USART0_CLK <0=>P0_8 <1=>P0_25 <2=>P0_52 <3=>P0_64 65 // <i> CLK of USART0 66 #define RTE_USART0_CLK_PORT_ID 0 67 #ifdef CHIP_917_6x6 68 #if((RTE_USART0_CLK_PORT_ID == 2)||(RTE_USART0_CLK_PORT_ID == 3)) 69 #error "Invalid USART0 RTE_USART0_CLK_PIN pin Configuration!" 70 #endif 71 #endif 72 #if(RTE_USART0_CLK_PORT_ID == 0) 73 #define RTE_USART0_CLK_PORT 0 74 #define RTE_USART0_CLK_PIN 8 75 #define RTE_USART0_CLK_MUX 2 76 #define RTE_USART0_CLK_PAD 3 77 #elif(RTE_USART0_CLK_PORT_ID ==1) 78 #define RTE_USART0_CLK_PORT 0 79 #define RTE_USART0_CLK_PIN 25 80 #define RTE_USART0_CLK_MUX 2 81 #define RTE_USART0_CLK_PAD 0//NO PAD 82 #elif(RTE_USART0_CLK_PORT_ID ==2) 83 #define RTE_USART0_CLK_PORT 0 84 #define RTE_USART0_CLK_PIN 52 85 #define RTE_USART0_CLK_MUX 2 86 #define RTE_USART0_CLK_PAD 16 87 #elif(RTE_USART0_CLK_PORT_ID ==3) 88 #define RTE_USART0_CLK_PORT 0 89 #define RTE_USART0_CLK_PIN 64 90 #define RTE_USART0_CLK_MUX 2 91 #define RTE_USART0_CLK_PAD 22 92 #else 93 #error "Invalid USART0 RTE_USART0_CLK_PIN Pin Configuration!" 94 #endif 95 96 // <o> USART0_TX <0=>P0_15 <1=>P0_30 <2=>P0_54 <3=>P0_68 <4=>P0_71 97 // <i> TX for USART0 98 #ifndef CHIP_917_6x6 99 #ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER 100 #define RTE_USART0_TX_PORT_ID 1 101 #else 102 #define RTE_USART0_TX_PORT_ID 0 103 #endif 104 #endif 105 106 #ifdef CHIP_917_6x6 107 #define RTE_USART0_TX_PORT_ID 3 108 #if((RTE_USART0_TX_PORT_ID == 0)||(RTE_USART0_TX_PORT_ID ==2)) 109 #error "Invalid USART0 RTE_USART0_TX_PIN pin Configuration!" 110 #endif 111 #endif 112 #if(RTE_USART0_TX_PORT_ID == 0) 113 #define RTE_USART0_TX_PORT 0 114 #define RTE_USART0_TX_PIN 15 115 #define RTE_USART0_TX_MUX 2 116 #define RTE_USART0_TX_PAD 8 117 #elif(RTE_USART0_TX_PORT_ID == 1) 118 #define RTE_USART0_TX_PORT 0 119 #define RTE_USART0_TX_PIN 30 120 #define RTE_USART0_TX_MUX 2 121 #define RTE_USART0_TX_PAD 0 //NO PAD 122 #elif(RTE_USART0_TX_PORT_ID ==2) 123 #define RTE_USART0_TX_PORT 0 124 #define RTE_USART0_TX_PIN 54 125 #define RTE_USART0_TX_MUX 2 126 #define RTE_USART0_TX_PAD 18 127 #elif(RTE_USART0_TX_PORT_ID ==3) 128 #define RTE_USART0_TX_PORT 0 129 #define RTE_USART0_TX_PIN 68 130 #define RTE_USART0_TX_MUX 2 131 #define RTE_USART0_TX_PAD 26 132 #elif(RTE_USART0_TX_PORT_ID ==4) 133 #define RTE_USART0_TX_PORT 0 134 #define RTE_USART0_TX_PIN 71 135 #define RTE_USART0_TX_MUX 4 136 #define RTE_USART0_TX_PAD 29 137 #else 138 #error "Invalid USART0 RTE_USART0_TX_PIN Pin Configuration!" 139 #endif 140 141 // <o> USART0_RX <0=>P0_10 <1=>P0_29 <2=>P0_55 <3=>P0_65 <4=>P0_70 142 // <i> RX for USART0 143 #ifndef CHIP_917_6x6 144 #ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER 145 #define RTE_USART0_RX_PORT_ID 1 146 #else 147 #define RTE_USART0_RX_PORT_ID 0 148 #endif 149 #endif 150 151 #ifdef CHIP_917_6x6 152 #define RTE_USART0_RX_PORT_ID 0 153 #if((RTE_USART0_RX_PORT_ID == 2)||(RTE_USART0_RX_PORT_ID == 3)) 154 #error "Invalid USART0 RTE_USART0_RX_PIN pin Configuration!" 155 #endif 156 #endif 157 #if(RTE_USART0_RX_PORT_ID ==0) 158 #define RTE_USART0_RX_PORT 0 159 #define RTE_USART0_RX_PIN 10 160 #define RTE_USART0_RX_MUX 2 161 #define RTE_USART0_RX_PAD 5 162 #elif(RTE_USART0_RX_PORT_ID ==1) 163 #define RTE_USART0_RX_PORT 0 164 #define RTE_USART0_RX_PIN 29 165 #define RTE_USART0_RX_MUX 2 166 #define RTE_USART0_RX_PAD 0//no pad 167 #elif(RTE_USART0_RX_PORT_ID ==2) 168 #define RTE_USART0_RX_PORT 0 169 #define RTE_USART0_RX_PIN 55 170 #define RTE_USART0_RX_MUX 2 171 #define RTE_USART0_RX_PAD 19 172 #elif(RTE_USART0_RX_PORT_ID ==3) 173 #define RTE_USART0_RX_PORT 0 174 #define RTE_USART0_RX_PIN 65 175 #define RTE_USART0_RX_MUX 2 176 #define RTE_USART0_RX_PAD 24 177 #elif(RTE_USART0_RX_PORT_ID ==4) 178 #define RTE_USART0_RX_PORT 0 179 #define RTE_USART0_RX_PIN 70 180 #define RTE_USART0_RX_MUX 4 181 #define RTE_USART0_RX_PAD 28 182 #else 183 #error "Invalid USART0 RTE_USART0_RX_PIN Pin Configuration!" 184 #endif 185 186 // <o> USART0_CTS <0=>P0_6 <1=>P0_26 <2=>P0_56 <3=>P0_70 187 // <i> CTS for USART0 188 #define RTE_USART0_CTS_PORT_ID 0 189 #ifdef CHIP_917_6x6 190 #if((RTE_USART0_CTS_PORT_ID == 2)) 191 #error "Invalid USART0 RTE_USART0_CTS_PIN pin Configuration!" 192 #endif 193 #endif 194 #if(RTE_USART0_CTS_PORT_ID ==0) 195 #define RTE_USART0_CTS_PORT 0 196 #define RTE_USART0_CTS_PIN 6 197 #define RTE_USART0_CTS_MUX 2 198 #define RTE_USART0_CTS_PAD 1 199 #elif(RTE_USART0_CTS_PORT_ID ==1) 200 #define RTE_USART0_CTS_PORT 0 201 #define RTE_USART0_CTS_PIN 26 202 #define RTE_USART0_CTS_MUX 2 203 #define RTE_USART0_CTS_PAD 0//NO PAD 204 #elif(RTE_USART0_CTS_PORT_ID ==2) 205 #define RTE_USART0_CTS_PORT 0 206 #define RTE_USART0_CTS_PIN 56 207 #define RTE_USART0_CTS_MUX 2 208 #define RTE_USART0_CTS_PAD 20 209 #elif(RTE_USART0_CTS_PORT_ID ==3) 210 #define RTE_USART0_CTS_PORT 0 211 #define RTE_USART0_CTS_PIN 70 212 #define RTE_USART0_CTS_MUX 2 213 #define RTE_USART0_CTS_PAD 28 214 #else 215 #error "Invalid USART0 RTE_USART0_CTS_PIN Pin Configuration!" 216 #endif 217 218 219 // <o> USART0_RTS <0=>P0_9 <1=>P0_28 <2=>P0_53 <3=>P0_69 220 // <i> RTS for USART0 221 #define RTE_USART0_RTS_PORT_ID 0 222 #ifdef CHIP_917_6x6 223 #if((RTE_USART0_RTS_PORT_ID == 2)) 224 #error "Invalid USART0 RTE_USART0_RTS_PIN pin Configuration!" 225 #endif 226 #endif 227 #if(RTE_USART0_RTS_PORT_ID ==0) 228 #define RTE_USART0_RTS_PORT 0 229 #define RTE_USART0_RTS_PIN 9 230 #define RTE_USART0_RTS_MUX 2 231 #define RTE_USART0_RTS_PAD 4 232 #elif(RTE_USART0_RTS_PORT_ID ==1) 233 #define RTE_USART0_RTS_PORT 0 234 #define RTE_USART0_RTS_PIN 28 235 #define RTE_USART0_RTS_MUX 2 236 #define RTE_USART0_RTS_PAD 0 //NO PAD 237 #elif(RTE_USART0_RTS_PORT_ID ==2) 238 #define RTE_USART0_RTS_PORT 0 239 #define RTE_USART0_RTS_PIN 53 240 #define RTE_USART0_RTS_MUX 2 241 #define RTE_USART0_RTS_PAD 17 242 #elif(RTE_USART0_RTS_PORT_ID ==3) 243 #define RTE_USART0_RTS_PORT 0 244 #define RTE_USART0_RTS_PIN 69 245 #define RTE_USART0_RTS_MUX 2 246 #define RTE_USART0_RTS_PAD 27 247 #else 248 #error "Invalid USART0 RTE_USART0_RTS_PIN Pin Configuration!" 249 #endif 250 251 // <o> USART0_IR_TX <0=>P0_48 <1=>P0_72 252 // <i> IR TX for USART0 253 #ifndef CHIP_917_6x6 254 #define RTE_IR_TX_PORT_ID 0 255 #if((RTE_IR_TX_PORT_ID ==2 )) 256 #error "Invalid USART0 RTE_USART0_IR_TX_PIN Pin Configuration!" 257 #endif 258 #endif 259 #ifdef CHIP_917_6x6 260 #define RTE_IR_TX_PORT_ID 2 261 #if((RTE_IR_TX_PORT_ID ==0 )||(RTE_IR_TX_PORT_ID ==1 )) 262 #error "Invalid USART0 RTE_USART0_IR_TX_PIN Pin Configuration!" 263 #endif 264 #endif 265 #if(RTE_IR_TX_PORT_ID ==0) 266 #define RTE_USART0_IR_TX_PORT 0 267 #define RTE_USART0_IR_TX_PIN 48 268 #define RTE_USART0_IR_TX_MUX 2 269 #define RTE_USART0_IR_TX_PAD 12 270 #elif(RTE_IR_TX_PORT_ID ==1) 271 #define RTE_USART0_IR_TX_PORT 0 272 #define RTE_USART0_IR_TX_PIN 72 273 #define RTE_USART0_IR_TX_MUX 2 274 #define RTE_USART0_IR_TX_PAD 30 275 #elif(RTE_IR_TX_PORT_ID ==2) 276 #define RTE_USART0_IR_TX_PORT 0 277 #define RTE_USART0_IR_TX_PIN 26 278 #define RTE_USART0_IR_TX_MUX 13 279 #define RTE_USART0_IR_TX_PAD 0//No pad 280 #else 281 #error "Invalid USART0 RTE_USART0_IR_TX_PIN Pin Configuration!" 282 #endif 283 284 285 // <o> USART0_IR_RX <0=>P0_47 <1=>P0_71 <2=>P0_64 <3=>P0_25 286 // <i> IR RX for USART0 287 #ifndef CHIP_917_6x6 288 #define RTE_IR_RX_PORT_ID 0 289 #if((RTE_IR_RX_PORT_ID ==2 )) 290 #error "Invalid USART0 RTE_USART0_IR_RX_PIN Pin Configuration!" 291 #endif 292 #endif 293 #ifdef CHIP_917_6x6 294 #define RTE_IR_RX_PORT_ID 2 295 #if((RTE_IR_RX_PORT_ID == 0)) 296 #error "Invalid USART0 RTE_USART0_IR_RX_PIN Pin Configuration!" 297 #endif 298 #endif 299 #if(RTE_IR_RX_PORT_ID ==0) 300 #define RTE_USART0_IR_RX_PORT 0 301 #define RTE_USART0_IR_RX_PIN 47 302 #define RTE_USART0_IR_RX_MUX 2 303 #define RTE_USART0_IR_RX_PAD 11 304 #elif(RTE_IR_RX_PORT_ID ==1) 305 #define RTE_USART0_IR_RX_PORT 0 306 #define RTE_USART0_IR_RX_PIN 71 307 #define RTE_USART0_IR_RX_MUX 2 308 #define RTE_USART0_IR_RX_PAD 29 309 #elif(RTE_IR_RX_PORT_ID ==2) 310 #define RTE_USART0_IR_RX_PORT 0 311 #define RTE_USART0_IR_RX_PIN 25 312 #define RTE_USART0_IR_RX_MUX 13 313 #define RTE_USART0_IR_RX_PAD 0//no pad 314 #else 315 #error "Invalid USART0 RTE_USART0_IR_RX_PIN Pin Configuration!" 316 #endif 317 318 319 // <o> USART0_RI <0=>P0_27 <1=>P0_46 <2=>P0_68 320 // <i> RI for USART0 321 #define RTE_RI_PORT_ID 0 322 323 #ifndef CHIP_917_6x6 324 325 #if((RTE_RI_PORT_ID == 2)) 326 #error "Invalid USART0 RTE_USART0_RI_PIN Pin Configuration!" 327 #endif 328 329 #endif 330 331 332 #ifdef CHIP_917_6x6 333 334 #if((RTE_RI_PORT_ID == 1)) 335 #error "Invalid USART0 RTE_USART0_RI_PIN Pin Configuration!" 336 #endif 337 338 #endif 339 #if(RTE_RI_PORT_ID ==0) 340 #define RTE_USART0_RI_PORT 0 341 #define RTE_USART0_RI_PIN 27 342 #define RTE_USART0_RI_MUX 2 343 #define RTE_USART0_RI_PAD 0//no pad 344 #elif(RTE_RI_PORT_ID ==1) 345 #define RTE_USART0_RI_PORT 0 346 #define RTE_USART0_RI_PIN 46 347 #define RTE_USART0_RI_MUX 2 348 #define RTE_USART0_RI_PAD 10 349 #elif(RTE_RI_PORT_ID ==2) 350 #define RTE_USART0_RI_PORT 0 351 #define RTE_USART0_RI_PIN 68 352 #define RTE_USART0_RI_MUX 11 353 #define RTE_USART0_RI_PAD 26 354 #else 355 #error "Invalid USART0 RTE_USART0_RI_PIN Pin Configuration!" 356 #endif 357 358 // <o> USART0_DSR <0=>P0_11 <1=>P0_57 359 // <i> DSR for USART0 360 #define RTE_DSR_PORT_ID 0 361 #ifdef CHIP_917_6x6 362 #if((RTE_DSR_PORT_ID == 1)) 363 #error "Invalid USART0 RTE_USART0_RI_PIN pin Configuration!" 364 #endif 365 #endif 366 #if(RTE_DSR_PORT_ID == 0) 367 #define RTE_USART0_DSR_PORT 0 368 #define RTE_USART0_DSR_PIN 11 369 #define RTE_USART0_DSR_MUX 2 370 #define RTE_USART0_DSR_PAD 6 371 #elif(RTE_DSR_PORT_ID == 1) 372 #define RTE_USART0_DSR_PORT 0 373 #define RTE_USART0_DSR_PIN 57 374 #define RTE_USART0_DSR_MUX 2 375 #define RTE_USART0_DSR_PAD 21 376 #else 377 #error "Invalid USART0 RTE_USART0_RI_PIN Pin Configuration!" 378 #endif 379 // <o> USART0_DCD <0=>P0_12 <1=>P0_29 380 // <i> DCD for USART0 381 382 #ifndef CHIP_917_6x6 383 #define RTE_USART0_DCD_PORT 0 384 #define RTE_USART0_DCD_PIN 12 385 #define RTE_USART0_DCD_MUX 2 386 #define RTE_USART0_DCD_PAD 7 387 #endif 388 389 #ifdef CHIP_917_6x6 390 #define RTE_USART0_DCD_PORT 0 391 #define RTE_USART0_DCD_PIN 29 392 #define RTE_USART0_DCD_MUX 12 393 #define RTE_USART0_DCD_PAD 0//no pad 394 #endif 395 396 397 // <o> USART0_DTR <0=>P0_7 398 // <i> DTR for USART0 399 #define RTE_USART0_DTR_PORT 0 400 #define RTE_USART0_DTR_PIN 7 401 #define RTE_USART0_DTR_MUX 2 402 #define RTE_USART0_DTR_PAD 2 403 // </e> 404 405 // <e> UART1 [Driver_UART1] 406 // <i> Configuration settings for Driver_UART1 in component ::CMSIS Driver:USART 407 #define RTE_UART1 1 408 409 #define RTE_UART1_CLK_SRC USART_INTFPLLCLK 410 #define RTE_UART1_CLK_DIV_FACT 1 411 #define RTE_UART1_FRAC_DIV_SEL USART_FRACTIONAL_DIVIDER 412 413 #define RTE_UART1_LOOPBACK 0 414 #define RTE_UART1_DMA_MODE1_EN 0 415 416 #define RTE_UART1_TX_FIFO_THRESHOLD USART_TRIGGER_TX_EMPTY 417 #define RTE_UART1_RX_FIFO_THRESHOLD USART_TRIGGER_RX_AEMPTY 418 419 #define RTE_UART1_DMA_TX_LEN_PER_DES 1024 420 #define RTE_UART1_DMA_RX_LEN_PER_DES 1024 421 422 #define RTE_UART1_CHNL_UDMA_TX_EN 0 423 #define RTE_UART1_CHNL_UDMA_TX_CH 27 424 425 #define RTE_UART1_CHNL_UDMA_RX_EN 0 426 #define RTE_UART1_CHNL_UDMA_RX_CH 26 427 428 /*UART1 PINS*/ 429 // <o> UART1_TX <0=>P0_7 <1=>P0_30 <2=>P0_67 <3=>P0_69 <4=>P0_73 <5=>P0_75 <6=>P0_34 430 // <i> TX of UART1 431 #ifndef CHIP_917_6x6 432 #ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER 433 #define RTE_UART1_TX_PORT_ID 4 434 #else 435 #define RTE_UART1_TX_PORT_ID 0 436 #endif 437 438 #if((RTE_UART1_TX_PORT_ID == 6)) 439 #error "Invalid UART1 RTE_UART1_TX_PIN Configuration!" 440 #endif 441 #endif 442 443 #ifdef CHIP_917_6x6 444 #define RTE_UART1_TX_PORT_ID 0 445 #if((RTE_UART1_TX_PORT_ID == 2)||(RTE_UART1_TX_PORT_ID == 4)||(RTE_UART1_TX_PORT_ID == 5)) 446 #error "Invalid UART1 RTE_UART1_TX_PIN Configuration!" 447 #endif 448 #endif 449 #if(RTE_UART1_TX_PORT_ID ==0) 450 #define RTE_UART1_TX_PORT 0 451 #define RTE_UART1_TX_PIN 7 452 #define RTE_UART1_TX_MUX 6 453 #define RTE_UART1_TX_PAD 2 454 #elif(RTE_UART1_TX_PORT_ID ==1) 455 #define RTE_UART1_TX_PORT 0 456 #define RTE_UART1_TX_PIN 30 457 #define RTE_UART1_TX_MUX 6 458 #define RTE_UART1_TX_PAD 0//no pad 459 #elif(RTE_UART1_TX_PORT_ID ==2) 460 #define RTE_UART1_TX_PORT 0 461 #define RTE_UART1_TX_PIN 67 462 #define RTE_UART1_TX_MUX 9 463 #define RTE_UART1_TX_PAD 25 464 #elif(RTE_UART1_TX_PORT_ID ==3) 465 #define RTE_UART1_TX_PORT 0 466 #define RTE_UART1_TX_PIN 69 467 #define RTE_UART1_TX_MUX 6 468 #define RTE_UART1_TX_PAD 27 469 #elif(RTE_UART1_TX_PORT_ID ==4) 470 #define RTE_UART1_TX_PORT 0 471 #define RTE_UART1_TX_PIN 73 472 #define RTE_UART1_TX_MUX 6 473 #define RTE_UART1_TX_PAD 31 474 #elif(RTE_UART1_TX_PORT_ID ==5) 475 #define RTE_UART1_TX_PORT 0 476 #define RTE_UART1_TX_PIN 75 477 #define RTE_UART1_TX_MUX 9 478 #define RTE_UART1_TX_PAD 33 479 #elif(RTE_UART1_TX_PORT_ID ==6) 480 #define RTE_UART1_TX_PORT 0 481 #define RTE_UART1_TX_PIN 34 482 #define RTE_UART1_TX_MUX 12 483 #define RTE_UART1_TX_PAD 9 484 #else 485 #error "Invalid UART1 RTE_UART1_TX_PIN Pin Configuration!" 486 #endif 487 488 // <o> UART1_RX <0=>P0_6 <1=>P0_29 <2=>P0_66 <3=>P0_68 <4=>P0_72 <5=>P0_74 <6=>P0_33 489 // <i> RX of UART1 490 491 #ifndef CHIP_917_6x6 492 #define RTE_UART1_RX_PORT_ID 0 493 #if((RTE_UART1_RX_PORT_ID == 6)) 494 #error "Invalid UART1 RTE_UART1_RX_PIN Configuration!" 495 #endif 496 #endif 497 498 #ifdef CHIP_917_6x6 499 #define RTE_UART1_RX_PORT_ID 0 500 #if((RTE_UART1_RX_PORT_ID == 2)||(RTE_UART1_RX_PORT_ID == 4)||(RTE_UART1_RX_PORT_ID == 5)) 501 #error "Invalid UART1 RTE_UART1_RX_PIN Configuration!" 502 #endif 503 #endif 504 #if(RTE_UART1_RX_PORT_ID ==0) 505 #define RTE_UART1_RX_PORT 0 506 #define RTE_UART1_RX_PIN 6 507 #define RTE_UART1_RX_MUX 6 508 #define RTE_UART1_RX_PAD 1 509 #elif(RTE_UART1_RX_PORT_ID ==1) 510 #define RTE_UART1_RX_PORT 0 511 #define RTE_UART1_RX_PIN 29 512 #define RTE_UART1_RX_MUX 6 513 #define RTE_UART1_RX_PAD 0//no pad 514 #elif(RTE_UART1_RX_PORT_ID ==2) 515 #define RTE_UART1_RX_PORT 0 516 #define RTE_UART1_RX_PIN 66 517 #define RTE_UART1_RX_MUX 9 518 #define RTE_UART1_RX_PAD 24 519 #elif(RTE_UART1_RX_PORT_ID ==3) 520 #define RTE_UART1_RX_PORT 0 521 #define RTE_UART1_RX_PIN 68 522 #define RTE_UART1_RX_MUX 6 523 #define RTE_UART1_RX_PAD 26 524 #elif(RTE_UART1_RX_PORT_ID ==4) 525 #define RTE_UART1_RX_PORT 0 526 #define RTE_UART1_RX_PIN 72 527 #define RTE_UART1_RX_MUX 6 528 #define RTE_UART1_RX_PAD 30 529 #elif(RTE_UART1_RX_PORT_ID ==5) 530 #define RTE_UART1_RX_PORT 0 531 #define RTE_UART1_RX_PIN 74 532 #define RTE_UART1_RX_MUX 9 533 #define RTE_UART1_RX_PAD 32 534 #elif(RTE_UART1_RX_PORT_ID ==6) 535 #define RTE_UART1_RX_PORT 0 536 #define RTE_UART1_RX_PIN 33 537 #define RTE_UART1_RX_MUX 12 538 #define RTE_UART1_RX_PAD 9 539 #else 540 #error "Invalid UART1 RTE_UART1_RX_PIN Pin Configuration!" 541 #endif 542 543 // <o> UART1_CTS <0=>P0_11 <1=>P0_28 <2=>P0_51 <3=>P0_65 <4=>P0_71 <5=>P0_73 <6=>P0_32 544 // <i> CTS of UART1 545 #ifndef CHIP_917_6x6 546 #define RTE_UART1_CTS_PORT_ID 0 547 #if((RTE_UART1_CTS_PORT_ID == 6)) 548 #error "Invalid UART1 RTE_UART1_CTS_PIN Configuration!" 549 #endif 550 #endif 551 552 #ifdef CHIP_917_6x6 553 #define RTE_UART1_CTS_PORT_ID 6 554 #if((RTE_UART1_CTS_PORT_ID == 2)||(RTE_UART1_CTS_PORT_ID == 3)||(RTE_UART1_CTS_PORT_ID == 5)) 555 #error "Invalid UART1 RTE_UART1_CTS_PIN Configuration!" 556 #endif 557 #endif 558 559 #if(RTE_UART1_CTS_PORT_ID ==0) 560 #define RTE_UART1_CTS_PORT 0 561 #define RTE_UART1_CTS_PIN 11 562 #define RTE_UART1_CTS_MUX 6 563 #define RTE_UART1_CTS_PAD 6 564 #elif(RTE_UART1_CTS_PORT_ID ==1) 565 #define RTE_UART1_CTS_PORT 0 566 #define RTE_UART1_CTS_PIN 28 567 #define RTE_UART1_CTS_MUX 6 568 #define RTE_UART1_CTS_PAD 0//no pad 569 #elif(RTE_UART1_CTS_PORT_ID ==2) 570 #define RTE_UART1_CTS_PORT 0 571 #define RTE_UART1_CTS_PIN 51 572 #define RTE_UART1_CTS_MUX 9 573 #define RTE_UART1_CTS_PAD 15 574 #elif(RTE_UART1_CTS_PORT_ID ==3) 575 #define RTE_UART1_CTS_PORT 0 576 #define RTE_UART1_CTS_PIN 65 577 #define RTE_UART1_CTS_MUX 9 578 #define RTE_UART1_CTS_PAD 23 579 #elif(RTE_UART1_CTS_PORT_ID ==4) 580 #define RTE_UART1_CTS_PORT 0 581 #define RTE_UART1_CTS_PIN 71 582 #define RTE_UART1_CTS_MUX 6 583 #define RTE_UART1_CTS_PAD 29 584 #elif(RTE_UART1_CTS_PORT_ID ==5) 585 #define RTE_UART1_CTS_PORT 0 586 #define RTE_UART1_CTS_PIN 73 587 #define RTE_UART1_CTS_MUX 9 588 #define RTE_UART1_CTS_PAD 31 589 #elif(RTE_UART1_CTS_PORT_ID ==6) 590 #define RTE_UART1_CTS_PORT 0 591 #define RTE_UART1_CTS_PIN 32 592 #define RTE_UART1_CTS_MUX 12 593 #define RTE_UART1_CTS_PAD 9 594 #else 595 #error "Invalid UART1 RTE_UART1_CTS_PIN Pin Configuration!" 596 #endif 597 598 // <o> UART1_RTS <0=>P0_10 <1=>P0_27 <2=>P0_50 <3=>P0_64 <4=>P0_70 <5=>P0_72 <6=>P0_31 599 // <i> RTS of UART1 600 #ifndef CHIP_917_6x6 601 #ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER 602 #define RTE_UART1_RTS_PORT_ID 1 603 #else 604 #define RTE_UART1_RTS_PORT_ID 0 605 #endif 606 #if((RTE_UART1_RTS_PORT_ID == 6)) 607 #error "Invalid UART1 RTE_UART1_RTS_PIN Configuration!" 608 #endif 609 #endif 610 611 #ifdef CHIP_917_6x6 612 #define RTE_UART1_RTS_PORT_ID 6 613 #if((RTE_UART1_RTS_PORT_ID == 2)||(RTE_UART1_RTS_PORT_ID == 3)||(RTE_UART1_RTS_PORT_ID == 5)) 614 #error "Invalid UART1 RTE_UART1_RTS_PIN Configuration!" 615 #endif 616 #endif 617 #if(RTE_UART1_RTS_PORT_ID ==0) 618 #define RTE_UART1_RTS_PORT 0 619 #define RTE_UART1_RTS_PIN 10 620 #define RTE_UART1_RTS_MUX 6 621 #define RTE_UART1_RTS_PAD 5 622 #elif(RTE_UART1_RTS_PORT_ID == 1) 623 #define RTE_UART1_RTS_PORT 0 624 #define RTE_UART1_RTS_PIN 27 625 #define RTE_UART1_RTS_MUX 6 626 #define RTE_UART1_RTS_PAD 0//no pad 627 #elif(RTE_UART1_RTS_PORT_ID ==2) 628 #define RTE_UART1_RTS_PORT 0 629 #define RTE_UART1_RTS_PIN 50 630 #define RTE_UART1_RTS_MUX 9 631 #define RTE_UART1_RTS_PAD 14 632 #elif(RTE_UART1_RTS_PORT_ID ==3) 633 #define RTE_UART1_RTS_PORT 0 634 #define RTE_UART1_RTS_PIN 64 635 #define RTE_UART1_RTS_MUX 9 636 #define RTE_UART1_RTS_PAD 22 637 #elif(RTE_UART1_RTS_PORT_ID ==4) 638 #define RTE_UART1_RTS_PORT 0 639 #define RTE_UART1_RTS_PIN 70 640 #define RTE_UART1_RTS_MUX 6 641 #define RTE_UART1_RTS_PAD 28 642 #elif(RTE_UART1_RTS_PORT_ID ==5) 643 #define RTE_UART1_RTS_PORT 0 644 #define RTE_UART1_RTS_PIN 72 645 #define RTE_UART1_RTS_MUX 9 646 #define RTE_UART1_RTS_PAD 30 647 #elif(RTE_UART1_RTS_PORT_ID ==6) 648 #define RTE_UART1_RTS_PORT 0 649 #define RTE_UART1_RTS_PIN 31 650 #define RTE_UART1_RTS_MUX 12 651 #define RTE_UART1_RTS_PAD 9 652 #else 653 #error "Invalid UART1 RTE_UART1_RTS_PIN Pin Configuration!" 654 #endif 655 // </e> 656 657 // <e> ULP_UART [Driver_ULP_UART] 658 // <i> Configuration settings for Driver_ULP_UART in component ::CMSIS Driver:USART 659 #define RTE_ULP_UART 1 660 661 #define RTE_ULP_UART_CLK_SRC ULP_UART_REF_CLK 662 #define RTE_ULP_UART_CLK_DIV_FACT 0 663 #define RTE_ULP_UART_FRAC_SEL USART_FRACTIONAL_DIVIDER 664 665 #define RTE_ULP_UART_LOOPBACK 0 666 #define RTE_ULP_UART_DMA_MODE1_EN 0 667 668 #define RTE_ULP_UART_TX_FIFO_THRESHOLD USART_TRIGGER_TX_EMPTY 669 #define RTE_ULP_UART_RX_FIFO_THRESHOLD USART_TRIGGER_RX_AEMPTY 670 671 #define RTE_ULP_UART_DMA_TX_LEN_PER_DES 1024 672 #define RTE_ULP_UART_DMA_RX_LEN_PER_DES 1024 673 674 #define RTE_ULPUART_CHNL_UDMA_TX_EN 0 675 #define RTE_ULPUART_CHNL_UDMA_TX_CH 1 676 677 #define RTE_ULPUART_CHNL_UDMA_RX_EN 0 678 #define RTE_ULPUART_CHNL_UDMA_RX_CH 0 679 680 /*ULPSS UART PINS*/ 681 // <o> UART1_TX <0=>P0_3 <1=>P0_7 <2=>P0_11 682 // <i> TX of ULPSS UART 683 #ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_VER2 684 #define RTE_ULP_UART_TX_PORT_ID 2 685 #else 686 #define RTE_ULP_UART_TX_PORT_ID 1 687 #endif 688 #if (RTE_ULP_UART_TX_PORT_ID == 0) 689 #define RTE_ULP_UART_TX_PORT 0 690 #define RTE_ULP_UART_TX_PIN 3 691 #define RTE_ULP_UART_TX_MUX 3 692 #elif (RTE_ULP_UART_TX_PORT_ID == 1) 693 #define RTE_ULP_UART_TX_PORT 0 694 #define RTE_ULP_UART_TX_PIN 7 695 #define RTE_ULP_UART_TX_MUX 3 696 #elif (RTE_ULP_UART_TX_PORT_ID == 2) 697 #define RTE_ULP_UART_TX_PORT 0 698 #define RTE_ULP_UART_TX_PIN 11 699 #define RTE_ULP_UART_TX_MUX 3 700 #else 701 #error "Invalid ULPSS UART RTE_ULP_UART_TX_PIN Pin Configuration!" 702 #endif 703 704 // <o> UART1_RX <0=>P0_2 <1=>P0_6 <2=>P0_9 705 // <i> RX of ULPSS UART 706 #ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_VER2 707 #define RTE_ULP_UART_RX_PORT_ID 2 708 #else 709 #define RTE_ULP_UART_RX_PORT_ID 1 710 #endif 711 #if (RTE_ULP_UART_RX_PORT_ID == 0) 712 #define RTE_ULP_UART_RX_PORT 0 713 #define RTE_ULP_UART_RX_PIN 2 714 #define RTE_ULP_UART_RX_MUX 3 715 #elif (RTE_ULP_UART_RX_PORT_ID == 1) 716 #define RTE_ULP_UART_RX_PORT 0 717 #define RTE_ULP_UART_RX_PIN 6 718 #define RTE_ULP_UART_RX_MUX 3 719 #elif (RTE_ULP_UART_RX_PORT_ID == 2) 720 #define RTE_ULP_UART_RX_PORT 0 721 #define RTE_ULP_UART_RX_PIN 9 722 #define RTE_ULP_UART_RX_MUX 3 723 #else 724 #error "Invalid ULPSS UART RTE_ULP_UART_RX_PIN Pin Configuration!" 725 #endif 726 727 // <o> UART1_CTS <0=>P0_1 <1=>P0_5 <2=>P0_8 728 // <i> CTS of ULPSS UART 729 #define RTE_ULP_UART_CTS_PORT_ID 1 730 #if(RTE_ULP_UART_CTS_PORT_ID ==0) 731 #define RTE_ULP_UART_CTS_PORT 0 732 #define RTE_ULP_UART_CTS_PIN 1 733 #define RTE_ULP_UART_CTS_MUX 3 734 #elif(RTE_ULP_UART_CTS_PORT_ID ==1) 735 #define RTE_ULP_UART_CTS_PORT 0 736 #define RTE_ULP_UART_CTS_PIN 5 737 #define RTE_ULP_UART_CTS_MUX 3 738 #elif(RTE_ULP_UART_CTS_PORT_ID ==2) 739 #define RTE_ULP_UART_CTS_PORT 0 740 #define RTE_ULP_UART_CTS_PIN 8 741 #define RTE_ULP_UART_CTS_MUX 3 742 #else 743 #error "Invalid ULPSS UART RTE_ULP_UART_CTS_PIN Pin Configuration!" 744 #endif 745 746 // <o> UART1_RTS <0=>P0_0 <1=>P0_4 <2=>P0_10 747 // <i> RTS of ULPSS UART 748 #define RTE_ULP_UART_RTS_PORT_ID 1 749 #if(RTE_ULP_UART_RTS_PORT_ID ==0) 750 #define RTE_ULP_UART_RTS_PORT 0 751 #define RTE_ULP_UART_RTS_PIN 0 752 #define RTE_ULP_UART_RTS_MUX 3 753 #elif(RTE_ULP_UART_RTS_PORT_ID ==1) 754 #define RTE_ULP_UART_RTS_PORT 0 755 #define RTE_ULP_UART_RTS_PIN 4 756 #define RTE_ULP_UART_RTS_MUX 3 757 #elif(RTE_ULP_UART_RTS_PORT_ID ==2) 758 #define RTE_ULP_UART_RTS_PORT 0 759 #define RTE_ULP_UART_RTS_PIN 10 760 #define RTE_ULP_UART_RTS_MUX 8 761 #else 762 #error "Invalid ULPSS UART RTE_ULP_UART_RTS_PIN Pin Configuration!" 763 #endif 764 // </e> 765 766 767 768 // <e> SSI_MASTER (Serial Peripheral Interface 1) [Driver_SSI_MASTER] 769 // <i> Configuration settings for Driver_SSI_MASTER in component ::CMSIS Driver:SPI 770 #define RTE_SSI_MASTER 1 771 772 // <o> SSI_MASTER_MISO Pin <0=>GPIO_12 <1=>GPIO_27 <2=>GPIO_57 773 #ifndef CHIP_917_6x6 774 #ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER 775 #define RTE_SSI_MASTER_MISO_PORT_ID 1 776 #else 777 #define RTE_SSI_MASTER_MISO_PORT_ID 0 778 #endif 779 #if((RTE_SSI_MASTER_MISO_PORT_ID == 3)) 780 #error "Invalid SSI RTE_SSI_MASTER_MISO_PIN Configuration!" 781 #endif 782 #endif 783 784 #ifdef CHIP_917_6x6 785 #define RTE_SSI_MASTER_MISO_PORT_ID 3 786 #if((RTE_SSI_MASTER_MISO_PORT_ID == 0)||(RTE_SSI_MASTER_MISO_PORT_ID == 2)) 787 #error "Invalid SSI RTE_SSI_MASTER_MISO_PIN Configuration!" 788 #endif 789 #endif 790 #if (RTE_SSI_MASTER_MISO_PORT_ID == 0) 791 #define RTE_SSI_MASTER_MISO 1 792 #define RTE_SSI_MASTER_MISO_PORT 0 793 #define RTE_SSI_MASTER_MISO_PIN 12 794 #define RTE_SSI_MASTER_MISO_MODE EGPIO_PIN_MUX_MODE3 795 #define RTE_SSI_MASTER_MISO_PADSEL 7 796 #elif (RTE_SSI_MASTER_MISO_PORT_ID == 1) 797 #define RTE_SSI_MASTER_MISO 1 798 #define RTE_SSI_MASTER_MISO_PORT 0 799 #define RTE_SSI_MASTER_MISO_PIN 27 800 #define RTE_SSI_MASTER_MISO_MODE EGPIO_PIN_MUX_MODE3 801 #define RTE_SSI_MASTER_MISO_PADSEL 0//NO PAD 802 #elif (RTE_SSI_MASTER_MISO_PORT_ID == 2) 803 #define RTE_SSI_MASTER_MISO 1 804 #define RTE_SSI_MASTER_MISO_PORT 0 805 #define RTE_SSI_MASTER_MISO_PIN 57 806 #define RTE_SSI_MASTER_MISO_MODE EGPIO_PIN_MUX_MODE3 807 #define RTE_SSI_MASTER_MISO_PADSEL 21 808 #elif (RTE_SSI_MASTER_MISO_PORT_ID == 3) 809 #define RTE_SSI_MASTER_MISO 1 810 #define RTE_SSI_MASTER_MISO_PORT 0 811 #define RTE_SSI_MASTER_MISO_PIN 10 812 #define RTE_SSI_MASTER_MISO_MODE 12 813 #define RTE_SSI_MASTER_MISO_PADSEL 5 814 #else 815 #error "Invalid SSI_MASTER_MISO Pin Configuration!" 816 #endif 817 818 // <o> SSI_MASTER_MOSI Pin <0=>GPIO_11 <1=>GPIO_26 <2=>GPIO_56 819 #define RTE_SSI_MASTER_MOSI_PORT_ID 1 820 #ifdef CHIP_917_6x6 821 #if((RTE_SSI_MASTER_MOSI_PORT_ID == 2)) 822 #error "Invalid SSI_MASTER_MOSI pin Configuration!" 823 #endif 824 #endif 825 #if (RTE_SSI_MASTER_MOSI_PORT_ID == 0) 826 #define RTE_SSI_MASTER_MOSI 1 827 #define RTE_SSI_MASTER_MOSI_PORT 0 828 #define RTE_SSI_MASTER_MOSI_PIN 11 829 #define RTE_SSI_MASTER_MOSI_MODE EGPIO_PIN_MUX_MODE3 830 #define RTE_SSI_MASTER_MOSI_PADSEL 6 831 #elif (RTE_SSI_MASTER_MOSI_PORT_ID == 1) 832 #define RTE_SSI_MASTER_MOSI 1 833 #define RTE_SSI_MASTER_MOSI_PORT 0 834 #define RTE_SSI_MASTER_MOSI_PIN 26 835 #define RTE_SSI_MASTER_MOSI_MODE EGPIO_PIN_MUX_MODE3 836 #define RTE_SSI_MASTER_MOSI_PADSEL 0//NO PAD 837 #elif (RTE_SSI_MASTER_MOSI_PORT_ID == 2) 838 #define RTE_SSI_MASTER_MOSI 1 839 #define RTE_SSI_MASTER_MOSI_PORT 0 840 #define RTE_SSI_MASTER_MOSI_PIN 56 841 #define RTE_SSI_MASTER_MOSI_MODE EGPIO_PIN_MUX_MODE3 842 #define RTE_SSI_MASTER_MOSI_PADSEL 20 843 #else 844 #error "Invalid SSI_MASTER_MOSI Pin Configuration!" 845 #endif 846 847 // <o> SSI_MASTER_SCK Pin <0=>GPIO_8 <1=>GPIO_25 <2=>GPIO_52 848 #define RTE_SSI_MASTER_SCK_PORT_ID 1 849 #ifdef CHIP_917_6x6 850 #if((RTE_SSI_MASTER_SCK_PORT_ID == 2)) 851 #error "Invalid SSI_MASTER_SCK pin Configuration!" 852 #endif 853 #endif 854 #if (RTE_SSI_MASTER_SCK_PORT_ID == 0) 855 #define RTE_SSI_MASTER_SCK 1 856 #define RTE_SSI_MASTER_SCK_PORT 0 857 #define RTE_SSI_MASTER_SCK_PIN 8 858 #define RTE_SSI_MASTER_SCK_MODE EGPIO_PIN_MUX_MODE3 859 #define RTE_SSI_MASTER_SCK_PADSEL 3 860 #elif (RTE_SSI_MASTER_SCK_PORT_ID == 1) 861 #define RTE_SSI_MASTER_SCK 1 862 #define RTE_SSI_MASTER_SCK_PORT 0 863 #define RTE_SSI_MASTER_SCK_PIN 25 864 #define RTE_SSI_MASTER_SCK_MODE EGPIO_PIN_MUX_MODE3 865 #define RTE_SSI_MASTER_SCK_PADSEL 0//NO PAD 866 #elif (RTE_SSI_MASTER_SCK_PORT_ID == 2) 867 #define RTE_SSI_MASTER_SCK 1 868 #define RTE_SSI_MASTER_SCK_PORT 0 869 #define RTE_SSI_MASTER_SCK_PIN 52 870 #define RTE_SSI_MASTER_SCK_MODE EGPIO_PIN_MUX_MODE3 871 #define RTE_SSI_MASTER_SCK_PADSEL 16 872 #else 873 #error "Invalid SSI_MASTER_SCK Pin Configuration!" 874 #endif 875 876 #define M4_SSI_CS0 1 877 #define M4_SSI_CS1 0 878 #ifndef CHIP_917_6x6 879 #define M4_SSI_CS2 0 880 #define M4_SSI_CS3 0 881 #endif 882 883 // <o> SSI_MASTER_CS Pin <0=>GPIO_9 <1=>GPIO_28 <2=>GPIO_53 <3=>GPIO_10 <4=>GPIO_15 <5=>GPIO_50 <6=>GPIO_51 884 #define RTE_SSI_MASTER_CS0_PORT_ID 1 885 #ifdef CHIP_917_6x6 886 #if((RTE_SSI_MASTER_CS0_PORT_ID == 2)) 887 #error "Invalid SSI_MASTER_CS pin Configuration!" 888 #endif 889 #endif 890 #if (RTE_SSI_MASTER_CS0_PORT_ID == 0) 891 #define RTE_SSI_MASTER_CS0 M4_SSI_CS0 892 #define RTE_SSI_MASTER_CS0_PORT 0 893 #define RTE_SSI_MASTER_CS0_PIN 9 894 #define RTE_SSI_MASTER_CS0_MODE EGPIO_PIN_MUX_MODE3 895 #define RTE_SSI_MASTER_CS0_PADSEL 4 896 #elif (RTE_SSI_MASTER_CS0_PORT_ID == 1) 897 #define RTE_SSI_MASTER_CS0 M4_SSI_CS0 898 #define RTE_SSI_MASTER_CS0_PORT 0 899 #define RTE_SSI_MASTER_CS0_PIN 28 900 #define RTE_SSI_MASTER_CS0_MODE EGPIO_PIN_MUX_MODE3 901 #define RTE_SSI_MASTER_CS0_PADSEL 0//NO PAD 902 #elif (RTE_SSI_MASTER_CS0_PORT_ID == 2) 903 #define RTE_SSI_MASTER_CS0 M4_SSI_CS0 904 #define RTE_SSI_MASTER_CS0_PORT 0 905 #define RTE_SSI_MASTER_CS0_PIN 53 906 #define RTE_SSI_MASTER_CS0_MODE EGPIO_PIN_MUX_MODE3 907 #define RTE_SSI_MASTER_CS0_PADSEL 17 908 #else 909 #error "Invalid SSI_MASTER_CS0 Pin Configuration!" 910 #endif 911 912 //CS1 913 #define RTE_SSI_MASTER_CS1_PORT_ID 0 914 #if (RTE_SSI_MASTER_CS1_PORT_ID == 0) 915 #define RTE_SSI_MASTER_CS1 M4_SSI_CS1 916 #define RTE_SSI_MASTER_CS1_PORT 0 917 #define RTE_SSI_MASTER_CS1_PIN 10 918 #define RTE_SSI_MASTER_CS1_MODE EGPIO_PIN_MUX_MODE3 919 #define RTE_SSI_MASTER_CS1_PADSEL 5 920 #else 921 #error "Invalid SSI_MASTER_CS1 Pin Configuration!" 922 #endif 923 924 #ifndef CHIP_917_6x6 925 //CS2 926 #define RTE_SSI_MASTER_CS2_PORT_ID 1 927 #if (RTE_SSI_MASTER_CS2_PORT_ID == 0) 928 #define RTE_SSI_MASTER_CS2 M4_SSI_CS2 929 #define RTE_SSI_MASTER_CS2_PORT 0 930 #define RTE_SSI_MASTER_CS2_PIN 15 931 #define RTE_SSI_MASTER_CS2_MODE EGPIO_PIN_MUX_MODE3 932 #define RTE_SSI_MASTER_CS2_PADSEL 8 933 #elif (RTE_SSI_MASTER_CS2_PORT_ID == 1) 934 #define RTE_SSI_MASTER_CS2 M4_SSI_CS2 935 #define RTE_SSI_MASTER_CS2_PORT 0 936 #define RTE_SSI_MASTER_CS2_PIN 50 937 #define RTE_SSI_MASTER_CS2_MODE EGPIO_PIN_MUX_MODE3 938 #define RTE_SSI_MASTER_CS2_PADSEL 14 939 #else 940 #error "Invalid SSI_MASTER_CS2 Pin Configuration!" 941 #endif 942 943 944 //CS3 945 #define RTE_SSI_MASTER_CS3_PORT_ID 0 946 #if (RTE_SSI_MASTER_CS3_PORT_ID == 0) 947 #define RTE_SSI_MASTER_CS3 M4_SSI_CS3 948 #define RTE_SSI_MASTER_CS3_PORT 0 949 #define RTE_SSI_MASTER_CS3_PIN 51 950 #define RTE_SSI_MASTER_CS3_MODE EGPIO_PIN_MUX_MODE3 951 #define RTE_SSI_MASTER_CS3_PADSEL 15 952 #else 953 #error "Invalid SSI_MASTER_CS3 Pin Configuration!" 954 #endif 955 #endif 956 957 // <e> DMA Rx 958 // <o3> Channel <28=>28 959 // <i> Selects DMA Channel (only Channel 28 can be used) 960 // </e> 961 #define RTE_SSI_MASTER_RX_DMA 0 962 #define RTE_SSI_MASTER_UDMA_RX_CH 28 963 964 // <e> DMA Tx 965 // <o3> Channel <29=>29 966 // <i> Selects DMA Channel (only Channel 29 can be used) 967 // </e> 968 #define RTE_SSI_MASTER_TX_DMA 0 969 #define RTE_SSI_MASTER_UDMA_TX_CH 29 970 // </e> 971 972 // <e> SSI_SLAVE (Serial Peripheral Interface 2) [Driver_SSI_SLAVE] 973 // <i> Configuration settings for Driver_SSI_SLAVE in component ::CMSIS Driver:SPI 974 #define RTE_SSI_SLAVE 1 975 976 977 #define RTE_SSI_SLAVE_INPUT_CLOCK SSISLAVE_CLK 978 979 // <o> SSI_SLAVE_MISO Pin <0=>Not Used <1=>GPIO_11 <2=>GPIO_28 <3=>GPIO_49 <4=>GPIO_57 980 #define RTE_SSI_SLAVE_MISO_PORT_ID 2 981 #ifdef CHIP_917_6x6 982 #if((RTE_SSI_SLAVE_MISO_PORT_ID == 3)||(RTE_SSI_SLAVE_MISO_PORT_ID == 4)) 983 #error "Invalid SSI_SLAVE_MISO pin Configuration!" 984 #endif 985 #endif 986 #if (RTE_SSI_SLAVE_MISO_PORT_ID == 0) 987 #define RTE_SSI_SLAVE_MISO 0 988 #elif (RTE_SSI_SLAVE_MISO_PORT_ID == 1) 989 #define RTE_SSI_SLAVE_MISO 1 990 #define RTE_SSI_SLAVE_MISO_PORT 0 991 #define RTE_SSI_SLAVE_MISO_PIN 11 992 #define RTE_SSI_SLAVE_MISO_MODE EGPIO_PIN_MUX_MODE8 993 #define RTE_SSI_SLAVE_MISO_PADSEL 6 994 #elif (RTE_SSI_SLAVE_MISO_PORT_ID == 2) 995 #define RTE_SSI_SLAVE_MISO 1 996 #define RTE_SSI_SLAVE_MISO_PORT 0 997 #define RTE_SSI_SLAVE_MISO_PIN 28 998 #define RTE_SSI_SLAVE_MISO_MODE EGPIO_PIN_MUX_MODE8 999 #define RTE_SSI_SLAVE_MISO_PADSEL 0//no pad 1000 #elif (RTE_SSI_SLAVE_MISO_PORT_ID == 3) 1001 #define RTE_SSI_SLAVE_MISO 1 1002 #define RTE_SSI_SLAVE_MISO_PORT 0 1003 #define RTE_SSI_SLAVE_MISO_PIN 49 1004 #define RTE_SSI_SLAVE_MISO_MODE EGPIO_PIN_MUX_MODE8 1005 #define RTE_SSI_SLAVE_MISO_PADSEL 13 1006 #elif (RTE_SSI_SLAVE_MISO_PORT_ID == 4) 1007 #define RTE_SSI_SLAVE_MISO 1 1008 #define RTE_SSI_SLAVE_MISO_PORT 0 1009 #define RTE_SSI_SLAVE_MISO_PIN 57 1010 #define RTE_SSI_SLAVE_MISO_MODE EGPIO_PIN_MUX_MODE8 1011 #define RTE_SSI_SLAVE_MISO_PADSEL 21 1012 #else 1013 #error "Invalid SSI_SLAVE_MISO Pin Configuration!" 1014 #endif 1015 1016 // <o> SSI_SLAVE_MOSI Pin <0=>Not Used <1=>GPIO_10 <2=>GPIO_27 <3=>GPIO_48 <4=>GPIO_56 1017 #ifndef CHIP_917_6x6 1018 #ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER 1019 #define RTE_SSI_SLAVE_MOSI_PORT_ID 2 1020 #else 1021 #define RTE_SSI_SLAVE_MOSI_PORT_ID 1 1022 #endif 1023 #endif 1024 1025 #ifdef CHIP_917_6x6 1026 #define RTE_SSI_SLAVE_MOSI_PORT_ID 2 1027 #if((RTE_SSI_SLAVE_MOSI_PORT_ID == 3)||(RTE_SSI_SLAVE_MOSI_PORT_ID == 4)) 1028 #error "Invalid SSI_SLAVE_MOSI pin Configuration!" 1029 #endif 1030 #endif 1031 #if (RTE_SSI_SLAVE_MOSI_PORT_ID == 0) 1032 #define RTE_SSI_SLAVE_MOSI 0 1033 #elif (RTE_SSI_SLAVE_MOSI_PORT_ID == 1) 1034 #define RTE_SSI_SLAVE_MOSI 1 1035 #define RTE_SSI_SLAVE_MOSI_PORT 0 1036 #define RTE_SSI_SLAVE_MOSI_PIN 10 1037 #define RTE_SSI_SLAVE_MOSI_MODE EGPIO_PIN_MUX_MODE8 1038 #define RTE_SSI_SLAVE_MOSI_PADSEL 5 1039 #elif (RTE_SSI_SLAVE_MOSI_PORT_ID == 2) 1040 #define RTE_SSI_SLAVE_MOSI 1 1041 #define RTE_SSI_SLAVE_MOSI_PORT 0 1042 #define RTE_SSI_SLAVE_MOSI_PIN 27 1043 #define RTE_SSI_SLAVE_MOSI_MODE EGPIO_PIN_MUX_MODE8 1044 #define RTE_SSI_SLAVE_MOSI_PADSEL 0 //no pad 1045 #elif (RTE_SSI_SLAVE_MOSI_PORT_ID == 3) 1046 #define RTE_SSI_SLAVE_MOSI 1 1047 #define RTE_SSI_SLAVE_MOSI_PORT 0 1048 #define RTE_SSI_SLAVE_MOSI_PIN 48 1049 #define RTE_SSI_SLAVE_MOSI_MODE EGPIO_PIN_MUX_MODE8 1050 #define RTE_SSI_SLAVE_MOSI_PADSEL 12 1051 #elif (RTE_SSI_SLAVE_MOSI_PORT_ID == 4) 1052 #define RTE_SSI_SLAVE_MOSI 1 1053 #define RTE_SSI_SLAVE_MOSI_PORT 0 1054 #define RTE_SSI_SLAVE_MOSI_PIN 56 1055 #define RTE_SSI_SLAVE_MOSI_MODE EGPIO_PIN_MUX_MODE8 1056 #define RTE_SSI_SLAVE_MOSI_PADSEL 20 1057 #else 1058 #error "Invalid SSI_SLAVE_MOSI Pin Configuration!" 1059 #endif 1060 1061 // <o> SSI_SLAVE_SCK Pin <0=>Not Used <1=>GPIO_8 <2=>GPIO_26 <3=>GPIO_47 <4=>GPIO_52 1062 #define RTE_SSI_SLAVE_SCK_PORT_ID 2 1063 #ifdef CHIP_917_6x6 1064 #if((RTE_SSI_SLAVE_SCK_PORT_ID == 3)||(RTE_SSI_SLAVE_SCK_PORT_ID == 4)) 1065 #error "Invalid SSI_SLAVE_SCK pin Configuration!" 1066 #endif 1067 #endif 1068 #if (RTE_SSI_SLAVE_SCK_PORT_ID == 0) 1069 #define RTE_SSI_SLAVE_SCK 0 1070 #elif (RTE_SSI_SLAVE_SCK_PORT_ID == 1) 1071 #define RTE_SSI_SLAVE_SCK 1 1072 #define RTE_SSI_SLAVE_SCK_PORT 0 1073 #define RTE_SSI_SLAVE_SCK_PIN 8 1074 #define RTE_SSI_SLAVE_SCK_MODE EGPIO_PIN_MUX_MODE8 1075 #define RTE_SSI_SLAVE_SCK_PADSEL 3 1076 #elif (RTE_SSI_SLAVE_SCK_PORT_ID == 2) 1077 #define RTE_SSI_SLAVE_SCK 1 1078 #define RTE_SSI_SLAVE_SCK_PORT 0 1079 #define RTE_SSI_SLAVE_SCK_PIN 26 1080 #define RTE_SSI_SLAVE_SCK_MODE EGPIO_PIN_MUX_MODE8 1081 #define RTE_SSI_SLAVE_SCK_PADSEL 0 //no pad 1082 #elif (RTE_SSI_SLAVE_SCK_PORT_ID == 3) 1083 #define RTE_SSI_SLAVE_SCK 1 1084 #define RTE_SSI_SLAVE_SCK_PORT 0 1085 #define RTE_SSI_SLAVE_SCK_PIN 47 1086 #define RTE_SSI_SLAVE_SCK_MODE EGPIO_PIN_MUX_MODE8 1087 #define RTE_SSI_SLAVE_SCK_PADSEL 11 1088 #elif (RTE_SSI_SLAVE_SCK_PORT_ID == 4) 1089 #define RTE_SSI_SLAVE_SCK 1 1090 #define RTE_SSI_SLAVE_SCK_PORT 0 1091 #define RTE_SSI_SLAVE_SCK_PIN 52 1092 #define RTE_SSI_SLAVE_SCK_MODE EGPIO_PIN_MUX_MODE8 1093 #define RTE_SSI_SLAVE_SCK_PADSEL 16 1094 #else 1095 #error "Invalid SSI_SLAVE_SCK Pin Configuration!" 1096 #endif 1097 1098 // <o> SSI_SLAVE_CS Pin <0=>Not Used <1=>GPIO_9 <2=>GPIO_25 <3=>GPIO_46 <4=>GPIO_53 1099 #define RTE_SSI_SLAVE_CS_PORT_ID 1 1100 #ifdef CHIP_917_6x6 1101 #if((RTE_SSI_SLAVE_CS_PORT_ID == 3)||(RTE_SSI_SLAVE_CS_PORT_ID == 4)) 1102 #error "Invalid SSI_SLAVE_CS pin Configuration!" 1103 #endif 1104 #endif 1105 #if (RTE_SSI_SLAVE_CS_PORT_ID == 0) 1106 #define RTE_SSI_SLAVE_CS 0 1107 #elif (RTE_SSI_SLAVE_CS_PORT_ID == 1) 1108 #define RTE_SSI_SLAVE_CS 1 1109 #define RTE_SSI_SLAVE_CS_PORT 0 1110 #define RTE_SSI_SLAVE_CS_PIN 9 1111 #define RTE_SSI_SLAVE_CS_MODE EGPIO_PIN_MUX_MODE8 1112 #define RTE_SSI_SLAVE_CS_PADSEL 4 1113 #elif (RTE_SSI_SLAVE_CS_PORT_ID == 2) 1114 #define RTE_SSI_SLAVE_CS 1 1115 #define RTE_SSI_SLAVE_CS_PORT 0 1116 #define RTE_SSI_SLAVE_CS_PIN 25 1117 #define RTE_SSI_SLAVE_CS_MODE EGPIO_PIN_MUX_MODE8 1118 #define RTE_SSI_SLAVE_CS_PADSEL 0//no pad 1119 #elif (RTE_SSI_SLAVE_CS_PORT_ID == 3) 1120 #define RTE_SSI_SLAVE_CS 1 1121 #define RTE_SSI_SLAVE_CS_PORT 0 1122 #define RTE_SSI_SLAVE_CS_PIN 46 1123 #define RTE_SSI_SLAVE_CS_MODE EGPIO_PIN_MUX_MODE8 1124 #define RTE_SSI_SLAVE_CS_PADSEL 10 1125 #elif (RTE_SSI_SLAVE_CS_PORT_ID == 4) 1126 #define RTE_SSI_SLAVE_CS 1 1127 #define RTE_SSI_SLAVE_CS_PORT 0 1128 #define RTE_SSI_SLAVE_CS_PIN 53 1129 #define RTE_SSI_SLAVE_CS_MODE EGPIO_PIN_MUX_MODE8 1130 #define RTE_SSI_SLAVE_CS_PADSEL 17 1131 #else 1132 #error "Invalid SSI_SLAVE_CS Pin Configuration!" 1133 #endif 1134 1135 // <e> DMA Rx 1136 // <o3> Channel <22=>22 1137 // <i> Selects DMA Channel (only Channel 22 can be used) 1138 // </e> 1139 #define RTE_SSI_SLAVE_RX_DMA 1 1140 #define RTE_SSI_SLAVE_UDMA_RX_CH 22 1141 #define RTE_SSI_SLAVE_DMA_RX_LEN_PER_DES 1024 1142 1143 // <e> DMA Tx 1144 // <o3> Channel <23=>23 1145 // <i> Selects DMA Channel (only Channel 23 can be used) 1146 // </e> 1147 #define RTE_SSI_SLAVE_TX_DMA 1 1148 #define RTE_SSI_SLAVE_UDMA_TX_CH 23 1149 #define RTE_SSI_SLAVE_DMA_TX_LEN_PER_DES 1024 1150 1151 // </e> 1152 1153 // <e> SSI_ULP_MASTER (Serial Peripheral Interface 3) [Driver_SSI_ULP_MASTER] 1154 // <i> Configuration settings for Driver_SSI_ULP_MASTER in component ::CMSIS Driver:SPI 1155 #define RTE_SSI_ULP_MASTER 1 1156 1157 // <e> Enable multiple CSN lines 1158 #define ULP_SSI_CS0 1 1159 #define ULP_SSI_CS1 0 1160 #define ULP_SSI_CS2 0 1161 1162 // <o> SSI_ULP_MASTER_MISO Pin <0=>Not Used <1=>ULP_GPIO_2 <2=>ULP_GPIO_9 1163 #define RTE_SSI_ULP_MASTER_MISO_PORT_ID 2 1164 #if (RTE_SSI_ULP_MASTER_MISO_PORT_ID == 0) 1165 #define RTE_SSI_ULP_MASTER_MISO 0 1166 #elif (RTE_SSI_ULP_MASTER_MISO_PORT_ID == 1) 1167 #if ( (PACKAGE_TYPE == CC0 ) || (PACKAGE_TYPE == SB0N_B00) || (PACKAGE_TYPE == SB00_B00) ) 1168 #define RTE_SSI_ULP_MASTER_MISO 1 1169 #define RTE_SSI_ULP_MASTER_MISO_PORT 0 1170 #define RTE_SSI_ULP_MASTER_MISO_PIN 2 1171 #define RTE_SSI_ULP_MASTER_MISO_MODE 1 1172 #else 1173 #error "Change RTE_SSI_ULP_MASTER_MISO_PORT_ID other than '1' as per PACKAGE_TYPE" 1174 #endif 1175 #elif (RTE_SSI_ULP_MASTER_MISO_PORT_ID == 2) 1176 #define RTE_SSI_ULP_MASTER_MISO 1 1177 #define RTE_SSI_ULP_MASTER_MISO_PORT 0 1178 #define RTE_SSI_ULP_MASTER_MISO_PIN 9 1179 #define RTE_SSI_ULP_MASTER_MISO_MODE 1 1180 #else 1181 #error "Invalid SSI_ULP_MISO Pin Configuration!" 1182 #endif 1183 1184 // <o> SSI_ULP_MASTER_MOSI Pin <0=>Not Used <1=>ULP_GPIO_1 <2=>ULP_GPIO_11 1185 #define RTE_SSI_ULP_MASTER_MOSI_PORT_ID 2 1186 #if (RTE_SSI_ULP_MASTER_MOSI_PORT_ID == 0) 1187 #define RTE_SSI_ULP_MASTER_MOSI 0 1188 #elif (RTE_SSI_ULP_MASTER_MOSI_PORT_ID == 1) 1189 #if ( !(PACKAGE_TYPE == SB0N_WMS )) 1190 #define RTE_SSI_ULP_MASTER_MOSI 1 1191 #define RTE_SSI_ULP_MASTER_MOSI_PORT 0 1192 #define RTE_SSI_ULP_MASTER_MOSI_PIN 1 1193 #define RTE_SSI_ULP_MASTER_MOSI_MODE 1 1194 #else 1195 #error "Change RTE_SSI_ULP_MASTER_MOSI_PORT_ID other than '1' as per PACKAGE_TYPE" 1196 #endif 1197 #elif (RTE_SSI_ULP_MASTER_MOSI_PORT_ID == 2) 1198 #define RTE_SSI_ULP_MASTER_MOSI 1 1199 #define RTE_SSI_ULP_MASTER_MOSI_PORT 0 1200 #define RTE_SSI_ULP_MASTER_MOSI_PIN 11 1201 #define RTE_SSI_ULP_MASTER_MOSI_MODE 1 1202 #else 1203 #error "Invalid SSI_ULP_MOSI Pin Configuration!" 1204 #endif 1205 1206 // <o> SSI_ULP_MASTER_SCK Pin <0=>Not Used <1=>ULP_GPIO_0 <2=>ULP_GPIO_8 1207 #ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER 1208 #define RTE_SSI_ULP_MASTER_SCK_PORT_ID 1 1209 #else 1210 #define RTE_SSI_ULP_MASTER_SCK_PORT_ID 2 1211 #endif 1212 #if (RTE_SSI_ULP_MASTER_SCK_PORT_ID == 0) 1213 #define RTE_SSI_ULP_MASTER_SCK 0 1214 #elif (RTE_SSI_ULP_MASTER_SCK_PORT_ID == 1) 1215 #define RTE_SSI_ULP_MASTER_SCK 1 1216 #define RTE_SSI_ULP_MASTER_SCK_PORT 0 1217 #define RTE_SSI_ULP_MASTER_SCK_PIN 0 1218 #define RTE_SSI_ULP_MASTER_SCK_MODE 1 1219 #elif (RTE_SSI_ULP_MASTER_SCK_PORT_ID == 2) 1220 #define RTE_SSI_ULP_MASTER_SCK 1 1221 #define RTE_SSI_ULP_MASTER_SCK_PORT 0 1222 #define RTE_SSI_ULP_MASTER_SCK_PIN 8 1223 #define RTE_SSI_ULP_MASTER_SCK_MODE 1 1224 #else 1225 #error "Invalid SSI_ULP_SCK Pin Configuration!" 1226 #endif 1227 1228 // CS0 1229 #define RTE_SSI_ULP_MASTER_CS0_PORT_ID 0 1230 #if (RTE_SSI_ULP_MASTER_CS0_PORT_ID == 0) 1231 #define RTE_SSI_ULP_MASTER_CS0 ULP_SSI_CS0 1232 #define RTE_SSI_ULP_MASTER_CS0_PORT 0 1233 #define RTE_SSI_ULP_MASTER_CS0_PIN 3 1234 #define RTE_SSI_ULP_MASTER_CS0_MODE 1 1235 #elif (RTE_SSI_ULP_MASTER_CS0_PORT_ID == 1) 1236 #define RTE_SSI_ULP_MASTER_CS0 ULP_SSI_CS0 1237 #define RTE_SSI_ULP_MASTER_CS0_PORT 0 1238 #define RTE_SSI_ULP_MASTER_CS0_PIN 10 1239 #define RTE_SSI_ULP_MASTER_CS0_MODE 1 1240 #else 1241 #error "Change RTE_SSI_ULP_MASTER_CS_PORT_ID other than '1' or'3' as per PACKAGE_TYPE" 1242 #endif 1243 1244 // CS1 1245 #define RTE_SSI_ULP_MASTER_CS1 ULP_SSI_CS1 1246 #define RTE_SSI_ULP_MASTER_CS1_PORT 0 1247 #define RTE_SSI_ULP_MASTER_CS1_PIN 4 1248 #define RTE_SSI_ULP_MASTER_CS1_MODE 1 1249 1250 // CS2 1251 #define RTE_SSI_ULP_MASTER_CS2 ULP_SSI_CS2 1252 #define RTE_SSI_ULP_MASTER_CS2_PORT 0 1253 #define RTE_SSI_ULP_MASTER_CS2_PIN 6 1254 #define RTE_SSI_ULP_MASTER_CS2_MODE 1 1255 1256 1257 // <e> DMA Rx 1258 // <o3> Channel <2=>2 1259 // <i> Selects DMA Channel (only Channel 2 can be used) 1260 // </e> 1261 #define RTE_SSI_ULP_MASTER_RX_DMA 1 1262 #define RTE_SSI_ULP_MASTER_UDMA_RX_CH 2 1263 #define RTE_SSI_ULP_MASTER_DMA_RX_LEN_PER_DES 96 1264 1265 // <e> DMA Tx 1266 // <o3> Channel <3=>3 1267 // <i> Selects DMA Channel (only Channel 3 can be used) 1268 // </e> 1269 #define RTE_SSI_ULP_MASTER_TX_DMA 1 1270 #define RTE_SSI_ULP_MASTER_UDMA_TX_CH 3 1271 #define RTE_SSI_ULP_MASTER_DMA_TX_LEN_PER_DES 96 1272 1273 // </e> 1274 /*=================================================================== 1275 UDMA Defines 1276 ====================================================================*/ 1277 // <e> UDMA [Driver_UDMA] 1278 #define DESC_MAX_LEN 0x400 1279 #define RTE_UDMA0 1 1280 #define UDMA0_IRQHandler IRQ033_Handler 1281 #define CHNL_MASK_REQ0 0 1282 #define CHNL_PRIORITY0 0 1283 #define DMA_PERI_ACK0 0 1284 #define BURST_REQ0_EN 1 1285 #define UDMA0_CHNL_PRIO_LVL 1 1286 #define UDMA0_SRAM_BASE 0x1FC00 1287 1288 #define RTE_UDMA1 1 1289 #define UDMA1_IRQHandler IRQ010_Handler 1290 #define CHNL_MASK_REQ1 0 1291 #define CHNL_PRIORITY1 0 1292 #define BURST_REQ1_EN 1 1293 #define CHNL_HIGH_PRIO_EN1 1 1294 #define UDMA1_CHNL_PRIO_LVL 1 1295 #define ULP_SRAM_START_ADDR 0x24060000 1296 #define ULP_SRAM_END_ADDR 0x24063E00 1297 // <o> RTE_UDMA1_BASE_MEM <0=>PS2 <1=>PS4 1298 #define RTE_UDMA1_BASE_MEM 0 1299 #if(RTE_UDMA1_BASE_MEM == 0) 1300 #define UDMA1_SRAM_BASE 0x24060000 1301 #elif(RTE_UDMA1_BASE_MEM == 1) 1302 #define UDMA1_SRAM_BASE 0x1CC00 1303 #else 1304 #error "Invalid UDMA1 Control Base Address!" 1305 #endif 1306 // </e> 1307 1308 // <e> I2S0 [Driver_I2S0] 1309 // <i> Configuration settings for Driver_I2S0 in component ::CMSIS Driver:I2S 1310 1311 #define RTE_I2S0 1 1312 #define I2S0_IRQHandler IRQ064_Handler 1313 /*I2S0 PINS*/ 1314 1315 // <o> I2S0_SCLK <0=>P0_8 <1=>P0_25 <2=>P0_46 <3=>P0_52 1316 // <i> SCLK of I2S0 1317 #define RTE_I2S0_SCLK_PORT_ID 1 1318 #ifdef CHIP_917_6x6 1319 #if((RTE_I2S0_SCLK_PORT_ID == 2)||(RTE_I2S0_SCLK_PORT_ID == 3)) 1320 #error "Invalid I2S0 RTE_I2S0_SCLK pin Configuration!" 1321 #endif 1322 #endif 1323 #if(RTE_I2S0_SCLK_PORT_ID == 0) 1324 #define RTE_I2S0_SCLK_PORT 0 1325 #define RTE_I2S0_SCLK_PIN 8 1326 #define RTE_I2S0_SCLK_MUX 7 1327 #define RTE_I2S0_SCLK_PAD 3 1328 #elif(RTE_I2S0_SCLK_PORT_ID ==1) 1329 #define RTE_I2S0_SCLK_PORT 0 1330 #define RTE_I2S0_SCLK_PIN 25 1331 #define RTE_I2S0_SCLK_MUX 7 1332 #define RTE_I2S0_SCLK_PAD 0//no pad 1333 #elif(RTE_I2S0_SCLK_PORT_ID ==2) 1334 #define RTE_I2S0_SCLK_PORT 0 1335 #define RTE_I2S0_SCLK_PIN 46 1336 #define RTE_I2S0_SCLK_MUX 7 1337 #define RTE_I2S0_SCLK_PAD 10 1338 #elif(RTE_I2S0_SCLK_PORT_ID ==3) 1339 #define RTE_I2S0_SCLK_PORT 0 1340 #define RTE_I2S0_SCLK_PIN 52 1341 #define RTE_I2S0_SCLK_MUX 7 1342 #define RTE_I2S0_SCLK_PAD 16 1343 #else 1344 #error "Invalid I2S0 RTE_I2S0_SCLK Pin Configuration!" 1345 #endif 1346 1347 // <o> I2S0_WSCLK <0=>P0_9 <1=>P0_26 <2=>P0_47 <3=>P0_53 1348 // <i> WSCLK for I2S0 1349 #define RTE_I2S0_WSCLK_PORT_ID 1 1350 #ifdef CHIP_917_6x6 1351 #if((RTE_I2S0_WSCLK_PORT_ID == 2)||(RTE_I2S0_WSCLK_PORT_ID == 3)) 1352 #error "Invalid I2S0 RTE_I2S0_WSCLK pin Configuration!" 1353 #endif 1354 #endif 1355 #if(RTE_I2S0_WSCLK_PORT_ID == 0) 1356 #define RTE_I2S0_WSCLK_PORT 0 1357 #define RTE_I2S0_WSCLK_PIN 9 1358 #define RTE_I2S0_WSCLK_MUX 7 1359 #define RTE_I2S0_WSCLK_PAD 4 1360 #elif(RTE_I2S0_WSCLK_PORT_ID == 1) 1361 #define RTE_I2S0_WSCLK_PORT 0 1362 #define RTE_I2S0_WSCLK_PIN 26 1363 #define RTE_I2S0_WSCLK_MUX 7 1364 #define RTE_I2S0_WSCLK_PAD 0//no pad 1365 #elif(RTE_I2S0_WSCLK_PORT_ID ==2) 1366 #define RTE_I2S0_WSCLK_PORT 0 1367 #define RTE_I2S0_WSCLK_PIN 47 1368 #define RTE_I2S0_WSCLK_MUX 7 1369 #define RTE_I2S0_WSCLK_PAD 11 1370 #elif(RTE_I2S0_WSCLK_PORT_ID ==3) 1371 #define RTE_I2S0_WSCLK_PORT 0 1372 #define RTE_I2S0_WSCLK_PIN 53 1373 #define RTE_I2S0_WSCLK_MUX 7 1374 #define RTE_I2S0_WSCLK_PAD 17 1375 #else 1376 #error "Invalid I2S0 RTE_I2S0_WSCLK Pin Configuration!" 1377 #endif 1378 1379 // <o> I2S0_DOUT0 <0=>P0_11 <1=>P0_28 <2=>P0_49 <3=>P0_57 1380 // <i> DOUT0 for I2S0 1381 #define RTE_I2S0_DOUT0_PORT_ID 1 1382 #ifdef CHIP_917_6x6 1383 #if((RTE_I2S0_DOUT0_PORT_ID == 2)||(RTE_I2S0_DOUT0_PORT_ID == 3)) 1384 #error "Invalid I2S0 RTE_I2S0_DOUT0 pin Configuration!" 1385 #endif 1386 #endif 1387 #if(RTE_I2S0_DOUT0_PORT_ID ==0) 1388 #define RTE_I2S0_DOUT0_PORT 0 1389 #define RTE_I2S0_DOUT0_PIN 11 1390 #define RTE_I2S0_DOUT0_MUX 7 1391 #define RTE_I2S0_DOUT0_PAD 6 1392 #elif(RTE_I2S0_DOUT0_PORT_ID ==1) 1393 #define RTE_I2S0_DOUT0_PORT 0 1394 #define RTE_I2S0_DOUT0_PIN 28 1395 #define RTE_I2S0_DOUT0_MUX 7 1396 #define RTE_I2S0_DOUT0_PAD 0// no pad 1397 #elif(RTE_I2S0_DOUT0_PORT_ID ==2) 1398 #define RTE_I2S0_DOUT0_PORT 0 1399 #define RTE_I2S0_DOUT0_PIN 49 1400 #define RTE_I2S0_DOUT0_MUX 7 1401 #define RTE_I2S0_DOUT0_PAD 13 1402 #elif(RTE_I2S0_DOUT0_PORT_ID ==3) 1403 #define RTE_I2S0_DOUT0_PORT 0 1404 #define RTE_I2S0_DOUT0_PIN 57 1405 #define RTE_I2S0_DOUT0_MUX 7 1406 #define RTE_I2S0_DOUT0_PAD 21 1407 #else 1408 #error "Invalid I2S0 RTE_I2S0_DOUT0 Pin Configuration!" 1409 #endif 1410 1411 // <o> I2S0_DIN0 <0=>P0_10 <1=>P0_27 <2=>P0_48 <3=>P0_56 1412 // <i> DIN0 for I2S0 1413 #define RTE_I2S0_DIN0_PORT_ID 1 1414 #ifdef CHIP_917_6x6 1415 #if((RTE_I2S0_DIN0_PORT_ID == 2)||(RTE_I2S0_DIN0_PORT_ID == 3)) 1416 #error "Invalid USART0 RTE_I2S0_DIN0 pin Configuration!" 1417 #endif 1418 #endif 1419 #if(RTE_I2S0_DIN0_PORT_ID ==0) 1420 #define RTE_I2S0_DIN0_PORT 0 1421 #define RTE_I2S0_DIN0_PIN 10 1422 #define RTE_I2S0_DIN0_MUX 7 1423 #define RTE_I2S0_DIN0_PAD 5 1424 #elif(RTE_I2S0_DIN0_PORT_ID ==1) 1425 #define RTE_I2S0_DIN0_PORT 0 1426 #define RTE_I2S0_DIN0_PIN 27 1427 #define RTE_I2S0_DIN0_MUX 7 1428 #define RTE_I2S0_DIN0_PAD 0 // no pad 1429 #elif(RTE_I2S0_DIN0_PORT_ID ==2) 1430 #define RTE_I2S0_DIN0_PORT 0 1431 #define RTE_I2S0_DIN0_PIN 48 1432 #define RTE_I2S0_DIN0_MUX 7 1433 #define RTE_I2S0_DIN0_PAD 12 1434 #elif(RTE_I2S0_DIN0_PORT_ID ==3) 1435 #define RTE_I2S0_DIN0_PORT 0 1436 #define RTE_I2S0_DIN0_PIN 56 1437 #define RTE_I2S0_DIN0_MUX 7 1438 #define RTE_I2S0_DIN0_PAD 20 1439 #else 1440 #error "Invalid I2S0 RTE_I2S0_DIN0 Pin Configuration!" 1441 #endif 1442 1443 // <o> I2S0_DOUT1 <0=>P0_7 <1=>P0_30 <2=>P0_51 <3=>P0_55 1444 // <i> DOUT1 for I2S0 1445 #ifndef CHIP_917_6x6 1446 #ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER 1447 #define RTE_I2S0_DOUT1_PORT_ID 1 1448 #else 1449 #define RTE_I2S0_DOUT1_PORT_ID 0 1450 #endif 1451 #endif 1452 #ifdef CHIP_917_6x6 1453 #define RTE_I2S0_DOUT1_PORT_ID 1 1454 #if((RTE_I2S0_DOUT1_PORT_ID == 2)||(RTE_I2S0_DOUT1_PORT_ID == 3)) 1455 #error "Invalid I2S0 RTE_I2S0_DOUT1 pin Configuration!" 1456 #endif 1457 #endif 1458 #if(RTE_I2S0_DOUT1_PORT_ID ==0) 1459 #define RTE_I2S0_DOUT1_PORT 0 1460 #define RTE_I2S0_DOUT1_PIN 7 1461 #define RTE_I2S0_DOUT1_MUX 7 1462 #define RTE_I2S0_DOUT1_PAD 2 1463 #elif(RTE_I2S0_DOUT1_PORT_ID ==1) 1464 #define RTE_I2S0_DOUT1_PORT 0 1465 #define RTE_I2S0_DOUT1_PIN 30 1466 #define RTE_I2S0_DOUT1_MUX 7 1467 #define RTE_I2S0_DOUT1_PAD 0//no pad 1468 #elif(RTE_I2S0_DOUT1_PORT_ID ==2) 1469 #define RTE_I2S0_DOUT1_PORT 0 1470 #define RTE_I2S0_DOUT1_PIN 51 1471 #define RTE_I2S0_DOUT1_MUX 7 1472 #define RTE_I2S0_DOUT1_PAD 15 1473 #elif(RTE_I2S0_DOUT1_PORT_ID ==3) 1474 #define RTE_I2S0_DOUT1_PORT 0 1475 #define RTE_I2S0_DOUT1_PIN 55 1476 #define RTE_I2S0_DOUT1_MUX 7 1477 #define RTE_I2S0_DOUT1_PAD 19 1478 #else 1479 #error "Invalid I2S0 RTE_I2S0_DOUT1 Pin Configuration!" 1480 #endif 1481 1482 // <o> I2S0_DIN1 <0=>P0_6 <1=>P0_29 <2=>P0_50 <3=>P0_54 1483 // <i> DIN1 for I2S0 1484 #define RTE_I2S0_DIN1_PORT_ID 0 1485 #ifdef CHIP_917_6x6 1486 #if((RTE_I2S0_DIN1_PORT_ID == 2)||(RTE_I2S0_DIN1_PORT_ID == 3)) 1487 #error "Invalid I2S0 RTE_I2S0_DIN1 pin Configuration!" 1488 #endif 1489 #endif 1490 #if(RTE_I2S0_DIN1_PORT_ID ==0) 1491 #define RTE_I2S0_DIN1_PORT 0 1492 #define RTE_I2S0_DIN1_PIN 6 1493 #define RTE_I2S0_DIN1_MUX 7 1494 #define RTE_I2S0_DIN1_PAD 1 1495 #elif(RTE_I2S0_DIN1_PORT_ID ==1) 1496 #define RTE_I2S0_DIN1_PORT 0 1497 #define RTE_I2S0_DIN1_PIN 29 1498 #define RTE_I2S0_DIN1_MUX 7 1499 #define RTE_I2S0_DIN1_PAD 0//no pad 1500 #elif(RTE_I2S0_DIN1_PORT_ID ==2) 1501 #define RTE_I2S0_DIN1_PORT 0 1502 #define RTE_I2S0_DIN1_PIN 50 1503 #define RTE_I2S0_DIN1_MUX 7 1504 #define RTE_I2S0_DIN1_PAD 14 1505 #elif(RTE_I2S0_DIN1_PORT_ID ==3) 1506 #define RTE_I2S0_DIN1_PORT 0 1507 #define RTE_I2S0_DIN1_PIN 54 1508 #define RTE_I2S0_DIN1_MUX 7 1509 #define RTE_I2S0_DIN1_PAD 18 1510 #else 1511 #error "Invalid I2S0 RTE_I2S0_DIN1 Pin Configuration!" 1512 #endif 1513 // FIFO level can have value 1 to 7 1514 #define I2S0_TX_FIFO_LEVEL ( 2U ) 1515 #define I2S0_RX_FIFO_LEVEL ( 2U ) 1516 1517 // <o> I2S0_TX_RES <0=>12 1518 // <1=>16 1519 // <2=>20 1520 // <3=>24 1521 #define RTE_I2S0_TX_RES 1 1522 #if (RTE_I2S0_TX_RES ==0) 1523 #define I2S0_TX_RES RES_12_BIT 1524 #elif(RTE_I2S0_TX_RES ==1) 1525 #define I2S0_TX_RES RES_16_BIT 1526 #elif(RTE_I2S0_TX_RES ==2) 1527 #define I2S0_TX_RES RES_20_BIT 1528 #elif(RTE_I2S0_TX_RES ==3) 1529 #define I2S0_TX_RES RES_24_BIT 1530 #else 1531 #error "Invalid I2S0 TX channel resolution!" 1532 #endif 1533 1534 // <o> I2S0_RX_RES <0=>12 1535 // <1=>16 1536 // <2=>20 1537 // <3=>24 1538 #define RTE_I2S0_RX_RES 1 1539 #if (RTE_I2S0_RX_RES ==0) 1540 #define I2S0_RX_RES RES_12_BIT 1541 #elif(RTE_I2S0_RX_RES ==1) 1542 #define I2S0_RX_RES RES_16_BIT 1543 #elif(RTE_I2S0_RX_RES ==2) 1544 #define I2S0_RX_RES RES_20_BIT 1545 #elif(RTE_I2S0_RX_RES ==3) 1546 #define I2S0_RX_RES RES_24_BIT 1547 #else 1548 #error "Invalid I2S0 RX channel resolution!" 1549 #endif 1550 1551 #define RTE_I2S0_CHNL_UDMA_TX_EN 1 1552 #define RTE_I2S0_CHNL_UDMA_TX_CH 15 1553 1554 #define RTE_I2S0_CHNL_UDMA_RX_EN 1 1555 #define RTE_I2S0_CHNL_UDMA_RX_CH 14 1556 1557 #define RTE_I2S0_DMA_TX_LEN_PER_DES 1024 1558 #define RTE_I2S0_DMA_RX_LEN_PER_DES 1024 1559 1560 // </e> 1561 1562 // <e> I2S1 [Driver_I2S1] 1563 // <i> Configuration settings for Driver_I2S1 in component ::Drivers:I2S 1564 #define RTE_I2S1 1 1565 #define I2S1_IRQHandler IRQ014_Handler 1566 1567 // <o> I2S1_SCLK Pin <0=>P0_3 <1=>P0_7 <2=>P0_8 1568 /*I2S1 PINS*/ 1569 #ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER 1570 #define RTE_I2S1_SCLK_PORT_ID 0 1571 #else 1572 #define RTE_I2S1_SCLK_PORT_ID 2 1573 #endif 1574 #if(RTE_I2S1_SCLK_PORT_ID == 0) 1575 #define RTE_I2S1_SCLK_PORT 0 1576 #define RTE_I2S1_SCLK_PIN 3 1577 #define RTE_I2S1_SCLK_MUX 2 1578 #elif(RTE_I2S1_SCLK_PORT_ID ==1) 1579 #define RTE_I2S1_SCLK_PORT 0 1580 #define RTE_I2S1_SCLK_PIN 7 1581 #define RTE_I2S1_SCLK_MUX 2 1582 #elif(RTE_I2S1_SCLK_PORT_ID ==2) 1583 #define RTE_I2S1_SCLK_PORT 0 1584 #define RTE_I2S1_SCLK_PIN 8 1585 #define RTE_I2S1_SCLK_MUX 2 1586 #else 1587 #error "Invalid I2S1 RTE_I2S1_SCLK Pin Configuration!" 1588 #endif 1589 1590 // <o> I2S1_WSCLK Pin <0=>P0_2 <1=>P0_4 <2=>P0_10 1591 #define RTE_I2S1_WSCLK_PORT_ID 0 1592 #if(RTE_I2S1_WSCLK_PORT_ID == 0) 1593 #define RTE_I2S1_WSCLK_PORT 0 1594 #define RTE_I2S1_WSCLK_PIN 2 1595 #define RTE_I2S1_WSCLK_MUX 2 1596 #elif(RTE_I2S0_WSCLK_PORT_ID == 1) 1597 #define RTE_I2S1_WSCLK_PORT 0 1598 #define RTE_I2S1_WSCLK_PIN 4 1599 #define RTE_I2S1_WSCLK_MUX 2 1600 #elif(RTE_I2S1_WSCLK_PORT_ID ==2) 1601 #define RTE_I2S1_WSCLK_PORT 0 1602 #define RTE_I2S1_WSCLK_PIN 10 1603 #define RTE_I2S1_WSCLK_MUX 2 1604 #else 1605 #error "Invalid I2S1 RTE_I2S1_WSCLK Pin Configuration!" 1606 #endif 1607 1608 // <o> I2S1_DOUT0 Pin <0=>P0_1 <1=>P0_5 <2=>P0_11 1609 #define RTE_I2S1_DOUT0_PORT_ID 1 1610 #if(RTE_I2S1_DOUT0_PORT_ID ==0) 1611 #define RTE_I2S1_DOUT0_PORT 0 1612 #define RTE_I2S1_DOUT0_PIN 1 1613 #define RTE_I2S1_DOUT0_MUX 2 1614 #elif(RTE_I2S1_DOUT0_PORT_ID ==1) 1615 #define RTE_I2S1_DOUT0_PORT 0 1616 #define RTE_I2S1_DOUT0_PIN 5 1617 #define RTE_I2S1_DOUT0_MUX 2 1618 #elif(RTE_I2S1_DOUT0_PORT_ID ==2) 1619 #define RTE_I2S1_DOUT0_PORT 0 1620 #define RTE_I2S1_DOUT0_PIN 11 1621 #define RTE_I2S1_DOUT0_MUX 2 1622 #else 1623 #error "Invalid I2S1 RTE_I2S1_DOUT0 Pin Configuration!" 1624 #endif 1625 1626 // <o> I2S1_DIN0 Pin <0=>P0_0 <1=>P0_6 <2=>P0_9 <3=>P0_13 1627 #define RTE_I2S1_DIN0_PORT_ID 1 1628 #if(RTE_I2S1_DIN0_PORT_ID ==0) 1629 #define RTE_I2S1_DIN0_PORT 0 1630 #define RTE_I2S1_DIN0_PIN 0 1631 #define RTE_I2S1_DIN0_MUX 2 1632 #elif(RTE_I2S1_DIN0_PORT_ID ==1) 1633 #define RTE_I2S1_DIN0_PORT 0 1634 #define RTE_I2S1_DIN0_PIN 6 1635 #define RTE_I2S1_DIN0_MUX 2 1636 #elif(RTE_I2S1_DIN0_PORT_ID ==2) 1637 #define RTE_I2S1_DIN0_PORT 0 1638 #define RTE_I2S1_DIN0_PIN 9 1639 #define RTE_I2S1_DIN0_MUX 2 1640 #else 1641 #error "Invalid I2S1 RTE_I2S1_DIN0 Pin Configuration!" 1642 #endif 1643 1644 // FIFO level can have value 1 to 7 1645 #define I2S1_TX_FIFO_LEVEL ( 2U ) 1646 #define I2S1_RX_FIFO_LEVEL ( 2U ) 1647 1648 // <o> I2S1_TX_RES <0=>12 1649 // <1=>16 1650 // <2=>20 1651 // <3=>24 1652 #define RTE_I2S1_TX_RES 1 1653 #if (RTE_I2S1_TX_RES ==0) 1654 #define I2S1_TX_RES RES_12_BIT 1655 #elif(RTE_I2S1_TX_RES ==1) 1656 #define I2S1_TX_RES RES_16_BIT 1657 #elif(RTE_I2S1_TX_RES ==2) 1658 #define I2S1_TX_RES RES_20_BIT 1659 #elif(RTE_I2S1_TX_RES ==3) 1660 #define I2S1_TX_RES RES_24_BIT 1661 #else 1662 #error "Invalid I2S1 TX channel resolution!" 1663 #endif 1664 1665 // <o> I2S1_RX_RES <0=>12 1666 // <1=>16 1667 // <2=>20 1668 // <3=>24 1669 #define RTE_I2S1_RX_RES 1 1670 #if (RTE_I2S1_RX_RES ==0) 1671 #define I2S1_RX_RES RES_12_BIT 1672 #elif(RTE_I2S1_RX_RES ==1) 1673 #define I2S1_RX_RES RES_16_BIT 1674 #elif(RTE_I2S1_RX_RES ==2) 1675 #define I2S1_RX_RES RES_20_BIT 1676 #elif(RTE_I2S1_RX_RES ==3) 1677 #define I2S1_RX_RES RES_24_BIT 1678 #else 1679 #error "Invalid I2S1 RX channel resolution!" 1680 #endif 1681 1682 #define RTE_I2S1_CHNL_UDMA_TX_EN 1 1683 #define RTE_I2S1_CHNL_UDMA_TX_CH 7 1684 1685 #define RTE_I2S1_CHNL_UDMA_RX_EN 1 1686 #define RTE_I2S1_CHNL_UDMA_RX_CH 6 1687 1688 #define RTE_I2S1_DMA_TX_LEN_PER_DES 1024 1689 #define RTE_I2S1_DMA_RX_LEN_PER_DES 1024 1690 1691 // </e> I2S1 [Driver_I2S1] 1692 1693 // <e> I2C0 (Inter-integrated Circuit Interface 0) [Driver_I2C0] 1694 // <i> Configuration settings for Driver_I2C0 in component ::Drivers:I2C 1695 1696 #define RTE_I2C0 1 1697 #define I2C0_IRQHandler IRQ042_Handler 1698 1699 // <o> I2C0_SCL Pin <0=>P0_7 <1=>P0_65 <2=>P0_66 <3=>P0_75 <4=>P0_32 1700 1701 #ifndef CHIP_917_6x6 1702 #define RTE_I2C0_SCL_PORT_ID 0 1703 #if((RTE_I2C0_SCL_PORT_ID == 4)) 1704 #error "Invalid I2C0 RTE_I2C0_SCL_PIN Configuration!" 1705 #endif 1706 #endif 1707 1708 #ifdef CHIP_917_6x6 1709 #define RTE_I2C0_SCL_PORT_ID 0 1710 #if((RTE_I2C0_SCL_PORT_ID == 1)||(RTE_I2C0_SCL_PORT_ID == 2)||(RTE_I2C0_SCL_PORT_ID == 3)) 1711 #error "Invalid I2C0 RTE_I2C0_SCL_PIN Configuration!" 1712 #endif 1713 #endif 1714 #if (RTE_I2C0_SCL_PORT_ID == 0) 1715 #define RTE_I2C0_SCL_PORT 0 1716 #define RTE_I2C0_SCL_PIN 7 1717 #define RTE_I2C0_SCL_MUX 4 1718 #define RTE_I2C0_SCL_PAD 2 1719 #define RTE_I2C0_SCL_I2C_REN 7 1720 #elif(RTE_I2C0_SCL_PORT_ID == 1) 1721 #define RTE_I2C0_SCL_PORT 0 1722 #define RTE_I2C0_SCL_PIN 65 1723 #define RTE_I2C0_SCL_MUX 4 1724 #define RTE_I2C0_SCL_PAD 23 1725 #define RTE_I2C0_SCL_I2C_REN 1 1726 #elif(RTE_I2C0_SCL_PORT_ID == 2) 1727 #define RTE_I2C0_SCL_PORT 0 1728 #define RTE_I2C0_SCL_PIN 66 1729 #define RTE_I2C0_SCL_MUX 4 1730 #define RTE_I2C0_SCL_PAD 24 1731 #define RTE_I2C0_SCL_I2C_REN 2 1732 #elif(RTE_I2C0_SCL_PORT_ID == 3) 1733 #define RTE_I2C0_SCL_PORT 0 1734 #define RTE_I2C0_SCL_PIN 75 1735 #define RTE_I2C0_SCL_MUX 4 1736 #define RTE_I2C0_SCL_PAD 33 1737 #define RTE_I2C0_SCL_I2C_REN 11 1738 #elif(RTE_I2C0_SCL_PORT_ID == 4) 1739 #define RTE_I2C0_SCL_PORT 0 1740 #define RTE_I2C0_SCL_PIN 32 1741 #define RTE_I2C0_SCL_MUX 11 1742 #define RTE_I2C0_SCL_PAD 9 1743 #define RTE_I2C0_SCL_I2C_REN 32 1744 #else 1745 #error "Invalid I2C0 RTE_I2C0_SCL Pin Configuration!" 1746 #endif 1747 1748 // <o> I2C0_SCL Pin <0=>P0_6 <1=>P0_64 <2=>P0_67 <3=>P0_74 <4=>P0_31 1749 #ifndef CHIP_917_6x6 1750 #ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER 1751 #define RTE_I2C0_SDA_PORT_ID 3 1752 #else 1753 #define RTE_I2C0_SDA_PORT_ID 0 1754 #endif 1755 #if((RTE_I2C0_SDA_PORT_ID == 4)) 1756 #error "Invalid I2C0 RTE_I2C0_SDA Configuration!" 1757 #endif 1758 #endif 1759 #ifdef CHIP_917_6x6 1760 #define RTE_I2C0_SDA_PORT_ID 0 1761 #if((RTE_I2C0_SDA_PORT_ID == 1)||(RTE_I2C0_SDA_PORT_ID == 2)||(RTE_I2C0_SDA_PORT_ID == 3)) 1762 #error "Invalid I2C0 RTE_I2C0_SDA Configuration!" 1763 #endif 1764 #endif 1765 #if (RTE_I2C0_SDA_PORT_ID == 0) 1766 #define RTE_I2C0_SDA_PORT 0 1767 #define RTE_I2C0_SDA_PIN 6 1768 #define RTE_I2C0_SDA_MUX 4 1769 #define RTE_I2C0_SDA_PAD 1 1770 #define RTE_I2C0_SDA_I2C_REN 6 1771 #elif(RTE_I2C0_SDA_PORT_ID == 1) 1772 #define RTE_I2C0_SDA_PORT 0 1773 #define RTE_I2C0_SDA_PIN 64 1774 #define RTE_I2C0_SDA_MUX 4 1775 #define RTE_I2C0_SDA_PAD 22 1776 #define RTE_I2C0_SDA_I2C_REN 0 1777 #elif(RTE_I2C0_SDA_PORT_ID == 2) 1778 #define RTE_I2C0_SDA_PORT 0 1779 #define RTE_I2C0_SDA_PIN 67 1780 #define RTE_I2C0_SDA_MUX 4 1781 #define RTE_I2C0_SDA_PAD 25 1782 #define RTE_I2C0_SDA_I2C_REN 3 1783 #elif(RTE_I2C0_SDA_PORT_ID == 3) 1784 #define RTE_I2C0_SDA_PORT 0 1785 #define RTE_I2C0_SDA_PIN 74 1786 #define RTE_I2C0_SDA_MUX 4 1787 #define RTE_I2C0_SDA_PAD 32 1788 #define RTE_I2C0_SDA_I2C_REN 10 1789 #elif(RTE_I2C0_SDA_PORT_ID == 4) 1790 #define RTE_I2C0_SDA_PORT 0 1791 #define RTE_I2C0_SDA_PIN 31 1792 #define RTE_I2C0_SDA_MUX 11 1793 #define RTE_I2C0_SDA_PAD 9 1794 #define RTE_I2C0_SDA_I2C_REN 31 1795 #else 1796 #error "Invalid I2C0 RTE_I2C0_SDA Pin Configuration!" 1797 #endif 1798 1799 #define IC_SCL_STUCK_TIMEOUT 20 1800 #define IC_SDA_STUCK_TIMEOUT 20 1801 1802 #define I2C_DMA 0 1803 #if (I2C_DMA == 1) 1804 #define DMA_TX_TL 1 1805 #define DMA_RX_TL 1 1806 #endif 1807 // </e> I2C0 [Driver_I2C0] 1808 1809 // <e> I2C1 (Inter-integrated Circuit Interface 1) [Driver_I2C1] 1810 // <i> Configuration settings for Driver_I2C1 in component ::Drivers:I2C 1811 1812 #define RTE_I2C1 1 1813 #define I2C1_IRQHandler IRQ061_Handler 1814 // <o> I2C1_SCL Pin <0=>P0_6 <1=>P0_29 <2=>P0_50 <3=>P0_54 <4=>P0_64 <4=>P0_66 <4=>P0_70 <7=>P0_33 1815 #ifndef CHIP_917_6x6 1816 #define RTE_I2C1_SCL_PORT_ID 2 1817 #if((RTE_I2C1_SCL_PORT_ID == 7)) 1818 #error "Invalid I2C1_SCL pin Configuration!" 1819 #endif 1820 #endif 1821 #ifdef CHIP_917_6x6 1822 #define RTE_I2C1_SCL_PORT_ID 7 1823 #if((RTE_I2C1_SCL_PORT_ID == 2)||(RTE_I2C1_SCL_PORT_ID == 3)||(RTE_I2C1_SCL_PORT_ID == 4)||(RTE_I2C1_SCL_PORT_ID == 5)) 1824 #error "Invalid I2C1_SCL pin Configuration!" 1825 #endif 1826 #endif 1827 #if (RTE_I2C1_SCL_PORT_ID == 0) 1828 #define RTE_I2C1_SCL_PORT 0 1829 #define RTE_I2C1_SCL_PIN 6 1830 #define RTE_I2C1_SCL_MUX 5 1831 #define RTE_I2C1_SCL_PAD 1 1832 #define RTE_I2C1_SCL_REN 6 1833 #elif(RTE_I2C1_SCL_PORT_ID == 1) 1834 #define RTE_I2C1_SCL_PORT 0 1835 #define RTE_I2C1_SCL_PIN 29 1836 #define RTE_I2C1_SCL_MUX 5 1837 #define RTE_I2C1_SCL_PAD 0//no pad 1838 #define RTE_I2C1_SCL_REN 29 1839 #elif(RTE_I2C1_SCL_PORT_ID == 2) 1840 #define RTE_I2C1_SCL_PORT 0 1841 #define RTE_I2C1_SCL_PIN 50 1842 #define RTE_I2C1_SCL_MUX 5 1843 #define RTE_I2C1_SCL_PAD 14 1844 #define RTE_I2C1_SCL_REN 50 1845 #elif(RTE_I2C1_SCL_PORT_ID == 3) 1846 #define RTE_I2C1_SCL_PORT 0 1847 #define RTE_I2C1_SCL_PIN 54 1848 #define RTE_I2C1_SCL_MUX 5 1849 #define RTE_I2C1_SCL_PAD 18 1850 #define RTE_I2C1_SCL_REN 54 1851 #elif(RTE_I2C1_SCL_PORT_ID == 4) 1852 #define RTE_I2C1_SCL_PORT 0 1853 #define RTE_I2C1_SCL_PIN 64 1854 #define RTE_I2C1_SCL_MUX 5 1855 #define RTE_I2C1_SCL_PAD 22 1856 #define RTE_I2C1_SCL_REN 0 1857 #elif(RTE_I2C1_SCL_PORT_ID == 5) 1858 #define RTE_I2C1_SCL_PORT 0 1859 #define RTE_I2C1_SCL_PIN 66 1860 #define RTE_I2C1_SCL_MUX 5 1861 #define RTE_I2C1_SCL_PAD 24 1862 #define RTE_I2C1_SCL_REN 2 1863 #elif(RTE_I2C1_SCL_PORT_ID == 6) 1864 #define RTE_I2C1_SCL_PORT 0 1865 #define RTE_I2C1_SCL_PIN 70 1866 #define RTE_I2C1_SCL_MUX 5 1867 #define RTE_I2C1_SCL_PAD 29 1868 #define RTE_I2C1_SCL_REN 6 1869 #elif(RTE_I2C1_SCL_PORT_ID == 7) 1870 #define RTE_I2C1_SCL_PORT 0 1871 #define RTE_I2C1_SCL_PIN 33 1872 #define RTE_I2C1_SCL_MUX 11 1873 #define RTE_I2C1_SCL_PAD 9 1874 #define RTE_I2C1_SCL_REN 33 1875 /**/ 1876 #else 1877 #error "Invalid I2C1_SCL Pin Configuration!" 1878 #endif 1879 1880 // <o> I2C1_SCL Pin <0=>P0_7 <1=>P0_30 <2=>P0_51 <3=>P0_55 <4=>P0_65 <4=>P0_67 <4=>P0_71 <7=>P0_34 1881 #ifdef CHIP_917_6x6 1882 #define RTE_I2C1_SDA_PORT_ID 7 1883 #if((RTE_I2C1_SDA_PORT_ID == 2)||(RTE_I2C1_SDA_PORT_ID == 3)||(RTE_I2C1_SDA_PORT_ID == 4)||(RTE_I2C1_SDA_PORT_ID == 5)) 1884 #error "Invalid I2C1_SDA pin Configuration!" 1885 #endif 1886 #endif 1887 1888 #ifndef CHIP_917_6x6 1889 #define RTE_I2C1_SDA_PORT_ID 2 1890 #if((RTE_I2C1_SDA_PORT_ID == 7)) 1891 #error "Invalid I2C1_SDA pin Configuration!" 1892 #endif 1893 #endif 1894 #if (RTE_I2C1_SDA_PORT_ID == 0) 1895 #define RTE_I2C1_SDA_PORT 0 1896 #define RTE_I2C1_SDA_PIN 7 1897 #define RTE_I2C1_SDA_MUX 5 1898 #define RTE_I2C1_SDA_PAD 2 1899 #define RTE_I2C1_SDA_REN 7 1900 #elif(RTE_I2C1_SDA_PORT_ID == 1) 1901 #define RTE_I2C1_SDA_PORT 0 1902 #define RTE_I2C1_SDA_PIN 30 1903 #define RTE_I2C1_SDA_MUX 5 1904 #define RTE_I2C1_SDA_PAD 0//no pad 1905 #define RTE_I2C1_SDA_REN 30 1906 #elif(RTE_I2C1_SDA_PORT_ID == 2) 1907 #define RTE_I2C1_SDA_PORT 0 1908 #define RTE_I2C1_SDA_PIN 51 1909 #define RTE_I2C1_SDA_MUX 5 1910 #define RTE_I2C1_SDA_PAD 15 1911 #define RTE_I2C1_SDA_REN 51 1912 #elif(RTE_I2C1_SDA_PORT_ID == 3) 1913 #define RTE_I2C1_SDA_PORT 0 1914 #define RTE_I2C1_SDA_PIN 55 1915 #define RTE_I2C1_SDA_MUX 5 1916 #define RTE_I2C1_SDA_PAD 19 1917 #define RTE_I2C1_SDA_REN 55 1918 #elif(RTE_I2C1_SDA_PORT_ID == 4) 1919 #define RTE_I2C1_SDA_PORT 0 1920 #define RTE_I2C1_SDA_PIN 65 1921 #define RTE_I2C1_SDA_MUX 5 1922 #define RTE_I2C1_SDA_PAD 23 1923 #define RTE_I2C1_SDA_REN 1 1924 #elif(RTE_I2C1_SDA_PORT_ID == 5) 1925 #define RTE_I2C1_SDA_PORT 0 1926 #define RTE_I2C1_SDA_PIN 67 1927 #define RTE_I2C1_SDA_MUX 5 1928 #define RTE_I2C1_SDA_PAD 25 1929 #define RTE_I2C1_SDA_REN 3 1930 #elif(RTE_I2C1_SDA_PORT_ID == 6) 1931 #define RTE_I2C1_SDA_PORT 0 1932 #define RTE_I2C1_SDA_PIN 71 1933 #define RTE_I2C1_SDA_MUX 5 1934 #define RTE_I2C1_SDA_PAD 29 1935 #define RTE_I2C1_SDA_REN 7 1936 #elif(RTE_I2C1_SDA_PORT_ID == 7) 1937 #define RTE_I2C1_SDA_PORT 0 1938 #define RTE_I2C1_SDA_PIN 34 1939 #define RTE_I2C1_SDA_MUX 11 1940 #define RTE_I2C1_SDA_PAD 9 1941 #define RTE_I2C1_SDA_REN 34 1942 #else 1943 #error "Invalid I2C1_SDA Pin Configuration!" 1944 #endif 1945 1946 1947 #define IC_SCL_STUCK_TIMEOUT 20 1948 #define IC_SDA_STUCK_TIMEOUT 20 1949 1950 #define DMA_EN 0 1951 #if (DMA_EN == 1) 1952 #define DMA_TX_TL 1 1953 #define DMA_RX_TL 1 1954 #endif 1955 1956 // </e> I2C1 [Driver_I2C1] 1957 1958 // <e> I2C2 (Inter-integrated Circuit Interface 2) [Driver_I2C2] 1959 // <i> Configuration settings for Driver_I2C2 in component ::Drivers:I2C 1960 #define RTE_I2C2 1 1961 #define I2C2_IRQHandler IRQ013_Handler 1962 1963 // <o> I2C2_SCL Pin <0=>P0_1 <1=>P0_5 <2=>P0_7 <3=>P0_8 <4=>P0_13 1964 #ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER 1965 #define RTE_I2C2_SCL_PORT_ID 1 1966 #else 1967 #define RTE_I2C2_SCL_PORT_ID 0 1968 #endif 1969 #if (RTE_I2C2_SCL_PORT_ID == 0) 1970 #define RTE_I2C2_SCL_PORT 0 1971 #define RTE_I2C2_SCL_PIN 1 1972 #define RTE_I2C2_SCL_MUX 4 1973 #define RTE_I2C2_SCL_REN 1 1974 #elif(RTE_I2C2_SCL_PORT_ID == 1) 1975 #define RTE_I2C2_SCL_PORT 0 1976 #define RTE_I2C2_SCL_PIN 5 1977 #define RTE_I2C2_SCL_MUX 4 1978 #define RTE_I2C2_SCL_REN 5 1979 #elif(RTE_I2C2_SCL_PORT_ID == 2) 1980 #define RTE_I2C2_SCL_PORT 0 1981 #define RTE_I2C2_SCL_PIN 7 1982 #define RTE_I2C2_SCL_MUX 4 1983 #define RTE_I2C2_SCL_REN 7 1984 #elif(RTE_I2C2_SCL_PORT_ID == 3) 1985 #define RTE_I2C2_SCL_PORT 0 1986 #define RTE_I2C2_SCL_PIN 8 1987 #define RTE_I2C2_SCL_MUX 4 1988 #define RTE_I2C2_SCL_REN 8 1989 #else 1990 #error "Invalid I2C2_SCL Pin Configuration!" 1991 #endif 1992 1993 // <o> I2C2_SDA Pin <0=>P0_0 <1=>P0_4 <2=>P0_6 <3=>P0_9 <4=>P0_11 <5=>P0_12 1994 #define RTE_I2C2_SDA_PORT_ID 1 1995 #if (RTE_I2C2_SDA_PORT_ID == 0) 1996 #define RTE_I2C2_SDA_PORT 0 1997 #define RTE_I2C2_SDA_PIN 0 1998 #define RTE_I2C2_SDA_MUX 4 1999 #define RTE_I2C2_SDA_I2C_REN 0 2000 #elif(RTE_I2C2_SDA_PORT_ID == 1) 2001 #define RTE_I2C2_SDA_PORT 0 2002 #define RTE_I2C2_SDA_PIN 4 2003 #define RTE_I2C2_SDA_MUX 4 2004 #define RTE_I2C2_SDA_REN 4 2005 #elif(RTE_I2C2_SDA_PORT_ID == 2) 2006 #define RTE_I2C2_SDA_PORT 0 2007 #define RTE_I2C2_SDA_PIN 6 2008 #define RTE_I2C2_SDA_MUX 4 2009 #define RTE_I2C2_SDA_REN 6 2010 #elif(RTE_I2C2_SDA_PORT_ID == 3) 2011 #define RTE_I2C2_SDA_PORT 0 2012 #define RTE_I2C2_SDA_PIN 9 2013 #define RTE_I2C2_SDA_MUX 4 2014 #define RTE_I2C2_SDA_I2C_REN 9 2015 #elif(RTE_I2C2_SDA_PORT_ID == 4) 2016 #define RTE_I2C2_SDA_PORT 0 2017 #define RTE_I2C2_SDA_PIN 11 2018 #define RTE_I2C2_SDA_MUX 4 2019 #define RTE_I2C2_SDA_REN 11 2020 #else 2021 #error "Invalid I2C2_SDA Pin Configuration!" 2022 #endif 2023 2024 #define IC_SCL_STUCK_TIMEOUT 20 2025 #define IC_SDA_STUCK_TIMEOUT 20 2026 2027 #define DMA_EN 0 2028 #if (DMA_EN == 1) 2029 #define DMA_TX_TL 1 2030 #define DMA_RX_TL 1 2031 #endif 2032 2033 // </e> I2C2 [Driver_I2C2] 2034 2035 // <e> GSPI (Generic SPI master) [Driver_GSPI_MASTER] 2036 // <i> Configuration settings for Driver_GSPI_MASTER in component ::Drivers:GSPI 2037 #define RTE_GSPI_MASTER 1 2038 2039 // <o> GSPI_MASTER_CLK <0=>P0_8 <1=>P0_25 <2=>P0_46 <3=>P0_52 2040 // <i> CLK of GSPI0 2041 #ifndef CHIP_917_6x6 2042 #define RTE_GSPI_MASTER_CLK_PORT_ID 1 2043 #endif 2044 2045 #ifdef CHIP_917_6x6 2046 #define RTE_GSPI_MASTER_CLK_PORT_ID 1 2047 #if((RTE_GSPI_MASTER_CLK_PORT_ID == 2)||(RTE_GSPI_MASTER_CLK_PORT_ID == 3)) 2048 #error "Invalid GSPI0 RTE_GSPI_MASTER_CLK_PIN pin Configuration!" 2049 #endif 2050 #endif 2051 #if(RTE_GSPI_MASTER_CLK_PORT_ID == 0) 2052 #define RTE_GSPI_MASTER_CLK_PORT 0 2053 #define RTE_GSPI_MASTER_CLK_PIN 8 2054 #define RTE_GSPI_MASTER_CLK_MUX 4 2055 #define RTE_GSPI_MASTER_CLK_PAD 3 2056 #elif(RTE_GSPI_MASTER_CLK_PORT_ID ==1) 2057 #define RTE_GSPI_MASTER_CLK_PORT 0 2058 #define RTE_GSPI_MASTER_CLK_PIN 25 2059 #define RTE_GSPI_MASTER_CLK_MUX 4 2060 #define RTE_GSPI_MASTER_CLK_PAD 0//NO PAD 2061 #elif(RTE_GSPI_MASTER_CLK_PORT_ID ==2) 2062 #define RTE_GSPI_MASTER_CLK_PORT 0 2063 #define RTE_GSPI_MASTER_CLK_PIN 46 2064 #define RTE_GSPI_MASTER_CLK_MUX 4 2065 #define RTE_GSPI_MASTER_CLK_PAD 10 2066 #elif(RTE_GSPI_MASTER_CLK_PORT_ID ==3) 2067 #define RTE_GSPI_MASTER_CLK_PORT 0 2068 #define RTE_GSPI_MASTER_CLK_PIN 52 2069 #define RTE_GSPI_MASTER_CLK_MUX 4 2070 #define RTE_GSPI_MASTER_CLK_PAD 16 2071 #else 2072 #error "Invalid GSPI0 RTE_GSPI_MASTER_CLK_PIN Pin Configuration!" 2073 #endif 2074 2075 // <e> GSPI_MASTER_CS0 2076 // <o> <0=>P0_9 <1=>P0_28 <2=>P0_49 <3=>P0_53 2077 // <i> CS0 of GSPI0 2078 // </e> 2079 #ifndef CHIP_917_6x6 2080 #define RTE_GSPI_MASTER_CS0_PORT_ID 0 2081 #endif 2082 2083 #ifdef CHIP_917_6x6 2084 #define RTE_GSPI_MASTER_CS0_PORT_ID 1 2085 #if((RTE_GSPI_MASTER_CS0_PORT_ID == 2)||(RTE_GSPI_MASTER_CS0_PORT_ID == 3)) 2086 #error "Invalid GSPI0 RTE_GSPI_MASTER_CS0_PIN pin Configuration!" 2087 #endif 2088 #endif 2089 #if(RTE_GSPI_MASTER_CS0_PORT_ID == 0) 2090 #define RTE_GSPI_MASTER_CS0 1 2091 #define RTE_GSPI_MASTER_CS0_PORT 0 2092 #define RTE_GSPI_MASTER_CS0_PIN 9 2093 #define RTE_GSPI_MASTER_CS0_MUX 4 2094 #define RTE_GSPI_MASTER_CS0_PAD 4 2095 #elif(RTE_GSPI_MASTER_CS0_PORT_ID ==1) 2096 #define RTE_GSPI_MASTER_CS0 1 2097 #define RTE_GSPI_MASTER_CS0_PORT 0 2098 #define RTE_GSPI_MASTER_CS0_PIN 28 2099 #define RTE_GSPI_MASTER_CS0_MUX 4 2100 #define RTE_GSPI_MASTER_CS0_PAD 0//NO PAD 2101 #elif(RTE_GSPI_MASTER_CS0_PORT_ID ==2) 2102 #define RTE_GSPI_MASTER_CS0 1 2103 #define RTE_GSPI_MASTER_CS0_PORT 0 2104 #define RTE_GSPI_MASTER_CS0_PIN 49 2105 #define RTE_GSPI_MASTER_CS0_MUX 4 2106 #define RTE_GSPI_MASTER_CS0_PAD 13 2107 #elif(RTE_GSPI_MASTER_CS0_PORT_ID ==3) 2108 #define RTE_GSPI_MASTER_CS0 1 2109 #define RTE_GSPI_MASTER_CS0_PORT 0 2110 #define RTE_GSPI_MASTER_CS0_PIN 53 2111 #define RTE_GSPI_MASTER_CS0_MUX 4 2112 #define RTE_GSPI_MASTER_CS0_PAD 17 2113 #else 2114 #error "Invalid GSPI0 RTE_GSPI_MASTER_CS0_PIN Pin Configuration!" 2115 #endif 2116 2117 #ifndef CHIP_917_6x6 2118 // <e> GSPI_MASTER_CS1 2119 // <o> <0=>P0_10 <1=>P0_29 <2=>P0_50 <3=>P0_54 2120 // <i> CS1 of GSPI0 2121 // </e> 2122 #define RTE_GSPI_MASTER_CS1_PORT_ID 2 2123 #if(RTE_GSPI_MASTER_CS1_PORT_ID == 0) 2124 #define RTE_GSPI_MASTER_CS1 1 2125 #define RTE_GSPI_MASTER_CS1_PORT 0 2126 #define RTE_GSPI_MASTER_CS1_PIN 10 2127 #define RTE_GSPI_MASTER_CS1_MUX 4 2128 #define RTE_GSPI_MASTER_CS1_PAD 5 2129 #elif(RTE_GSPI_MASTER_CS1_PORT_ID ==1) 2130 #define RTE_GSPI_MASTER_CS1 1 2131 #define RTE_GSPI_MASTER_CS1_PORT 0 2132 #define RTE_GSPI_MASTER_CS1_PIN 29 2133 #define RTE_GSPI_MASTER_CS1_MUX 4 2134 #define RTE_GSPI_MASTER_CS1_PAD 0//NO PAD 2135 #elif(RTE_GSPI_MASTER_CS1_PORT_ID ==2) 2136 #define RTE_GSPI_MASTER_CS1 1 2137 #define RTE_GSPI_MASTER_CS1_PORT 0 2138 #define RTE_GSPI_MASTER_CS1_PIN 50 2139 #define RTE_GSPI_MASTER_CS1_MUX 4 2140 #define RTE_GSPI_MASTER_CS1_PAD 14 2141 #elif(RTE_GSPI_MASTER_CS1_PORT_ID ==3) 2142 #define RTE_GSPI_MASTER_CS1 1 2143 #define RTE_GSPI_MASTER_CS1_PORT 0 2144 #define RTE_GSPI_MASTER_CS1_PIN 54 2145 #define RTE_GSPI_MASTER_CS1_MUX 4 2146 #define RTE_GSPI_MASTER_CS1_PAD 18 2147 #else 2148 #error "Invalid GSPI0 RTE_GSPI_MASTER_CS1_PIN Pin Configuration!" 2149 #endif 2150 2151 // <e> GSPI_MASTER_CS2 2152 // <o> <0=>P0_15 <1=>P0_30 <2=>P0_51 <3=>P0_55 2153 // <i> CS2 of GSPI0 2154 // </e> 2155 #define RTE_GSPI_MASTER_CS2_PORT_ID 1 2156 #if(RTE_GSPI_MASTER_CS2_PORT_ID == 0) 2157 #define RTE_GSPI_MASTER_CS2 1 2158 #define RTE_GSPI_MASTER_CS2_PORT 0 2159 #define RTE_GSPI_MASTER_CS2_PIN 15 2160 #define RTE_GSPI_MASTER_CS2_MUX 4 2161 #define RTE_GSPI_MASTER_CS2_PAD 8 2162 #elif(RTE_GSPI_MASTER_CS2_PORT_ID ==1) 2163 #define RTE_GSPI_MASTER_CS2 1 2164 #define RTE_GSPI_MASTER_CS2_PORT 0 2165 #define RTE_GSPI_MASTER_CS2_PIN 30 2166 #define RTE_GSPI_MASTER_CS2_MUX 4 2167 #define RTE_GSPI_MASTER_CS2_PAD 0//NO PAD 2168 #elif(RTE_GSPI_MASTER_CS2_PORT_ID ==2) 2169 #define RTE_GSPI_MASTER_CS2 1 2170 #define RTE_GSPI_MASTER_CS2_PORT 0 2171 #define RTE_GSPI_MASTER_CS2_PIN 51 2172 #define RTE_GSPI_MASTER_CS2_MUX 4 2173 #define RTE_GSPI_MASTER_CS2_PAD 15 2174 #elif(RTE_GSPI_MASTER_CS2_PORT_ID ==3) 2175 #define RTE_GSPI_MASTER_CS2 1 2176 #define RTE_GSPI_MASTER_CS2_PORT 0 2177 #define RTE_GSPI_MASTER_CS2_PIN 55 2178 #define RTE_GSPI_MASTER_CS2_MUX 4 2179 #define RTE_GSPI_MASTER_CS2_PAD 19 2180 #else 2181 #error "Invalid GSPI0 RTE_GSPI_MASTER_CS2_PIN Pin Configuration!" 2182 #endif 2183 #endif 2184 2185 // <o> GSPI_MASTER_MOSI <0=>P0_12 <1=>P0_27 <2=>P0_48 <3=>P0_57 <4=>P0_6 2186 // <i> MOSI of GSPI0 2187 #ifndef CHIP_917_6x6 2188 #define RTE_GSPI_MASTER_MOSI_PORT_ID 1 2189 #if((RTE_GSPI_MASTER_MOSI_PORT_ID == 4)) 2190 #error "Invalid GSPI0 RTE_GSPI_MASTER_MOSI_PIN pin Configuration!" 2191 #endif 2192 #endif 2193 2194 #ifdef CHIP_917_6x6 2195 #define RTE_GSPI_MASTER_MOSI_PORT_ID 1 2196 #if((RTE_GSPI_MASTER_MOSI_PORT_ID == 0)||(RTE_GSPI_MASTER_MOSI_PORT_ID == 2)||(RTE_GSPI_MASTER_MOSI_PORT_ID == 3)) 2197 #error "Invalid GSPI0 RTE_GSPI_MASTER_MOSI_PIN pin Configuration!" 2198 #endif 2199 #endif 2200 #if(RTE_GSPI_MASTER_MOSI_PORT_ID == 0) 2201 #define RTE_GSPI_MASTER_MOSI_PORT 0 2202 #define RTE_GSPI_MASTER_MOSI_PIN 12 2203 #define RTE_GSPI_MASTER_MOSI_MUX 4 2204 #define RTE_GSPI_MASTER_MOSI_PAD 7 2205 #elif(RTE_GSPI_MASTER_MOSI_PORT_ID ==1) 2206 #define RTE_GSPI_MASTER_MOSI_PORT 0 2207 #define RTE_GSPI_MASTER_MOSI_PIN 27 2208 #define RTE_GSPI_MASTER_MOSI_MUX 4 2209 #define RTE_GSPI_MASTER_MOSI_PAD 0//NO PAD 2210 #elif(RTE_GSPI_MASTER_MOSI_PORT_ID ==2) 2211 #define RTE_GSPI_MASTER_MOSI_PORT 0 2212 #define RTE_GSPI_MASTER_MOSI_PIN 48 2213 #define RTE_GSPI_MASTER_MOSI_MUX 4 2214 #define RTE_GSPI_MASTER_MOSI_PAD 12 2215 #elif(RTE_GSPI_MASTER_MOSI_PORT_ID ==3) 2216 #define RTE_GSPI_MASTER_MOSI_PORT 0 2217 #define RTE_GSPI_MASTER_MOSI_PIN 57 2218 #define RTE_GSPI_MASTER_MOSI_MUX 4 2219 #define RTE_GSPI_MASTER_MOSI_PAD 21 2220 #elif(RTE_GSPI_MASTER_MOSI_PORT_ID ==4) 2221 #define RTE_GSPI_MASTER_MOSI_PORT 0 2222 #define RTE_GSPI_MASTER_MOSI_PIN 6 2223 #define RTE_GSPI_MASTER_MOSI_MUX 12 2224 #define RTE_GSPI_MASTER_MOSI_PAD 1 2225 #else 2226 #error "Invalid GSPI0 RTE_GSPI_MASTER_MOSI_PIN Pin Configuration!" 2227 #endif 2228 2229 // <o> GSPI_MASTER_MISO <0=>P0_11 <1=>P0_26 <2=>P0_47 <3=>P0_56 2230 // <i> MISO of GSPI0 2231 #ifndef CHIP_917_6x6 2232 #define RTE_GSPI_MASTER_MISO_PORT_ID 1 2233 #endif 2234 #ifdef CHIP_917_6x6 2235 #define RTE_GSPI_MASTER_MISO_PORT_ID 1 2236 #if((RTE_GSPI_MASTER_MISO_PORT_ID == 2)||(RTE_GSPI_MASTER_MISO_PORT_ID == 3)) 2237 #error "Invalid GSPI0 RTE_GSPI_MASTER_MISO_PIN pin Configuration!" 2238 #endif 2239 #endif 2240 #if(RTE_GSPI_MASTER_MISO_PORT_ID == 0) 2241 #define RTE_GSPI_MASTER_MISO_PORT 0 2242 #define RTE_GSPI_MASTER_MISO_PIN 11 2243 #define RTE_GSPI_MASTER_MISO_MUX 4 2244 #define RTE_GSPI_MASTER_MISO_PAD 6 2245 #elif(RTE_GSPI_MASTER_MISO_PORT_ID ==1) 2246 #define RTE_GSPI_MASTER_MISO_PORT 0 2247 #define RTE_GSPI_MASTER_MISO_PIN 26 2248 #define RTE_GSPI_MASTER_MISO_MUX 4 2249 #define RTE_GSPI_MASTER_MISO_PAD 0//NO PAD 2250 #elif(RTE_GSPI_MASTER_MISO_PORT_ID ==2) 2251 #define RTE_GSPI_MASTER_MISO_PORT 0 2252 #define RTE_GSPI_MASTER_MISO_PIN 47 2253 #define RTE_GSPI_MASTER_MISO_MUX 4 2254 #define RTE_GSPI_MASTER_MISO_PAD 11 2255 #elif(RTE_GSPI_MASTER_MISO_PORT_ID ==3) 2256 #define RTE_GSPI_MASTER_MISO_PORT 0 2257 #define RTE_GSPI_MASTER_MISO_PIN 56 2258 #define RTE_GSPI_MASTER_MISO_MUX 4 2259 #define RTE_GSPI_MASTER_MISO_PAD 20 2260 #else 2261 #error "Invalid GSPI0 RTE_GSPI_MASTER_MISO_PIN Pin Configuration!" 2262 #endif 2263 2264 #if defined(HIGH_THROUGHPUT_EN) && (HIGH_THROUGHPUT_EN == 1) 2265 #define RTE_GSPI_MASTER_CHNL_UDMA_TX_EN 1 2266 #define RTE_GSPI_MASTER_CHNL_UDMA_TX_CH 11 2267 2268 2269 #define RTE_GSPI_MASTER_CHNL_UDMA_RX_EN 1 2270 #define RTE_GSPI_MASTER_CHNL_UDMA_RX_CH 10 2271 2272 #define RTE_FIFO_AFULL_THRLD 3 2273 #define RTE_FIFO_AEMPTY_THRLD 7 2274 2275 #define TX_DMA_ARB_SIZE ARBSIZE_4 2276 #define RX_DMA_ARB_SIZE ARBSIZE_8 2277 #else 2278 #define RTE_GSPI_MASTER_CHNL_UDMA_TX_EN 0 2279 #define RTE_GSPI_MASTER_CHNL_UDMA_TX_CH 11 2280 2281 #define RTE_GSPI_MASTER_CHNL_UDMA_RX_EN 0 2282 #define RTE_GSPI_MASTER_CHNL_UDMA_RX_CH 10 2283 2284 #define RTE_FIFO_AFULL_THRLD 0 2285 #define RTE_FIFO_AEMPTY_THRLD 0 2286 2287 #define TX_DMA_ARB_SIZE ARBSIZE_1 2288 #define RX_DMA_ARB_SIZE ARBSIZE_1 2289 #endif 2290 2291 // </e>(Generic SPI master)[Driver_GSPI_MASTER] 2292 2293 2294 // <o>(State Configurable Timer) Interface 2295 #define SCT_CLOCK_SOURCE CT_INTFPLLCLK 2296 #define SCT_CLOCK_DIV_FACT 2 2297 2298 //SCT_IN_0 <0=>GPIO_25 <1=>GPIO_64 <2=>GPIO_68 2299 #ifndef CHIP_917_6x6 2300 #define RTE_SCT_IN_0_PORT_ID 1 2301 #endif 2302 #ifdef CHIP_917_6x6 2303 #define RTE_SCT_IN_0_PORT_ID 0 2304 #if((RTE_SCT_IN_0_PORT_ID == 1)) 2305 #error "Invalid RTE_SCT_IN_0_PIN pin Configuration!" 2306 #endif 2307 #endif 2308 #if(RTE_SCT_IN_0_PORT_ID == 0) 2309 #define RTE_SCT_IN_0_PORT 0 2310 #define RTE_SCT_IN_0_PIN 25 2311 #define RTE_SCT_IN_0_MUX 9 2312 #define RTE_SCT_IN_0_PAD 0//no pad 2313 #elif(RTE_SCT_IN_0_PORT_ID == 1) 2314 #define RTE_SCT_IN_0_PORT 0 2315 #define RTE_SCT_IN_0_PIN 64 2316 #define RTE_SCT_IN_0_MUX 7 2317 #define RTE_SCT_IN_0_PAD 22 2318 #elif(RTE_SCT_IN_0_PORT_ID == 2) 2319 #define RTE_SCT_IN_0_PORT 0 2320 #define RTE_SCT_IN_0_PIN 68 2321 #define RTE_SCT_IN_0_MUX 9 2322 #define RTE_SCT_IN_0_PAD 26 2323 #else 2324 #error "Invalid RTE_SCT_IN_0_PIN Pin Configuration!" 2325 #endif 2326 2327 //SCT_IN_1 <0=>GPIO_26 <1=>GPIO_65 <2=>GPIO_69 2328 #ifndef CHIP_917_6x6 2329 #define RTE_SCT_IN_1_PORT_ID 1 2330 #endif 2331 #ifdef CHIP_917_6x6 2332 #define RTE_SCT_IN_1_PORT_ID 0 2333 #if((RTE_SCT_IN_1_PORT_ID == 1)) 2334 #error "Invalid RTE_SCT_IN_1_PIN pin Configuration!" 2335 #endif 2336 #endif 2337 #if(RTE_SCT_IN_1_PORT_ID == 0) 2338 #define RTE_SCT_IN_1_PORT 0 2339 #define RTE_SCT_IN_1_PIN 26 2340 #define RTE_SCT_IN_1_MUX 9 2341 #define RTE_SCT_IN_1_PAD 0//no pad 2342 #elif(RTE_SCT_IN_1_PORT_ID == 1) 2343 #define RTE_SCT_IN_1_PORT 0 2344 #define RTE_SCT_IN_1_PIN 65 2345 #define RTE_SCT_IN_1_MUX 7 2346 #define RTE_SCT_IN_1_PAD 23 2347 #elif(RTE_SCT_IN_1_PORT_ID == 2) 2348 #define RTE_SCT_IN_1_PORT 0 2349 #define RTE_SCT_IN_1_PIN 69 2350 #define RTE_SCT_IN_1_MUX 9 2351 #define RTE_SCT_IN_1_PAD 27 2352 #else 2353 #error "Invalid RTE_SCT_IN_1_PIN Pin Configuration!" 2354 #endif 2355 2356 //SCT_IN_2 <0=>GPIO_27 <1=>GPIO_66 <2=>GPIO_70 2357 #ifndef CHIP_917_6x6 2358 #ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER 2359 #define RTE_SCT_IN_2_PORT_ID 0 2360 #else 2361 #define RTE_SCT_IN_2_PORT_ID 1 2362 #endif 2363 #endif 2364 #ifdef CHIP_917_6x6 2365 #define RTE_SCT_IN_2_PORT_ID 0 2366 #if((RTE_SCT_IN_2_PORT_ID == 1)) 2367 #error "Invalid RTE_SCT_IN_2_PIN pin Configuration!" 2368 #endif 2369 #endif 2370 #if(RTE_SCT_IN_2_PORT_ID == 0) 2371 #define RTE_SCT_IN_2_PORT 0 2372 #define RTE_SCT_IN_2_PIN 27 2373 #define RTE_SCT_IN_2_MUX 9 2374 #define RTE_SCT_IN_2_PAD 0//no pad 2375 #elif(RTE_SCT_IN_2_PORT_ID == 1) 2376 #define RTE_SCT_IN_2_PORT 0 2377 #define RTE_SCT_IN_2_PIN 66 2378 #define RTE_SCT_IN_2_MUX 7 2379 #define RTE_SCT_IN_2_PAD 24 2380 #elif(RTE_SCT_IN_2_PORT_ID == 2) 2381 #define RTE_SCT_IN_2_PORT 0 2382 #define RTE_SCT_IN_2_PIN 70 2383 #define RTE_SCT_IN_2_MUX 9 2384 #define RTE_SCT_IN_2_PAD 28 2385 #else 2386 #error "Invalid RTE_SCT_IN_0_PIN Pin Configuration!" 2387 #endif 2388 2389 //SCT_IN_3 <0=>GPIO_28 <1=>GPIO_67 <2=>GPIO_71 2390 #ifndef CHIP_917_6x6 2391 #ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER 2392 #define RTE_SCT_IN_3_PORT_ID 0 2393 #else 2394 #define RTE_SCT_IN_3_PORT_ID 1 2395 #endif 2396 #endif 2397 #ifdef CHIP_917_6x6 2398 #define RTE_SCT_IN_3_PORT_ID 0 2399 #if((RTE_SCT_IN_3_PORT_ID == 1)) 2400 #error "Invalid RTE_SCT_IN_3_PIN pin Configuration!" 2401 #endif 2402 #endif 2403 #if(RTE_SCT_IN_3_PORT_ID == 0) 2404 #define RTE_SCT_IN_3_PORT 0 2405 #define RTE_SCT_IN_3_PIN 28 2406 #define RTE_SCT_IN_3_MUX 9 2407 #define RTE_SCT_IN_3_PAD 0//no pad 2408 #elif(RTE_SCT_IN_3_PORT_ID == 1) 2409 #define RTE_SCT_IN_3_PORT 0 2410 #define RTE_SCT_IN_3_PIN 67 2411 #define RTE_SCT_IN_3_MUX 7 2412 #define RTE_SCT_IN_3_PAD 25 2413 #elif(RTE_SCT_IN_3_PORT_ID == 2) 2414 #define RTE_SCT_IN_3_PORT 0 2415 #define RTE_SCT_IN_3_PIN 71 2416 #define RTE_SCT_IN_3_MUX 9 2417 #define RTE_SCT_IN_3_PAD 29 2418 #else 2419 #error "Invalid RTE_SCT_IN_0_PIN Pin Configuration!" 2420 #endif 2421 2422 // SCT_OUT_0 <0=>GPIO_29 <1=>GPIO_68 2423 #define RTE_SCT_OUT_0_PORT_ID 0 2424 #if(RTE_SCT_OUT_0_PORT_ID == 0) 2425 #define RTE_SCT_OUT_0_PORT 0 2426 #define RTE_SCT_OUT_0_PIN 29 2427 #define RTE_SCT_OUT_0_MUX 9 2428 #define RTE_SCT_OUT_0_PAD 0//no pad 2429 #elif(RTE_SCT_OUT_0_PORT_ID ==1) 2430 #define RTE_SCT_OUT_0_PORT 0 2431 #define RTE_SCT_OUT_0_PIN 68 2432 #define RTE_SCT_OUT_0_MUX 7 2433 #define RTE_SCT_OUT_0_PAD 26 2434 #else 2435 #error "Invalid RTE_SCT_OUT_0_PIN Pin Configuration!" 2436 #endif 2437 2438 // SCT_OUT_1 <0=>GPIO_30 <1=>GPIO_69 2439 #define RTE_SCT_OUT_1_PORT_ID 0 2440 #if(RTE_SCT_OUT_1_PORT_ID == 0) 2441 #define RTE_SCT_OUT_1_PORT 0 2442 #define RTE_SCT_OUT_1_PIN 30 2443 #define RTE_SCT_OUT_1_MUX 9 2444 #define RTE_SCT_OUT_1_PAD 0//no pad 2445 #elif(RTE_SCT_OUT_1_PORT_ID == 1) 2446 #define RTE_SCT_OUT_1_PORT 0 2447 #define RTE_SCT_OUT_1_PIN 69 2448 #define RTE_SCT_OUT_1_MUX 7 2449 #define RTE_SCT_OUT_1_PAD 27 2450 #else 2451 #error "Invalid RTE_SCT_OUT_1_PIN Pin Configuration!" 2452 #endif 2453 2454 /// SCT_OUT_2 <0=>GPIO_70 <1=>GPIO_8 2455 #define RTE_SCT_OUT_2_PORT_ID 0 2456 #ifndef CHIP_917_6x6 2457 #if((RTE_SCT_OUT_2_PORT_ID == 1)) 2458 #error "Invalid RTE_SCT_OUT_2_PIN pin Configuration!" 2459 #endif 2460 #endif 2461 #if(RTE_SCT_OUT_2_PORT_ID == 0) 2462 #define RTE_SCT_OUT_2_PORT 0 2463 #define RTE_SCT_OUT_2_PIN 70 2464 #define RTE_SCT_OUT_2_MUX 7 2465 #define RTE_SCT_OUT_2_PAD 28 2466 #elif(RTE_SCT_OUT_2_PORT_ID == 1) 2467 #define RTE_SCT_OUT_2_PORT 0 2468 #define RTE_SCT_OUT_2_PIN 8 2469 #define RTE_SCT_OUT_2_MUX 12 2470 #define RTE_SCT_OUT_2_PAD 3 2471 #else 2472 #error "Invalid RTE_SCT_OUT_2_PIN Pin Configuration!" 2473 #endif 2474 /**/ 2475 //SCT_OUT_3 <0=>GPIO_71 <1=>GPIO_9 2476 #define RTE_SCT_OUT_3_PORT_ID 0 2477 #ifndef CHIP_917_6x6 2478 #if((RTE_SCT_OUT_3_PORT_ID == 1)) 2479 #error "Invalid RTE_SCT_OUT_3_PIN pin Configuration!" 2480 #endif 2481 #endif 2482 #if(RTE_SCT_OUT_3_PORT_ID == 0) 2483 #define RTE_SCT_OUT_3_PORT 0 2484 #define RTE_SCT_OUT_3_PIN 71 2485 #define RTE_SCT_OUT_3_MUX 7 2486 #define RTE_SCT_OUT_3_PAD 29 2487 #elif(RTE_SCT_OUT_3_PORT_ID == 1) 2488 #define RTE_SCT_OUT_3_PORT 0 2489 #define RTE_SCT_OUT_3_PIN 9 2490 #define RTE_SCT_OUT_3_MUX 12 2491 #define RTE_SCT_OUT_3_PAD 4 2492 #else 2493 #error "Invalid RTE_SCT_OUT_3_PIN Pin Configuration!" 2494 #endif 2495 2496 //SCT_OUT_4 <0=>GPIO_72 <1=>GPIO_68 2497 2498 #ifndef CHIP_917_6x6 2499 #define RTE_SCT_OUT_4_PORT_ID 0 2500 #if((RTE_SCT_OUT_4_PORT_ID == 1)) 2501 #error "Invalid RTE_SCT_OUT_4_PIN pin Configuration!" 2502 #endif 2503 #endif 2504 #ifdef CHIP_917_6x6 2505 #define RTE_SCT_OUT_4_PORT_ID 1 2506 #if((RTE_SCT_OUT_4_PORT_ID == 0)) 2507 #error "Invalid RTE_SCT_OUT_4_PIN pin Configuration!" 2508 #endif 2509 #endif 2510 #if(RTE_SCT_OUT_4_PORT_ID == 0) 2511 /**/ 2512 #define RTE_SCT_OUT_4_PORT 0 2513 #define RTE_SCT_OUT_4_PIN 72 2514 #define RTE_SCT_OUT_4_MUX 7 2515 #define RTE_SCT_OUT_4_PAD 30 2516 #elif(RTE_SCT_OUT_4_PORT_ID == 1) 2517 #define RTE_SCT_OUT_4_PORT 0 2518 #define RTE_SCT_OUT_4_PIN 68 2519 #define RTE_SCT_OUT_4_MUX 13 2520 #define RTE_SCT_OUT_4_PAD 26 2521 #else 2522 #error "Invalid RTE_SCT_OUT_4_PIN Pin Configuration!" 2523 #endif 2524 //SCT_OUT_5 <0=>GPIO_73 <1=>GPIO_69 2525 #ifndef CHIP_917_6x6 2526 #define RTE_SCT_OUT_5_PORT_ID 0 2527 #if((RTE_SCT_OUT_5_PORT_ID == 1)) 2528 #error "Invalid RTE_SCT_OUT_5_PIN pin Configuration!" 2529 #endif 2530 #endif 2531 #ifdef CHIP_917_6x6 2532 #define RTE_SCT_OUT_5_PORT_ID 1 2533 #if((RTE_SCT_OUT_5_PORT_ID == 0)) 2534 #error "Invalid RTE_SCT_OUT_5_PIN pin Configuration!" 2535 #endif 2536 #endif 2537 #if(RTE_SCT_OUT_5_PORT_ID == 0) 2538 #define RTE_SCT_OUT_5_PORT 2 2539 #define RTE_SCT_OUT_5_PIN 73 2540 #define RTE_SCT_OUT_5_MUX 7 2541 #define RTE_SCT_OUT_5_PAD 31 2542 #elif(RTE_SCT_OUT_5_PORT_ID == 1) 2543 #define RTE_SCT_OUT_5_PORT 0 2544 #define RTE_SCT_OUT_5_PIN 69 2545 #define RTE_SCT_OUT_5_MUX 13 2546 #define RTE_SCT_OUT_5_PAD 27 2547 #else 2548 #error "Invalid RTE_SCT_OUT_5_PIN Pin Configuration!" 2549 #endif 2550 2551 //SCT_OUT_6 <0=>GPIO_74 <1=>GPIO_70 2552 #ifndef CHIP_917_6x6 2553 #define RTE_SCT_OUT_6_PORT_ID 0 2554 #if((RTE_SCT_OUT_6_PORT_ID == 1)) 2555 #error "Invalid RTE_SCT_OUT_6_PIN pin Configuration!" 2556 #endif 2557 #endif 2558 #ifdef CHIP_917_6x6 2559 #define RTE_SCT_OUT_6_PORT_ID 1 2560 #if((RTE_SCT_OUT_6_PORT_ID == 0)) 2561 #error "Invalid RTE_SCT_OUT_6_PIN pin Configuration!" 2562 #endif 2563 #endif 2564 #if(RTE_SCT_OUT_6_PORT_ID == 0) 2565 #define RTE_SCT_OUT_6_PORT 0 2566 #define RTE_SCT_OUT_6_PIN 74 2567 #define RTE_SCT_OUT_6_MUX 7 2568 #define RTE_SCT_OUT_6_PAD 32 2569 #elif(RTE_SCT_OUT_6_PORT_ID == 1) 2570 #define RTE_SCT_OUT_6_PORT 0 2571 #define RTE_SCT_OUT_6_PIN 70 2572 #define RTE_SCT_OUT_6_MUX 13 2573 #define RTE_SCT_OUT_6_PAD 28 2574 #else 2575 #error "Invalid RTE_SCT_OUT_6_PIN Pin Configuration!" 2576 #endif 2577 2578 // SCT_OUT_7 <0=>GPIO_75 <1=>GPIO_71 2579 2580 #ifndef CHIP_917_6x6 2581 #define RTE_SCT_OUT_7_PORT_ID 0 2582 #if((RTE_SCT_OUT_7_PORT_ID == 1)) 2583 #error "Invalid RTE_SCT_OUT_7_PIN pin Configuration!" 2584 #endif 2585 #endif 2586 #ifdef CHIP_917_6x6 2587 #define RTE_SCT_OUT_7_PORT_ID 1 2588 #if((RTE_SCT_OUT_7_PORT_ID == 0)) 2589 #error "Invalid RTE_SCT_OUT_7_PIN pin Configuration!" 2590 #endif 2591 #endif 2592 #if(RTE_SCT_OUT_7_PORT_ID == 0) 2593 #define RTE_SCT_OUT_7_PORT 0 2594 #define RTE_SCT_OUT_7_PIN 75 2595 #define RTE_SCT_OUT_7_MUX 7 2596 #define RTE_SCT_OUT_7_PAD 33 2597 #elif(RTE_SCT_OUT_7_PORT_ID == 1) 2598 #define RTE_SCT_OUT_7_PORT 0 2599 #define RTE_SCT_OUT_7_PIN 71 2600 #define RTE_SCT_OUT_7_MUX 13 2601 #define RTE_SCT_OUT_7_PAD 29 2602 #else 2603 #error "Invalid RTE_SCT_OUT_7_PIN Pin Configuration!" 2604 #endif 2605 2606 // SIO // 2607 //<> Serial Input Output 2608 //SIO_0 <0=>GPIO_6 <1=>GPIO_25 <2=>GPIO_64 <3=>GPIO_72 2609 #ifndef CHIP_917_6x6 2610 #define RTE_SIO_0_PORT_ID 0 2611 #endif 2612 #ifdef CHIP_917_6x6 2613 #define RTE_SIO_0_PORT_ID 0 2614 #if((RTE_SIO_0_PORT_ID == 2)||(RTE_SIO_0_PORT_ID == 3)) 2615 #error "Invalid RTE_SIO_0_PIN pin Configuration!" 2616 #endif 2617 #endif 2618 #if(RTE_SIO_0_PORT_ID == 0) 2619 #define RTE_SIO_0_PORT 0 2620 #define RTE_SIO_0_PIN 6 2621 #define RTE_SIO_0_MUX 1 2622 #define RTE_SIO_0_PAD 1 2623 #elif(RTE_SIO_0_PORT_ID == 1) 2624 #define RTE_SIO_0_PORT 0 2625 #define RTE_SIO_0_PIN 25 2626 #define RTE_SIO_0_MUX 1 2627 #define RTE_SIO_0_PAD 0//no pad 2628 #elif(RTE_SIO_0_PORT_ID == 2) 2629 #define RTE_SIO_0_PORT 0 2630 #define RTE_SIO_0_PIN 64 2631 #define RTE_SIO_0_MUX 1 2632 #define RTE_SIO_0_PAD 22 2633 #elif(RTE_SIO_0_PORT_ID == 3) 2634 #define RTE_SIO_0_PORT 0 2635 #define RTE_SIO_0_PIN 72 2636 #define RTE_SIO_0_MUX 1 2637 #define RTE_SIO_0_PAD 30 2638 #else 2639 #error "Invalid RTE_SIO_0_PIN Pin Configuration!" 2640 #endif 2641 2642 //SIO_1 <0=>GPIO_7 <1=>GPIO_26 <2=>GPIO_65 <3=>GPIO_73 2643 #ifndef CHIP_917_6x6 2644 #ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER 2645 #define RTE_SIO_1_PORT_ID 1 2646 #else 2647 #define RTE_SIO_1_PORT_ID 0 2648 #endif 2649 #endif 2650 #ifdef CHIP_917_6x6 2651 #define RTE_SIO_1_PORT_ID 1 2652 #if((RTE_SIO_1_PORT_ID == 2)||(RTE_SIO_1_PORT_ID == 3)) 2653 #error "Invalid RTE_SIO_1_PIN Configuration!" 2654 #endif 2655 #endif 2656 #if(RTE_SIO_1_PORT_ID == 0) 2657 #define RTE_SIO_1_PORT 0 2658 #define RTE_SIO_1_PIN 7 2659 #define RTE_SIO_1_MUX 1 2660 #define RTE_SIO_1_PAD 2 2661 #elif(RTE_SIO_1_PORT_ID == 1) 2662 #define RTE_SIO_1_PORT 0 2663 #define RTE_SIO_1_PIN 26 2664 #define RTE_SIO_1_MUX 1 2665 #define RTE_SIO_1_PAD 0// no pad 2666 #elif(RTE_SIO_1_PORT_ID == 2) 2667 #define RTE_SIO_1_PORT 0 2668 #define RTE_SIO_1_PIN 65 2669 #define RTE_SIO_1_MUX 1 2670 #define RTE_SIO_1_PAD 23 2671 #elif(RTE_SIO_1_PORT_ID == 3) 2672 #define RTE_SIO_1_PORT 0 2673 #define RTE_SIO_1_PIN 73 2674 #define RTE_SIO_1_MUX 1 2675 #define RTE_SIO_1_PAD 31 2676 #else 2677 #error "Invalid RTE_SIO_1_PIN Pin Configuration!" 2678 #endif 2679 2680 2681 // SIO_2 <0=>GPIO_8 <1=>GPIO_27 <2=>GPIO_66 <3=>GPIO_74 2682 #ifndef CHIP_917_6x6 2683 #define RTE_SIO_2_PORT_ID 1 2684 #endif 2685 #ifdef CHIP_917_6x6 2686 #define RTE_SIO_2_PORT_ID 0 2687 #if((RTE_SIO_2_PORT_ID == 2)||(RTE_SIO_2_PORT_ID == 3)) 2688 #error "Invalid RTE_SIO_2_PIN Configuration!" 2689 #endif 2690 #endif 2691 #if(RTE_SIO_2_PORT_ID == 0) 2692 #define RTE_SIO_2_PORT 0 2693 #define RTE_SIO_2_PIN 8 2694 #define RTE_SIO_2_MUX 1 2695 #define RTE_SIO_2_PAD 3 2696 #elif(RTE_SIO_2_PORT_ID == 1) 2697 #define RTE_SIO_2_PORT 0 2698 #define RTE_SIO_2_PIN 27 2699 #define RTE_SIO_2_MUX 1 2700 #define RTE_SIO_2_PAD 0//no pad 2701 #elif(RTE_SIO_2_PORT_ID == 2) 2702 #define RTE_SIO_2_PORT 0 2703 #define RTE_SIO_2_PIN 66 2704 #define RTE_SIO_2_MUX 1 2705 #define RTE_SIO_2_PAD 24 2706 #elif(RTE_SIO_2_PORT_ID == 3) 2707 #define RTE_SIO_2_PORT 0 2708 #define RTE_SIO_2_PIN 74 2709 #define RTE_SIO_2_MUX 1 2710 #define RTE_SIO_2_PAD 32 2711 #else 2712 #error "Invalid RTE_SIO_2_PIN Pin Configuration!" 2713 #endif 2714 2715 2716 2717 //SIO_3 <0=>GPIO_9 <1=>GPIO_28 <2=>GPIO_67 <3=>GPIO_75 2718 #ifndef CHIP_917_6x6 2719 #define RTE_SIO_3_PORT_ID 1 2720 #endif 2721 #ifdef CHIP_917_6x6 2722 #define RTE_SIO_3_PORT_ID 0 2723 #if((RTE_SIO_3_PORT_ID == 2)||(RTE_SIO_3_PORT_ID == 3)) 2724 #error "Invalid RTE_SIO_3_PIN Configuration!" 2725 #endif 2726 #endif 2727 #if(RTE_SIO_3_PORT_ID == 0) 2728 #define RTE_SIO_3_PORT 0 2729 #define RTE_SIO_3_PIN 9 2730 #define RTE_SIO_3_MUX 1 2731 #define RTE_SIO_3_PAD 4 2732 #elif(RTE_SIO_3_PORT_ID == 1) 2733 #define RTE_SIO_3_PORT 0 2734 #define RTE_SIO_3_PIN 28 2735 #define RTE_SIO_3_MUX 1 2736 #define RTE_SIO_3_PAD 0//no pad 2737 #elif(RTE_SIO_3_PORT_ID == 2) 2738 #define RTE_SIO_3_PORT 0 2739 #define RTE_SIO_3_PIN 67 2740 #define RTE_SIO_3_MUX 1 2741 #define RTE_SIO_3_PAD 25 2742 #elif(RTE_SIO_3_PORT_ID == 3) 2743 #define RTE_SIO_3_PORT 0 2744 #define RTE_SIO_3_PIN 75 2745 #define RTE_SIO_3_MUX 1 2746 #define RTE_SIO_3_PAD 33 2747 #else 2748 #error "Invalid RTE_SIO_3_PIN Pin Configuration!" 2749 #endif 2750 2751 2752 //SIO_4 <0=>GPIO_10 <1=>GPIO_29 <2=>GPIO_68 2753 #ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER 2754 #define RTE_SIO_4_PORT_ID 1 2755 #else 2756 #define RTE_SIO_4_PORT_ID 0 2757 #endif 2758 #if(RTE_SIO_4_PORT_ID == 0) 2759 #define RTE_SIO_4_PORT 0 2760 #define RTE_SIO_4_PIN 10 2761 #define RTE_SIO_4_MUX 1 2762 #define RTE_SIO_4_PAD 5 2763 #elif(RTE_SIO_4_PORT_ID == 1) 2764 #define RTE_SIO_4_PORT 0 2765 #define RTE_SIO_4_PIN 29 2766 #define RTE_SIO_4_MUX 1 2767 #define RTE_SIO_4_PAD 0//NO PAD 2768 #elif(RTE_SIO_4_PORT_ID == 2) 2769 #define RTE_SIO_4_PORT 0 2770 #define RTE_SIO_4_PIN 68 2771 #define RTE_SIO_4_MUX 1 2772 #define RTE_SIO_4_PAD 26 2773 #else 2774 #error "Invalid RTE_SIO_3_PIN Pin Configuration!" 2775 #endif 2776 2777 // SIO_5 <0=>GPIO_11 <1=>GPIO_30 <2=>GPIO_69 2778 #define RTE_SIO_5_PORT_ID 0 2779 #if(RTE_SIO_5_PORT_ID == 0) 2780 #define RTE_SIO_5_PORT 0 2781 #define RTE_SIO_5_PIN 11 2782 #define RTE_SIO_5_MUX 1 2783 #define RTE_SIO_5_PAD 6 2784 #elif(RTE_SIO_5_PORT_ID == 1) 2785 #define RTE_SIO_5_PORT 0 2786 #define RTE_SIO_5_PIN 30 2787 #define RTE_SIO_5_MUX 1 2788 #define RTE_SIO_5_PAD 0//no pad 2789 #elif(RTE_SIO_5_PORT_ID == 2) 2790 #define RTE_SIO_5_PORT 0 2791 #define RTE_SIO_5_PIN 69 2792 #define RTE_SIO_5_MUX 1 2793 #define RTE_SIO_5_PAD 27 2794 #else 2795 #error "Invalid RTE_SIO_5_PIN Pin Configuration!" 2796 #endif 2797 2798 // SIO_6 GPIO_70 2799 #define RTE_SIO_6_PORT 0 2800 #define RTE_SIO_6_PIN 70 2801 #define RTE_SIO_6_MUX 1 2802 #define RTE_SIO_6_PAD 28 2803 2804 // SIO_7 <0=>GPIO_15 <1=>GPIO_71 2805 #ifndef CHIP_917_6x6 2806 #ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER 2807 #define RTE_SIO_7_PORT_ID 1 2808 #else 2809 #define RTE_SIO_7_PORT_ID 0 2810 #endif 2811 #endif 2812 #ifdef CHIP_917_6x6 2813 #define RTE_SIO_7_PORT_ID 1 2814 #if((RTE_SIO_7_PORT_ID == 0)) 2815 #error "Invalid RTE_SIO_7_PIN Configuration!" 2816 #endif 2817 #endif 2818 #if(RTE_SIO_7_PORT_ID == 0) 2819 #define RTE_SIO_7_PORT 0 2820 #define RTE_SIO_7_PIN 15 2821 #define RTE_SIO_7_MUX 1 2822 #define RTE_SIO_7_PAD 8 2823 #elif(RTE_SIO_7_PORT_ID == 1) 2824 #define RTE_SIO_7_PORT 0 2825 #define RTE_SIO_7_PIN 71 2826 #define RTE_SIO_7_MUX 1 2827 #define RTE_SIO_7_PAD 29 2828 #else 2829 #error "Invalid RTE_SIO_7_PIN Pin Configuration!" 2830 #endif 2831 2832 2833 //<> Pulse Width Modulation 2834 //PWM_1H <0=>GPIO_7 <1=>GPIO_64 <2=>GPIO_65 2835 #ifndef CHIP_917_6x6 2836 #ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER 2837 #define RTE_PWM_1H_PORT_ID 0 2838 #else 2839 #define RTE_PWM_1H_PORT_ID 1 2840 #endif 2841 #endif 2842 #ifdef CHIP_917_6x6 2843 #define RTE_PWM_1H_PORT_ID 0 2844 #if((RTE_PWM_1H_PORT_ID == 1)) 2845 #error "Invalid RTE_PWM_1H_PIN Configuration!" 2846 #endif 2847 #endif 2848 #if(RTE_PWM_1H_PORT_ID == 0) 2849 #define RTE_PWM_1H_PORT 0 2850 #define RTE_PWM_1H_PIN 7 2851 #define RTE_PWM_1H_MUX 10 2852 #define RTE_PWM_1H_PAD 2 2853 #elif(RTE_PWM_1H_PORT_ID == 1) 2854 #define RTE_PWM_1H_PORT 0 2855 #define RTE_PWM_1H_PIN 65 2856 #define RTE_PWM_1H_MUX 8 2857 #define RTE_PWM_1H_PAD 22 2858 #else 2859 #error "Invalid RTE_PWM_1H_PIN Pin Configuration!" 2860 #endif 2861 2862 2863 // PWM_1L <0=>GPIO_6 <1=>GPIO_64 <2=>GPIO_64 2864 #ifndef CHIP_917_6x6 2865 #ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER 2866 #define RTE_PWM_1L_PORT_ID 1 2867 #else 2868 #define RTE_PWM_1L_PORT_ID 0 2869 #endif 2870 #endif 2871 #ifdef CHIP_917_6x6 2872 #define RTE_PWM_1L_PORT_ID 0 2873 #if((RTE_PWM_1L_PORT_ID == 1)) 2874 #error "Invalid RTE_PWM_1L_PIN Configuration!" 2875 #endif 2876 #endif 2877 #if(RTE_PWM_1L_PORT_ID == 0) 2878 #define RTE_PWM_1L_PORT 0 2879 #define RTE_PWM_1L_PIN 6 2880 #define RTE_PWM_1L_MUX 10 2881 #define RTE_PWM_1L_PAD 1 2882 #elif(RTE_PWM_1L_PORT_ID == 1) 2883 #define RTE_PWM_1L_PORT 0 2884 #define RTE_PWM_1L_PIN 64 2885 #define RTE_PWM_1L_MUX 8 2886 #define RTE_PWM_1L_PAD 22 2887 #else 2888 #error "Invalid RTE_PWM_1L_PIN Pin Configuration!" 2889 #endif 2890 2891 //PWM_2H <0=>GPIO_9 <1=>GPIO_67 <2=>GPIO_69 2892 #ifndef CHIP_917_6x6 2893 #define RTE_PWM_2H_PORT_ID 0 2894 #if((RTE_PWM_2H_PORT_ID == 2)) 2895 #error "Invalid RTE_PWM_2H_PIN pin Configuration!" 2896 #endif 2897 #endif 2898 #ifdef CHIP_917_6x6 2899 #define RTE_PWM_2H_PORT_ID 0 2900 #if((RTE_PWM_2H_PORT_ID == 1)) 2901 #error "Invalid RTE_PWM_2H_PIN pin Configuration!" 2902 #endif 2903 #endif 2904 #if(RTE_PWM_2H_PORT_ID == 0) 2905 #define RTE_PWM_2H_PORT 0 2906 #define RTE_PWM_2H_PIN 9 2907 #define RTE_PWM_2H_MUX 10 2908 #define RTE_PWM_2H_PAD 4 2909 #elif(RTE_PWM_2H_PORT_ID == 1) 2910 #define RTE_PWM_2H_PORT 0 2911 #define RTE_PWM_2H_PIN 67 2912 #define RTE_PWM_2H_MUX 8 2913 #define RTE_PWM_2H_PAD 25 2914 #elif(RTE_PWM_2H_PORT_ID == 2) 2915 #define RTE_PWM_2H_PORT 0 2916 #define RTE_PWM_2H_PIN 69 2917 #define RTE_PWM_2H_MUX 12 2918 #define RTE_PWM_2H_PAD 27 2919 #else 2920 #error "Invalid RTE_PWM_2H_PIN Pin Configuration!" 2921 #endif 2922 2923 2924 // PWM_2L <0=>GPIO_8 <1=>GPIO_66 <2=>GPIO_68 2925 #ifndef CHIP_917_6x6 2926 #define RTE_PWM_2L_PORT_ID 0 2927 #if((RTE_PWM_2L_PORT_ID == 2)) 2928 #error "Invalid RTE_PWM_2L_PIN pin Configuration!" 2929 #endif 2930 #endif 2931 #ifdef CHIP_917_6x6 2932 #define RTE_PWM_2L_PORT_ID 0 2933 #if((RTE_PWM_2L_PORT_ID == 1)) 2934 #error "Invalid RTE_PWM_2L_PIN pin Configuration!" 2935 #endif 2936 #endif 2937 #if(RTE_PWM_2L_PORT_ID == 0) 2938 #define RTE_PWM_2L_PORT 0 2939 #define RTE_PWM_2L_PIN 8 2940 #define RTE_PWM_2L_MUX 10 2941 #define RTE_PWM_2L_PAD 3 2942 #elif(RTE_PWM_2L_PORT_ID == 1) 2943 #define RTE_PWM_2L_PORT 0 2944 #define RTE_PWM_2L_PIN 66 2945 #define RTE_PWM_2L_MUX 8 2946 #define RTE_PWM_2L_PAD 24 2947 #elif(RTE_PWM_2L_PORT_ID == 2) 2948 #define RTE_PWM_2L_PORT 0 2949 #define RTE_PWM_2L_PIN 68 2950 #define RTE_PWM_2L_MUX 12 2951 #define RTE_PWM_2L_PAD 26 2952 #else 2953 #error "Invalid RTE_PWM_2L_PIN Pin Configuration!" 2954 #endif 2955 2956 // PWM_3H <0=>GPIO_11 <1=>GPIO_69 2957 #define RTE_PWM_3H_PORT_ID 0 2958 #if(RTE_PWM_3H_PORT_ID == 0) 2959 #define RTE_PWM_3H_PORT 0 2960 #define RTE_PWM_3H_PIN 11 2961 #define RTE_PWM_3H_MUX 10 2962 #define RTE_PWM_3H_PAD 6 2963 #elif(RTE_PWM_3H_PORT_ID == 1) 2964 #define RTE_PWM_3H_PORT 0 2965 #define RTE_PWM_3H_PIN 69 2966 #define RTE_PWM_3H_MUX 8 2967 #define RTE_PWM_3H_PAD 27 2968 #else 2969 #error "Invalid RTE_PWM_3H_PIN Pin Configuration!" 2970 #endif 2971 2972 // PWM_3L <0=>GPIO_10 <1=>GPIO_68 2973 #ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER 2974 #define RTE_PWM_3L_PORT_ID 1 2975 #else 2976 #define RTE_PWM_3L_PORT_ID 0 2977 #endif 2978 #if(RTE_PWM_3L_PORT_ID == 0) 2979 #define RTE_PWM_3L_PORT 0 2980 #define RTE_PWM_3L_PIN 10 2981 #define RTE_PWM_3L_MUX 10 2982 #define RTE_PWM_3L_PAD 5 2983 #elif(RTE_PWM_3L_PORT_ID == 1) 2984 #define RTE_PWM_3L_PORT 0 2985 #define RTE_PWM_3L_PIN 68 2986 #define RTE_PWM_3L_MUX 8 2987 #define RTE_PWM_3L_PAD 26 2988 #else 2989 #error "Invalid RTE_PWM_3L_PIN Pin Configuration!" 2990 #endif 2991 2992 2993 // PWM_4H <0=>GPIO_15 <1=>GPIO_71 2994 2995 #ifndef CHIP_917_6x6 2996 #ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER 2997 #define RTE_PWM_4H_PORT_ID 1 2998 #else 2999 #define RTE_PWM_4H_PORT_ID 0 3000 #endif 3001 #endif 3002 #ifdef CHIP_917_6x6 3003 #define RTE_PWM_4H_PORT_ID 1 3004 #if((RTE_PWM_4H_PORT_ID == 0)) 3005 #error "Invalid RTE_PWM_4H_PIN pin Configuration!" 3006 #endif 3007 #endif 3008 #if(RTE_PWM_4H_PORT_ID == 0) 3009 #define RTE_PWM_4H_PORT 0 3010 #define RTE_PWM_4H_PIN 15 3011 #define RTE_PWM_4H_MUX 10 3012 #define RTE_PWM_4H_PAD 8 3013 #elif(RTE_PWM_4H_PORT_ID == 1) 3014 #define RTE_PWM_4H_PORT 0 3015 #define RTE_PWM_4H_PIN 71 3016 #define RTE_PWM_4H_MUX 8 3017 #define RTE_PWM_4H_PAD 29 3018 #else 3019 #error "Invalid RTE_PWM_4H_PIN Pin Configuration!" 3020 #endif 3021 3022 3023 // PWM_4H <0=>GPIO_12 <1=>GPIO_70 3024 #ifndef CHIP_917_6x6 3025 #ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER 3026 #define RTE_PWM_4L_PORT_ID 1 3027 #else 3028 #define RTE_PWM_4L_PORT_ID 0 3029 #endif 3030 #endif 3031 #ifdef CHIP_917_6x6 3032 #define RTE_PWM_4L_PORT_ID 1 3033 #if(RTE_PWM_4L_PORT_ID == 0) 3034 #error "Invalid RTE_PWM_4L_PIN pin Configuration!" 3035 #endif 3036 #endif 3037 #if(RTE_PWM_4L_PORT_ID == 0) 3038 #define RTE_PWM_4L_PORT 0 3039 #define RTE_PWM_4L_PIN 12 3040 #define RTE_PWM_4L_MUX 10 3041 #define RTE_PWM_4L_PAD 7 3042 #elif(RTE_PWM_4L_PORT_ID == 1) 3043 #define RTE_PWM_4L_PORT 0 3044 #define RTE_PWM_4L_PIN 70 3045 #define RTE_PWM_4L_MUX 8 3046 #define RTE_PWM_4L_PAD 28 3047 #else 3048 #error "Invalid RTE_PWM_4L_PIN Pin Configuration!" 3049 #endif 3050 3051 3052 // PWM_FAULTA <0=>GPIO_25 <1=>GPIO_68 <1=>GPIO_73 3053 #define RTE_PWM_FAULTA_PORT_ID 0 3054 #ifdef CHIP_917_6x6 3055 #if((RTE_PWM_FAULTA_PORT_ID == 2)) 3056 #error "Invalid RTE_PWM_FAULTA_PIN pin Configuration!" 3057 #endif 3058 #endif 3059 #if(RTE_PWM_FAULTA_PORT_ID == 0) 3060 #define RTE_PWM_FAULTA_PORT 0 3061 #define RTE_PWM_FAULTA_PIN 25 3062 #define RTE_PWM_FAULTA_MUX 10 3063 #define RTE_PWM_FAULTA_PAD 0//no pad 3064 #elif(RTE_PWM_FAULTA_PORT_ID == 1) 3065 #define RTE_PWM_FAULTA_PORT 0 3066 #define RTE_PWM_FAULTA_PIN 68 3067 #define RTE_PWM_FAULTA_MUX 10 3068 #define RTE_PWM_FAULTA_PAD 26 3069 #elif(RTE_PWM_FAULTA_PORT_ID == 2) 3070 #define RTE_PWM_FAULTA_PORT 0 3071 #define RTE_PWM_FAULTA_PIN 73 3072 #define RTE_PWM_FAULTA_MUX 8 3073 #define RTE_PWM_FAULTA_PAD 31 3074 #else 3075 #error "Invalid RTE_PWM_FAULTA_PIN Pin Configuration!" 3076 #endif 3077 3078 // PWM_FAULTB <0=>GPIO_26 <1=>GPIO_69 <1=>GPIO_74 3079 #define RTE_PWM_FAULTB_PORT_ID 0 3080 #ifdef CHIP_917_6x6 3081 #if((RTE_PWM_FAULTB_PORT_ID == 2)) 3082 #error "Invalid RTE_PWM_FAULTB_PIN pin Configuration!" 3083 #endif 3084 #endif 3085 #if(RTE_PWM_FAULTB_PORT_ID == 0) 3086 #define RTE_PWM_FAULTB_PORT 0 3087 #define RTE_PWM_FAULTB_PIN 26 3088 #define RTE_PWM_FAULTB_MUX 10 3089 #define RTE_PWM_FAULTB_PAD 0//no pad 3090 #elif(RTE_PWM_FAULTB_PORT_ID == 1) 3091 #define RTE_PWM_FAULTB_PORT 0 3092 #define RTE_PWM_FAULTB_PIN 69 3093 #define RTE_PWM_FAULTB_MUX 10 3094 #define RTE_PWM_FAULTB_PAD 27 3095 #elif(RTE_PWM_FAULTB_PORT_ID == 2) 3096 #define RTE_PWM_FAULTB_PORT 0 3097 #define RTE_PWM_FAULTB_PIN 74 3098 #define RTE_PWM_FAULTB_MUX 8 3099 #define RTE_PWM_FAULTB_PAD 32 3100 #else 3101 #error "Invalid RTE_PWM_FAULTB_PIN Pin Configuration!" 3102 #endif 3103 //PWM_SLP_EVENT_TRIG GPIO_72 3104 #define RTE_PWM_SLP_EVENT_TRIG_PORT 0 3105 #define RTE_PWM_SLP_EVENT_TRIG_PIN 72 3106 #define RTE_PWM_SLP_EVENT_TRIG_MUX 8 3107 #define RTE_PWM_SLP_EVENT_TRIG_PAD 30 3108 3109 //PWM_TMR_EXT_TRIG_1 <0=>GPIO_27 <1=>GPIO_51 <2=>GPIO_70 <3=>GPIO_75 3110 #define RTE_PWM_TMR_EXT_TRIG_1_PORT_ID 0 3111 #ifdef CHIP_917_6x6 3112 #if((RTE_PWM_TMR_EXT_TRIG_1_PORT_ID == 1)||(RTE_PWM_TMR_EXT_TRIG_1_PORT_ID == 3)) 3113 #error "Invalid RTE_PWM_TMR_EXT_TRIG_1_PIN pin Configuration!" 3114 #endif 3115 #endif 3116 #if(RTE_PWM_TMR_EXT_TRIG_1_PORT_ID == 0) 3117 #define RTE_PWM_TMR_EXT_TRIG_1_PORT 0 3118 #define RTE_PWM_TMR_EXT_TRIG_1_PIN 27 3119 #define RTE_PWM_TMR_EXT_TRIG_1_MUX 10 3120 #define RTE_PWM_TMR_EXT_TRIG_1_PAD 0//no pad 3121 #elif(RTE_PWM_TMR_EXT_TRIG_1_PORT_ID == 1) 3122 #define RTE_PWM_TMR_EXT_TRIG_1_PORT 0 3123 #define RTE_PWM_TMR_EXT_TRIG_1_PIN 51 3124 #define RTE_PWM_TMR_EXT_TRIG_1_MUX 8 3125 #define RTE_PWM_TMR_EXT_TRIG_1_PAD 15 3126 #elif(RTE_PWM_TMR_EXT_TRIG_1_PORT_ID == 2) 3127 #define RTE_PWM_TMR_EXT_TRIG_1_PORT 0 3128 #define RTE_PWM_TMR_EXT_TRIG_1_PIN 70 3129 #define RTE_PWM_TMR_EXT_TRIG_1_MUX 10 3130 #define RTE_PWM_TMR_EXT_TRIG_1_PAD 28 3131 #elif(RTE_PWM_TMR_EXT_TRIG_1_PORT_ID == 3) 3132 #define RTE_PWM_TMR_EXT_TRIG_1_PORT 0 3133 #define RTE_PWM_TMR_EXT_TRIG_1_PIN 75 3134 #define RTE_PWM_TMR_EXT_TRIG_1_MUX 8 3135 #define RTE_PWM_TMR_EXT_TRIG_1_PAD 33 3136 #else 3137 #error "Invalid RTE_PWM_TMR_EXT_TRIG_1_PIN Pin Configuration!" 3138 #endif 3139 3140 3141 //PWM_TMR_EXT_TRIG_2 <0=>GPIO_28 <1=>GPIO_54 <2=>GPIO_71 3142 #define RTE_PWM_TMR_EXT_TRIG_2_PORT_ID 0 3143 #ifdef CHIP_917_6x6 3144 #if((RTE_PWM_TMR_EXT_TRIG_2_PORT_ID == 1)) 3145 #error "Invalid RTE_PWM_TMR_EXT_TRIG_2_PIN pin Configuration!" 3146 #endif 3147 #endif 3148 #if(RTE_PWM_TMR_EXT_TRIG_2_PORT_ID == 0) 3149 #define RTE_PWM_TMR_EXT_TRIG_2_PORT 0 3150 #define RTE_PWM_TMR_EXT_TRIG_2_PIN 28 3151 #define RTE_PWM_TMR_EXT_TRIG_2_MUX 10 3152 #define RTE_PWM_TMR_EXT_TRIG_2_PAD 0//no pad 3153 #elif(RTE_PWM_TMR_EXT_TRIG_2_PORT_ID == 1) 3154 #define RTE_PWM_TMR_EXT_TRIG_2_PORT 0 3155 #define RTE_PWM_TMR_EXT_TRIG_2_PIN 54 3156 #define RTE_PWM_TMR_EXT_TRIG_2_MUX 8 3157 #define RTE_PWM_TMR_EXT_TRIG_2_PAD 18 3158 #elif(RTE_PWM_TMR_EXT_TRIG_2_PORT_ID == 2) 3159 #define RTE_PWM_TMR_EXT_TRIG_2_PORT 0 3160 #define RTE_PWM_TMR_EXT_TRIG_2_PIN 71 3161 #define RTE_PWM_TMR_EXT_TRIG_2_MUX 10 3162 #define RTE_PWM_TMR_EXT_TRIG_2_PAD 29 3163 #else 3164 #error "Invalid RTE_PWM_TMR_EXT_TRIG_2_PIN Pin Configuration!" 3165 #endif 3166 3167 3168 //<> QEI (Quadrature Encode Interface) 3169 3170 //QEI_DIR <0=>GPIO_28 <1=>GPIO_49 <2=>GPIO_57 <3=>GPIO_67 <4=>GPIO_71 <5=>GPIO_73 <6=>GPIO_11 <7=>GPIO_34 3171 #ifndef CHIP_917_6x6 3172 #define RTE_QEI_DIR_PORT_ID 4 3173 #if((RTE_QEI_DIR_PORT_ID == 7)||(RTE_QEI_DIR_PORT_ID == 6)) 3174 #error "Invalid RTE_QEI_DIR_PIN pin Configuration!" 3175 #endif 3176 #endif 3177 #ifdef CHIP_917_6x6 3178 #define RTE_QEI_DIR_PORT_ID 6 3179 #if((RTE_QEI_DIR_PORT_ID == 1)||(RTE_QEI_DIR_PORT_ID == 2)|| (RTE_QEI_DIR_PORT_ID == 3)||(RTE_QEI_DIR_PORT_ID == 5)) 3180 #error "Invalid RTE_QEI_DIR_PIN pin Configuration!" 3181 #endif 3182 #endif 3183 #if(RTE_QEI_DIR_PORT_ID == 0) 3184 #define RTE_QEI_DIR_PORT 0 3185 #define RTE_QEI_DIR_PIN 28 3186 #define RTE_QEI_DIR_MUX 5 3187 #define RTE_QEI_DIR_PAD 0//no pad 3188 #elif(RTE_QEI_DIR_PORT_ID == 1) 3189 #define RTE_QEI_DIR_PORT 0 3190 #define RTE_QEI_DIR_PIN 49 3191 #define RTE_QEI_DIR_MUX 3 3192 #define RTE_QEI_DIR_PAD 13 3193 #elif(RTE_QEI_DIR_PORT_ID == 2) 3194 #define RTE_QEI_DIR_PORT 0 3195 #define RTE_QEI_DIR_PIN 57 3196 #define RTE_QEI_DIR_MUX 5 3197 #define RTE_QEI_DIR_PAD 21 3198 #elif(RTE_QEI_DIR_PORT_ID == 3) 3199 #define RTE_QEI_DIR_PORT 0 3200 #define RTE_QEI_DIR_PIN 67 3201 #define RTE_QEI_DIR_MUX 3 3202 #define RTE_QEI_DIR_PAD 25 3203 #elif(RTE_QEI_DIR_PORT_ID == 4) 3204 #define RTE_QEI_DIR_PORT 0 3205 #define RTE_QEI_DIR_PIN 71 3206 #define RTE_QEI_DIR_MUX 3 3207 #define RTE_QEI_DIR_PAD 29 3208 #elif(RTE_QEI_DIR_PORT_ID == 5) 3209 #define RTE_QEI_DIR_PORT 0 3210 #define RTE_QEI_DIR_PIN 73 3211 #define RTE_QEI_DIR_MUX 3 3212 #define RTE_QEI_DIR_PAD 31 3213 #elif(RTE_QEI_DIR_PORT_ID == 6) 3214 #define RTE_QEI_DIR_PORT 0 3215 #define RTE_QEI_DIR_PIN 11 3216 #define RTE_QEI_DIR_MUX 5 3217 #define RTE_QEI_DIR_PAD 6 3218 #elif(RTE_QEI_DIR_PORT_ID == 7) 3219 #define RTE_QEI_DIR_PORT 0 3220 #define RTE_QEI_DIR_PIN 34 3221 #define RTE_QEI_DIR_MUX 13 3222 #define RTE_QEI_DIR_PAD 9 3223 #else 3224 #error "Invalid RTE_QEI_DIR_PIN Pin Configuration!" 3225 #endif 3226 3227 3228 //QEI_IDX <0=>GPIO_25 <1=>GPIO_46 <2=>GPIO_52 <3=>GPIO_64 <4=>GPIO_68 <5=>GPIO_72 <6=>GPIO_8 <7=>GPIO_13 3229 #ifndef CHIP_917_6x6 3230 #define RTE_QEI_IDX_PORT_ID 4 3231 #if((RTE_QEI_IDX_PORT_ID == 7)||(RTE_QEI_IDX_PORT_ID == 6)) 3232 #error "Invalid RTE_QEI_IDX_PIN pin Configuration!" 3233 #endif 3234 #endif 3235 #ifdef CHIP_917_6x6 3236 #define RTE_QEI_IDX_PORT_ID 6 3237 #if((RTE_QEI_IDX_PORT_ID == 1) || (RTE_QEI_IDX_PORT_ID == 2)||(RTE_QEI_IDX_PORT_ID == 3)||(RTE_QEI_IDX_PORT_ID == 5)) 3238 #error "Invalid RTE_QEI_IDX_PIN pin Configuration!" 3239 #endif 3240 #endif 3241 #if(RTE_QEI_IDX_PORT_ID == 0) 3242 #define RTE_QEI_IDX_PORT 0 3243 #define RTE_QEI_IDX_PIN 25 3244 #define RTE_QEI_IDX_MUX 5 3245 #define RTE_QEI_IDX_PAD 0//no pad 3246 #elif(RTE_QEI_IDX_PORT_ID == 1) 3247 #define RTE_QEI_IDX_PORT 0 3248 #define RTE_QEI_IDX_PIN 46 3249 #define RTE_QEI_IDX_MUX 3 3250 #define RTE_QEI_IDX_PAD 10 3251 #elif(RTE_QEI_IDX_PORT_ID == 2) 3252 #define RTE_QEI_IDX_PORT 0 3253 #define RTE_QEI_IDX_PIN 52 3254 #define RTE_QEI_IDX_MUX 5 3255 #define RTE_QEI_IDX_PAD 16 3256 #elif(RTE_QEI_IDX_PORT_ID == 3) 3257 #define RTE_QEI_IDX_PORT 0 3258 #define RTE_QEI_IDX_PIN 64 3259 #define RTE_QEI_IDX_MUX 3 3260 #define RTE_QEI_IDX_PAD 22 3261 #elif(RTE_QEI_IDX_PORT_ID == 4) 3262 #define RTE_QEI_IDX_PORT 0 3263 #define RTE_QEI_IDX_PIN 68 3264 #define RTE_QEI_IDX_MUX 3 3265 #define RTE_QEI_IDX_PAD 26 3266 #elif(RTE_QEI_IDX_PORT_ID == 5) 3267 #define RTE_QEI_IDX_PORT 0 3268 #define RTE_QEI_IDX_PIN 72 3269 #define RTE_QEI_IDX_MUX 3 3270 #define RTE_QEI_IDX_PAD 30 3271 #elif(RTE_QEI_IDX_PORT_ID == 6) 3272 #define RTE_QEI_IDX_PORT 0 3273 #define RTE_QEI_IDX_PIN 8 3274 #define RTE_QEI_IDX_MUX 5 3275 #define RTE_QEI_IDX_PAD 3 3276 #elif(RTE_QEI_IDX_PORT_ID == 7) 3277 #define RTE_QEI_IDX_PORT 0 3278 #define RTE_QEI_IDX_PIN 31 3279 #define RTE_QEI_IDX_MUX 13 3280 #define RTE_QEI_IDX_PAD 9 3281 #else 3282 #error "Invalid RTE_QEI_IDX_PIN Pin Configuration!" 3283 #endif 3284 3285 3286 //QEI_PHA <0=>GPIO_26 <1=>GPIO_47 <2=>GPIO_53 <3=>GPIO_65 <4=>GPIO_69 <5=>GPIO_73 <6=>GPIO_9 <7=>GPIO_32 3287 #ifndef CHIP_917_6x6 3288 #ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER 3289 #define RTE_QEI_PHA_PORT_ID 4 3290 #else 3291 #define RTE_QEI_PHA_PORT_ID 5 3292 #endif 3293 #if((RTE_QEI_PHA_PORT_ID == 7)||(RTE_QEI_PHA_PORT_ID == 6)) 3294 #error "Invalid RTE_QEI_PHA_PIN pin Configuration!" 3295 #endif 3296 #endif 3297 #ifdef CHIP_917_6x6 3298 #define RTE_QEI_PHA_PORT_ID 6 3299 #if((RTE_QEI_PHA_PORT_ID == 1)||(RTE_QEI_PHA_PORT_ID == 2)||(RTE_QEI_PHA_PORT_ID == 3)||(RTE_QEI_PHA_PORT_ID == 5)) 3300 #error "Invalid RTE_QEI_PHA_PIN pin Configuration!" 3301 #endif 3302 #endif 3303 #if(RTE_QEI_PHA_PORT_ID == 0) 3304 #define RTE_QEI_PHA_PORT 0 3305 #define RTE_QEI_PHA_PIN 26 3306 #define RTE_QEI_PHA_MUX 5 3307 #define RTE_QEI_PHA_PAD 0//no pad 3308 #elif(RTE_QEI_PHA_PORT_ID == 1) 3309 #define RTE_QEI_PHA_PORT 0 3310 #define RTE_QEI_PHA_PIN 47 3311 #define RTE_QEI_PHA_MUX 3 3312 #define RTE_QEI_PHA_PAD 11 3313 #elif(RTE_QEI_PHA_PORT_ID == 2) 3314 #define RTE_QEI_PHA_PORT 0 3315 #define RTE_QEI_PHA_PIN 53 3316 #define RTE_QEI_PHA_MUX 5 3317 #define RTE_QEI_PHA_PAD 17 3318 #elif(RTE_QEI_PHA_PORT_ID == 3) 3319 #define RTE_QEI_PHA_PORT 0 3320 #define RTE_QEI_PHA_PIN 65 3321 #define RTE_QEI_PHA_MUX 3 3322 #define RTE_QEI_PHA_PAD 23 3323 #elif(RTE_QEI_PHA_PORT_ID == 4) 3324 #define RTE_QEI_PHA_PORT 0 3325 #define RTE_QEI_PHA_PIN 69 3326 #define RTE_QEI_PHA_MUX 3 3327 #define RTE_QEI_PHA_PAD 27 3328 #elif(RTE_QEI_PHA_PORT_ID == 5) 3329 #define RTE_QEI_PHA_PORT 0 3330 #define RTE_QEI_PHA_PIN 73 3331 #define RTE_QEI_PHA_MUX 3 3332 #define RTE_QEI_PHA_PAD 31 3333 #elif(RTE_QEI_PHA_PORT_ID == 6) 3334 #define RTE_QEI_PHA_PORT 0 3335 #define RTE_QEI_PHA_PIN 9 3336 #define RTE_QEI_PHA_MUX 5 3337 #define RTE_QEI_PHA_PAD 4 3338 #elif(RTE_QEI_PHA_PORT_ID == 7) 3339 #define RTE_QEI_PHA_PORT 0 3340 #define RTE_QEI_PHA_PIN 32 3341 #define RTE_QEI_PHA_MUX 13 3342 #define RTE_QEI_PHA_PAD 9 3343 #else 3344 #error "Invalid RTE_QEI_PHA_PIN Pin Configuration!" 3345 #endif 3346 3347 //QEI_PHB <0=>GPIO_27 <1=>GPIO_48 <1=>GPIO_56 <1=>GPIO_66 <1=>GPIO_70 <1=>GPIO_74 <7=>GPIO_33 3348 #ifndef CHIP_917_6x6 3349 #ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER 3350 #define RTE_QEI_PHB_PORT_ID 5 3351 #else 3352 #define RTE_QEI_PHB_PORT_ID 4 3353 #endif 3354 #if((RTE_QEI_PHB_PORT_ID == 6) || (RTE_QEI_PHB_PORT_ID == 7)) 3355 #error "Invalid RTE_QEI_PHB_PIN Configuration!" 3356 #endif 3357 #endif 3358 #ifdef CHIP_917_6x6 3359 #define RTE_QEI_PHB_PORT_ID 6 3360 #if((RTE_QEI_PHB_PORT_ID == 1) || (RTE_QEI_PHB_PORT_ID == 2)||(RTE_QEI_PHB_PORT_ID == 3)||(RTE_QEI_PHB_PORT_ID == 5) ) 3361 #error "Invalid RTE_QEI_PHB_PIN Configuration!" 3362 #endif 3363 #endif 3364 #if(RTE_QEI_PHB_PORT_ID == 0) 3365 #define RTE_QEI_PHB_PORT 0 3366 #define RTE_QEI_PHB_PIN 27 3367 #define RTE_QEI_PHB_MUX 5 3368 #define RTE_QEI_PHB_PAD 0//no pad 3369 #elif(RTE_QEI_PHB_PORT_ID == 1) 3370 #define RTE_QEI_PHB_PORT 0 3371 #define RTE_QEI_PHB_PIN 48 3372 #define RTE_QEI_PHB_MUX 3 3373 #define RTE_QEI_PHB_PAD 12 3374 #elif(RTE_QEI_PHB_PORT_ID == 2) 3375 #define RTE_QEI_PHB_PORT 0 3376 #define RTE_QEI_PHB_PIN 56 3377 #define RTE_QEI_PHB_MUX 5 3378 #define RTE_QEI_PHB_PAD 20 3379 #elif(RTE_QEI_PHB_PORT_ID == 3) 3380 #define RTE_QEI_PHB_PORT 0 3381 #define RTE_QEI_PHB_PIN 66 3382 #define RTE_QEI_PHB_MUX 3 3383 #define RTE_QEI_PHB_PAD 24 3384 #elif(RTE_QEI_PHB_PORT_ID == 4) 3385 #define RTE_QEI_PHB_PORT 0 3386 #define RTE_QEI_PHB_PIN 70 3387 #define RTE_QEI_PHB_MUX 3 3388 #define RTE_QEI_PHB_PAD 28 3389 #elif(RTE_QEI_PHB_PORT_ID == 5) 3390 #define RTE_QEI_PHB_PORT 0 3391 #define RTE_QEI_PHB_PIN 74 3392 #define RTE_QEI_PHB_MUX 3 3393 #define RTE_QEI_PHB_PAD 32 3394 #elif(RTE_QEI_PHB_PORT_ID == 6) 3395 #define RTE_QEI_PHB_PORT 0 3396 #define RTE_QEI_PHB_PIN 10 3397 #define RTE_QEI_PHB_MUX 5 3398 #define RTE_QEI_PHB_PAD 5 3399 #elif(RTE_QEI_PHB_PORT_ID == 7) 3400 #define RTE_QEI_PHB_PORT 0 3401 #define RTE_QEI_PHB_PIN 33 3402 #define RTE_QEI_PHB_MUX 13 3403 #define RTE_QEI_PHB_PAD 9 3404 #else 3405 #error "Invalid RTE_QEI_PHB_PIN Pin Configuration!" 3406 #endif 3407 3408 3409 #endif 3410
