1 /*----------------------------------------------------------------------------- 2 * Name: CV_Config.h 3 * Purpose: CV Config header 4 *---------------------------------------------------------------------------- 5 * Copyright (c) 2017 - 2018 Arm Limited. All rights reserved. 6 *----------------------------------------------------------------------------*/ 7 #ifndef __CV_CONFIG_H 8 #define __CV_CONFIG_H 9 10 #include "RTE_Components.h" 11 #include CMSIS_device_header 12 13 #define RTE_CV_COREINSTR 1 14 #define RTE_CV_COREFUNC 1 15 #define RTE_CV_CORESIMD 1 16 #define RTE_CV_MPUFUNC (__MPU_PRESENT) 17 #if defined __ICACHE_PRESENT || defined __DCACHE_PRESENT 18 #define RTE_CV_L1CACHE (__ICACHE_PRESENT || __DCACHE_PRESENT) 19 #endif 20 21 //-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- 22 23 // <h> Common Test Settings 24 // <o> Print Output Format <0=> Plain Text <1=> XML 25 // <i> Set the test results output format to plain text or XML 26 #ifndef PRINT_XML_REPORT 27 #define PRINT_XML_REPORT 1 28 #endif 29 // <o> Buffer size for assertions results 30 // <i> Set the buffer size for assertions results buffer 31 #define BUFFER_ASSERTIONS 128U 32 // </h> 33 34 // <h> Disable Test Cases 35 // <i> Uncheck to disable an individual test case 36 // <q0> TC_CoreInstr_NOP 37 #define TC_COREINSTR_NOP_EN 1 38 // <q0> TC_CoreInstr_SEV 39 #define TC_COREINSTR_SEV_EN 1 40 // <q0> TC_CoreInstr_BKPT 41 #define TC_COREINSTR_BKPT_EN 1 42 // <q0> TC_CoreInstr_ISB 43 #define TC_COREINSTR_ISB_EN 1 44 // <q0> TC_CoreInstr_DSB 45 #define TC_COREINSTR_DSB_EN 1 46 // <q0> TC_CoreInstr_DMB 47 #define TC_COREINSTR_DMB_EN 1 48 // <q0> TC_CoreInstr_WFI 49 #define TC_COREINSTR_WFI_EN 0 50 // <q0> TC_CoreInstr_WFE 51 #define TC_COREINSTR_WFE_EN 0 52 53 // <q0> TC_CoreInstr_REV 54 #define TC_COREINSTR_REV_EN 1 55 // <q0> TC_CoreInstr_REV16 56 #define TC_COREINSTR_REV16_EN 1 57 // <q0> TC_CoreInstr_REVSH 58 #define TC_COREINSTR_REVSH_EN 1 59 // <q0> TC_CoreInstr_ROR 60 #define TC_COREINSTR_ROR_EN 1 61 // <q0> TC_CoreInstr_RBIT 62 #define TC_COREINSTR_RBIT_EN 1 63 // <q0> TC_CoreInstr_CLZ 64 #define TC_COREINSTR_CLZ_EN 1 65 // <q0> TC_CoreInstr_SSAT 66 #define TC_COREINSTR_SSAT_EN 1 67 // <q0> TC_CoreInstr_USAT 68 #define TC_COREINSTR_USAT_EN 1 69 // <q0> TC_CoreInstr_RRX 70 #define TC_COREINSTR_RRX_EN 1 71 // <q0> TC_CoreInstr_LoadStoreExlusive 72 #define TC_COREINSTR_LOADSTOREEXCLUSIVE_EN 1 73 // <q0> TC_CoreInstr_LoadStoreUnpriv 74 #define TC_COREINSTR_LOADSTOREUNPRIV_EN 1 75 // <q0> TC_CoreInstr_LoadStoreAcquire 76 #define TC_COREINSTR_LOADSTOREACQUIRE_EN 1 77 // <q0> TC_CoreInstr_LoadStoreAcquireExclusive 78 #define TC_COREINSTR_LOADSTOREACQUIREEXCLUSIVE_EN 1 79 // <q0> TC_CoreInstr_UnalignedUint16 80 #define TC_COREINSTR_UNALIGNEDUINT16_EN 1 81 // <q0> TC_CoreInstr_UnalignedUint32 82 #define TC_COREINSTR_UNALIGNEDUINT32_EN 1 83 84 // <q0> TC_CoreSimd_SatAddSub 85 #define TC_CORESIMD_SATADDSUB_EN 1 86 // <q0> TC_CoreSimd_ParSat16 87 #define TC_CORESIMD_PARSAT16_EN 1 88 // <q0> TC_CoreSimd_PackUnpack 89 #define TC_CORESIMD_PACKUNPACK_EN 1 90 // <q0> TC_CoreSimd_ParSel 91 #define TC_CORESIMD_PARSEL_EN 1 92 // <q0> TC_CoreSimd_ParAddSub8 93 #define TC_CORESIMD_PARADDSUB8_EN 1 94 // <q0> TC_CoreSimd_AbsDif8 95 #define TC_CORESIMD_ABSDIF8_EN 1 96 // <q0> TC_CoreSimd_ParAddSub16 97 #define TC_CORESIMD_PARADDSUB16_EN 1 98 // <q0> TC_CoreSimd_ParMul16 99 #define TC_CORESIMD_PARMUL16_EN 1 100 // <q0> TC_CoreSimd_Pack16 101 #define TC_CORESIMD_PACK16_EN 1 102 // <q0> TC_CoreSimd_MulAcc32 103 #define TC_CORESIMD_MULACC32_EN 1 104 105 // <q0> TC_CoreFunc_EnDisIRQ 106 #define TC_COREFUNC_ENDISIRQ_EN 1 107 // <q0> TC_CoreFunc_IRQPrio 108 #define TC_COREFUNC_IRQPRIO_EN 1 109 // <q0> TC_CoreFunc_EncDecIRQPrio 110 #define TC_COREFUNC_ENCDECIRQPRIO_EN 1 111 // <q0> TC_CoreFunc_IRQVect 112 #define TC_COREFUNC_IRQVECT_EN 1 113 // <q0> TC_CoreFunc_Control 114 #define TC_COREFUNC_CONTROL_EN 1 115 // <q0> TC_CoreFunc_IPSR 116 #define TC_COREFUNC_IPSR_EN 1 117 // <q0> TC_CoreFunc_APSR 118 #define TC_COREFUNC_APSR_EN 1 119 // <q0> TC_CoreFunc_PSP 120 #define TC_COREFUNC_PSP_EN 1 121 // <q0> TC_CoreFunc_MSP 122 #define TC_COREFUNC_MSP_EN 1 123 124 // <q0> TC_CoreFunc_PSPLIM 125 #define TC_COREFUNC_PSPLIM_EN 1 126 // <q0> TC_CoreFunc_PSPLIM_NS 127 #define TC_COREFUNC_PSPLIM_NS_EN 1 128 // <q0> TC_CoreFunc_MSPLIM 129 #define TC_COREFUNC_MSPLIM_EN 1 130 // <q0> TC_CoreFunc_MSPLIM_NS 131 #define TC_COREFUNC_MSPLIM_NS_EN 1 132 // <q0> TC_CoreFunc_PRIMASK 133 #define TC_COREFUNC_PRIMASK_EN 1 134 // <q0> TC_CoreFunc_FAULTMASK 135 #define TC_COREFUNC_FAULTMASK_EN 1 136 // <q0> TC_CoreFunc_BASEPRI 137 #define TC_COREFUNC_BASEPRI_EN 1 138 // <q0> TC_CoreFunc_FPUType 139 #define TC_COREFUNC_FPUTYPE_EN 1 140 // <q0> TC_CoreFunc_FPSCR 141 #define TC_COREFUNC_FPSCR_EN 1 142 143 // <q0> TC_MPU_SetClear 144 #define TC_MPU_SETCLEAR_EN 1 145 // <q0> TC_MPU_Load 146 #define TC_MPU_LOAD_EN 1 147 148 // <q0> TC_CML1Cache_EnDisableICache 149 #define TC_CML1CACHE_ENDISABLE_ICACHE 1 150 // <q0> TC_CML1Cache_EnDisableDCache 151 #define TC_CML1CACHE_ENDISABLE_DCACHE 1 152 // <q0> TC_CML1Cache_CleanDCacheByAddrWhileDisabled 153 #define TC_CML1CACHE_CLEANDCACHEBYADDRWHILEDISABLED 1 154 155 // </h> 156 157 #endif /* __CV_CONFIG_H */ 158 159
