1 /** 2 * \file 3 * 4 * \brief Component description for RTC 5 * 6 * Copyright (c) 2016 Atmel Corporation, 7 * a wholly owned subsidiary of Microchip Technology Inc. 8 * 9 * \asf_license_start 10 * 11 * \page License 12 * 13 * Licensed under the Apache License, Version 2.0 (the "License"); 14 * you may not use this file except in compliance with the License. 15 * You may obtain a copy of the Licence at 16 * 17 * http://www.apache.org/licenses/LICENSE-2.0 18 * 19 * Unless required by applicable law or agreed to in writing, software 20 * distributed under the License is distributed on an "AS IS" BASIS, 21 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 22 * See the License for the specific language governing permissions and 23 * limitations under the License. 24 * 25 * \asf_license_stop 26 * 27 */ 28 29 #ifndef _SAML21_RTC_COMPONENT_ 30 #define _SAML21_RTC_COMPONENT_ 31 32 /* ========================================================================== */ 33 /** SOFTWARE API DEFINITION FOR RTC */ 34 /* ========================================================================== */ 35 /** \addtogroup SAML21_RTC Real-Time Counter */ 36 /*@{*/ 37 38 #define RTC_U2250 39 #define REV_RTC 0x110 40 41 /* -------- RTC_MODE0_CTRLA : (RTC Offset: 0x00) (R/W 16) MODE0 MODE0 Control A -------- */ 42 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 43 typedef union { 44 struct { 45 uint16_t SWRST:1; /*!< bit: 0 Software Reset */ 46 uint16_t ENABLE:1; /*!< bit: 1 Enable */ 47 uint16_t MODE:2; /*!< bit: 2.. 3 Operating Mode */ 48 uint16_t :3; /*!< bit: 4.. 6 Reserved */ 49 uint16_t MATCHCLR:1; /*!< bit: 7 Clear on Match */ 50 uint16_t PRESCALER:4; /*!< bit: 8..11 Prescaler */ 51 uint16_t :3; /*!< bit: 12..14 Reserved */ 52 uint16_t COUNTSYNC:1; /*!< bit: 15 Count Read Synchronization Enable */ 53 } bit; /*!< Structure used for bit access */ 54 uint16_t reg; /*!< Type used for register access */ 55 } RTC_MODE0_CTRLA_Type; 56 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 57 58 #define RTC_MODE0_CTRLA_OFFSET 0x00 /**< \brief (RTC_MODE0_CTRLA offset) MODE0 Control A */ 59 #define RTC_MODE0_CTRLA_RESETVALUE _U(0x0000) /**< \brief (RTC_MODE0_CTRLA reset_value) MODE0 Control A */ 60 61 #define RTC_MODE0_CTRLA_SWRST_Pos 0 /**< \brief (RTC_MODE0_CTRLA) Software Reset */ 62 #define RTC_MODE0_CTRLA_SWRST (_U(0x1) << RTC_MODE0_CTRLA_SWRST_Pos) 63 #define RTC_MODE0_CTRLA_ENABLE_Pos 1 /**< \brief (RTC_MODE0_CTRLA) Enable */ 64 #define RTC_MODE0_CTRLA_ENABLE (_U(0x1) << RTC_MODE0_CTRLA_ENABLE_Pos) 65 #define RTC_MODE0_CTRLA_MODE_Pos 2 /**< \brief (RTC_MODE0_CTRLA) Operating Mode */ 66 #define RTC_MODE0_CTRLA_MODE_Msk (_U(0x3) << RTC_MODE0_CTRLA_MODE_Pos) 67 #define RTC_MODE0_CTRLA_MODE(value) (RTC_MODE0_CTRLA_MODE_Msk & ((value) << RTC_MODE0_CTRLA_MODE_Pos)) 68 #define RTC_MODE0_CTRLA_MODE_COUNT32_Val _U(0x0) /**< \brief (RTC_MODE0_CTRLA) Mode 0: 32-bit Counter */ 69 #define RTC_MODE0_CTRLA_MODE_COUNT16_Val _U(0x1) /**< \brief (RTC_MODE0_CTRLA) Mode 1: 16-bit Counter */ 70 #define RTC_MODE0_CTRLA_MODE_CLOCK_Val _U(0x2) /**< \brief (RTC_MODE0_CTRLA) Mode 2: Clock/Calendar */ 71 #define RTC_MODE0_CTRLA_MODE_COUNT32 (RTC_MODE0_CTRLA_MODE_COUNT32_Val << RTC_MODE0_CTRLA_MODE_Pos) 72 #define RTC_MODE0_CTRLA_MODE_COUNT16 (RTC_MODE0_CTRLA_MODE_COUNT16_Val << RTC_MODE0_CTRLA_MODE_Pos) 73 #define RTC_MODE0_CTRLA_MODE_CLOCK (RTC_MODE0_CTRLA_MODE_CLOCK_Val << RTC_MODE0_CTRLA_MODE_Pos) 74 #define RTC_MODE0_CTRLA_MATCHCLR_Pos 7 /**< \brief (RTC_MODE0_CTRLA) Clear on Match */ 75 #define RTC_MODE0_CTRLA_MATCHCLR (_U(0x1) << RTC_MODE0_CTRLA_MATCHCLR_Pos) 76 #define RTC_MODE0_CTRLA_PRESCALER_Pos 8 /**< \brief (RTC_MODE0_CTRLA) Prescaler */ 77 #define RTC_MODE0_CTRLA_PRESCALER_Msk (_U(0xF) << RTC_MODE0_CTRLA_PRESCALER_Pos) 78 #define RTC_MODE0_CTRLA_PRESCALER(value) (RTC_MODE0_CTRLA_PRESCALER_Msk & ((value) << RTC_MODE0_CTRLA_PRESCALER_Pos)) 79 #define RTC_MODE0_CTRLA_PRESCALER_OFF_Val _U(0x0) /**< \brief (RTC_MODE0_CTRLA) CLK_RTC_CNT = GCLK_RTC/1 */ 80 #define RTC_MODE0_CTRLA_PRESCALER_DIV1_Val _U(0x1) /**< \brief (RTC_MODE0_CTRLA) CLK_RTC_CNT = GCLK_RTC/1 */ 81 #define RTC_MODE0_CTRLA_PRESCALER_DIV2_Val _U(0x2) /**< \brief (RTC_MODE0_CTRLA) CLK_RTC_CNT = GCLK_RTC/2 */ 82 #define RTC_MODE0_CTRLA_PRESCALER_DIV4_Val _U(0x3) /**< \brief (RTC_MODE0_CTRLA) CLK_RTC_CNT = GCLK_RTC/4 */ 83 #define RTC_MODE0_CTRLA_PRESCALER_DIV8_Val _U(0x4) /**< \brief (RTC_MODE0_CTRLA) CLK_RTC_CNT = GCLK_RTC/8 */ 84 #define RTC_MODE0_CTRLA_PRESCALER_DIV16_Val _U(0x5) /**< \brief (RTC_MODE0_CTRLA) CLK_RTC_CNT = GCLK_RTC/16 */ 85 #define RTC_MODE0_CTRLA_PRESCALER_DIV32_Val _U(0x6) /**< \brief (RTC_MODE0_CTRLA) CLK_RTC_CNT = GCLK_RTC/32 */ 86 #define RTC_MODE0_CTRLA_PRESCALER_DIV64_Val _U(0x7) /**< \brief (RTC_MODE0_CTRLA) CLK_RTC_CNT = GCLK_RTC/64 */ 87 #define RTC_MODE0_CTRLA_PRESCALER_DIV128_Val _U(0x8) /**< \brief (RTC_MODE0_CTRLA) CLK_RTC_CNT = GCLK_RTC/128 */ 88 #define RTC_MODE0_CTRLA_PRESCALER_DIV256_Val _U(0x9) /**< \brief (RTC_MODE0_CTRLA) CLK_RTC_CNT = GCLK_RTC/256 */ 89 #define RTC_MODE0_CTRLA_PRESCALER_DIV512_Val _U(0xA) /**< \brief (RTC_MODE0_CTRLA) CLK_RTC_CNT = GCLK_RTC/512 */ 90 #define RTC_MODE0_CTRLA_PRESCALER_DIV1024_Val _U(0xB) /**< \brief (RTC_MODE0_CTRLA) CLK_RTC_CNT = GCLK_RTC/1024 */ 91 #define RTC_MODE0_CTRLA_PRESCALER_OFF (RTC_MODE0_CTRLA_PRESCALER_OFF_Val << RTC_MODE0_CTRLA_PRESCALER_Pos) 92 #define RTC_MODE0_CTRLA_PRESCALER_DIV1 (RTC_MODE0_CTRLA_PRESCALER_DIV1_Val << RTC_MODE0_CTRLA_PRESCALER_Pos) 93 #define RTC_MODE0_CTRLA_PRESCALER_DIV2 (RTC_MODE0_CTRLA_PRESCALER_DIV2_Val << RTC_MODE0_CTRLA_PRESCALER_Pos) 94 #define RTC_MODE0_CTRLA_PRESCALER_DIV4 (RTC_MODE0_CTRLA_PRESCALER_DIV4_Val << RTC_MODE0_CTRLA_PRESCALER_Pos) 95 #define RTC_MODE0_CTRLA_PRESCALER_DIV8 (RTC_MODE0_CTRLA_PRESCALER_DIV8_Val << RTC_MODE0_CTRLA_PRESCALER_Pos) 96 #define RTC_MODE0_CTRLA_PRESCALER_DIV16 (RTC_MODE0_CTRLA_PRESCALER_DIV16_Val << RTC_MODE0_CTRLA_PRESCALER_Pos) 97 #define RTC_MODE0_CTRLA_PRESCALER_DIV32 (RTC_MODE0_CTRLA_PRESCALER_DIV32_Val << RTC_MODE0_CTRLA_PRESCALER_Pos) 98 #define RTC_MODE0_CTRLA_PRESCALER_DIV64 (RTC_MODE0_CTRLA_PRESCALER_DIV64_Val << RTC_MODE0_CTRLA_PRESCALER_Pos) 99 #define RTC_MODE0_CTRLA_PRESCALER_DIV128 (RTC_MODE0_CTRLA_PRESCALER_DIV128_Val << RTC_MODE0_CTRLA_PRESCALER_Pos) 100 #define RTC_MODE0_CTRLA_PRESCALER_DIV256 (RTC_MODE0_CTRLA_PRESCALER_DIV256_Val << RTC_MODE0_CTRLA_PRESCALER_Pos) 101 #define RTC_MODE0_CTRLA_PRESCALER_DIV512 (RTC_MODE0_CTRLA_PRESCALER_DIV512_Val << RTC_MODE0_CTRLA_PRESCALER_Pos) 102 #define RTC_MODE0_CTRLA_PRESCALER_DIV1024 (RTC_MODE0_CTRLA_PRESCALER_DIV1024_Val << RTC_MODE0_CTRLA_PRESCALER_Pos) 103 #define RTC_MODE0_CTRLA_COUNTSYNC_Pos 15 /**< \brief (RTC_MODE0_CTRLA) Count Read Synchronization Enable */ 104 #define RTC_MODE0_CTRLA_COUNTSYNC (_U(0x1) << RTC_MODE0_CTRLA_COUNTSYNC_Pos) 105 #define RTC_MODE0_CTRLA_MASK _U(0x8F8F) /**< \brief (RTC_MODE0_CTRLA) MASK Register */ 106 107 /* -------- RTC_MODE1_CTRLA : (RTC Offset: 0x00) (R/W 16) MODE1 MODE1 Control A -------- */ 108 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 109 typedef union { 110 struct { 111 uint16_t SWRST:1; /*!< bit: 0 Software Reset */ 112 uint16_t ENABLE:1; /*!< bit: 1 Enable */ 113 uint16_t MODE:2; /*!< bit: 2.. 3 Operating Mode */ 114 uint16_t :4; /*!< bit: 4.. 7 Reserved */ 115 uint16_t PRESCALER:4; /*!< bit: 8..11 Prescaler */ 116 uint16_t :3; /*!< bit: 12..14 Reserved */ 117 uint16_t COUNTSYNC:1; /*!< bit: 15 Count Read Synchronization Enable */ 118 } bit; /*!< Structure used for bit access */ 119 uint16_t reg; /*!< Type used for register access */ 120 } RTC_MODE1_CTRLA_Type; 121 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 122 123 #define RTC_MODE1_CTRLA_OFFSET 0x00 /**< \brief (RTC_MODE1_CTRLA offset) MODE1 Control A */ 124 #define RTC_MODE1_CTRLA_RESETVALUE _U(0x0000) /**< \brief (RTC_MODE1_CTRLA reset_value) MODE1 Control A */ 125 126 #define RTC_MODE1_CTRLA_SWRST_Pos 0 /**< \brief (RTC_MODE1_CTRLA) Software Reset */ 127 #define RTC_MODE1_CTRLA_SWRST (_U(0x1) << RTC_MODE1_CTRLA_SWRST_Pos) 128 #define RTC_MODE1_CTRLA_ENABLE_Pos 1 /**< \brief (RTC_MODE1_CTRLA) Enable */ 129 #define RTC_MODE1_CTRLA_ENABLE (_U(0x1) << RTC_MODE1_CTRLA_ENABLE_Pos) 130 #define RTC_MODE1_CTRLA_MODE_Pos 2 /**< \brief (RTC_MODE1_CTRLA) Operating Mode */ 131 #define RTC_MODE1_CTRLA_MODE_Msk (_U(0x3) << RTC_MODE1_CTRLA_MODE_Pos) 132 #define RTC_MODE1_CTRLA_MODE(value) (RTC_MODE1_CTRLA_MODE_Msk & ((value) << RTC_MODE1_CTRLA_MODE_Pos)) 133 #define RTC_MODE1_CTRLA_MODE_COUNT32_Val _U(0x0) /**< \brief (RTC_MODE1_CTRLA) Mode 0: 32-bit Counter */ 134 #define RTC_MODE1_CTRLA_MODE_COUNT16_Val _U(0x1) /**< \brief (RTC_MODE1_CTRLA) Mode 1: 16-bit Counter */ 135 #define RTC_MODE1_CTRLA_MODE_CLOCK_Val _U(0x2) /**< \brief (RTC_MODE1_CTRLA) Mode 2: Clock/Calendar */ 136 #define RTC_MODE1_CTRLA_MODE_COUNT32 (RTC_MODE1_CTRLA_MODE_COUNT32_Val << RTC_MODE1_CTRLA_MODE_Pos) 137 #define RTC_MODE1_CTRLA_MODE_COUNT16 (RTC_MODE1_CTRLA_MODE_COUNT16_Val << RTC_MODE1_CTRLA_MODE_Pos) 138 #define RTC_MODE1_CTRLA_MODE_CLOCK (RTC_MODE1_CTRLA_MODE_CLOCK_Val << RTC_MODE1_CTRLA_MODE_Pos) 139 #define RTC_MODE1_CTRLA_PRESCALER_Pos 8 /**< \brief (RTC_MODE1_CTRLA) Prescaler */ 140 #define RTC_MODE1_CTRLA_PRESCALER_Msk (_U(0xF) << RTC_MODE1_CTRLA_PRESCALER_Pos) 141 #define RTC_MODE1_CTRLA_PRESCALER(value) (RTC_MODE1_CTRLA_PRESCALER_Msk & ((value) << RTC_MODE1_CTRLA_PRESCALER_Pos)) 142 #define RTC_MODE1_CTRLA_PRESCALER_OFF_Val _U(0x0) /**< \brief (RTC_MODE1_CTRLA) CLK_RTC_CNT = GCLK_RTC/1 */ 143 #define RTC_MODE1_CTRLA_PRESCALER_DIV1_Val _U(0x1) /**< \brief (RTC_MODE1_CTRLA) CLK_RTC_CNT = GCLK_RTC/1 */ 144 #define RTC_MODE1_CTRLA_PRESCALER_DIV2_Val _U(0x2) /**< \brief (RTC_MODE1_CTRLA) CLK_RTC_CNT = GCLK_RTC/2 */ 145 #define RTC_MODE1_CTRLA_PRESCALER_DIV4_Val _U(0x3) /**< \brief (RTC_MODE1_CTRLA) CLK_RTC_CNT = GCLK_RTC/4 */ 146 #define RTC_MODE1_CTRLA_PRESCALER_DIV8_Val _U(0x4) /**< \brief (RTC_MODE1_CTRLA) CLK_RTC_CNT = GCLK_RTC/8 */ 147 #define RTC_MODE1_CTRLA_PRESCALER_DIV16_Val _U(0x5) /**< \brief (RTC_MODE1_CTRLA) CLK_RTC_CNT = GCLK_RTC/16 */ 148 #define RTC_MODE1_CTRLA_PRESCALER_DIV32_Val _U(0x6) /**< \brief (RTC_MODE1_CTRLA) CLK_RTC_CNT = GCLK_RTC/32 */ 149 #define RTC_MODE1_CTRLA_PRESCALER_DIV64_Val _U(0x7) /**< \brief (RTC_MODE1_CTRLA) CLK_RTC_CNT = GCLK_RTC/64 */ 150 #define RTC_MODE1_CTRLA_PRESCALER_DIV128_Val _U(0x8) /**< \brief (RTC_MODE1_CTRLA) CLK_RTC_CNT = GCLK_RTC/128 */ 151 #define RTC_MODE1_CTRLA_PRESCALER_DIV256_Val _U(0x9) /**< \brief (RTC_MODE1_CTRLA) CLK_RTC_CNT = GCLK_RTC/256 */ 152 #define RTC_MODE1_CTRLA_PRESCALER_DIV512_Val _U(0xA) /**< \brief (RTC_MODE1_CTRLA) CLK_RTC_CNT = GCLK_RTC/512 */ 153 #define RTC_MODE1_CTRLA_PRESCALER_DIV1024_Val _U(0xB) /**< \brief (RTC_MODE1_CTRLA) CLK_RTC_CNT = GCLK_RTC/1024 */ 154 #define RTC_MODE1_CTRLA_PRESCALER_OFF (RTC_MODE1_CTRLA_PRESCALER_OFF_Val << RTC_MODE1_CTRLA_PRESCALER_Pos) 155 #define RTC_MODE1_CTRLA_PRESCALER_DIV1 (RTC_MODE1_CTRLA_PRESCALER_DIV1_Val << RTC_MODE1_CTRLA_PRESCALER_Pos) 156 #define RTC_MODE1_CTRLA_PRESCALER_DIV2 (RTC_MODE1_CTRLA_PRESCALER_DIV2_Val << RTC_MODE1_CTRLA_PRESCALER_Pos) 157 #define RTC_MODE1_CTRLA_PRESCALER_DIV4 (RTC_MODE1_CTRLA_PRESCALER_DIV4_Val << RTC_MODE1_CTRLA_PRESCALER_Pos) 158 #define RTC_MODE1_CTRLA_PRESCALER_DIV8 (RTC_MODE1_CTRLA_PRESCALER_DIV8_Val << RTC_MODE1_CTRLA_PRESCALER_Pos) 159 #define RTC_MODE1_CTRLA_PRESCALER_DIV16 (RTC_MODE1_CTRLA_PRESCALER_DIV16_Val << RTC_MODE1_CTRLA_PRESCALER_Pos) 160 #define RTC_MODE1_CTRLA_PRESCALER_DIV32 (RTC_MODE1_CTRLA_PRESCALER_DIV32_Val << RTC_MODE1_CTRLA_PRESCALER_Pos) 161 #define RTC_MODE1_CTRLA_PRESCALER_DIV64 (RTC_MODE1_CTRLA_PRESCALER_DIV64_Val << RTC_MODE1_CTRLA_PRESCALER_Pos) 162 #define RTC_MODE1_CTRLA_PRESCALER_DIV128 (RTC_MODE1_CTRLA_PRESCALER_DIV128_Val << RTC_MODE1_CTRLA_PRESCALER_Pos) 163 #define RTC_MODE1_CTRLA_PRESCALER_DIV256 (RTC_MODE1_CTRLA_PRESCALER_DIV256_Val << RTC_MODE1_CTRLA_PRESCALER_Pos) 164 #define RTC_MODE1_CTRLA_PRESCALER_DIV512 (RTC_MODE1_CTRLA_PRESCALER_DIV512_Val << RTC_MODE1_CTRLA_PRESCALER_Pos) 165 #define RTC_MODE1_CTRLA_PRESCALER_DIV1024 (RTC_MODE1_CTRLA_PRESCALER_DIV1024_Val << RTC_MODE1_CTRLA_PRESCALER_Pos) 166 #define RTC_MODE1_CTRLA_COUNTSYNC_Pos 15 /**< \brief (RTC_MODE1_CTRLA) Count Read Synchronization Enable */ 167 #define RTC_MODE1_CTRLA_COUNTSYNC (_U(0x1) << RTC_MODE1_CTRLA_COUNTSYNC_Pos) 168 #define RTC_MODE1_CTRLA_MASK _U(0x8F0F) /**< \brief (RTC_MODE1_CTRLA) MASK Register */ 169 170 /* -------- RTC_MODE2_CTRLA : (RTC Offset: 0x00) (R/W 16) MODE2 MODE2 Control A -------- */ 171 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 172 typedef union { 173 struct { 174 uint16_t SWRST:1; /*!< bit: 0 Software Reset */ 175 uint16_t ENABLE:1; /*!< bit: 1 Enable */ 176 uint16_t MODE:2; /*!< bit: 2.. 3 Operating Mode */ 177 uint16_t :2; /*!< bit: 4.. 5 Reserved */ 178 uint16_t CLKREP:1; /*!< bit: 6 Clock Representation */ 179 uint16_t MATCHCLR:1; /*!< bit: 7 Clear on Match */ 180 uint16_t PRESCALER:4; /*!< bit: 8..11 Prescaler */ 181 uint16_t :3; /*!< bit: 12..14 Reserved */ 182 uint16_t CLOCKSYNC:1; /*!< bit: 15 Clock Read Synchronization Enable */ 183 } bit; /*!< Structure used for bit access */ 184 uint16_t reg; /*!< Type used for register access */ 185 } RTC_MODE2_CTRLA_Type; 186 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 187 188 #define RTC_MODE2_CTRLA_OFFSET 0x00 /**< \brief (RTC_MODE2_CTRLA offset) MODE2 Control A */ 189 #define RTC_MODE2_CTRLA_RESETVALUE _U(0x0000) /**< \brief (RTC_MODE2_CTRLA reset_value) MODE2 Control A */ 190 191 #define RTC_MODE2_CTRLA_SWRST_Pos 0 /**< \brief (RTC_MODE2_CTRLA) Software Reset */ 192 #define RTC_MODE2_CTRLA_SWRST (_U(0x1) << RTC_MODE2_CTRLA_SWRST_Pos) 193 #define RTC_MODE2_CTRLA_ENABLE_Pos 1 /**< \brief (RTC_MODE2_CTRLA) Enable */ 194 #define RTC_MODE2_CTRLA_ENABLE (_U(0x1) << RTC_MODE2_CTRLA_ENABLE_Pos) 195 #define RTC_MODE2_CTRLA_MODE_Pos 2 /**< \brief (RTC_MODE2_CTRLA) Operating Mode */ 196 #define RTC_MODE2_CTRLA_MODE_Msk (_U(0x3) << RTC_MODE2_CTRLA_MODE_Pos) 197 #define RTC_MODE2_CTRLA_MODE(value) (RTC_MODE2_CTRLA_MODE_Msk & ((value) << RTC_MODE2_CTRLA_MODE_Pos)) 198 #define RTC_MODE2_CTRLA_MODE_COUNT32_Val _U(0x0) /**< \brief (RTC_MODE2_CTRLA) Mode 0: 32-bit Counter */ 199 #define RTC_MODE2_CTRLA_MODE_COUNT16_Val _U(0x1) /**< \brief (RTC_MODE2_CTRLA) Mode 1: 16-bit Counter */ 200 #define RTC_MODE2_CTRLA_MODE_CLOCK_Val _U(0x2) /**< \brief (RTC_MODE2_CTRLA) Mode 2: Clock/Calendar */ 201 #define RTC_MODE2_CTRLA_MODE_COUNT32 (RTC_MODE2_CTRLA_MODE_COUNT32_Val << RTC_MODE2_CTRLA_MODE_Pos) 202 #define RTC_MODE2_CTRLA_MODE_COUNT16 (RTC_MODE2_CTRLA_MODE_COUNT16_Val << RTC_MODE2_CTRLA_MODE_Pos) 203 #define RTC_MODE2_CTRLA_MODE_CLOCK (RTC_MODE2_CTRLA_MODE_CLOCK_Val << RTC_MODE2_CTRLA_MODE_Pos) 204 #define RTC_MODE2_CTRLA_CLKREP_Pos 6 /**< \brief (RTC_MODE2_CTRLA) Clock Representation */ 205 #define RTC_MODE2_CTRLA_CLKREP (_U(0x1) << RTC_MODE2_CTRLA_CLKREP_Pos) 206 #define RTC_MODE2_CTRLA_MATCHCLR_Pos 7 /**< \brief (RTC_MODE2_CTRLA) Clear on Match */ 207 #define RTC_MODE2_CTRLA_MATCHCLR (_U(0x1) << RTC_MODE2_CTRLA_MATCHCLR_Pos) 208 #define RTC_MODE2_CTRLA_PRESCALER_Pos 8 /**< \brief (RTC_MODE2_CTRLA) Prescaler */ 209 #define RTC_MODE2_CTRLA_PRESCALER_Msk (_U(0xF) << RTC_MODE2_CTRLA_PRESCALER_Pos) 210 #define RTC_MODE2_CTRLA_PRESCALER(value) (RTC_MODE2_CTRLA_PRESCALER_Msk & ((value) << RTC_MODE2_CTRLA_PRESCALER_Pos)) 211 #define RTC_MODE2_CTRLA_PRESCALER_OFF_Val _U(0x0) /**< \brief (RTC_MODE2_CTRLA) CLK_RTC_CNT = GCLK_RTC/1 */ 212 #define RTC_MODE2_CTRLA_PRESCALER_DIV1_Val _U(0x1) /**< \brief (RTC_MODE2_CTRLA) CLK_RTC_CNT = GCLK_RTC/1 */ 213 #define RTC_MODE2_CTRLA_PRESCALER_DIV2_Val _U(0x2) /**< \brief (RTC_MODE2_CTRLA) CLK_RTC_CNT = GCLK_RTC/2 */ 214 #define RTC_MODE2_CTRLA_PRESCALER_DIV4_Val _U(0x3) /**< \brief (RTC_MODE2_CTRLA) CLK_RTC_CNT = GCLK_RTC/4 */ 215 #define RTC_MODE2_CTRLA_PRESCALER_DIV8_Val _U(0x4) /**< \brief (RTC_MODE2_CTRLA) CLK_RTC_CNT = GCLK_RTC/8 */ 216 #define RTC_MODE2_CTRLA_PRESCALER_DIV16_Val _U(0x5) /**< \brief (RTC_MODE2_CTRLA) CLK_RTC_CNT = GCLK_RTC/16 */ 217 #define RTC_MODE2_CTRLA_PRESCALER_DIV32_Val _U(0x6) /**< \brief (RTC_MODE2_CTRLA) CLK_RTC_CNT = GCLK_RTC/32 */ 218 #define RTC_MODE2_CTRLA_PRESCALER_DIV64_Val _U(0x7) /**< \brief (RTC_MODE2_CTRLA) CLK_RTC_CNT = GCLK_RTC/64 */ 219 #define RTC_MODE2_CTRLA_PRESCALER_DIV128_Val _U(0x8) /**< \brief (RTC_MODE2_CTRLA) CLK_RTC_CNT = GCLK_RTC/128 */ 220 #define RTC_MODE2_CTRLA_PRESCALER_DIV256_Val _U(0x9) /**< \brief (RTC_MODE2_CTRLA) CLK_RTC_CNT = GCLK_RTC/256 */ 221 #define RTC_MODE2_CTRLA_PRESCALER_DIV512_Val _U(0xA) /**< \brief (RTC_MODE2_CTRLA) CLK_RTC_CNT = GCLK_RTC/512 */ 222 #define RTC_MODE2_CTRLA_PRESCALER_DIV1024_Val _U(0xB) /**< \brief (RTC_MODE2_CTRLA) CLK_RTC_CNT = GCLK_RTC/1024 */ 223 #define RTC_MODE2_CTRLA_PRESCALER_OFF (RTC_MODE2_CTRLA_PRESCALER_OFF_Val << RTC_MODE2_CTRLA_PRESCALER_Pos) 224 #define RTC_MODE2_CTRLA_PRESCALER_DIV1 (RTC_MODE2_CTRLA_PRESCALER_DIV1_Val << RTC_MODE2_CTRLA_PRESCALER_Pos) 225 #define RTC_MODE2_CTRLA_PRESCALER_DIV2 (RTC_MODE2_CTRLA_PRESCALER_DIV2_Val << RTC_MODE2_CTRLA_PRESCALER_Pos) 226 #define RTC_MODE2_CTRLA_PRESCALER_DIV4 (RTC_MODE2_CTRLA_PRESCALER_DIV4_Val << RTC_MODE2_CTRLA_PRESCALER_Pos) 227 #define RTC_MODE2_CTRLA_PRESCALER_DIV8 (RTC_MODE2_CTRLA_PRESCALER_DIV8_Val << RTC_MODE2_CTRLA_PRESCALER_Pos) 228 #define RTC_MODE2_CTRLA_PRESCALER_DIV16 (RTC_MODE2_CTRLA_PRESCALER_DIV16_Val << RTC_MODE2_CTRLA_PRESCALER_Pos) 229 #define RTC_MODE2_CTRLA_PRESCALER_DIV32 (RTC_MODE2_CTRLA_PRESCALER_DIV32_Val << RTC_MODE2_CTRLA_PRESCALER_Pos) 230 #define RTC_MODE2_CTRLA_PRESCALER_DIV64 (RTC_MODE2_CTRLA_PRESCALER_DIV64_Val << RTC_MODE2_CTRLA_PRESCALER_Pos) 231 #define RTC_MODE2_CTRLA_PRESCALER_DIV128 (RTC_MODE2_CTRLA_PRESCALER_DIV128_Val << RTC_MODE2_CTRLA_PRESCALER_Pos) 232 #define RTC_MODE2_CTRLA_PRESCALER_DIV256 (RTC_MODE2_CTRLA_PRESCALER_DIV256_Val << RTC_MODE2_CTRLA_PRESCALER_Pos) 233 #define RTC_MODE2_CTRLA_PRESCALER_DIV512 (RTC_MODE2_CTRLA_PRESCALER_DIV512_Val << RTC_MODE2_CTRLA_PRESCALER_Pos) 234 #define RTC_MODE2_CTRLA_PRESCALER_DIV1024 (RTC_MODE2_CTRLA_PRESCALER_DIV1024_Val << RTC_MODE2_CTRLA_PRESCALER_Pos) 235 #define RTC_MODE2_CTRLA_CLOCKSYNC_Pos 15 /**< \brief (RTC_MODE2_CTRLA) Clock Read Synchronization Enable */ 236 #define RTC_MODE2_CTRLA_CLOCKSYNC (_U(0x1) << RTC_MODE2_CTRLA_CLOCKSYNC_Pos) 237 #define RTC_MODE2_CTRLA_MASK _U(0x8FCF) /**< \brief (RTC_MODE2_CTRLA) MASK Register */ 238 239 /* -------- RTC_MODE0_EVCTRL : (RTC Offset: 0x04) (R/W 32) MODE0 MODE0 Event Control -------- */ 240 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 241 typedef union { 242 struct { 243 uint32_t PEREO0:1; /*!< bit: 0 Periodic Interval 0 Event Output Enable */ 244 uint32_t PEREO1:1; /*!< bit: 1 Periodic Interval 1 Event Output Enable */ 245 uint32_t PEREO2:1; /*!< bit: 2 Periodic Interval 2 Event Output Enable */ 246 uint32_t PEREO3:1; /*!< bit: 3 Periodic Interval 3 Event Output Enable */ 247 uint32_t PEREO4:1; /*!< bit: 4 Periodic Interval 4 Event Output Enable */ 248 uint32_t PEREO5:1; /*!< bit: 5 Periodic Interval 5 Event Output Enable */ 249 uint32_t PEREO6:1; /*!< bit: 6 Periodic Interval 6 Event Output Enable */ 250 uint32_t PEREO7:1; /*!< bit: 7 Periodic Interval 7 Event Output Enable */ 251 uint32_t CMPEO0:1; /*!< bit: 8 Compare 0 Event Output Enable */ 252 uint32_t :6; /*!< bit: 9..14 Reserved */ 253 uint32_t OVFEO:1; /*!< bit: 15 Overflow Event Output Enable */ 254 uint32_t :16; /*!< bit: 16..31 Reserved */ 255 } bit; /*!< Structure used for bit access */ 256 struct { 257 uint32_t PEREO:8; /*!< bit: 0.. 7 Periodic Interval x Event Output Enable */ 258 uint32_t CMPEO:1; /*!< bit: 8 Compare x Event Output Enable */ 259 uint32_t :23; /*!< bit: 9..31 Reserved */ 260 } vec; /*!< Structure used for vec access */ 261 uint32_t reg; /*!< Type used for register access */ 262 } RTC_MODE0_EVCTRL_Type; 263 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 264 265 #define RTC_MODE0_EVCTRL_OFFSET 0x04 /**< \brief (RTC_MODE0_EVCTRL offset) MODE0 Event Control */ 266 #define RTC_MODE0_EVCTRL_RESETVALUE _U(0x00000000) /**< \brief (RTC_MODE0_EVCTRL reset_value) MODE0 Event Control */ 267 268 #define RTC_MODE0_EVCTRL_PEREO0_Pos 0 /**< \brief (RTC_MODE0_EVCTRL) Periodic Interval 0 Event Output Enable */ 269 #define RTC_MODE0_EVCTRL_PEREO0 (1 << RTC_MODE0_EVCTRL_PEREO0_Pos) 270 #define RTC_MODE0_EVCTRL_PEREO1_Pos 1 /**< \brief (RTC_MODE0_EVCTRL) Periodic Interval 1 Event Output Enable */ 271 #define RTC_MODE0_EVCTRL_PEREO1 (1 << RTC_MODE0_EVCTRL_PEREO1_Pos) 272 #define RTC_MODE0_EVCTRL_PEREO2_Pos 2 /**< \brief (RTC_MODE0_EVCTRL) Periodic Interval 2 Event Output Enable */ 273 #define RTC_MODE0_EVCTRL_PEREO2 (1 << RTC_MODE0_EVCTRL_PEREO2_Pos) 274 #define RTC_MODE0_EVCTRL_PEREO3_Pos 3 /**< \brief (RTC_MODE0_EVCTRL) Periodic Interval 3 Event Output Enable */ 275 #define RTC_MODE0_EVCTRL_PEREO3 (1 << RTC_MODE0_EVCTRL_PEREO3_Pos) 276 #define RTC_MODE0_EVCTRL_PEREO4_Pos 4 /**< \brief (RTC_MODE0_EVCTRL) Periodic Interval 4 Event Output Enable */ 277 #define RTC_MODE0_EVCTRL_PEREO4 (1 << RTC_MODE0_EVCTRL_PEREO4_Pos) 278 #define RTC_MODE0_EVCTRL_PEREO5_Pos 5 /**< \brief (RTC_MODE0_EVCTRL) Periodic Interval 5 Event Output Enable */ 279 #define RTC_MODE0_EVCTRL_PEREO5 (1 << RTC_MODE0_EVCTRL_PEREO5_Pos) 280 #define RTC_MODE0_EVCTRL_PEREO6_Pos 6 /**< \brief (RTC_MODE0_EVCTRL) Periodic Interval 6 Event Output Enable */ 281 #define RTC_MODE0_EVCTRL_PEREO6 (1 << RTC_MODE0_EVCTRL_PEREO6_Pos) 282 #define RTC_MODE0_EVCTRL_PEREO7_Pos 7 /**< \brief (RTC_MODE0_EVCTRL) Periodic Interval 7 Event Output Enable */ 283 #define RTC_MODE0_EVCTRL_PEREO7 (1 << RTC_MODE0_EVCTRL_PEREO7_Pos) 284 #define RTC_MODE0_EVCTRL_PEREO_Pos 0 /**< \brief (RTC_MODE0_EVCTRL) Periodic Interval x Event Output Enable */ 285 #define RTC_MODE0_EVCTRL_PEREO_Msk (_U(0xFF) << RTC_MODE0_EVCTRL_PEREO_Pos) 286 #define RTC_MODE0_EVCTRL_PEREO(value) (RTC_MODE0_EVCTRL_PEREO_Msk & ((value) << RTC_MODE0_EVCTRL_PEREO_Pos)) 287 #define RTC_MODE0_EVCTRL_CMPEO0_Pos 8 /**< \brief (RTC_MODE0_EVCTRL) Compare 0 Event Output Enable */ 288 #define RTC_MODE0_EVCTRL_CMPEO0 (1 << RTC_MODE0_EVCTRL_CMPEO0_Pos) 289 #define RTC_MODE0_EVCTRL_CMPEO_Pos 8 /**< \brief (RTC_MODE0_EVCTRL) Compare x Event Output Enable */ 290 #define RTC_MODE0_EVCTRL_CMPEO_Msk (_U(0x1) << RTC_MODE0_EVCTRL_CMPEO_Pos) 291 #define RTC_MODE0_EVCTRL_CMPEO(value) (RTC_MODE0_EVCTRL_CMPEO_Msk & ((value) << RTC_MODE0_EVCTRL_CMPEO_Pos)) 292 #define RTC_MODE0_EVCTRL_OVFEO_Pos 15 /**< \brief (RTC_MODE0_EVCTRL) Overflow Event Output Enable */ 293 #define RTC_MODE0_EVCTRL_OVFEO (_U(0x1) << RTC_MODE0_EVCTRL_OVFEO_Pos) 294 #define RTC_MODE0_EVCTRL_MASK _U(0x000081FF) /**< \brief (RTC_MODE0_EVCTRL) MASK Register */ 295 296 /* -------- RTC_MODE1_EVCTRL : (RTC Offset: 0x04) (R/W 32) MODE1 MODE1 Event Control -------- */ 297 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 298 typedef union { 299 struct { 300 uint32_t PEREO0:1; /*!< bit: 0 Periodic Interval 0 Event Output Enable */ 301 uint32_t PEREO1:1; /*!< bit: 1 Periodic Interval 1 Event Output Enable */ 302 uint32_t PEREO2:1; /*!< bit: 2 Periodic Interval 2 Event Output Enable */ 303 uint32_t PEREO3:1; /*!< bit: 3 Periodic Interval 3 Event Output Enable */ 304 uint32_t PEREO4:1; /*!< bit: 4 Periodic Interval 4 Event Output Enable */ 305 uint32_t PEREO5:1; /*!< bit: 5 Periodic Interval 5 Event Output Enable */ 306 uint32_t PEREO6:1; /*!< bit: 6 Periodic Interval 6 Event Output Enable */ 307 uint32_t PEREO7:1; /*!< bit: 7 Periodic Interval 7 Event Output Enable */ 308 uint32_t CMPEO0:1; /*!< bit: 8 Compare 0 Event Output Enable */ 309 uint32_t CMPEO1:1; /*!< bit: 9 Compare 1 Event Output Enable */ 310 uint32_t :5; /*!< bit: 10..14 Reserved */ 311 uint32_t OVFEO:1; /*!< bit: 15 Overflow Event Output Enable */ 312 uint32_t :16; /*!< bit: 16..31 Reserved */ 313 } bit; /*!< Structure used for bit access */ 314 struct { 315 uint32_t PEREO:8; /*!< bit: 0.. 7 Periodic Interval x Event Output Enable */ 316 uint32_t CMPEO:2; /*!< bit: 8.. 9 Compare x Event Output Enable */ 317 uint32_t :22; /*!< bit: 10..31 Reserved */ 318 } vec; /*!< Structure used for vec access */ 319 uint32_t reg; /*!< Type used for register access */ 320 } RTC_MODE1_EVCTRL_Type; 321 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 322 323 #define RTC_MODE1_EVCTRL_OFFSET 0x04 /**< \brief (RTC_MODE1_EVCTRL offset) MODE1 Event Control */ 324 #define RTC_MODE1_EVCTRL_RESETVALUE _U(0x00000000) /**< \brief (RTC_MODE1_EVCTRL reset_value) MODE1 Event Control */ 325 326 #define RTC_MODE1_EVCTRL_PEREO0_Pos 0 /**< \brief (RTC_MODE1_EVCTRL) Periodic Interval 0 Event Output Enable */ 327 #define RTC_MODE1_EVCTRL_PEREO0 (1 << RTC_MODE1_EVCTRL_PEREO0_Pos) 328 #define RTC_MODE1_EVCTRL_PEREO1_Pos 1 /**< \brief (RTC_MODE1_EVCTRL) Periodic Interval 1 Event Output Enable */ 329 #define RTC_MODE1_EVCTRL_PEREO1 (1 << RTC_MODE1_EVCTRL_PEREO1_Pos) 330 #define RTC_MODE1_EVCTRL_PEREO2_Pos 2 /**< \brief (RTC_MODE1_EVCTRL) Periodic Interval 2 Event Output Enable */ 331 #define RTC_MODE1_EVCTRL_PEREO2 (1 << RTC_MODE1_EVCTRL_PEREO2_Pos) 332 #define RTC_MODE1_EVCTRL_PEREO3_Pos 3 /**< \brief (RTC_MODE1_EVCTRL) Periodic Interval 3 Event Output Enable */ 333 #define RTC_MODE1_EVCTRL_PEREO3 (1 << RTC_MODE1_EVCTRL_PEREO3_Pos) 334 #define RTC_MODE1_EVCTRL_PEREO4_Pos 4 /**< \brief (RTC_MODE1_EVCTRL) Periodic Interval 4 Event Output Enable */ 335 #define RTC_MODE1_EVCTRL_PEREO4 (1 << RTC_MODE1_EVCTRL_PEREO4_Pos) 336 #define RTC_MODE1_EVCTRL_PEREO5_Pos 5 /**< \brief (RTC_MODE1_EVCTRL) Periodic Interval 5 Event Output Enable */ 337 #define RTC_MODE1_EVCTRL_PEREO5 (1 << RTC_MODE1_EVCTRL_PEREO5_Pos) 338 #define RTC_MODE1_EVCTRL_PEREO6_Pos 6 /**< \brief (RTC_MODE1_EVCTRL) Periodic Interval 6 Event Output Enable */ 339 #define RTC_MODE1_EVCTRL_PEREO6 (1 << RTC_MODE1_EVCTRL_PEREO6_Pos) 340 #define RTC_MODE1_EVCTRL_PEREO7_Pos 7 /**< \brief (RTC_MODE1_EVCTRL) Periodic Interval 7 Event Output Enable */ 341 #define RTC_MODE1_EVCTRL_PEREO7 (1 << RTC_MODE1_EVCTRL_PEREO7_Pos) 342 #define RTC_MODE1_EVCTRL_PEREO_Pos 0 /**< \brief (RTC_MODE1_EVCTRL) Periodic Interval x Event Output Enable */ 343 #define RTC_MODE1_EVCTRL_PEREO_Msk (_U(0xFF) << RTC_MODE1_EVCTRL_PEREO_Pos) 344 #define RTC_MODE1_EVCTRL_PEREO(value) (RTC_MODE1_EVCTRL_PEREO_Msk & ((value) << RTC_MODE1_EVCTRL_PEREO_Pos)) 345 #define RTC_MODE1_EVCTRL_CMPEO0_Pos 8 /**< \brief (RTC_MODE1_EVCTRL) Compare 0 Event Output Enable */ 346 #define RTC_MODE1_EVCTRL_CMPEO0 (1 << RTC_MODE1_EVCTRL_CMPEO0_Pos) 347 #define RTC_MODE1_EVCTRL_CMPEO1_Pos 9 /**< \brief (RTC_MODE1_EVCTRL) Compare 1 Event Output Enable */ 348 #define RTC_MODE1_EVCTRL_CMPEO1 (1 << RTC_MODE1_EVCTRL_CMPEO1_Pos) 349 #define RTC_MODE1_EVCTRL_CMPEO_Pos 8 /**< \brief (RTC_MODE1_EVCTRL) Compare x Event Output Enable */ 350 #define RTC_MODE1_EVCTRL_CMPEO_Msk (_U(0x3) << RTC_MODE1_EVCTRL_CMPEO_Pos) 351 #define RTC_MODE1_EVCTRL_CMPEO(value) (RTC_MODE1_EVCTRL_CMPEO_Msk & ((value) << RTC_MODE1_EVCTRL_CMPEO_Pos)) 352 #define RTC_MODE1_EVCTRL_OVFEO_Pos 15 /**< \brief (RTC_MODE1_EVCTRL) Overflow Event Output Enable */ 353 #define RTC_MODE1_EVCTRL_OVFEO (_U(0x1) << RTC_MODE1_EVCTRL_OVFEO_Pos) 354 #define RTC_MODE1_EVCTRL_MASK _U(0x000083FF) /**< \brief (RTC_MODE1_EVCTRL) MASK Register */ 355 356 /* -------- RTC_MODE2_EVCTRL : (RTC Offset: 0x04) (R/W 32) MODE2 MODE2 Event Control -------- */ 357 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 358 typedef union { 359 struct { 360 uint32_t PEREO0:1; /*!< bit: 0 Periodic Interval 0 Event Output Enable */ 361 uint32_t PEREO1:1; /*!< bit: 1 Periodic Interval 1 Event Output Enable */ 362 uint32_t PEREO2:1; /*!< bit: 2 Periodic Interval 2 Event Output Enable */ 363 uint32_t PEREO3:1; /*!< bit: 3 Periodic Interval 3 Event Output Enable */ 364 uint32_t PEREO4:1; /*!< bit: 4 Periodic Interval 4 Event Output Enable */ 365 uint32_t PEREO5:1; /*!< bit: 5 Periodic Interval 5 Event Output Enable */ 366 uint32_t PEREO6:1; /*!< bit: 6 Periodic Interval 6 Event Output Enable */ 367 uint32_t PEREO7:1; /*!< bit: 7 Periodic Interval 7 Event Output Enable */ 368 uint32_t ALARMEO0:1; /*!< bit: 8 Alarm 0 Event Output Enable */ 369 uint32_t :6; /*!< bit: 9..14 Reserved */ 370 uint32_t OVFEO:1; /*!< bit: 15 Overflow Event Output Enable */ 371 uint32_t :16; /*!< bit: 16..31 Reserved */ 372 } bit; /*!< Structure used for bit access */ 373 struct { 374 uint32_t PEREO:8; /*!< bit: 0.. 7 Periodic Interval x Event Output Enable */ 375 uint32_t ALARMEO:1; /*!< bit: 8 Alarm x Event Output Enable */ 376 uint32_t :23; /*!< bit: 9..31 Reserved */ 377 } vec; /*!< Structure used for vec access */ 378 uint32_t reg; /*!< Type used for register access */ 379 } RTC_MODE2_EVCTRL_Type; 380 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 381 382 #define RTC_MODE2_EVCTRL_OFFSET 0x04 /**< \brief (RTC_MODE2_EVCTRL offset) MODE2 Event Control */ 383 #define RTC_MODE2_EVCTRL_RESETVALUE _U(0x00000000) /**< \brief (RTC_MODE2_EVCTRL reset_value) MODE2 Event Control */ 384 385 #define RTC_MODE2_EVCTRL_PEREO0_Pos 0 /**< \brief (RTC_MODE2_EVCTRL) Periodic Interval 0 Event Output Enable */ 386 #define RTC_MODE2_EVCTRL_PEREO0 (1 << RTC_MODE2_EVCTRL_PEREO0_Pos) 387 #define RTC_MODE2_EVCTRL_PEREO1_Pos 1 /**< \brief (RTC_MODE2_EVCTRL) Periodic Interval 1 Event Output Enable */ 388 #define RTC_MODE2_EVCTRL_PEREO1 (1 << RTC_MODE2_EVCTRL_PEREO1_Pos) 389 #define RTC_MODE2_EVCTRL_PEREO2_Pos 2 /**< \brief (RTC_MODE2_EVCTRL) Periodic Interval 2 Event Output Enable */ 390 #define RTC_MODE2_EVCTRL_PEREO2 (1 << RTC_MODE2_EVCTRL_PEREO2_Pos) 391 #define RTC_MODE2_EVCTRL_PEREO3_Pos 3 /**< \brief (RTC_MODE2_EVCTRL) Periodic Interval 3 Event Output Enable */ 392 #define RTC_MODE2_EVCTRL_PEREO3 (1 << RTC_MODE2_EVCTRL_PEREO3_Pos) 393 #define RTC_MODE2_EVCTRL_PEREO4_Pos 4 /**< \brief (RTC_MODE2_EVCTRL) Periodic Interval 4 Event Output Enable */ 394 #define RTC_MODE2_EVCTRL_PEREO4 (1 << RTC_MODE2_EVCTRL_PEREO4_Pos) 395 #define RTC_MODE2_EVCTRL_PEREO5_Pos 5 /**< \brief (RTC_MODE2_EVCTRL) Periodic Interval 5 Event Output Enable */ 396 #define RTC_MODE2_EVCTRL_PEREO5 (1 << RTC_MODE2_EVCTRL_PEREO5_Pos) 397 #define RTC_MODE2_EVCTRL_PEREO6_Pos 6 /**< \brief (RTC_MODE2_EVCTRL) Periodic Interval 6 Event Output Enable */ 398 #define RTC_MODE2_EVCTRL_PEREO6 (1 << RTC_MODE2_EVCTRL_PEREO6_Pos) 399 #define RTC_MODE2_EVCTRL_PEREO7_Pos 7 /**< \brief (RTC_MODE2_EVCTRL) Periodic Interval 7 Event Output Enable */ 400 #define RTC_MODE2_EVCTRL_PEREO7 (1 << RTC_MODE2_EVCTRL_PEREO7_Pos) 401 #define RTC_MODE2_EVCTRL_PEREO_Pos 0 /**< \brief (RTC_MODE2_EVCTRL) Periodic Interval x Event Output Enable */ 402 #define RTC_MODE2_EVCTRL_PEREO_Msk (_U(0xFF) << RTC_MODE2_EVCTRL_PEREO_Pos) 403 #define RTC_MODE2_EVCTRL_PEREO(value) (RTC_MODE2_EVCTRL_PEREO_Msk & ((value) << RTC_MODE2_EVCTRL_PEREO_Pos)) 404 #define RTC_MODE2_EVCTRL_ALARMEO0_Pos 8 /**< \brief (RTC_MODE2_EVCTRL) Alarm 0 Event Output Enable */ 405 #define RTC_MODE2_EVCTRL_ALARMEO0 (1 << RTC_MODE2_EVCTRL_ALARMEO0_Pos) 406 #define RTC_MODE2_EVCTRL_ALARMEO_Pos 8 /**< \brief (RTC_MODE2_EVCTRL) Alarm x Event Output Enable */ 407 #define RTC_MODE2_EVCTRL_ALARMEO_Msk (_U(0x1) << RTC_MODE2_EVCTRL_ALARMEO_Pos) 408 #define RTC_MODE2_EVCTRL_ALARMEO(value) (RTC_MODE2_EVCTRL_ALARMEO_Msk & ((value) << RTC_MODE2_EVCTRL_ALARMEO_Pos)) 409 #define RTC_MODE2_EVCTRL_OVFEO_Pos 15 /**< \brief (RTC_MODE2_EVCTRL) Overflow Event Output Enable */ 410 #define RTC_MODE2_EVCTRL_OVFEO (_U(0x1) << RTC_MODE2_EVCTRL_OVFEO_Pos) 411 #define RTC_MODE2_EVCTRL_MASK _U(0x000081FF) /**< \brief (RTC_MODE2_EVCTRL) MASK Register */ 412 413 /* -------- RTC_MODE0_INTENCLR : (RTC Offset: 0x08) (R/W 16) MODE0 MODE0 Interrupt Enable Clear -------- */ 414 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 415 typedef union { 416 struct { 417 uint16_t PER0:1; /*!< bit: 0 Periodic Interval 0 Interrupt Enable */ 418 uint16_t PER1:1; /*!< bit: 1 Periodic Interval 1 Interrupt Enable */ 419 uint16_t PER2:1; /*!< bit: 2 Periodic Interval 2 Interrupt Enable */ 420 uint16_t PER3:1; /*!< bit: 3 Periodic Interval 3 Interrupt Enable */ 421 uint16_t PER4:1; /*!< bit: 4 Periodic Interval 4 Interrupt Enable */ 422 uint16_t PER5:1; /*!< bit: 5 Periodic Interval 5 Interrupt Enable */ 423 uint16_t PER6:1; /*!< bit: 6 Periodic Interval 6 Interrupt Enable */ 424 uint16_t PER7:1; /*!< bit: 7 Periodic Interval 7 Interrupt Enable */ 425 uint16_t CMP0:1; /*!< bit: 8 Compare 0 Interrupt Enable */ 426 uint16_t :6; /*!< bit: 9..14 Reserved */ 427 uint16_t OVF:1; /*!< bit: 15 Overflow Interrupt Enable */ 428 } bit; /*!< Structure used for bit access */ 429 struct { 430 uint16_t PER:8; /*!< bit: 0.. 7 Periodic Interval x Interrupt Enable */ 431 uint16_t CMP:1; /*!< bit: 8 Compare x Interrupt Enable */ 432 uint16_t :7; /*!< bit: 9..15 Reserved */ 433 } vec; /*!< Structure used for vec access */ 434 uint16_t reg; /*!< Type used for register access */ 435 } RTC_MODE0_INTENCLR_Type; 436 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 437 438 #define RTC_MODE0_INTENCLR_OFFSET 0x08 /**< \brief (RTC_MODE0_INTENCLR offset) MODE0 Interrupt Enable Clear */ 439 #define RTC_MODE0_INTENCLR_RESETVALUE _U(0x0000) /**< \brief (RTC_MODE0_INTENCLR reset_value) MODE0 Interrupt Enable Clear */ 440 441 #define RTC_MODE0_INTENCLR_PER0_Pos 0 /**< \brief (RTC_MODE0_INTENCLR) Periodic Interval 0 Interrupt Enable */ 442 #define RTC_MODE0_INTENCLR_PER0 (1 << RTC_MODE0_INTENCLR_PER0_Pos) 443 #define RTC_MODE0_INTENCLR_PER1_Pos 1 /**< \brief (RTC_MODE0_INTENCLR) Periodic Interval 1 Interrupt Enable */ 444 #define RTC_MODE0_INTENCLR_PER1 (1 << RTC_MODE0_INTENCLR_PER1_Pos) 445 #define RTC_MODE0_INTENCLR_PER2_Pos 2 /**< \brief (RTC_MODE0_INTENCLR) Periodic Interval 2 Interrupt Enable */ 446 #define RTC_MODE0_INTENCLR_PER2 (1 << RTC_MODE0_INTENCLR_PER2_Pos) 447 #define RTC_MODE0_INTENCLR_PER3_Pos 3 /**< \brief (RTC_MODE0_INTENCLR) Periodic Interval 3 Interrupt Enable */ 448 #define RTC_MODE0_INTENCLR_PER3 (1 << RTC_MODE0_INTENCLR_PER3_Pos) 449 #define RTC_MODE0_INTENCLR_PER4_Pos 4 /**< \brief (RTC_MODE0_INTENCLR) Periodic Interval 4 Interrupt Enable */ 450 #define RTC_MODE0_INTENCLR_PER4 (1 << RTC_MODE0_INTENCLR_PER4_Pos) 451 #define RTC_MODE0_INTENCLR_PER5_Pos 5 /**< \brief (RTC_MODE0_INTENCLR) Periodic Interval 5 Interrupt Enable */ 452 #define RTC_MODE0_INTENCLR_PER5 (1 << RTC_MODE0_INTENCLR_PER5_Pos) 453 #define RTC_MODE0_INTENCLR_PER6_Pos 6 /**< \brief (RTC_MODE0_INTENCLR) Periodic Interval 6 Interrupt Enable */ 454 #define RTC_MODE0_INTENCLR_PER6 (1 << RTC_MODE0_INTENCLR_PER6_Pos) 455 #define RTC_MODE0_INTENCLR_PER7_Pos 7 /**< \brief (RTC_MODE0_INTENCLR) Periodic Interval 7 Interrupt Enable */ 456 #define RTC_MODE0_INTENCLR_PER7 (1 << RTC_MODE0_INTENCLR_PER7_Pos) 457 #define RTC_MODE0_INTENCLR_PER_Pos 0 /**< \brief (RTC_MODE0_INTENCLR) Periodic Interval x Interrupt Enable */ 458 #define RTC_MODE0_INTENCLR_PER_Msk (_U(0xFF) << RTC_MODE0_INTENCLR_PER_Pos) 459 #define RTC_MODE0_INTENCLR_PER(value) (RTC_MODE0_INTENCLR_PER_Msk & ((value) << RTC_MODE0_INTENCLR_PER_Pos)) 460 #define RTC_MODE0_INTENCLR_CMP0_Pos 8 /**< \brief (RTC_MODE0_INTENCLR) Compare 0 Interrupt Enable */ 461 #define RTC_MODE0_INTENCLR_CMP0 (1 << RTC_MODE0_INTENCLR_CMP0_Pos) 462 #define RTC_MODE0_INTENCLR_CMP_Pos 8 /**< \brief (RTC_MODE0_INTENCLR) Compare x Interrupt Enable */ 463 #define RTC_MODE0_INTENCLR_CMP_Msk (_U(0x1) << RTC_MODE0_INTENCLR_CMP_Pos) 464 #define RTC_MODE0_INTENCLR_CMP(value) (RTC_MODE0_INTENCLR_CMP_Msk & ((value) << RTC_MODE0_INTENCLR_CMP_Pos)) 465 #define RTC_MODE0_INTENCLR_OVF_Pos 15 /**< \brief (RTC_MODE0_INTENCLR) Overflow Interrupt Enable */ 466 #define RTC_MODE0_INTENCLR_OVF (_U(0x1) << RTC_MODE0_INTENCLR_OVF_Pos) 467 #define RTC_MODE0_INTENCLR_MASK _U(0x81FF) /**< \brief (RTC_MODE0_INTENCLR) MASK Register */ 468 469 /* -------- RTC_MODE1_INTENCLR : (RTC Offset: 0x08) (R/W 16) MODE1 MODE1 Interrupt Enable Clear -------- */ 470 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 471 typedef union { 472 struct { 473 uint16_t PER0:1; /*!< bit: 0 Periodic Interval 0 Interrupt Enable */ 474 uint16_t PER1:1; /*!< bit: 1 Periodic Interval 1 Interrupt Enable */ 475 uint16_t PER2:1; /*!< bit: 2 Periodic Interval 2 Interrupt Enable */ 476 uint16_t PER3:1; /*!< bit: 3 Periodic Interval 3 Interrupt Enable */ 477 uint16_t PER4:1; /*!< bit: 4 Periodic Interval 4 Interrupt Enable */ 478 uint16_t PER5:1; /*!< bit: 5 Periodic Interval 5 Interrupt Enable */ 479 uint16_t PER6:1; /*!< bit: 6 Periodic Interval 6 Interrupt Enable */ 480 uint16_t PER7:1; /*!< bit: 7 Periodic Interval 7 Interrupt Enable */ 481 uint16_t CMP0:1; /*!< bit: 8 Compare 0 Interrupt Enable */ 482 uint16_t CMP1:1; /*!< bit: 9 Compare 1 Interrupt Enable */ 483 uint16_t :5; /*!< bit: 10..14 Reserved */ 484 uint16_t OVF:1; /*!< bit: 15 Overflow Interrupt Enable */ 485 } bit; /*!< Structure used for bit access */ 486 struct { 487 uint16_t PER:8; /*!< bit: 0.. 7 Periodic Interval x Interrupt Enable */ 488 uint16_t CMP:2; /*!< bit: 8.. 9 Compare x Interrupt Enable */ 489 uint16_t :6; /*!< bit: 10..15 Reserved */ 490 } vec; /*!< Structure used for vec access */ 491 uint16_t reg; /*!< Type used for register access */ 492 } RTC_MODE1_INTENCLR_Type; 493 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 494 495 #define RTC_MODE1_INTENCLR_OFFSET 0x08 /**< \brief (RTC_MODE1_INTENCLR offset) MODE1 Interrupt Enable Clear */ 496 #define RTC_MODE1_INTENCLR_RESETVALUE _U(0x0000) /**< \brief (RTC_MODE1_INTENCLR reset_value) MODE1 Interrupt Enable Clear */ 497 498 #define RTC_MODE1_INTENCLR_PER0_Pos 0 /**< \brief (RTC_MODE1_INTENCLR) Periodic Interval 0 Interrupt Enable */ 499 #define RTC_MODE1_INTENCLR_PER0 (1 << RTC_MODE1_INTENCLR_PER0_Pos) 500 #define RTC_MODE1_INTENCLR_PER1_Pos 1 /**< \brief (RTC_MODE1_INTENCLR) Periodic Interval 1 Interrupt Enable */ 501 #define RTC_MODE1_INTENCLR_PER1 (1 << RTC_MODE1_INTENCLR_PER1_Pos) 502 #define RTC_MODE1_INTENCLR_PER2_Pos 2 /**< \brief (RTC_MODE1_INTENCLR) Periodic Interval 2 Interrupt Enable */ 503 #define RTC_MODE1_INTENCLR_PER2 (1 << RTC_MODE1_INTENCLR_PER2_Pos) 504 #define RTC_MODE1_INTENCLR_PER3_Pos 3 /**< \brief (RTC_MODE1_INTENCLR) Periodic Interval 3 Interrupt Enable */ 505 #define RTC_MODE1_INTENCLR_PER3 (1 << RTC_MODE1_INTENCLR_PER3_Pos) 506 #define RTC_MODE1_INTENCLR_PER4_Pos 4 /**< \brief (RTC_MODE1_INTENCLR) Periodic Interval 4 Interrupt Enable */ 507 #define RTC_MODE1_INTENCLR_PER4 (1 << RTC_MODE1_INTENCLR_PER4_Pos) 508 #define RTC_MODE1_INTENCLR_PER5_Pos 5 /**< \brief (RTC_MODE1_INTENCLR) Periodic Interval 5 Interrupt Enable */ 509 #define RTC_MODE1_INTENCLR_PER5 (1 << RTC_MODE1_INTENCLR_PER5_Pos) 510 #define RTC_MODE1_INTENCLR_PER6_Pos 6 /**< \brief (RTC_MODE1_INTENCLR) Periodic Interval 6 Interrupt Enable */ 511 #define RTC_MODE1_INTENCLR_PER6 (1 << RTC_MODE1_INTENCLR_PER6_Pos) 512 #define RTC_MODE1_INTENCLR_PER7_Pos 7 /**< \brief (RTC_MODE1_INTENCLR) Periodic Interval 7 Interrupt Enable */ 513 #define RTC_MODE1_INTENCLR_PER7 (1 << RTC_MODE1_INTENCLR_PER7_Pos) 514 #define RTC_MODE1_INTENCLR_PER_Pos 0 /**< \brief (RTC_MODE1_INTENCLR) Periodic Interval x Interrupt Enable */ 515 #define RTC_MODE1_INTENCLR_PER_Msk (_U(0xFF) << RTC_MODE1_INTENCLR_PER_Pos) 516 #define RTC_MODE1_INTENCLR_PER(value) (RTC_MODE1_INTENCLR_PER_Msk & ((value) << RTC_MODE1_INTENCLR_PER_Pos)) 517 #define RTC_MODE1_INTENCLR_CMP0_Pos 8 /**< \brief (RTC_MODE1_INTENCLR) Compare 0 Interrupt Enable */ 518 #define RTC_MODE1_INTENCLR_CMP0 (1 << RTC_MODE1_INTENCLR_CMP0_Pos) 519 #define RTC_MODE1_INTENCLR_CMP1_Pos 9 /**< \brief (RTC_MODE1_INTENCLR) Compare 1 Interrupt Enable */ 520 #define RTC_MODE1_INTENCLR_CMP1 (1 << RTC_MODE1_INTENCLR_CMP1_Pos) 521 #define RTC_MODE1_INTENCLR_CMP_Pos 8 /**< \brief (RTC_MODE1_INTENCLR) Compare x Interrupt Enable */ 522 #define RTC_MODE1_INTENCLR_CMP_Msk (_U(0x3) << RTC_MODE1_INTENCLR_CMP_Pos) 523 #define RTC_MODE1_INTENCLR_CMP(value) (RTC_MODE1_INTENCLR_CMP_Msk & ((value) << RTC_MODE1_INTENCLR_CMP_Pos)) 524 #define RTC_MODE1_INTENCLR_OVF_Pos 15 /**< \brief (RTC_MODE1_INTENCLR) Overflow Interrupt Enable */ 525 #define RTC_MODE1_INTENCLR_OVF (_U(0x1) << RTC_MODE1_INTENCLR_OVF_Pos) 526 #define RTC_MODE1_INTENCLR_MASK _U(0x83FF) /**< \brief (RTC_MODE1_INTENCLR) MASK Register */ 527 528 /* -------- RTC_MODE2_INTENCLR : (RTC Offset: 0x08) (R/W 16) MODE2 MODE2 Interrupt Enable Clear -------- */ 529 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 530 typedef union { 531 struct { 532 uint16_t PER0:1; /*!< bit: 0 Periodic Interval 0 Interrupt Enable */ 533 uint16_t PER1:1; /*!< bit: 1 Periodic Interval 1 Interrupt Enable */ 534 uint16_t PER2:1; /*!< bit: 2 Periodic Interval 2 Interrupt Enable */ 535 uint16_t PER3:1; /*!< bit: 3 Periodic Interval 3 Interrupt Enable */ 536 uint16_t PER4:1; /*!< bit: 4 Periodic Interval 4 Interrupt Enable */ 537 uint16_t PER5:1; /*!< bit: 5 Periodic Interval 5 Interrupt Enable */ 538 uint16_t PER6:1; /*!< bit: 6 Periodic Interval 6 Interrupt Enable */ 539 uint16_t PER7:1; /*!< bit: 7 Periodic Interval 7 Interrupt Enable */ 540 uint16_t ALARM0:1; /*!< bit: 8 Alarm 0 Interrupt Enable */ 541 uint16_t :6; /*!< bit: 9..14 Reserved */ 542 uint16_t OVF:1; /*!< bit: 15 Overflow Interrupt Enable */ 543 } bit; /*!< Structure used for bit access */ 544 struct { 545 uint16_t PER:8; /*!< bit: 0.. 7 Periodic Interval x Interrupt Enable */ 546 uint16_t ALARM:1; /*!< bit: 8 Alarm x Interrupt Enable */ 547 uint16_t :7; /*!< bit: 9..15 Reserved */ 548 } vec; /*!< Structure used for vec access */ 549 uint16_t reg; /*!< Type used for register access */ 550 } RTC_MODE2_INTENCLR_Type; 551 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 552 553 #define RTC_MODE2_INTENCLR_OFFSET 0x08 /**< \brief (RTC_MODE2_INTENCLR offset) MODE2 Interrupt Enable Clear */ 554 #define RTC_MODE2_INTENCLR_RESETVALUE _U(0x0000) /**< \brief (RTC_MODE2_INTENCLR reset_value) MODE2 Interrupt Enable Clear */ 555 556 #define RTC_MODE2_INTENCLR_PER0_Pos 0 /**< \brief (RTC_MODE2_INTENCLR) Periodic Interval 0 Interrupt Enable */ 557 #define RTC_MODE2_INTENCLR_PER0 (1 << RTC_MODE2_INTENCLR_PER0_Pos) 558 #define RTC_MODE2_INTENCLR_PER1_Pos 1 /**< \brief (RTC_MODE2_INTENCLR) Periodic Interval 1 Interrupt Enable */ 559 #define RTC_MODE2_INTENCLR_PER1 (1 << RTC_MODE2_INTENCLR_PER1_Pos) 560 #define RTC_MODE2_INTENCLR_PER2_Pos 2 /**< \brief (RTC_MODE2_INTENCLR) Periodic Interval 2 Interrupt Enable */ 561 #define RTC_MODE2_INTENCLR_PER2 (1 << RTC_MODE2_INTENCLR_PER2_Pos) 562 #define RTC_MODE2_INTENCLR_PER3_Pos 3 /**< \brief (RTC_MODE2_INTENCLR) Periodic Interval 3 Interrupt Enable */ 563 #define RTC_MODE2_INTENCLR_PER3 (1 << RTC_MODE2_INTENCLR_PER3_Pos) 564 #define RTC_MODE2_INTENCLR_PER4_Pos 4 /**< \brief (RTC_MODE2_INTENCLR) Periodic Interval 4 Interrupt Enable */ 565 #define RTC_MODE2_INTENCLR_PER4 (1 << RTC_MODE2_INTENCLR_PER4_Pos) 566 #define RTC_MODE2_INTENCLR_PER5_Pos 5 /**< \brief (RTC_MODE2_INTENCLR) Periodic Interval 5 Interrupt Enable */ 567 #define RTC_MODE2_INTENCLR_PER5 (1 << RTC_MODE2_INTENCLR_PER5_Pos) 568 #define RTC_MODE2_INTENCLR_PER6_Pos 6 /**< \brief (RTC_MODE2_INTENCLR) Periodic Interval 6 Interrupt Enable */ 569 #define RTC_MODE2_INTENCLR_PER6 (1 << RTC_MODE2_INTENCLR_PER6_Pos) 570 #define RTC_MODE2_INTENCLR_PER7_Pos 7 /**< \brief (RTC_MODE2_INTENCLR) Periodic Interval 7 Interrupt Enable */ 571 #define RTC_MODE2_INTENCLR_PER7 (1 << RTC_MODE2_INTENCLR_PER7_Pos) 572 #define RTC_MODE2_INTENCLR_PER_Pos 0 /**< \brief (RTC_MODE2_INTENCLR) Periodic Interval x Interrupt Enable */ 573 #define RTC_MODE2_INTENCLR_PER_Msk (_U(0xFF) << RTC_MODE2_INTENCLR_PER_Pos) 574 #define RTC_MODE2_INTENCLR_PER(value) (RTC_MODE2_INTENCLR_PER_Msk & ((value) << RTC_MODE2_INTENCLR_PER_Pos)) 575 #define RTC_MODE2_INTENCLR_ALARM0_Pos 8 /**< \brief (RTC_MODE2_INTENCLR) Alarm 0 Interrupt Enable */ 576 #define RTC_MODE2_INTENCLR_ALARM0 (1 << RTC_MODE2_INTENCLR_ALARM0_Pos) 577 #define RTC_MODE2_INTENCLR_ALARM_Pos 8 /**< \brief (RTC_MODE2_INTENCLR) Alarm x Interrupt Enable */ 578 #define RTC_MODE2_INTENCLR_ALARM_Msk (_U(0x1) << RTC_MODE2_INTENCLR_ALARM_Pos) 579 #define RTC_MODE2_INTENCLR_ALARM(value) (RTC_MODE2_INTENCLR_ALARM_Msk & ((value) << RTC_MODE2_INTENCLR_ALARM_Pos)) 580 #define RTC_MODE2_INTENCLR_OVF_Pos 15 /**< \brief (RTC_MODE2_INTENCLR) Overflow Interrupt Enable */ 581 #define RTC_MODE2_INTENCLR_OVF (_U(0x1) << RTC_MODE2_INTENCLR_OVF_Pos) 582 #define RTC_MODE2_INTENCLR_MASK _U(0x81FF) /**< \brief (RTC_MODE2_INTENCLR) MASK Register */ 583 584 /* -------- RTC_MODE0_INTENSET : (RTC Offset: 0x0A) (R/W 16) MODE0 MODE0 Interrupt Enable Set -------- */ 585 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 586 typedef union { 587 struct { 588 uint16_t PER0:1; /*!< bit: 0 Periodic Interval 0 Interrupt Enable */ 589 uint16_t PER1:1; /*!< bit: 1 Periodic Interval 1 Interrupt Enable */ 590 uint16_t PER2:1; /*!< bit: 2 Periodic Interval 2 Interrupt Enable */ 591 uint16_t PER3:1; /*!< bit: 3 Periodic Interval 3 Interrupt Enable */ 592 uint16_t PER4:1; /*!< bit: 4 Periodic Interval 4 Interrupt Enable */ 593 uint16_t PER5:1; /*!< bit: 5 Periodic Interval 5 Interrupt Enable */ 594 uint16_t PER6:1; /*!< bit: 6 Periodic Interval 6 Interrupt Enable */ 595 uint16_t PER7:1; /*!< bit: 7 Periodic Interval 7 Interrupt Enable */ 596 uint16_t CMP0:1; /*!< bit: 8 Compare 0 Interrupt Enable */ 597 uint16_t :6; /*!< bit: 9..14 Reserved */ 598 uint16_t OVF:1; /*!< bit: 15 Overflow Interrupt Enable */ 599 } bit; /*!< Structure used for bit access */ 600 struct { 601 uint16_t PER:8; /*!< bit: 0.. 7 Periodic Interval x Interrupt Enable */ 602 uint16_t CMP:1; /*!< bit: 8 Compare x Interrupt Enable */ 603 uint16_t :7; /*!< bit: 9..15 Reserved */ 604 } vec; /*!< Structure used for vec access */ 605 uint16_t reg; /*!< Type used for register access */ 606 } RTC_MODE0_INTENSET_Type; 607 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 608 609 #define RTC_MODE0_INTENSET_OFFSET 0x0A /**< \brief (RTC_MODE0_INTENSET offset) MODE0 Interrupt Enable Set */ 610 #define RTC_MODE0_INTENSET_RESETVALUE _U(0x0000) /**< \brief (RTC_MODE0_INTENSET reset_value) MODE0 Interrupt Enable Set */ 611 612 #define RTC_MODE0_INTENSET_PER0_Pos 0 /**< \brief (RTC_MODE0_INTENSET) Periodic Interval 0 Interrupt Enable */ 613 #define RTC_MODE0_INTENSET_PER0 (1 << RTC_MODE0_INTENSET_PER0_Pos) 614 #define RTC_MODE0_INTENSET_PER1_Pos 1 /**< \brief (RTC_MODE0_INTENSET) Periodic Interval 1 Interrupt Enable */ 615 #define RTC_MODE0_INTENSET_PER1 (1 << RTC_MODE0_INTENSET_PER1_Pos) 616 #define RTC_MODE0_INTENSET_PER2_Pos 2 /**< \brief (RTC_MODE0_INTENSET) Periodic Interval 2 Interrupt Enable */ 617 #define RTC_MODE0_INTENSET_PER2 (1 << RTC_MODE0_INTENSET_PER2_Pos) 618 #define RTC_MODE0_INTENSET_PER3_Pos 3 /**< \brief (RTC_MODE0_INTENSET) Periodic Interval 3 Interrupt Enable */ 619 #define RTC_MODE0_INTENSET_PER3 (1 << RTC_MODE0_INTENSET_PER3_Pos) 620 #define RTC_MODE0_INTENSET_PER4_Pos 4 /**< \brief (RTC_MODE0_INTENSET) Periodic Interval 4 Interrupt Enable */ 621 #define RTC_MODE0_INTENSET_PER4 (1 << RTC_MODE0_INTENSET_PER4_Pos) 622 #define RTC_MODE0_INTENSET_PER5_Pos 5 /**< \brief (RTC_MODE0_INTENSET) Periodic Interval 5 Interrupt Enable */ 623 #define RTC_MODE0_INTENSET_PER5 (1 << RTC_MODE0_INTENSET_PER5_Pos) 624 #define RTC_MODE0_INTENSET_PER6_Pos 6 /**< \brief (RTC_MODE0_INTENSET) Periodic Interval 6 Interrupt Enable */ 625 #define RTC_MODE0_INTENSET_PER6 (1 << RTC_MODE0_INTENSET_PER6_Pos) 626 #define RTC_MODE0_INTENSET_PER7_Pos 7 /**< \brief (RTC_MODE0_INTENSET) Periodic Interval 7 Interrupt Enable */ 627 #define RTC_MODE0_INTENSET_PER7 (1 << RTC_MODE0_INTENSET_PER7_Pos) 628 #define RTC_MODE0_INTENSET_PER_Pos 0 /**< \brief (RTC_MODE0_INTENSET) Periodic Interval x Interrupt Enable */ 629 #define RTC_MODE0_INTENSET_PER_Msk (_U(0xFF) << RTC_MODE0_INTENSET_PER_Pos) 630 #define RTC_MODE0_INTENSET_PER(value) (RTC_MODE0_INTENSET_PER_Msk & ((value) << RTC_MODE0_INTENSET_PER_Pos)) 631 #define RTC_MODE0_INTENSET_CMP0_Pos 8 /**< \brief (RTC_MODE0_INTENSET) Compare 0 Interrupt Enable */ 632 #define RTC_MODE0_INTENSET_CMP0 (1 << RTC_MODE0_INTENSET_CMP0_Pos) 633 #define RTC_MODE0_INTENSET_CMP_Pos 8 /**< \brief (RTC_MODE0_INTENSET) Compare x Interrupt Enable */ 634 #define RTC_MODE0_INTENSET_CMP_Msk (_U(0x1) << RTC_MODE0_INTENSET_CMP_Pos) 635 #define RTC_MODE0_INTENSET_CMP(value) (RTC_MODE0_INTENSET_CMP_Msk & ((value) << RTC_MODE0_INTENSET_CMP_Pos)) 636 #define RTC_MODE0_INTENSET_OVF_Pos 15 /**< \brief (RTC_MODE0_INTENSET) Overflow Interrupt Enable */ 637 #define RTC_MODE0_INTENSET_OVF (_U(0x1) << RTC_MODE0_INTENSET_OVF_Pos) 638 #define RTC_MODE0_INTENSET_MASK _U(0x81FF) /**< \brief (RTC_MODE0_INTENSET) MASK Register */ 639 640 /* -------- RTC_MODE1_INTENSET : (RTC Offset: 0x0A) (R/W 16) MODE1 MODE1 Interrupt Enable Set -------- */ 641 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 642 typedef union { 643 struct { 644 uint16_t PER0:1; /*!< bit: 0 Periodic Interval 0 Interrupt Enable */ 645 uint16_t PER1:1; /*!< bit: 1 Periodic Interval 1 Interrupt Enable */ 646 uint16_t PER2:1; /*!< bit: 2 Periodic Interval 2 Interrupt Enable */ 647 uint16_t PER3:1; /*!< bit: 3 Periodic Interval 3 Interrupt Enable */ 648 uint16_t PER4:1; /*!< bit: 4 Periodic Interval 4 Interrupt Enable */ 649 uint16_t PER5:1; /*!< bit: 5 Periodic Interval 5 Interrupt Enable */ 650 uint16_t PER6:1; /*!< bit: 6 Periodic Interval 6 Interrupt Enable */ 651 uint16_t PER7:1; /*!< bit: 7 Periodic Interval 7 Interrupt Enable */ 652 uint16_t CMP0:1; /*!< bit: 8 Compare 0 Interrupt Enable */ 653 uint16_t CMP1:1; /*!< bit: 9 Compare 1 Interrupt Enable */ 654 uint16_t :5; /*!< bit: 10..14 Reserved */ 655 uint16_t OVF:1; /*!< bit: 15 Overflow Interrupt Enable */ 656 } bit; /*!< Structure used for bit access */ 657 struct { 658 uint16_t PER:8; /*!< bit: 0.. 7 Periodic Interval x Interrupt Enable */ 659 uint16_t CMP:2; /*!< bit: 8.. 9 Compare x Interrupt Enable */ 660 uint16_t :6; /*!< bit: 10..15 Reserved */ 661 } vec; /*!< Structure used for vec access */ 662 uint16_t reg; /*!< Type used for register access */ 663 } RTC_MODE1_INTENSET_Type; 664 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 665 666 #define RTC_MODE1_INTENSET_OFFSET 0x0A /**< \brief (RTC_MODE1_INTENSET offset) MODE1 Interrupt Enable Set */ 667 #define RTC_MODE1_INTENSET_RESETVALUE _U(0x0000) /**< \brief (RTC_MODE1_INTENSET reset_value) MODE1 Interrupt Enable Set */ 668 669 #define RTC_MODE1_INTENSET_PER0_Pos 0 /**< \brief (RTC_MODE1_INTENSET) Periodic Interval 0 Interrupt Enable */ 670 #define RTC_MODE1_INTENSET_PER0 (1 << RTC_MODE1_INTENSET_PER0_Pos) 671 #define RTC_MODE1_INTENSET_PER1_Pos 1 /**< \brief (RTC_MODE1_INTENSET) Periodic Interval 1 Interrupt Enable */ 672 #define RTC_MODE1_INTENSET_PER1 (1 << RTC_MODE1_INTENSET_PER1_Pos) 673 #define RTC_MODE1_INTENSET_PER2_Pos 2 /**< \brief (RTC_MODE1_INTENSET) Periodic Interval 2 Interrupt Enable */ 674 #define RTC_MODE1_INTENSET_PER2 (1 << RTC_MODE1_INTENSET_PER2_Pos) 675 #define RTC_MODE1_INTENSET_PER3_Pos 3 /**< \brief (RTC_MODE1_INTENSET) Periodic Interval 3 Interrupt Enable */ 676 #define RTC_MODE1_INTENSET_PER3 (1 << RTC_MODE1_INTENSET_PER3_Pos) 677 #define RTC_MODE1_INTENSET_PER4_Pos 4 /**< \brief (RTC_MODE1_INTENSET) Periodic Interval 4 Interrupt Enable */ 678 #define RTC_MODE1_INTENSET_PER4 (1 << RTC_MODE1_INTENSET_PER4_Pos) 679 #define RTC_MODE1_INTENSET_PER5_Pos 5 /**< \brief (RTC_MODE1_INTENSET) Periodic Interval 5 Interrupt Enable */ 680 #define RTC_MODE1_INTENSET_PER5 (1 << RTC_MODE1_INTENSET_PER5_Pos) 681 #define RTC_MODE1_INTENSET_PER6_Pos 6 /**< \brief (RTC_MODE1_INTENSET) Periodic Interval 6 Interrupt Enable */ 682 #define RTC_MODE1_INTENSET_PER6 (1 << RTC_MODE1_INTENSET_PER6_Pos) 683 #define RTC_MODE1_INTENSET_PER7_Pos 7 /**< \brief (RTC_MODE1_INTENSET) Periodic Interval 7 Interrupt Enable */ 684 #define RTC_MODE1_INTENSET_PER7 (1 << RTC_MODE1_INTENSET_PER7_Pos) 685 #define RTC_MODE1_INTENSET_PER_Pos 0 /**< \brief (RTC_MODE1_INTENSET) Periodic Interval x Interrupt Enable */ 686 #define RTC_MODE1_INTENSET_PER_Msk (_U(0xFF) << RTC_MODE1_INTENSET_PER_Pos) 687 #define RTC_MODE1_INTENSET_PER(value) (RTC_MODE1_INTENSET_PER_Msk & ((value) << RTC_MODE1_INTENSET_PER_Pos)) 688 #define RTC_MODE1_INTENSET_CMP0_Pos 8 /**< \brief (RTC_MODE1_INTENSET) Compare 0 Interrupt Enable */ 689 #define RTC_MODE1_INTENSET_CMP0 (1 << RTC_MODE1_INTENSET_CMP0_Pos) 690 #define RTC_MODE1_INTENSET_CMP1_Pos 9 /**< \brief (RTC_MODE1_INTENSET) Compare 1 Interrupt Enable */ 691 #define RTC_MODE1_INTENSET_CMP1 (1 << RTC_MODE1_INTENSET_CMP1_Pos) 692 #define RTC_MODE1_INTENSET_CMP_Pos 8 /**< \brief (RTC_MODE1_INTENSET) Compare x Interrupt Enable */ 693 #define RTC_MODE1_INTENSET_CMP_Msk (_U(0x3) << RTC_MODE1_INTENSET_CMP_Pos) 694 #define RTC_MODE1_INTENSET_CMP(value) (RTC_MODE1_INTENSET_CMP_Msk & ((value) << RTC_MODE1_INTENSET_CMP_Pos)) 695 #define RTC_MODE1_INTENSET_OVF_Pos 15 /**< \brief (RTC_MODE1_INTENSET) Overflow Interrupt Enable */ 696 #define RTC_MODE1_INTENSET_OVF (_U(0x1) << RTC_MODE1_INTENSET_OVF_Pos) 697 #define RTC_MODE1_INTENSET_MASK _U(0x83FF) /**< \brief (RTC_MODE1_INTENSET) MASK Register */ 698 699 /* -------- RTC_MODE2_INTENSET : (RTC Offset: 0x0A) (R/W 16) MODE2 MODE2 Interrupt Enable Set -------- */ 700 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 701 typedef union { 702 struct { 703 uint16_t PER0:1; /*!< bit: 0 Periodic Interval 0 Enable */ 704 uint16_t PER1:1; /*!< bit: 1 Periodic Interval 1 Enable */ 705 uint16_t PER2:1; /*!< bit: 2 Periodic Interval 2 Enable */ 706 uint16_t PER3:1; /*!< bit: 3 Periodic Interval 3 Enable */ 707 uint16_t PER4:1; /*!< bit: 4 Periodic Interval 4 Enable */ 708 uint16_t PER5:1; /*!< bit: 5 Periodic Interval 5 Enable */ 709 uint16_t PER6:1; /*!< bit: 6 Periodic Interval 6 Enable */ 710 uint16_t PER7:1; /*!< bit: 7 Periodic Interval 7 Enable */ 711 uint16_t ALARM0:1; /*!< bit: 8 Alarm 0 Interrupt Enable */ 712 uint16_t :6; /*!< bit: 9..14 Reserved */ 713 uint16_t OVF:1; /*!< bit: 15 Overflow Interrupt Enable */ 714 } bit; /*!< Structure used for bit access */ 715 struct { 716 uint16_t PER:8; /*!< bit: 0.. 7 Periodic Interval x Enable */ 717 uint16_t ALARM:1; /*!< bit: 8 Alarm x Interrupt Enable */ 718 uint16_t :7; /*!< bit: 9..15 Reserved */ 719 } vec; /*!< Structure used for vec access */ 720 uint16_t reg; /*!< Type used for register access */ 721 } RTC_MODE2_INTENSET_Type; 722 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 723 724 #define RTC_MODE2_INTENSET_OFFSET 0x0A /**< \brief (RTC_MODE2_INTENSET offset) MODE2 Interrupt Enable Set */ 725 #define RTC_MODE2_INTENSET_RESETVALUE _U(0x0000) /**< \brief (RTC_MODE2_INTENSET reset_value) MODE2 Interrupt Enable Set */ 726 727 #define RTC_MODE2_INTENSET_PER0_Pos 0 /**< \brief (RTC_MODE2_INTENSET) Periodic Interval 0 Enable */ 728 #define RTC_MODE2_INTENSET_PER0 (1 << RTC_MODE2_INTENSET_PER0_Pos) 729 #define RTC_MODE2_INTENSET_PER1_Pos 1 /**< \brief (RTC_MODE2_INTENSET) Periodic Interval 1 Enable */ 730 #define RTC_MODE2_INTENSET_PER1 (1 << RTC_MODE2_INTENSET_PER1_Pos) 731 #define RTC_MODE2_INTENSET_PER2_Pos 2 /**< \brief (RTC_MODE2_INTENSET) Periodic Interval 2 Enable */ 732 #define RTC_MODE2_INTENSET_PER2 (1 << RTC_MODE2_INTENSET_PER2_Pos) 733 #define RTC_MODE2_INTENSET_PER3_Pos 3 /**< \brief (RTC_MODE2_INTENSET) Periodic Interval 3 Enable */ 734 #define RTC_MODE2_INTENSET_PER3 (1 << RTC_MODE2_INTENSET_PER3_Pos) 735 #define RTC_MODE2_INTENSET_PER4_Pos 4 /**< \brief (RTC_MODE2_INTENSET) Periodic Interval 4 Enable */ 736 #define RTC_MODE2_INTENSET_PER4 (1 << RTC_MODE2_INTENSET_PER4_Pos) 737 #define RTC_MODE2_INTENSET_PER5_Pos 5 /**< \brief (RTC_MODE2_INTENSET) Periodic Interval 5 Enable */ 738 #define RTC_MODE2_INTENSET_PER5 (1 << RTC_MODE2_INTENSET_PER5_Pos) 739 #define RTC_MODE2_INTENSET_PER6_Pos 6 /**< \brief (RTC_MODE2_INTENSET) Periodic Interval 6 Enable */ 740 #define RTC_MODE2_INTENSET_PER6 (1 << RTC_MODE2_INTENSET_PER6_Pos) 741 #define RTC_MODE2_INTENSET_PER7_Pos 7 /**< \brief (RTC_MODE2_INTENSET) Periodic Interval 7 Enable */ 742 #define RTC_MODE2_INTENSET_PER7 (1 << RTC_MODE2_INTENSET_PER7_Pos) 743 #define RTC_MODE2_INTENSET_PER_Pos 0 /**< \brief (RTC_MODE2_INTENSET) Periodic Interval x Enable */ 744 #define RTC_MODE2_INTENSET_PER_Msk (_U(0xFF) << RTC_MODE2_INTENSET_PER_Pos) 745 #define RTC_MODE2_INTENSET_PER(value) (RTC_MODE2_INTENSET_PER_Msk & ((value) << RTC_MODE2_INTENSET_PER_Pos)) 746 #define RTC_MODE2_INTENSET_ALARM0_Pos 8 /**< \brief (RTC_MODE2_INTENSET) Alarm 0 Interrupt Enable */ 747 #define RTC_MODE2_INTENSET_ALARM0 (1 << RTC_MODE2_INTENSET_ALARM0_Pos) 748 #define RTC_MODE2_INTENSET_ALARM_Pos 8 /**< \brief (RTC_MODE2_INTENSET) Alarm x Interrupt Enable */ 749 #define RTC_MODE2_INTENSET_ALARM_Msk (_U(0x1) << RTC_MODE2_INTENSET_ALARM_Pos) 750 #define RTC_MODE2_INTENSET_ALARM(value) (RTC_MODE2_INTENSET_ALARM_Msk & ((value) << RTC_MODE2_INTENSET_ALARM_Pos)) 751 #define RTC_MODE2_INTENSET_OVF_Pos 15 /**< \brief (RTC_MODE2_INTENSET) Overflow Interrupt Enable */ 752 #define RTC_MODE2_INTENSET_OVF (_U(0x1) << RTC_MODE2_INTENSET_OVF_Pos) 753 #define RTC_MODE2_INTENSET_MASK _U(0x81FF) /**< \brief (RTC_MODE2_INTENSET) MASK Register */ 754 755 /* -------- RTC_MODE0_INTFLAG : (RTC Offset: 0x0C) (R/W 16) MODE0 MODE0 Interrupt Flag Status and Clear -------- */ 756 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 757 typedef union { // __I to avoid read-modify-write on write-to-clear register 758 struct { 759 __I uint16_t PER0:1; /*!< bit: 0 Periodic Interval 0 */ 760 __I uint16_t PER1:1; /*!< bit: 1 Periodic Interval 1 */ 761 __I uint16_t PER2:1; /*!< bit: 2 Periodic Interval 2 */ 762 __I uint16_t PER3:1; /*!< bit: 3 Periodic Interval 3 */ 763 __I uint16_t PER4:1; /*!< bit: 4 Periodic Interval 4 */ 764 __I uint16_t PER5:1; /*!< bit: 5 Periodic Interval 5 */ 765 __I uint16_t PER6:1; /*!< bit: 6 Periodic Interval 6 */ 766 __I uint16_t PER7:1; /*!< bit: 7 Periodic Interval 7 */ 767 __I uint16_t CMP0:1; /*!< bit: 8 Compare 0 */ 768 __I uint16_t :6; /*!< bit: 9..14 Reserved */ 769 __I uint16_t OVF:1; /*!< bit: 15 Overflow */ 770 } bit; /*!< Structure used for bit access */ 771 struct { 772 __I uint16_t PER:8; /*!< bit: 0.. 7 Periodic Interval x */ 773 __I uint16_t CMP:1; /*!< bit: 8 Compare x */ 774 __I uint16_t :7; /*!< bit: 9..15 Reserved */ 775 } vec; /*!< Structure used for vec access */ 776 uint16_t reg; /*!< Type used for register access */ 777 } RTC_MODE0_INTFLAG_Type; 778 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 779 780 #define RTC_MODE0_INTFLAG_OFFSET 0x0C /**< \brief (RTC_MODE0_INTFLAG offset) MODE0 Interrupt Flag Status and Clear */ 781 #define RTC_MODE0_INTFLAG_RESETVALUE _U(0x0000) /**< \brief (RTC_MODE0_INTFLAG reset_value) MODE0 Interrupt Flag Status and Clear */ 782 783 #define RTC_MODE0_INTFLAG_PER0_Pos 0 /**< \brief (RTC_MODE0_INTFLAG) Periodic Interval 0 */ 784 #define RTC_MODE0_INTFLAG_PER0 (1 << RTC_MODE0_INTFLAG_PER0_Pos) 785 #define RTC_MODE0_INTFLAG_PER1_Pos 1 /**< \brief (RTC_MODE0_INTFLAG) Periodic Interval 1 */ 786 #define RTC_MODE0_INTFLAG_PER1 (1 << RTC_MODE0_INTFLAG_PER1_Pos) 787 #define RTC_MODE0_INTFLAG_PER2_Pos 2 /**< \brief (RTC_MODE0_INTFLAG) Periodic Interval 2 */ 788 #define RTC_MODE0_INTFLAG_PER2 (1 << RTC_MODE0_INTFLAG_PER2_Pos) 789 #define RTC_MODE0_INTFLAG_PER3_Pos 3 /**< \brief (RTC_MODE0_INTFLAG) Periodic Interval 3 */ 790 #define RTC_MODE0_INTFLAG_PER3 (1 << RTC_MODE0_INTFLAG_PER3_Pos) 791 #define RTC_MODE0_INTFLAG_PER4_Pos 4 /**< \brief (RTC_MODE0_INTFLAG) Periodic Interval 4 */ 792 #define RTC_MODE0_INTFLAG_PER4 (1 << RTC_MODE0_INTFLAG_PER4_Pos) 793 #define RTC_MODE0_INTFLAG_PER5_Pos 5 /**< \brief (RTC_MODE0_INTFLAG) Periodic Interval 5 */ 794 #define RTC_MODE0_INTFLAG_PER5 (1 << RTC_MODE0_INTFLAG_PER5_Pos) 795 #define RTC_MODE0_INTFLAG_PER6_Pos 6 /**< \brief (RTC_MODE0_INTFLAG) Periodic Interval 6 */ 796 #define RTC_MODE0_INTFLAG_PER6 (1 << RTC_MODE0_INTFLAG_PER6_Pos) 797 #define RTC_MODE0_INTFLAG_PER7_Pos 7 /**< \brief (RTC_MODE0_INTFLAG) Periodic Interval 7 */ 798 #define RTC_MODE0_INTFLAG_PER7 (1 << RTC_MODE0_INTFLAG_PER7_Pos) 799 #define RTC_MODE0_INTFLAG_PER_Pos 0 /**< \brief (RTC_MODE0_INTFLAG) Periodic Interval x */ 800 #define RTC_MODE0_INTFLAG_PER_Msk (_U(0xFF) << RTC_MODE0_INTFLAG_PER_Pos) 801 #define RTC_MODE0_INTFLAG_PER(value) (RTC_MODE0_INTFLAG_PER_Msk & ((value) << RTC_MODE0_INTFLAG_PER_Pos)) 802 #define RTC_MODE0_INTFLAG_CMP0_Pos 8 /**< \brief (RTC_MODE0_INTFLAG) Compare 0 */ 803 #define RTC_MODE0_INTFLAG_CMP0 (1 << RTC_MODE0_INTFLAG_CMP0_Pos) 804 #define RTC_MODE0_INTFLAG_CMP_Pos 8 /**< \brief (RTC_MODE0_INTFLAG) Compare x */ 805 #define RTC_MODE0_INTFLAG_CMP_Msk (_U(0x1) << RTC_MODE0_INTFLAG_CMP_Pos) 806 #define RTC_MODE0_INTFLAG_CMP(value) (RTC_MODE0_INTFLAG_CMP_Msk & ((value) << RTC_MODE0_INTFLAG_CMP_Pos)) 807 #define RTC_MODE0_INTFLAG_OVF_Pos 15 /**< \brief (RTC_MODE0_INTFLAG) Overflow */ 808 #define RTC_MODE0_INTFLAG_OVF (_U(0x1) << RTC_MODE0_INTFLAG_OVF_Pos) 809 #define RTC_MODE0_INTFLAG_MASK _U(0x81FF) /**< \brief (RTC_MODE0_INTFLAG) MASK Register */ 810 811 /* -------- RTC_MODE1_INTFLAG : (RTC Offset: 0x0C) (R/W 16) MODE1 MODE1 Interrupt Flag Status and Clear -------- */ 812 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 813 typedef union { // __I to avoid read-modify-write on write-to-clear register 814 struct { 815 __I uint16_t PER0:1; /*!< bit: 0 Periodic Interval 0 */ 816 __I uint16_t PER1:1; /*!< bit: 1 Periodic Interval 1 */ 817 __I uint16_t PER2:1; /*!< bit: 2 Periodic Interval 2 */ 818 __I uint16_t PER3:1; /*!< bit: 3 Periodic Interval 3 */ 819 __I uint16_t PER4:1; /*!< bit: 4 Periodic Interval 4 */ 820 __I uint16_t PER5:1; /*!< bit: 5 Periodic Interval 5 */ 821 __I uint16_t PER6:1; /*!< bit: 6 Periodic Interval 6 */ 822 __I uint16_t PER7:1; /*!< bit: 7 Periodic Interval 7 */ 823 __I uint16_t CMP0:1; /*!< bit: 8 Compare 0 */ 824 __I uint16_t CMP1:1; /*!< bit: 9 Compare 1 */ 825 __I uint16_t :5; /*!< bit: 10..14 Reserved */ 826 __I uint16_t OVF:1; /*!< bit: 15 Overflow */ 827 } bit; /*!< Structure used for bit access */ 828 struct { 829 __I uint16_t PER:8; /*!< bit: 0.. 7 Periodic Interval x */ 830 __I uint16_t CMP:2; /*!< bit: 8.. 9 Compare x */ 831 __I uint16_t :6; /*!< bit: 10..15 Reserved */ 832 } vec; /*!< Structure used for vec access */ 833 uint16_t reg; /*!< Type used for register access */ 834 } RTC_MODE1_INTFLAG_Type; 835 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 836 837 #define RTC_MODE1_INTFLAG_OFFSET 0x0C /**< \brief (RTC_MODE1_INTFLAG offset) MODE1 Interrupt Flag Status and Clear */ 838 #define RTC_MODE1_INTFLAG_RESETVALUE _U(0x0000) /**< \brief (RTC_MODE1_INTFLAG reset_value) MODE1 Interrupt Flag Status and Clear */ 839 840 #define RTC_MODE1_INTFLAG_PER0_Pos 0 /**< \brief (RTC_MODE1_INTFLAG) Periodic Interval 0 */ 841 #define RTC_MODE1_INTFLAG_PER0 (1 << RTC_MODE1_INTFLAG_PER0_Pos) 842 #define RTC_MODE1_INTFLAG_PER1_Pos 1 /**< \brief (RTC_MODE1_INTFLAG) Periodic Interval 1 */ 843 #define RTC_MODE1_INTFLAG_PER1 (1 << RTC_MODE1_INTFLAG_PER1_Pos) 844 #define RTC_MODE1_INTFLAG_PER2_Pos 2 /**< \brief (RTC_MODE1_INTFLAG) Periodic Interval 2 */ 845 #define RTC_MODE1_INTFLAG_PER2 (1 << RTC_MODE1_INTFLAG_PER2_Pos) 846 #define RTC_MODE1_INTFLAG_PER3_Pos 3 /**< \brief (RTC_MODE1_INTFLAG) Periodic Interval 3 */ 847 #define RTC_MODE1_INTFLAG_PER3 (1 << RTC_MODE1_INTFLAG_PER3_Pos) 848 #define RTC_MODE1_INTFLAG_PER4_Pos 4 /**< \brief (RTC_MODE1_INTFLAG) Periodic Interval 4 */ 849 #define RTC_MODE1_INTFLAG_PER4 (1 << RTC_MODE1_INTFLAG_PER4_Pos) 850 #define RTC_MODE1_INTFLAG_PER5_Pos 5 /**< \brief (RTC_MODE1_INTFLAG) Periodic Interval 5 */ 851 #define RTC_MODE1_INTFLAG_PER5 (1 << RTC_MODE1_INTFLAG_PER5_Pos) 852 #define RTC_MODE1_INTFLAG_PER6_Pos 6 /**< \brief (RTC_MODE1_INTFLAG) Periodic Interval 6 */ 853 #define RTC_MODE1_INTFLAG_PER6 (1 << RTC_MODE1_INTFLAG_PER6_Pos) 854 #define RTC_MODE1_INTFLAG_PER7_Pos 7 /**< \brief (RTC_MODE1_INTFLAG) Periodic Interval 7 */ 855 #define RTC_MODE1_INTFLAG_PER7 (1 << RTC_MODE1_INTFLAG_PER7_Pos) 856 #define RTC_MODE1_INTFLAG_PER_Pos 0 /**< \brief (RTC_MODE1_INTFLAG) Periodic Interval x */ 857 #define RTC_MODE1_INTFLAG_PER_Msk (_U(0xFF) << RTC_MODE1_INTFLAG_PER_Pos) 858 #define RTC_MODE1_INTFLAG_PER(value) (RTC_MODE1_INTFLAG_PER_Msk & ((value) << RTC_MODE1_INTFLAG_PER_Pos)) 859 #define RTC_MODE1_INTFLAG_CMP0_Pos 8 /**< \brief (RTC_MODE1_INTFLAG) Compare 0 */ 860 #define RTC_MODE1_INTFLAG_CMP0 (1 << RTC_MODE1_INTFLAG_CMP0_Pos) 861 #define RTC_MODE1_INTFLAG_CMP1_Pos 9 /**< \brief (RTC_MODE1_INTFLAG) Compare 1 */ 862 #define RTC_MODE1_INTFLAG_CMP1 (1 << RTC_MODE1_INTFLAG_CMP1_Pos) 863 #define RTC_MODE1_INTFLAG_CMP_Pos 8 /**< \brief (RTC_MODE1_INTFLAG) Compare x */ 864 #define RTC_MODE1_INTFLAG_CMP_Msk (_U(0x3) << RTC_MODE1_INTFLAG_CMP_Pos) 865 #define RTC_MODE1_INTFLAG_CMP(value) (RTC_MODE1_INTFLAG_CMP_Msk & ((value) << RTC_MODE1_INTFLAG_CMP_Pos)) 866 #define RTC_MODE1_INTFLAG_OVF_Pos 15 /**< \brief (RTC_MODE1_INTFLAG) Overflow */ 867 #define RTC_MODE1_INTFLAG_OVF (_U(0x1) << RTC_MODE1_INTFLAG_OVF_Pos) 868 #define RTC_MODE1_INTFLAG_MASK _U(0x83FF) /**< \brief (RTC_MODE1_INTFLAG) MASK Register */ 869 870 /* -------- RTC_MODE2_INTFLAG : (RTC Offset: 0x0C) (R/W 16) MODE2 MODE2 Interrupt Flag Status and Clear -------- */ 871 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 872 typedef union { // __I to avoid read-modify-write on write-to-clear register 873 struct { 874 __I uint16_t PER0:1; /*!< bit: 0 Periodic Interval 0 */ 875 __I uint16_t PER1:1; /*!< bit: 1 Periodic Interval 1 */ 876 __I uint16_t PER2:1; /*!< bit: 2 Periodic Interval 2 */ 877 __I uint16_t PER3:1; /*!< bit: 3 Periodic Interval 3 */ 878 __I uint16_t PER4:1; /*!< bit: 4 Periodic Interval 4 */ 879 __I uint16_t PER5:1; /*!< bit: 5 Periodic Interval 5 */ 880 __I uint16_t PER6:1; /*!< bit: 6 Periodic Interval 6 */ 881 __I uint16_t PER7:1; /*!< bit: 7 Periodic Interval 7 */ 882 __I uint16_t ALARM0:1; /*!< bit: 8 Alarm 0 */ 883 __I uint16_t :6; /*!< bit: 9..14 Reserved */ 884 __I uint16_t OVF:1; /*!< bit: 15 Overflow */ 885 } bit; /*!< Structure used for bit access */ 886 struct { 887 __I uint16_t PER:8; /*!< bit: 0.. 7 Periodic Interval x */ 888 __I uint16_t ALARM:1; /*!< bit: 8 Alarm x */ 889 __I uint16_t :7; /*!< bit: 9..15 Reserved */ 890 } vec; /*!< Structure used for vec access */ 891 uint16_t reg; /*!< Type used for register access */ 892 } RTC_MODE2_INTFLAG_Type; 893 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 894 895 #define RTC_MODE2_INTFLAG_OFFSET 0x0C /**< \brief (RTC_MODE2_INTFLAG offset) MODE2 Interrupt Flag Status and Clear */ 896 #define RTC_MODE2_INTFLAG_RESETVALUE _U(0x0000) /**< \brief (RTC_MODE2_INTFLAG reset_value) MODE2 Interrupt Flag Status and Clear */ 897 898 #define RTC_MODE2_INTFLAG_PER0_Pos 0 /**< \brief (RTC_MODE2_INTFLAG) Periodic Interval 0 */ 899 #define RTC_MODE2_INTFLAG_PER0 (1 << RTC_MODE2_INTFLAG_PER0_Pos) 900 #define RTC_MODE2_INTFLAG_PER1_Pos 1 /**< \brief (RTC_MODE2_INTFLAG) Periodic Interval 1 */ 901 #define RTC_MODE2_INTFLAG_PER1 (1 << RTC_MODE2_INTFLAG_PER1_Pos) 902 #define RTC_MODE2_INTFLAG_PER2_Pos 2 /**< \brief (RTC_MODE2_INTFLAG) Periodic Interval 2 */ 903 #define RTC_MODE2_INTFLAG_PER2 (1 << RTC_MODE2_INTFLAG_PER2_Pos) 904 #define RTC_MODE2_INTFLAG_PER3_Pos 3 /**< \brief (RTC_MODE2_INTFLAG) Periodic Interval 3 */ 905 #define RTC_MODE2_INTFLAG_PER3 (1 << RTC_MODE2_INTFLAG_PER3_Pos) 906 #define RTC_MODE2_INTFLAG_PER4_Pos 4 /**< \brief (RTC_MODE2_INTFLAG) Periodic Interval 4 */ 907 #define RTC_MODE2_INTFLAG_PER4 (1 << RTC_MODE2_INTFLAG_PER4_Pos) 908 #define RTC_MODE2_INTFLAG_PER5_Pos 5 /**< \brief (RTC_MODE2_INTFLAG) Periodic Interval 5 */ 909 #define RTC_MODE2_INTFLAG_PER5 (1 << RTC_MODE2_INTFLAG_PER5_Pos) 910 #define RTC_MODE2_INTFLAG_PER6_Pos 6 /**< \brief (RTC_MODE2_INTFLAG) Periodic Interval 6 */ 911 #define RTC_MODE2_INTFLAG_PER6 (1 << RTC_MODE2_INTFLAG_PER6_Pos) 912 #define RTC_MODE2_INTFLAG_PER7_Pos 7 /**< \brief (RTC_MODE2_INTFLAG) Periodic Interval 7 */ 913 #define RTC_MODE2_INTFLAG_PER7 (1 << RTC_MODE2_INTFLAG_PER7_Pos) 914 #define RTC_MODE2_INTFLAG_PER_Pos 0 /**< \brief (RTC_MODE2_INTFLAG) Periodic Interval x */ 915 #define RTC_MODE2_INTFLAG_PER_Msk (_U(0xFF) << RTC_MODE2_INTFLAG_PER_Pos) 916 #define RTC_MODE2_INTFLAG_PER(value) (RTC_MODE2_INTFLAG_PER_Msk & ((value) << RTC_MODE2_INTFLAG_PER_Pos)) 917 #define RTC_MODE2_INTFLAG_ALARM0_Pos 8 /**< \brief (RTC_MODE2_INTFLAG) Alarm 0 */ 918 #define RTC_MODE2_INTFLAG_ALARM0 (1 << RTC_MODE2_INTFLAG_ALARM0_Pos) 919 #define RTC_MODE2_INTFLAG_ALARM_Pos 8 /**< \brief (RTC_MODE2_INTFLAG) Alarm x */ 920 #define RTC_MODE2_INTFLAG_ALARM_Msk (_U(0x1) << RTC_MODE2_INTFLAG_ALARM_Pos) 921 #define RTC_MODE2_INTFLAG_ALARM(value) (RTC_MODE2_INTFLAG_ALARM_Msk & ((value) << RTC_MODE2_INTFLAG_ALARM_Pos)) 922 #define RTC_MODE2_INTFLAG_OVF_Pos 15 /**< \brief (RTC_MODE2_INTFLAG) Overflow */ 923 #define RTC_MODE2_INTFLAG_OVF (_U(0x1) << RTC_MODE2_INTFLAG_OVF_Pos) 924 #define RTC_MODE2_INTFLAG_MASK _U(0x81FF) /**< \brief (RTC_MODE2_INTFLAG) MASK Register */ 925 926 /* -------- RTC_DBGCTRL : (RTC Offset: 0x0E) (R/W 8) Debug Control -------- */ 927 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 928 typedef union { 929 struct { 930 uint8_t DBGRUN:1; /*!< bit: 0 Run During Debug */ 931 uint8_t :7; /*!< bit: 1.. 7 Reserved */ 932 } bit; /*!< Structure used for bit access */ 933 uint8_t reg; /*!< Type used for register access */ 934 } RTC_DBGCTRL_Type; 935 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 936 937 #define RTC_DBGCTRL_OFFSET 0x0E /**< \brief (RTC_DBGCTRL offset) Debug Control */ 938 #define RTC_DBGCTRL_RESETVALUE _U(0x00) /**< \brief (RTC_DBGCTRL reset_value) Debug Control */ 939 940 #define RTC_DBGCTRL_DBGRUN_Pos 0 /**< \brief (RTC_DBGCTRL) Run During Debug */ 941 #define RTC_DBGCTRL_DBGRUN (_U(0x1) << RTC_DBGCTRL_DBGRUN_Pos) 942 #define RTC_DBGCTRL_MASK _U(0x01) /**< \brief (RTC_DBGCTRL) MASK Register */ 943 944 /* -------- RTC_MODE0_SYNCBUSY : (RTC Offset: 0x10) (R/ 32) MODE0 MODE0 Synchronization Busy Status -------- */ 945 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 946 typedef union { 947 struct { 948 uint32_t SWRST:1; /*!< bit: 0 Software Reset Busy */ 949 uint32_t ENABLE:1; /*!< bit: 1 Enable Bit Busy */ 950 uint32_t FREQCORR:1; /*!< bit: 2 FREQCORR Register Busy */ 951 uint32_t COUNT:1; /*!< bit: 3 COUNT Register Busy */ 952 uint32_t :1; /*!< bit: 4 Reserved */ 953 uint32_t COMP0:1; /*!< bit: 5 COMP 0 Register Busy */ 954 uint32_t :9; /*!< bit: 6..14 Reserved */ 955 uint32_t COUNTSYNC:1; /*!< bit: 15 Count Read Synchronization Enable Bit Busy */ 956 uint32_t :16; /*!< bit: 16..31 Reserved */ 957 } bit; /*!< Structure used for bit access */ 958 struct { 959 uint32_t :5; /*!< bit: 0.. 4 Reserved */ 960 uint32_t COMP:1; /*!< bit: 5 COMP x Register Busy */ 961 uint32_t :26; /*!< bit: 6..31 Reserved */ 962 } vec; /*!< Structure used for vec access */ 963 uint32_t reg; /*!< Type used for register access */ 964 } RTC_MODE0_SYNCBUSY_Type; 965 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 966 967 #define RTC_MODE0_SYNCBUSY_OFFSET 0x10 /**< \brief (RTC_MODE0_SYNCBUSY offset) MODE0 Synchronization Busy Status */ 968 #define RTC_MODE0_SYNCBUSY_RESETVALUE _U(0x00000000) /**< \brief (RTC_MODE0_SYNCBUSY reset_value) MODE0 Synchronization Busy Status */ 969 970 #define RTC_MODE0_SYNCBUSY_SWRST_Pos 0 /**< \brief (RTC_MODE0_SYNCBUSY) Software Reset Busy */ 971 #define RTC_MODE0_SYNCBUSY_SWRST (_U(0x1) << RTC_MODE0_SYNCBUSY_SWRST_Pos) 972 #define RTC_MODE0_SYNCBUSY_ENABLE_Pos 1 /**< \brief (RTC_MODE0_SYNCBUSY) Enable Bit Busy */ 973 #define RTC_MODE0_SYNCBUSY_ENABLE (_U(0x1) << RTC_MODE0_SYNCBUSY_ENABLE_Pos) 974 #define RTC_MODE0_SYNCBUSY_FREQCORR_Pos 2 /**< \brief (RTC_MODE0_SYNCBUSY) FREQCORR Register Busy */ 975 #define RTC_MODE0_SYNCBUSY_FREQCORR (_U(0x1) << RTC_MODE0_SYNCBUSY_FREQCORR_Pos) 976 #define RTC_MODE0_SYNCBUSY_COUNT_Pos 3 /**< \brief (RTC_MODE0_SYNCBUSY) COUNT Register Busy */ 977 #define RTC_MODE0_SYNCBUSY_COUNT (_U(0x1) << RTC_MODE0_SYNCBUSY_COUNT_Pos) 978 #define RTC_MODE0_SYNCBUSY_COMP0_Pos 5 /**< \brief (RTC_MODE0_SYNCBUSY) COMP 0 Register Busy */ 979 #define RTC_MODE0_SYNCBUSY_COMP0 (1 << RTC_MODE0_SYNCBUSY_COMP0_Pos) 980 #define RTC_MODE0_SYNCBUSY_COMP_Pos 5 /**< \brief (RTC_MODE0_SYNCBUSY) COMP x Register Busy */ 981 #define RTC_MODE0_SYNCBUSY_COMP_Msk (_U(0x1) << RTC_MODE0_SYNCBUSY_COMP_Pos) 982 #define RTC_MODE0_SYNCBUSY_COMP(value) (RTC_MODE0_SYNCBUSY_COMP_Msk & ((value) << RTC_MODE0_SYNCBUSY_COMP_Pos)) 983 #define RTC_MODE0_SYNCBUSY_COUNTSYNC_Pos 15 /**< \brief (RTC_MODE0_SYNCBUSY) Count Read Synchronization Enable Bit Busy */ 984 #define RTC_MODE0_SYNCBUSY_COUNTSYNC (_U(0x1) << RTC_MODE0_SYNCBUSY_COUNTSYNC_Pos) 985 #define RTC_MODE0_SYNCBUSY_MASK _U(0x0000802F) /**< \brief (RTC_MODE0_SYNCBUSY) MASK Register */ 986 987 /* -------- RTC_MODE1_SYNCBUSY : (RTC Offset: 0x10) (R/ 32) MODE1 MODE1 Synchronization Busy Status -------- */ 988 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 989 typedef union { 990 struct { 991 uint32_t SWRST:1; /*!< bit: 0 Software Reset Bit Busy */ 992 uint32_t ENABLE:1; /*!< bit: 1 Enable Bit Busy */ 993 uint32_t FREQCORR:1; /*!< bit: 2 FREQCORR Register Busy */ 994 uint32_t COUNT:1; /*!< bit: 3 COUNT Register Busy */ 995 uint32_t PER:1; /*!< bit: 4 PER Register Busy */ 996 uint32_t COMP0:1; /*!< bit: 5 COMP 0 Register Busy */ 997 uint32_t COMP1:1; /*!< bit: 6 COMP 1 Register Busy */ 998 uint32_t :8; /*!< bit: 7..14 Reserved */ 999 uint32_t COUNTSYNC:1; /*!< bit: 15 Count Read Synchronization Enable Bit Busy */ 1000 uint32_t :16; /*!< bit: 16..31 Reserved */ 1001 } bit; /*!< Structure used for bit access */ 1002 struct { 1003 uint32_t :5; /*!< bit: 0.. 4 Reserved */ 1004 uint32_t COMP:2; /*!< bit: 5.. 6 COMP x Register Busy */ 1005 uint32_t :25; /*!< bit: 7..31 Reserved */ 1006 } vec; /*!< Structure used for vec access */ 1007 uint32_t reg; /*!< Type used for register access */ 1008 } RTC_MODE1_SYNCBUSY_Type; 1009 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 1010 1011 #define RTC_MODE1_SYNCBUSY_OFFSET 0x10 /**< \brief (RTC_MODE1_SYNCBUSY offset) MODE1 Synchronization Busy Status */ 1012 #define RTC_MODE1_SYNCBUSY_RESETVALUE _U(0x00000000) /**< \brief (RTC_MODE1_SYNCBUSY reset_value) MODE1 Synchronization Busy Status */ 1013 1014 #define RTC_MODE1_SYNCBUSY_SWRST_Pos 0 /**< \brief (RTC_MODE1_SYNCBUSY) Software Reset Bit Busy */ 1015 #define RTC_MODE1_SYNCBUSY_SWRST (_U(0x1) << RTC_MODE1_SYNCBUSY_SWRST_Pos) 1016 #define RTC_MODE1_SYNCBUSY_ENABLE_Pos 1 /**< \brief (RTC_MODE1_SYNCBUSY) Enable Bit Busy */ 1017 #define RTC_MODE1_SYNCBUSY_ENABLE (_U(0x1) << RTC_MODE1_SYNCBUSY_ENABLE_Pos) 1018 #define RTC_MODE1_SYNCBUSY_FREQCORR_Pos 2 /**< \brief (RTC_MODE1_SYNCBUSY) FREQCORR Register Busy */ 1019 #define RTC_MODE1_SYNCBUSY_FREQCORR (_U(0x1) << RTC_MODE1_SYNCBUSY_FREQCORR_Pos) 1020 #define RTC_MODE1_SYNCBUSY_COUNT_Pos 3 /**< \brief (RTC_MODE1_SYNCBUSY) COUNT Register Busy */ 1021 #define RTC_MODE1_SYNCBUSY_COUNT (_U(0x1) << RTC_MODE1_SYNCBUSY_COUNT_Pos) 1022 #define RTC_MODE1_SYNCBUSY_PER_Pos 4 /**< \brief (RTC_MODE1_SYNCBUSY) PER Register Busy */ 1023 #define RTC_MODE1_SYNCBUSY_PER (_U(0x1) << RTC_MODE1_SYNCBUSY_PER_Pos) 1024 #define RTC_MODE1_SYNCBUSY_COMP0_Pos 5 /**< \brief (RTC_MODE1_SYNCBUSY) COMP 0 Register Busy */ 1025 #define RTC_MODE1_SYNCBUSY_COMP0 (1 << RTC_MODE1_SYNCBUSY_COMP0_Pos) 1026 #define RTC_MODE1_SYNCBUSY_COMP1_Pos 6 /**< \brief (RTC_MODE1_SYNCBUSY) COMP 1 Register Busy */ 1027 #define RTC_MODE1_SYNCBUSY_COMP1 (1 << RTC_MODE1_SYNCBUSY_COMP1_Pos) 1028 #define RTC_MODE1_SYNCBUSY_COMP_Pos 5 /**< \brief (RTC_MODE1_SYNCBUSY) COMP x Register Busy */ 1029 #define RTC_MODE1_SYNCBUSY_COMP_Msk (_U(0x3) << RTC_MODE1_SYNCBUSY_COMP_Pos) 1030 #define RTC_MODE1_SYNCBUSY_COMP(value) (RTC_MODE1_SYNCBUSY_COMP_Msk & ((value) << RTC_MODE1_SYNCBUSY_COMP_Pos)) 1031 #define RTC_MODE1_SYNCBUSY_COUNTSYNC_Pos 15 /**< \brief (RTC_MODE1_SYNCBUSY) Count Read Synchronization Enable Bit Busy */ 1032 #define RTC_MODE1_SYNCBUSY_COUNTSYNC (_U(0x1) << RTC_MODE1_SYNCBUSY_COUNTSYNC_Pos) 1033 #define RTC_MODE1_SYNCBUSY_MASK _U(0x0000807F) /**< \brief (RTC_MODE1_SYNCBUSY) MASK Register */ 1034 1035 /* -------- RTC_MODE2_SYNCBUSY : (RTC Offset: 0x10) (R/ 32) MODE2 MODE2 Synchronization Busy Status -------- */ 1036 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 1037 typedef union { 1038 struct { 1039 uint32_t SWRST:1; /*!< bit: 0 Software Reset Bit Busy */ 1040 uint32_t ENABLE:1; /*!< bit: 1 Enable Bit Busy */ 1041 uint32_t FREQCORR:1; /*!< bit: 2 FREQCORR Register Busy */ 1042 uint32_t CLOCK:1; /*!< bit: 3 CLOCK Register Busy */ 1043 uint32_t :1; /*!< bit: 4 Reserved */ 1044 uint32_t ALARM0:1; /*!< bit: 5 ALARM 0 Register Busy */ 1045 uint32_t :5; /*!< bit: 6..10 Reserved */ 1046 uint32_t MASK0:1; /*!< bit: 11 MASK 0 Register Busy */ 1047 uint32_t :3; /*!< bit: 12..14 Reserved */ 1048 uint32_t CLOCKSYNC:1; /*!< bit: 15 Clock Read Synchronization Enable Bit Busy */ 1049 uint32_t :16; /*!< bit: 16..31 Reserved */ 1050 } bit; /*!< Structure used for bit access */ 1051 struct { 1052 uint32_t :5; /*!< bit: 0.. 4 Reserved */ 1053 uint32_t ALARM:1; /*!< bit: 5 ALARM x Register Busy */ 1054 uint32_t :5; /*!< bit: 6..10 Reserved */ 1055 uint32_t MASK:1; /*!< bit: 11 MASK x Register Busy */ 1056 uint32_t :20; /*!< bit: 12..31 Reserved */ 1057 } vec; /*!< Structure used for vec access */ 1058 uint32_t reg; /*!< Type used for register access */ 1059 } RTC_MODE2_SYNCBUSY_Type; 1060 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 1061 1062 #define RTC_MODE2_SYNCBUSY_OFFSET 0x10 /**< \brief (RTC_MODE2_SYNCBUSY offset) MODE2 Synchronization Busy Status */ 1063 #define RTC_MODE2_SYNCBUSY_RESETVALUE _U(0x00000000) /**< \brief (RTC_MODE2_SYNCBUSY reset_value) MODE2 Synchronization Busy Status */ 1064 1065 #define RTC_MODE2_SYNCBUSY_SWRST_Pos 0 /**< \brief (RTC_MODE2_SYNCBUSY) Software Reset Bit Busy */ 1066 #define RTC_MODE2_SYNCBUSY_SWRST (_U(0x1) << RTC_MODE2_SYNCBUSY_SWRST_Pos) 1067 #define RTC_MODE2_SYNCBUSY_ENABLE_Pos 1 /**< \brief (RTC_MODE2_SYNCBUSY) Enable Bit Busy */ 1068 #define RTC_MODE2_SYNCBUSY_ENABLE (_U(0x1) << RTC_MODE2_SYNCBUSY_ENABLE_Pos) 1069 #define RTC_MODE2_SYNCBUSY_FREQCORR_Pos 2 /**< \brief (RTC_MODE2_SYNCBUSY) FREQCORR Register Busy */ 1070 #define RTC_MODE2_SYNCBUSY_FREQCORR (_U(0x1) << RTC_MODE2_SYNCBUSY_FREQCORR_Pos) 1071 #define RTC_MODE2_SYNCBUSY_CLOCK_Pos 3 /**< \brief (RTC_MODE2_SYNCBUSY) CLOCK Register Busy */ 1072 #define RTC_MODE2_SYNCBUSY_CLOCK (_U(0x1) << RTC_MODE2_SYNCBUSY_CLOCK_Pos) 1073 #define RTC_MODE2_SYNCBUSY_ALARM0_Pos 5 /**< \brief (RTC_MODE2_SYNCBUSY) ALARM 0 Register Busy */ 1074 #define RTC_MODE2_SYNCBUSY_ALARM0 (1 << RTC_MODE2_SYNCBUSY_ALARM0_Pos) 1075 #define RTC_MODE2_SYNCBUSY_ALARM_Pos 5 /**< \brief (RTC_MODE2_SYNCBUSY) ALARM x Register Busy */ 1076 #define RTC_MODE2_SYNCBUSY_ALARM_Msk (_U(0x1) << RTC_MODE2_SYNCBUSY_ALARM_Pos) 1077 #define RTC_MODE2_SYNCBUSY_ALARM(value) (RTC_MODE2_SYNCBUSY_ALARM_Msk & ((value) << RTC_MODE2_SYNCBUSY_ALARM_Pos)) 1078 #define RTC_MODE2_SYNCBUSY_MASK0_Pos 11 /**< \brief (RTC_MODE2_SYNCBUSY) MASK 0 Register Busy */ 1079 #define RTC_MODE2_SYNCBUSY_MASK0 (1 << RTC_MODE2_SYNCBUSY_MASK0_Pos) 1080 #define RTC_MODE2_SYNCBUSY_MASK_Pos 11 /**< \brief (RTC_MODE2_SYNCBUSY) MASK x Register Busy */ 1081 #define RTC_MODE2_SYNCBUSY_MASK_Msk (_U(0x1) << RTC_MODE2_SYNCBUSY_MASK_Pos) 1082 #define RTC_MODE2_SYNCBUSY_MASK(value) (RTC_MODE2_SYNCBUSY_MASK_Msk & ((value) << RTC_MODE2_SYNCBUSY_MASK_Pos)) 1083 #define RTC_MODE2_SYNCBUSY_CLOCKSYNC_Pos 15 /**< \brief (RTC_MODE2_SYNCBUSY) Clock Read Synchronization Enable Bit Busy */ 1084 #define RTC_MODE2_SYNCBUSY_CLOCKSYNC (_U(0x1) << RTC_MODE2_SYNCBUSY_CLOCKSYNC_Pos) 1085 #define RTC_MODE2_SYNCBUSY_MASK_ _U(0x0000882F) /**< \brief (RTC_MODE2_SYNCBUSY) MASK Register */ 1086 1087 /* -------- RTC_FREQCORR : (RTC Offset: 0x14) (R/W 8) Frequency Correction -------- */ 1088 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 1089 typedef union { 1090 struct { 1091 uint8_t VALUE:7; /*!< bit: 0.. 6 Correction Value */ 1092 uint8_t SIGN:1; /*!< bit: 7 Correction Sign */ 1093 } bit; /*!< Structure used for bit access */ 1094 uint8_t reg; /*!< Type used for register access */ 1095 } RTC_FREQCORR_Type; 1096 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 1097 1098 #define RTC_FREQCORR_OFFSET 0x14 /**< \brief (RTC_FREQCORR offset) Frequency Correction */ 1099 #define RTC_FREQCORR_RESETVALUE _U(0x00) /**< \brief (RTC_FREQCORR reset_value) Frequency Correction */ 1100 1101 #define RTC_FREQCORR_VALUE_Pos 0 /**< \brief (RTC_FREQCORR) Correction Value */ 1102 #define RTC_FREQCORR_VALUE_Msk (_U(0x7F) << RTC_FREQCORR_VALUE_Pos) 1103 #define RTC_FREQCORR_VALUE(value) (RTC_FREQCORR_VALUE_Msk & ((value) << RTC_FREQCORR_VALUE_Pos)) 1104 #define RTC_FREQCORR_SIGN_Pos 7 /**< \brief (RTC_FREQCORR) Correction Sign */ 1105 #define RTC_FREQCORR_SIGN (_U(0x1) << RTC_FREQCORR_SIGN_Pos) 1106 #define RTC_FREQCORR_MASK _U(0xFF) /**< \brief (RTC_FREQCORR) MASK Register */ 1107 1108 /* -------- RTC_MODE0_COUNT : (RTC Offset: 0x18) (R/W 32) MODE0 MODE0 Counter Value -------- */ 1109 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 1110 typedef union { 1111 struct { 1112 uint32_t COUNT:32; /*!< bit: 0..31 Counter Value */ 1113 } bit; /*!< Structure used for bit access */ 1114 uint32_t reg; /*!< Type used for register access */ 1115 } RTC_MODE0_COUNT_Type; 1116 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 1117 1118 #define RTC_MODE0_COUNT_OFFSET 0x18 /**< \brief (RTC_MODE0_COUNT offset) MODE0 Counter Value */ 1119 #define RTC_MODE0_COUNT_RESETVALUE _U(0x00000000) /**< \brief (RTC_MODE0_COUNT reset_value) MODE0 Counter Value */ 1120 1121 #define RTC_MODE0_COUNT_COUNT_Pos 0 /**< \brief (RTC_MODE0_COUNT) Counter Value */ 1122 #define RTC_MODE0_COUNT_COUNT_Msk (_U(0xFFFFFFFF) << RTC_MODE0_COUNT_COUNT_Pos) 1123 #define RTC_MODE0_COUNT_COUNT(value) (RTC_MODE0_COUNT_COUNT_Msk & ((value) << RTC_MODE0_COUNT_COUNT_Pos)) 1124 #define RTC_MODE0_COUNT_MASK _U(0xFFFFFFFF) /**< \brief (RTC_MODE0_COUNT) MASK Register */ 1125 1126 /* -------- RTC_MODE1_COUNT : (RTC Offset: 0x18) (R/W 16) MODE1 MODE1 Counter Value -------- */ 1127 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 1128 typedef union { 1129 struct { 1130 uint16_t COUNT:16; /*!< bit: 0..15 Counter Value */ 1131 } bit; /*!< Structure used for bit access */ 1132 uint16_t reg; /*!< Type used for register access */ 1133 } RTC_MODE1_COUNT_Type; 1134 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 1135 1136 #define RTC_MODE1_COUNT_OFFSET 0x18 /**< \brief (RTC_MODE1_COUNT offset) MODE1 Counter Value */ 1137 #define RTC_MODE1_COUNT_RESETVALUE _U(0x0000) /**< \brief (RTC_MODE1_COUNT reset_value) MODE1 Counter Value */ 1138 1139 #define RTC_MODE1_COUNT_COUNT_Pos 0 /**< \brief (RTC_MODE1_COUNT) Counter Value */ 1140 #define RTC_MODE1_COUNT_COUNT_Msk (_U(0xFFFF) << RTC_MODE1_COUNT_COUNT_Pos) 1141 #define RTC_MODE1_COUNT_COUNT(value) (RTC_MODE1_COUNT_COUNT_Msk & ((value) << RTC_MODE1_COUNT_COUNT_Pos)) 1142 #define RTC_MODE1_COUNT_MASK _U(0xFFFF) /**< \brief (RTC_MODE1_COUNT) MASK Register */ 1143 1144 /* -------- RTC_MODE2_CLOCK : (RTC Offset: 0x18) (R/W 32) MODE2 MODE2 Clock Value -------- */ 1145 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 1146 typedef union { 1147 struct { 1148 uint32_t SECOND:6; /*!< bit: 0.. 5 Second */ 1149 uint32_t MINUTE:6; /*!< bit: 6..11 Minute */ 1150 uint32_t HOUR:5; /*!< bit: 12..16 Hour */ 1151 uint32_t DAY:5; /*!< bit: 17..21 Day */ 1152 uint32_t MONTH:4; /*!< bit: 22..25 Month */ 1153 uint32_t YEAR:6; /*!< bit: 26..31 Year */ 1154 } bit; /*!< Structure used for bit access */ 1155 uint32_t reg; /*!< Type used for register access */ 1156 } RTC_MODE2_CLOCK_Type; 1157 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 1158 1159 #define RTC_MODE2_CLOCK_OFFSET 0x18 /**< \brief (RTC_MODE2_CLOCK offset) MODE2 Clock Value */ 1160 #define RTC_MODE2_CLOCK_RESETVALUE _U(0x00000000) /**< \brief (RTC_MODE2_CLOCK reset_value) MODE2 Clock Value */ 1161 1162 #define RTC_MODE2_CLOCK_SECOND_Pos 0 /**< \brief (RTC_MODE2_CLOCK) Second */ 1163 #define RTC_MODE2_CLOCK_SECOND_Msk (_U(0x3F) << RTC_MODE2_CLOCK_SECOND_Pos) 1164 #define RTC_MODE2_CLOCK_SECOND(value) (RTC_MODE2_CLOCK_SECOND_Msk & ((value) << RTC_MODE2_CLOCK_SECOND_Pos)) 1165 #define RTC_MODE2_CLOCK_MINUTE_Pos 6 /**< \brief (RTC_MODE2_CLOCK) Minute */ 1166 #define RTC_MODE2_CLOCK_MINUTE_Msk (_U(0x3F) << RTC_MODE2_CLOCK_MINUTE_Pos) 1167 #define RTC_MODE2_CLOCK_MINUTE(value) (RTC_MODE2_CLOCK_MINUTE_Msk & ((value) << RTC_MODE2_CLOCK_MINUTE_Pos)) 1168 #define RTC_MODE2_CLOCK_HOUR_Pos 12 /**< \brief (RTC_MODE2_CLOCK) Hour */ 1169 #define RTC_MODE2_CLOCK_HOUR_Msk (_U(0x1F) << RTC_MODE2_CLOCK_HOUR_Pos) 1170 #define RTC_MODE2_CLOCK_HOUR(value) (RTC_MODE2_CLOCK_HOUR_Msk & ((value) << RTC_MODE2_CLOCK_HOUR_Pos)) 1171 #define RTC_MODE2_CLOCK_HOUR_AM_Val _U(0x0) /**< \brief (RTC_MODE2_CLOCK) AM when CLKREP in 12-hour */ 1172 #define RTC_MODE2_CLOCK_HOUR_PM_Val _U(0x10) /**< \brief (RTC_MODE2_CLOCK) PM when CLKREP in 12-hour */ 1173 #define RTC_MODE2_CLOCK_HOUR_AM (RTC_MODE2_CLOCK_HOUR_AM_Val << RTC_MODE2_CLOCK_HOUR_Pos) 1174 #define RTC_MODE2_CLOCK_HOUR_PM (RTC_MODE2_CLOCK_HOUR_PM_Val << RTC_MODE2_CLOCK_HOUR_Pos) 1175 #define RTC_MODE2_CLOCK_DAY_Pos 17 /**< \brief (RTC_MODE2_CLOCK) Day */ 1176 #define RTC_MODE2_CLOCK_DAY_Msk (_U(0x1F) << RTC_MODE2_CLOCK_DAY_Pos) 1177 #define RTC_MODE2_CLOCK_DAY(value) (RTC_MODE2_CLOCK_DAY_Msk & ((value) << RTC_MODE2_CLOCK_DAY_Pos)) 1178 #define RTC_MODE2_CLOCK_MONTH_Pos 22 /**< \brief (RTC_MODE2_CLOCK) Month */ 1179 #define RTC_MODE2_CLOCK_MONTH_Msk (_U(0xF) << RTC_MODE2_CLOCK_MONTH_Pos) 1180 #define RTC_MODE2_CLOCK_MONTH(value) (RTC_MODE2_CLOCK_MONTH_Msk & ((value) << RTC_MODE2_CLOCK_MONTH_Pos)) 1181 #define RTC_MODE2_CLOCK_YEAR_Pos 26 /**< \brief (RTC_MODE2_CLOCK) Year */ 1182 #define RTC_MODE2_CLOCK_YEAR_Msk (_U(0x3F) << RTC_MODE2_CLOCK_YEAR_Pos) 1183 #define RTC_MODE2_CLOCK_YEAR(value) (RTC_MODE2_CLOCK_YEAR_Msk & ((value) << RTC_MODE2_CLOCK_YEAR_Pos)) 1184 #define RTC_MODE2_CLOCK_MASK _U(0xFFFFFFFF) /**< \brief (RTC_MODE2_CLOCK) MASK Register */ 1185 1186 /* -------- RTC_MODE1_PER : (RTC Offset: 0x1C) (R/W 16) MODE1 MODE1 Counter Period -------- */ 1187 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 1188 typedef union { 1189 struct { 1190 uint16_t PER:16; /*!< bit: 0..15 Counter Period */ 1191 } bit; /*!< Structure used for bit access */ 1192 uint16_t reg; /*!< Type used for register access */ 1193 } RTC_MODE1_PER_Type; 1194 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 1195 1196 #define RTC_MODE1_PER_OFFSET 0x1C /**< \brief (RTC_MODE1_PER offset) MODE1 Counter Period */ 1197 #define RTC_MODE1_PER_RESETVALUE _U(0x0000) /**< \brief (RTC_MODE1_PER reset_value) MODE1 Counter Period */ 1198 1199 #define RTC_MODE1_PER_PER_Pos 0 /**< \brief (RTC_MODE1_PER) Counter Period */ 1200 #define RTC_MODE1_PER_PER_Msk (_U(0xFFFF) << RTC_MODE1_PER_PER_Pos) 1201 #define RTC_MODE1_PER_PER(value) (RTC_MODE1_PER_PER_Msk & ((value) << RTC_MODE1_PER_PER_Pos)) 1202 #define RTC_MODE1_PER_MASK _U(0xFFFF) /**< \brief (RTC_MODE1_PER) MASK Register */ 1203 1204 /* -------- RTC_MODE0_COMP : (RTC Offset: 0x20) (R/W 32) MODE0 MODE0 Compare n Value -------- */ 1205 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 1206 typedef union { 1207 struct { 1208 uint32_t COMP:32; /*!< bit: 0..31 Compare Value */ 1209 } bit; /*!< Structure used for bit access */ 1210 uint32_t reg; /*!< Type used for register access */ 1211 } RTC_MODE0_COMP_Type; 1212 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 1213 1214 #define RTC_MODE0_COMP_OFFSET 0x20 /**< \brief (RTC_MODE0_COMP offset) MODE0 Compare n Value */ 1215 #define RTC_MODE0_COMP_RESETVALUE _U(0x00000000) /**< \brief (RTC_MODE0_COMP reset_value) MODE0 Compare n Value */ 1216 1217 #define RTC_MODE0_COMP_COMP_Pos 0 /**< \brief (RTC_MODE0_COMP) Compare Value */ 1218 #define RTC_MODE0_COMP_COMP_Msk (_U(0xFFFFFFFF) << RTC_MODE0_COMP_COMP_Pos) 1219 #define RTC_MODE0_COMP_COMP(value) (RTC_MODE0_COMP_COMP_Msk & ((value) << RTC_MODE0_COMP_COMP_Pos)) 1220 #define RTC_MODE0_COMP_MASK _U(0xFFFFFFFF) /**< \brief (RTC_MODE0_COMP) MASK Register */ 1221 1222 /* -------- RTC_MODE1_COMP : (RTC Offset: 0x20) (R/W 16) MODE1 MODE1 Compare n Value -------- */ 1223 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 1224 typedef union { 1225 struct { 1226 uint16_t COMP:16; /*!< bit: 0..15 Compare Value */ 1227 } bit; /*!< Structure used for bit access */ 1228 uint16_t reg; /*!< Type used for register access */ 1229 } RTC_MODE1_COMP_Type; 1230 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 1231 1232 #define RTC_MODE1_COMP_OFFSET 0x20 /**< \brief (RTC_MODE1_COMP offset) MODE1 Compare n Value */ 1233 #define RTC_MODE1_COMP_RESETVALUE _U(0x0000) /**< \brief (RTC_MODE1_COMP reset_value) MODE1 Compare n Value */ 1234 1235 #define RTC_MODE1_COMP_COMP_Pos 0 /**< \brief (RTC_MODE1_COMP) Compare Value */ 1236 #define RTC_MODE1_COMP_COMP_Msk (_U(0xFFFF) << RTC_MODE1_COMP_COMP_Pos) 1237 #define RTC_MODE1_COMP_COMP(value) (RTC_MODE1_COMP_COMP_Msk & ((value) << RTC_MODE1_COMP_COMP_Pos)) 1238 #define RTC_MODE1_COMP_MASK _U(0xFFFF) /**< \brief (RTC_MODE1_COMP) MASK Register */ 1239 1240 /* -------- RTC_MODE2_ALARM : (RTC Offset: 0x20) (R/W 32) MODE2 MODE2_ALARM Alarm n Value -------- */ 1241 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 1242 typedef union { 1243 struct { 1244 uint32_t SECOND:6; /*!< bit: 0.. 5 Second */ 1245 uint32_t MINUTE:6; /*!< bit: 6..11 Minute */ 1246 uint32_t HOUR:5; /*!< bit: 12..16 Hour */ 1247 uint32_t DAY:5; /*!< bit: 17..21 Day */ 1248 uint32_t MONTH:4; /*!< bit: 22..25 Month */ 1249 uint32_t YEAR:6; /*!< bit: 26..31 Year */ 1250 } bit; /*!< Structure used for bit access */ 1251 uint32_t reg; /*!< Type used for register access */ 1252 } RTC_MODE2_ALARM_Type; 1253 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 1254 1255 #define RTC_MODE2_ALARM_OFFSET 0x20 /**< \brief (RTC_MODE2_ALARM offset) MODE2_ALARM Alarm n Value */ 1256 #define RTC_MODE2_ALARM_RESETVALUE _U(0x00000000) /**< \brief (RTC_MODE2_ALARM reset_value) MODE2_ALARM Alarm n Value */ 1257 1258 #define RTC_MODE2_ALARM_SECOND_Pos 0 /**< \brief (RTC_MODE2_ALARM) Second */ 1259 #define RTC_MODE2_ALARM_SECOND_Msk (_U(0x3F) << RTC_MODE2_ALARM_SECOND_Pos) 1260 #define RTC_MODE2_ALARM_SECOND(value) (RTC_MODE2_ALARM_SECOND_Msk & ((value) << RTC_MODE2_ALARM_SECOND_Pos)) 1261 #define RTC_MODE2_ALARM_MINUTE_Pos 6 /**< \brief (RTC_MODE2_ALARM) Minute */ 1262 #define RTC_MODE2_ALARM_MINUTE_Msk (_U(0x3F) << RTC_MODE2_ALARM_MINUTE_Pos) 1263 #define RTC_MODE2_ALARM_MINUTE(value) (RTC_MODE2_ALARM_MINUTE_Msk & ((value) << RTC_MODE2_ALARM_MINUTE_Pos)) 1264 #define RTC_MODE2_ALARM_HOUR_Pos 12 /**< \brief (RTC_MODE2_ALARM) Hour */ 1265 #define RTC_MODE2_ALARM_HOUR_Msk (_U(0x1F) << RTC_MODE2_ALARM_HOUR_Pos) 1266 #define RTC_MODE2_ALARM_HOUR(value) (RTC_MODE2_ALARM_HOUR_Msk & ((value) << RTC_MODE2_ALARM_HOUR_Pos)) 1267 #define RTC_MODE2_ALARM_HOUR_AM_Val _U(0x0) /**< \brief (RTC_MODE2_ALARM) Morning hour */ 1268 #define RTC_MODE2_ALARM_HOUR_PM_Val _U(0x10) /**< \brief (RTC_MODE2_ALARM) Afternoon hour */ 1269 #define RTC_MODE2_ALARM_HOUR_AM (RTC_MODE2_ALARM_HOUR_AM_Val << RTC_MODE2_ALARM_HOUR_Pos) 1270 #define RTC_MODE2_ALARM_HOUR_PM (RTC_MODE2_ALARM_HOUR_PM_Val << RTC_MODE2_ALARM_HOUR_Pos) 1271 #define RTC_MODE2_ALARM_DAY_Pos 17 /**< \brief (RTC_MODE2_ALARM) Day */ 1272 #define RTC_MODE2_ALARM_DAY_Msk (_U(0x1F) << RTC_MODE2_ALARM_DAY_Pos) 1273 #define RTC_MODE2_ALARM_DAY(value) (RTC_MODE2_ALARM_DAY_Msk & ((value) << RTC_MODE2_ALARM_DAY_Pos)) 1274 #define RTC_MODE2_ALARM_MONTH_Pos 22 /**< \brief (RTC_MODE2_ALARM) Month */ 1275 #define RTC_MODE2_ALARM_MONTH_Msk (_U(0xF) << RTC_MODE2_ALARM_MONTH_Pos) 1276 #define RTC_MODE2_ALARM_MONTH(value) (RTC_MODE2_ALARM_MONTH_Msk & ((value) << RTC_MODE2_ALARM_MONTH_Pos)) 1277 #define RTC_MODE2_ALARM_YEAR_Pos 26 /**< \brief (RTC_MODE2_ALARM) Year */ 1278 #define RTC_MODE2_ALARM_YEAR_Msk (_U(0x3F) << RTC_MODE2_ALARM_YEAR_Pos) 1279 #define RTC_MODE2_ALARM_YEAR(value) (RTC_MODE2_ALARM_YEAR_Msk & ((value) << RTC_MODE2_ALARM_YEAR_Pos)) 1280 #define RTC_MODE2_ALARM_MASK _U(0xFFFFFFFF) /**< \brief (RTC_MODE2_ALARM) MASK Register */ 1281 1282 /* -------- RTC_MODE2_MASK : (RTC Offset: 0x24) (R/W 8) MODE2 MODE2_ALARM Alarm n Mask -------- */ 1283 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 1284 typedef union { 1285 struct { 1286 uint8_t SEL:3; /*!< bit: 0.. 2 Alarm Mask Selection */ 1287 uint8_t :5; /*!< bit: 3.. 7 Reserved */ 1288 } bit; /*!< Structure used for bit access */ 1289 uint8_t reg; /*!< Type used for register access */ 1290 } RTC_MODE2_MASK_Type; 1291 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 1292 1293 #define RTC_MODE2_MASK_OFFSET 0x24 /**< \brief (RTC_MODE2_MASK offset) MODE2_ALARM Alarm n Mask */ 1294 #define RTC_MODE2_MASK_RESETVALUE _U(0x00) /**< \brief (RTC_MODE2_MASK reset_value) MODE2_ALARM Alarm n Mask */ 1295 1296 #define RTC_MODE2_MASK_SEL_Pos 0 /**< \brief (RTC_MODE2_MASK) Alarm Mask Selection */ 1297 #define RTC_MODE2_MASK_SEL_Msk (_U(0x7) << RTC_MODE2_MASK_SEL_Pos) 1298 #define RTC_MODE2_MASK_SEL(value) (RTC_MODE2_MASK_SEL_Msk & ((value) << RTC_MODE2_MASK_SEL_Pos)) 1299 #define RTC_MODE2_MASK_SEL_OFF_Val _U(0x0) /**< \brief (RTC_MODE2_MASK) Alarm Disabled */ 1300 #define RTC_MODE2_MASK_SEL_SS_Val _U(0x1) /**< \brief (RTC_MODE2_MASK) Match seconds only */ 1301 #define RTC_MODE2_MASK_SEL_MMSS_Val _U(0x2) /**< \brief (RTC_MODE2_MASK) Match seconds and minutes only */ 1302 #define RTC_MODE2_MASK_SEL_HHMMSS_Val _U(0x3) /**< \brief (RTC_MODE2_MASK) Match seconds, minutes, and hours only */ 1303 #define RTC_MODE2_MASK_SEL_DDHHMMSS_Val _U(0x4) /**< \brief (RTC_MODE2_MASK) Match seconds, minutes, hours, and days only */ 1304 #define RTC_MODE2_MASK_SEL_MMDDHHMMSS_Val _U(0x5) /**< \brief (RTC_MODE2_MASK) Match seconds, minutes, hours, days, and months only */ 1305 #define RTC_MODE2_MASK_SEL_YYMMDDHHMMSS_Val _U(0x6) /**< \brief (RTC_MODE2_MASK) Match seconds, minutes, hours, days, months, and years */ 1306 #define RTC_MODE2_MASK_SEL_OFF (RTC_MODE2_MASK_SEL_OFF_Val << RTC_MODE2_MASK_SEL_Pos) 1307 #define RTC_MODE2_MASK_SEL_SS (RTC_MODE2_MASK_SEL_SS_Val << RTC_MODE2_MASK_SEL_Pos) 1308 #define RTC_MODE2_MASK_SEL_MMSS (RTC_MODE2_MASK_SEL_MMSS_Val << RTC_MODE2_MASK_SEL_Pos) 1309 #define RTC_MODE2_MASK_SEL_HHMMSS (RTC_MODE2_MASK_SEL_HHMMSS_Val << RTC_MODE2_MASK_SEL_Pos) 1310 #define RTC_MODE2_MASK_SEL_DDHHMMSS (RTC_MODE2_MASK_SEL_DDHHMMSS_Val << RTC_MODE2_MASK_SEL_Pos) 1311 #define RTC_MODE2_MASK_SEL_MMDDHHMMSS (RTC_MODE2_MASK_SEL_MMDDHHMMSS_Val << RTC_MODE2_MASK_SEL_Pos) 1312 #define RTC_MODE2_MASK_SEL_YYMMDDHHMMSS (RTC_MODE2_MASK_SEL_YYMMDDHHMMSS_Val << RTC_MODE2_MASK_SEL_Pos) 1313 #define RTC_MODE2_MASK_MASK _U(0x07) /**< \brief (RTC_MODE2_MASK) MASK Register */ 1314 1315 /* -------- RTC_GP : (RTC Offset: 0x40) (R/W 32) General Purpose -------- */ 1316 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 1317 typedef union { 1318 uint32_t reg; /*!< Type used for register access */ 1319 } RTC_GP_Type; 1320 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 1321 1322 #define RTC_GP_OFFSET 0x40 /**< \brief (RTC_GP offset) General Purpose */ 1323 #define RTC_GP_RESETVALUE _U(0x00000000) /**< \brief (RTC_GP reset_value) General Purpose */ 1324 #define RTC_GP_MASK _U(0xFFFFFFFF) /**< \brief (RTC_GP) MASK Register */ 1325 1326 /** \brief RtcMode2Alarm hardware registers */ 1327 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 1328 typedef struct { 1329 __IO RTC_MODE2_ALARM_Type ALARM; /**< \brief Offset: 0x00 (R/W 32) MODE2_ALARM Alarm n Value */ 1330 __IO RTC_MODE2_MASK_Type MASK; /**< \brief Offset: 0x04 (R/W 8) MODE2_ALARM Alarm n Mask */ 1331 RoReg8 Reserved1[0x3]; 1332 } RtcMode2Alarm; 1333 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 1334 1335 /** \brief RTC_MODE0 hardware registers */ 1336 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 1337 typedef struct { /* 32-bit Counter with Single 32-bit Compare */ 1338 __IO RTC_MODE0_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 16) MODE0 Control A */ 1339 RoReg8 Reserved1[0x2]; 1340 __IO RTC_MODE0_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x04 (R/W 32) MODE0 Event Control */ 1341 __IO RTC_MODE0_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x08 (R/W 16) MODE0 Interrupt Enable Clear */ 1342 __IO RTC_MODE0_INTENSET_Type INTENSET; /**< \brief Offset: 0x0A (R/W 16) MODE0 Interrupt Enable Set */ 1343 __IO RTC_MODE0_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x0C (R/W 16) MODE0 Interrupt Flag Status and Clear */ 1344 __IO RTC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x0E (R/W 8) Debug Control */ 1345 RoReg8 Reserved2[0x1]; 1346 __I RTC_MODE0_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x10 (R/ 32) MODE0 Synchronization Busy Status */ 1347 __IO RTC_FREQCORR_Type FREQCORR; /**< \brief Offset: 0x14 (R/W 8) Frequency Correction */ 1348 RoReg8 Reserved3[0x3]; 1349 __IO RTC_MODE0_COUNT_Type COUNT; /**< \brief Offset: 0x18 (R/W 32) MODE0 Counter Value */ 1350 RoReg8 Reserved4[0x4]; 1351 __IO RTC_MODE0_COMP_Type COMP[1]; /**< \brief Offset: 0x20 (R/W 32) MODE0 Compare n Value */ 1352 RoReg8 Reserved5[0x1C]; 1353 __IO RTC_GP_Type GP[4]; /**< \brief Offset: 0x40 (R/W 32) General Purpose */ 1354 } RtcMode0; 1355 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 1356 1357 /** \brief RTC_MODE1 hardware registers */ 1358 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 1359 typedef struct { /* 16-bit Counter with Two 16-bit Compares */ 1360 __IO RTC_MODE1_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 16) MODE1 Control A */ 1361 RoReg8 Reserved1[0x2]; 1362 __IO RTC_MODE1_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x04 (R/W 32) MODE1 Event Control */ 1363 __IO RTC_MODE1_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x08 (R/W 16) MODE1 Interrupt Enable Clear */ 1364 __IO RTC_MODE1_INTENSET_Type INTENSET; /**< \brief Offset: 0x0A (R/W 16) MODE1 Interrupt Enable Set */ 1365 __IO RTC_MODE1_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x0C (R/W 16) MODE1 Interrupt Flag Status and Clear */ 1366 __IO RTC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x0E (R/W 8) Debug Control */ 1367 RoReg8 Reserved2[0x1]; 1368 __I RTC_MODE1_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x10 (R/ 32) MODE1 Synchronization Busy Status */ 1369 __IO RTC_FREQCORR_Type FREQCORR; /**< \brief Offset: 0x14 (R/W 8) Frequency Correction */ 1370 RoReg8 Reserved3[0x3]; 1371 __IO RTC_MODE1_COUNT_Type COUNT; /**< \brief Offset: 0x18 (R/W 16) MODE1 Counter Value */ 1372 RoReg8 Reserved4[0x2]; 1373 __IO RTC_MODE1_PER_Type PER; /**< \brief Offset: 0x1C (R/W 16) MODE1 Counter Period */ 1374 RoReg8 Reserved5[0x2]; 1375 __IO RTC_MODE1_COMP_Type COMP[2]; /**< \brief Offset: 0x20 (R/W 16) MODE1 Compare n Value */ 1376 RoReg8 Reserved6[0x1C]; 1377 __IO RTC_GP_Type GP[4]; /**< \brief Offset: 0x40 (R/W 32) General Purpose */ 1378 } RtcMode1; 1379 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 1380 1381 /** \brief RTC_MODE2 hardware registers */ 1382 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 1383 typedef struct { /* Clock/Calendar with Alarm */ 1384 __IO RTC_MODE2_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 16) MODE2 Control A */ 1385 RoReg8 Reserved1[0x2]; 1386 __IO RTC_MODE2_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x04 (R/W 32) MODE2 Event Control */ 1387 __IO RTC_MODE2_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x08 (R/W 16) MODE2 Interrupt Enable Clear */ 1388 __IO RTC_MODE2_INTENSET_Type INTENSET; /**< \brief Offset: 0x0A (R/W 16) MODE2 Interrupt Enable Set */ 1389 __IO RTC_MODE2_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x0C (R/W 16) MODE2 Interrupt Flag Status and Clear */ 1390 __IO RTC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x0E (R/W 8) Debug Control */ 1391 RoReg8 Reserved2[0x1]; 1392 __I RTC_MODE2_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x10 (R/ 32) MODE2 Synchronization Busy Status */ 1393 __IO RTC_FREQCORR_Type FREQCORR; /**< \brief Offset: 0x14 (R/W 8) Frequency Correction */ 1394 RoReg8 Reserved3[0x3]; 1395 __IO RTC_MODE2_CLOCK_Type CLOCK; /**< \brief Offset: 0x18 (R/W 32) MODE2 Clock Value */ 1396 RoReg8 Reserved4[0x4]; 1397 RtcMode2Alarm Mode2Alarm[1]; /**< \brief Offset: 0x20 RtcMode2Alarm groups [ALARM_NUM] */ 1398 RoReg8 Reserved5[0x18]; 1399 __IO RTC_GP_Type GP[4]; /**< \brief Offset: 0x40 (R/W 32) General Purpose */ 1400 } RtcMode2; 1401 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 1402 1403 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 1404 typedef union { 1405 RtcMode0 MODE0; /**< \brief Offset: 0x00 32-bit Counter with Single 32-bit Compare */ 1406 RtcMode1 MODE1; /**< \brief Offset: 0x00 16-bit Counter with Two 16-bit Compares */ 1407 RtcMode2 MODE2; /**< \brief Offset: 0x00 Clock/Calendar with Alarm */ 1408 } Rtc; 1409 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 1410 1411 /*@}*/ 1412 1413 #endif /* _SAML21_RTC_COMPONENT_ */ 1414
