1 /*
2  * SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD
3  *
4  * SPDX-License-Identifier: Apache-2.0
5  */
6 #ifndef _SOC_RTC_CNTL_REG_H_
7 #define _SOC_RTC_CNTL_REG_H_
8 
9 /* The value that needs to be written to RTC_CNTL_WDT_WKEY to write-enable the wdt registers */
10 #define RTC_CNTL_WDT_WKEY_VALUE 0x50D83AA1
11 
12 /* Possible values for RTC_CNTL_WDT_CPU_RESET_LENGTH and RTC_CNTL_WDT_SYS_RESET_LENGTH */
13 #define RTC_WDT_RESET_LENGTH_100_NS    0
14 #define RTC_WDT_RESET_LENGTH_200_NS    1
15 #define RTC_WDT_RESET_LENGTH_300_NS    2
16 #define RTC_WDT_RESET_LENGTH_400_NS    3
17 #define RTC_WDT_RESET_LENGTH_500_NS    4
18 #define RTC_WDT_RESET_LENGTH_800_NS    5
19 #define RTC_WDT_RESET_LENGTH_1600_NS   6
20 #define RTC_WDT_RESET_LENGTH_3200_NS   7
21 
22 #include "soc.h"
23 #define RTC_CNTL_OPTIONS0_REG          (DR_REG_RTCCNTL_BASE + 0x0)
24 /* RTC_CNTL_SW_SYS_RST : WO ;bitpos:[31] ;default: 1'd0 ; */
25 /*description: SW system reset*/
26 #define RTC_CNTL_SW_SYS_RST  (BIT(31))
27 #define RTC_CNTL_SW_SYS_RST_M  (BIT(31))
28 #define RTC_CNTL_SW_SYS_RST_V  0x1
29 #define RTC_CNTL_SW_SYS_RST_S  31
30 /* RTC_CNTL_DG_WRAP_FORCE_NORST : R/W ;bitpos:[30] ;default: 1'd0 ; */
31 /*description: digital core force no reset in deep sleep*/
32 #define RTC_CNTL_DG_WRAP_FORCE_NORST  (BIT(30))
33 #define RTC_CNTL_DG_WRAP_FORCE_NORST_M  (BIT(30))
34 #define RTC_CNTL_DG_WRAP_FORCE_NORST_V  0x1
35 #define RTC_CNTL_DG_WRAP_FORCE_NORST_S  30
36 /* RTC_CNTL_DG_WRAP_FORCE_RST : R/W ;bitpos:[29] ;default: 1'd0 ; */
37 /*description: digital wrap force reset in deep sleep*/
38 #define RTC_CNTL_DG_WRAP_FORCE_RST  (BIT(29))
39 #define RTC_CNTL_DG_WRAP_FORCE_RST_M  (BIT(29))
40 #define RTC_CNTL_DG_WRAP_FORCE_RST_V  0x1
41 #define RTC_CNTL_DG_WRAP_FORCE_RST_S  29
42 /* RTC_CNTL_ANALOG_FORCE_NOISO : R/W ;bitpos:[28] ;default: 1'd1 ; */
43 /*description: */
44 #define RTC_CNTL_ANALOG_FORCE_NOISO  (BIT(28))
45 #define RTC_CNTL_ANALOG_FORCE_NOISO_M  (BIT(28))
46 #define RTC_CNTL_ANALOG_FORCE_NOISO_V  0x1
47 #define RTC_CNTL_ANALOG_FORCE_NOISO_S  28
48 /* RTC_CNTL_PLL_FORCE_NOISO : R/W ;bitpos:[27] ;default: 1'd1 ; */
49 /*description: */
50 #define RTC_CNTL_PLL_FORCE_NOISO  (BIT(27))
51 #define RTC_CNTL_PLL_FORCE_NOISO_M  (BIT(27))
52 #define RTC_CNTL_PLL_FORCE_NOISO_V  0x1
53 #define RTC_CNTL_PLL_FORCE_NOISO_S  27
54 /* RTC_CNTL_XTL_FORCE_NOISO : R/W ;bitpos:[26] ;default: 1'd1 ; */
55 /*description: */
56 #define RTC_CNTL_XTL_FORCE_NOISO  (BIT(26))
57 #define RTC_CNTL_XTL_FORCE_NOISO_M  (BIT(26))
58 #define RTC_CNTL_XTL_FORCE_NOISO_V  0x1
59 #define RTC_CNTL_XTL_FORCE_NOISO_S  26
60 /* RTC_CNTL_ANALOG_FORCE_ISO : R/W ;bitpos:[25] ;default: 1'd0 ; */
61 /*description: */
62 #define RTC_CNTL_ANALOG_FORCE_ISO  (BIT(25))
63 #define RTC_CNTL_ANALOG_FORCE_ISO_M  (BIT(25))
64 #define RTC_CNTL_ANALOG_FORCE_ISO_V  0x1
65 #define RTC_CNTL_ANALOG_FORCE_ISO_S  25
66 /* RTC_CNTL_PLL_FORCE_ISO : R/W ;bitpos:[24] ;default: 1'd0 ; */
67 /*description: */
68 #define RTC_CNTL_PLL_FORCE_ISO  (BIT(24))
69 #define RTC_CNTL_PLL_FORCE_ISO_M  (BIT(24))
70 #define RTC_CNTL_PLL_FORCE_ISO_V  0x1
71 #define RTC_CNTL_PLL_FORCE_ISO_S  24
72 /* RTC_CNTL_XTL_FORCE_ISO : R/W ;bitpos:[23] ;default: 1'd0 ; */
73 /*description: */
74 #define RTC_CNTL_XTL_FORCE_ISO  (BIT(23))
75 #define RTC_CNTL_XTL_FORCE_ISO_M  (BIT(23))
76 #define RTC_CNTL_XTL_FORCE_ISO_V  0x1
77 #define RTC_CNTL_XTL_FORCE_ISO_S  23
78 /* RTC_CNTL_BIAS_CORE_FORCE_PU : R/W ;bitpos:[22] ;default: 1'd1 ; */
79 /*description: BIAS_CORE force power up*/
80 #define RTC_CNTL_BIAS_CORE_FORCE_PU  (BIT(22))
81 #define RTC_CNTL_BIAS_CORE_FORCE_PU_M  (BIT(22))
82 #define RTC_CNTL_BIAS_CORE_FORCE_PU_V  0x1
83 #define RTC_CNTL_BIAS_CORE_FORCE_PU_S  22
84 /* RTC_CNTL_BIAS_CORE_FORCE_PD : R/W ;bitpos:[21] ;default: 1'b0 ; */
85 /*description: BIAS_CORE force power down*/
86 #define RTC_CNTL_BIAS_CORE_FORCE_PD  (BIT(21))
87 #define RTC_CNTL_BIAS_CORE_FORCE_PD_M  (BIT(21))
88 #define RTC_CNTL_BIAS_CORE_FORCE_PD_V  0x1
89 #define RTC_CNTL_BIAS_CORE_FORCE_PD_S  21
90 /* RTC_CNTL_BIAS_CORE_FOLW_8M : R/W ;bitpos:[20] ;default: 1'd0 ; */
91 /*description: BIAS_CORE follow CK8M*/
92 #define RTC_CNTL_BIAS_CORE_FOLW_8M  (BIT(20))
93 #define RTC_CNTL_BIAS_CORE_FOLW_8M_M  (BIT(20))
94 #define RTC_CNTL_BIAS_CORE_FOLW_8M_V  0x1
95 #define RTC_CNTL_BIAS_CORE_FOLW_8M_S  20
96 /* RTC_CNTL_BIAS_I2C_FORCE_PU : R/W ;bitpos:[19] ;default: 1'd1 ; */
97 /*description: BIAS_I2C force power up*/
98 #define RTC_CNTL_BIAS_I2C_FORCE_PU  (BIT(19))
99 #define RTC_CNTL_BIAS_I2C_FORCE_PU_M  (BIT(19))
100 #define RTC_CNTL_BIAS_I2C_FORCE_PU_V  0x1
101 #define RTC_CNTL_BIAS_I2C_FORCE_PU_S  19
102 /* RTC_CNTL_BIAS_I2C_FORCE_PD : R/W ;bitpos:[18] ;default: 1'b0 ; */
103 /*description: BIAS_I2C force power down*/
104 #define RTC_CNTL_BIAS_I2C_FORCE_PD  (BIT(18))
105 #define RTC_CNTL_BIAS_I2C_FORCE_PD_M  (BIT(18))
106 #define RTC_CNTL_BIAS_I2C_FORCE_PD_V  0x1
107 #define RTC_CNTL_BIAS_I2C_FORCE_PD_S  18
108 /* RTC_CNTL_BIAS_I2C_FOLW_8M : R/W ;bitpos:[17] ;default: 1'd0 ; */
109 /*description: BIAS_I2C follow CK8M*/
110 #define RTC_CNTL_BIAS_I2C_FOLW_8M  (BIT(17))
111 #define RTC_CNTL_BIAS_I2C_FOLW_8M_M  (BIT(17))
112 #define RTC_CNTL_BIAS_I2C_FOLW_8M_V  0x1
113 #define RTC_CNTL_BIAS_I2C_FOLW_8M_S  17
114 /* RTC_CNTL_BIAS_FORCE_NOSLEEP : R/W ;bitpos:[16] ;default: 1'd1 ; */
115 /*description: BIAS_SLEEP force no sleep*/
116 #define RTC_CNTL_BIAS_FORCE_NOSLEEP  (BIT(16))
117 #define RTC_CNTL_BIAS_FORCE_NOSLEEP_M  (BIT(16))
118 #define RTC_CNTL_BIAS_FORCE_NOSLEEP_V  0x1
119 #define RTC_CNTL_BIAS_FORCE_NOSLEEP_S  16
120 /* RTC_CNTL_BIAS_FORCE_SLEEP : R/W ;bitpos:[15] ;default: 1'b0 ; */
121 /*description: BIAS_SLEEP force sleep*/
122 #define RTC_CNTL_BIAS_FORCE_SLEEP  (BIT(15))
123 #define RTC_CNTL_BIAS_FORCE_SLEEP_M  (BIT(15))
124 #define RTC_CNTL_BIAS_FORCE_SLEEP_V  0x1
125 #define RTC_CNTL_BIAS_FORCE_SLEEP_S  15
126 /* RTC_CNTL_BIAS_SLEEP_FOLW_8M : R/W ;bitpos:[14] ;default: 1'b0 ; */
127 /*description: BIAS_SLEEP follow CK8M*/
128 #define RTC_CNTL_BIAS_SLEEP_FOLW_8M  (BIT(14))
129 #define RTC_CNTL_BIAS_SLEEP_FOLW_8M_M  (BIT(14))
130 #define RTC_CNTL_BIAS_SLEEP_FOLW_8M_V  0x1
131 #define RTC_CNTL_BIAS_SLEEP_FOLW_8M_S  14
132 /* RTC_CNTL_XTL_FORCE_PU : R/W ;bitpos:[13] ;default: 1'd1 ; */
133 /*description: crystall force power up*/
134 #define RTC_CNTL_XTL_FORCE_PU  (BIT(13))
135 #define RTC_CNTL_XTL_FORCE_PU_M  (BIT(13))
136 #define RTC_CNTL_XTL_FORCE_PU_V  0x1
137 #define RTC_CNTL_XTL_FORCE_PU_S  13
138 /* RTC_CNTL_XTL_FORCE_PD : R/W ;bitpos:[12] ;default: 1'b0 ; */
139 /*description: crystall force power down*/
140 #define RTC_CNTL_XTL_FORCE_PD  (BIT(12))
141 #define RTC_CNTL_XTL_FORCE_PD_M  (BIT(12))
142 #define RTC_CNTL_XTL_FORCE_PD_V  0x1
143 #define RTC_CNTL_XTL_FORCE_PD_S  12
144 /* RTC_CNTL_BBPLL_FORCE_PU : R/W ;bitpos:[11] ;default: 1'd0 ; */
145 /*description: BB_PLL force power up*/
146 #define RTC_CNTL_BBPLL_FORCE_PU  (BIT(11))
147 #define RTC_CNTL_BBPLL_FORCE_PU_M  (BIT(11))
148 #define RTC_CNTL_BBPLL_FORCE_PU_V  0x1
149 #define RTC_CNTL_BBPLL_FORCE_PU_S  11
150 /* RTC_CNTL_BBPLL_FORCE_PD : R/W ;bitpos:[10] ;default: 1'b0 ; */
151 /*description: BB_PLL force power down*/
152 #define RTC_CNTL_BBPLL_FORCE_PD  (BIT(10))
153 #define RTC_CNTL_BBPLL_FORCE_PD_M  (BIT(10))
154 #define RTC_CNTL_BBPLL_FORCE_PD_V  0x1
155 #define RTC_CNTL_BBPLL_FORCE_PD_S  10
156 /* RTC_CNTL_BBPLL_I2C_FORCE_PU : R/W ;bitpos:[9] ;default: 1'd0 ; */
157 /*description: BB_PLL_I2C force power up*/
158 #define RTC_CNTL_BBPLL_I2C_FORCE_PU  (BIT(9))
159 #define RTC_CNTL_BBPLL_I2C_FORCE_PU_M  (BIT(9))
160 #define RTC_CNTL_BBPLL_I2C_FORCE_PU_V  0x1
161 #define RTC_CNTL_BBPLL_I2C_FORCE_PU_S  9
162 /* RTC_CNTL_BBPLL_I2C_FORCE_PD : R/W ;bitpos:[8] ;default: 1'b0 ; */
163 /*description: BB_PLL _I2C force power down*/
164 #define RTC_CNTL_BBPLL_I2C_FORCE_PD  (BIT(8))
165 #define RTC_CNTL_BBPLL_I2C_FORCE_PD_M  (BIT(8))
166 #define RTC_CNTL_BBPLL_I2C_FORCE_PD_V  0x1
167 #define RTC_CNTL_BBPLL_I2C_FORCE_PD_S  8
168 /* RTC_CNTL_BB_I2C_FORCE_PU : R/W ;bitpos:[7] ;default: 1'd0 ; */
169 /*description: BB_I2C force power up*/
170 #define RTC_CNTL_BB_I2C_FORCE_PU  (BIT(7))
171 #define RTC_CNTL_BB_I2C_FORCE_PU_M  (BIT(7))
172 #define RTC_CNTL_BB_I2C_FORCE_PU_V  0x1
173 #define RTC_CNTL_BB_I2C_FORCE_PU_S  7
174 /* RTC_CNTL_BB_I2C_FORCE_PD : R/W ;bitpos:[6] ;default: 1'b0 ; */
175 /*description: BB_I2C force power down*/
176 #define RTC_CNTL_BB_I2C_FORCE_PD  (BIT(6))
177 #define RTC_CNTL_BB_I2C_FORCE_PD_M  (BIT(6))
178 #define RTC_CNTL_BB_I2C_FORCE_PD_V  0x1
179 #define RTC_CNTL_BB_I2C_FORCE_PD_S  6
180 /* RTC_CNTL_SW_PROCPU_RST : WO ;bitpos:[5] ;default: 1'b0 ; */
181 /*description: PRO CPU SW reset*/
182 #define RTC_CNTL_SW_PROCPU_RST  (BIT(5))
183 #define RTC_CNTL_SW_PROCPU_RST_M  (BIT(5))
184 #define RTC_CNTL_SW_PROCPU_RST_V  0x1
185 #define RTC_CNTL_SW_PROCPU_RST_S  5
186 /* RTC_CNTL_SW_APPCPU_RST : WO ;bitpos:[4] ;default: 1'b0 ; */
187 /*description: APP CPU SW reset*/
188 #define RTC_CNTL_SW_APPCPU_RST  (BIT(4))
189 #define RTC_CNTL_SW_APPCPU_RST_M  (BIT(4))
190 #define RTC_CNTL_SW_APPCPU_RST_V  0x1
191 #define RTC_CNTL_SW_APPCPU_RST_S  4
192 /* RTC_CNTL_SW_STALL_PROCPU_C0 : R/W ;bitpos:[3:2] ;default: 2'b0 ; */
193 /*description: {reg_sw_stall_procpu_c1[5:0]   reg_sw_stall_procpu_c0[1:0]} ==
194  0x86 will stall PRO CPU*/
195 #define RTC_CNTL_SW_STALL_PROCPU_C0  0x00000003
196 #define RTC_CNTL_SW_STALL_PROCPU_C0_M  ((RTC_CNTL_SW_STALL_PROCPU_C0_V)<<(RTC_CNTL_SW_STALL_PROCPU_C0_S))
197 #define RTC_CNTL_SW_STALL_PROCPU_C0_V  0x3
198 #define RTC_CNTL_SW_STALL_PROCPU_C0_S  2
199 /* RTC_CNTL_SW_STALL_APPCPU_C0 : R/W ;bitpos:[1:0] ;default: 2'b0 ; */
200 /*description: {reg_sw_stall_appcpu_c1[5:0]   reg_sw_stall_appcpu_c0[1:0]} ==
201  0x86 will stall APP CPU*/
202 #define RTC_CNTL_SW_STALL_APPCPU_C0  0x00000003
203 #define RTC_CNTL_SW_STALL_APPCPU_C0_M  ((RTC_CNTL_SW_STALL_APPCPU_C0_V)<<(RTC_CNTL_SW_STALL_APPCPU_C0_S))
204 #define RTC_CNTL_SW_STALL_APPCPU_C0_V  0x3
205 #define RTC_CNTL_SW_STALL_APPCPU_C0_S  0
206 
207 #define RTC_CNTL_SLP_TIMER0_REG          (DR_REG_RTCCNTL_BASE + 0x4)
208 /* RTC_CNTL_SLP_VAL_LO : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
209 /*description: RTC sleep timer low 32 bits*/
210 #define RTC_CNTL_SLP_VAL_LO  0xFFFFFFFF
211 #define RTC_CNTL_SLP_VAL_LO_M  ((RTC_CNTL_SLP_VAL_LO_V)<<(RTC_CNTL_SLP_VAL_LO_S))
212 #define RTC_CNTL_SLP_VAL_LO_V  0xFFFFFFFF
213 #define RTC_CNTL_SLP_VAL_LO_S  0
214 
215 #define RTC_CNTL_SLP_TIMER1_REG          (DR_REG_RTCCNTL_BASE + 0x8)
216 /* RTC_CNTL_MAIN_TIMER_ALARM_EN : R/W ;bitpos:[16] ;default: 1'h0 ; */
217 /*description: timer alarm enable bit*/
218 #define RTC_CNTL_MAIN_TIMER_ALARM_EN  (BIT(16))
219 #define RTC_CNTL_MAIN_TIMER_ALARM_EN_M  (BIT(16))
220 #define RTC_CNTL_MAIN_TIMER_ALARM_EN_V  0x1
221 #define RTC_CNTL_MAIN_TIMER_ALARM_EN_S  16
222 /* RTC_CNTL_SLP_VAL_HI : R/W ;bitpos:[15:0] ;default: 16'h0 ; */
223 /*description: RTC sleep timer high 16 bits*/
224 #define RTC_CNTL_SLP_VAL_HI  0x0000FFFF
225 #define RTC_CNTL_SLP_VAL_HI_M  ((RTC_CNTL_SLP_VAL_HI_V)<<(RTC_CNTL_SLP_VAL_HI_S))
226 #define RTC_CNTL_SLP_VAL_HI_V  0xFFFF
227 #define RTC_CNTL_SLP_VAL_HI_S  0
228 
229 #define RTC_CNTL_TIME_UPDATE_REG          (DR_REG_RTCCNTL_BASE + 0xc)
230 /* RTC_CNTL_TIME_UPDATE : WO ;bitpos:[31] ;default: 1'h0 ; */
231 /*description: Set 1: to update register with RTC timer*/
232 #define RTC_CNTL_TIME_UPDATE  (BIT(31))
233 #define RTC_CNTL_TIME_UPDATE_M  (BIT(31))
234 #define RTC_CNTL_TIME_UPDATE_V  0x1
235 #define RTC_CNTL_TIME_UPDATE_S  31
236 /* RTC_CNTL_TIME_VALID : RO ;bitpos:[30] ;default: 1'b0 ; */
237 /*description: To indicate the register is updated*/
238 #define RTC_CNTL_TIME_VALID  (BIT(30))
239 #define RTC_CNTL_TIME_VALID_M  (BIT(30))
240 #define RTC_CNTL_TIME_VALID_V  0x1
241 #define RTC_CNTL_TIME_VALID_S  30
242 
243 #define RTC_CNTL_TIME0_REG          (DR_REG_RTCCNTL_BASE + 0x10)
244 /* RTC_CNTL_TIME_LO : RO ;bitpos:[31:0] ;default: 32'h0 ; */
245 /*description: RTC timer low 32 bits*/
246 #define RTC_CNTL_TIME_LO  0xFFFFFFFF
247 #define RTC_CNTL_TIME_LO_M  ((RTC_CNTL_TIME_LO_V)<<(RTC_CNTL_TIME_LO_S))
248 #define RTC_CNTL_TIME_LO_V  0xFFFFFFFF
249 #define RTC_CNTL_TIME_LO_S  0
250 
251 #define RTC_CNTL_TIME1_REG          (DR_REG_RTCCNTL_BASE + 0x14)
252 /* RTC_CNTL_TIME_HI : RO ;bitpos:[15:0] ;default: 16'h0 ; */
253 /*description: RTC timer high 16 bits*/
254 #define RTC_CNTL_TIME_HI  0x0000FFFF
255 #define RTC_CNTL_TIME_HI_M  ((RTC_CNTL_TIME_HI_V)<<(RTC_CNTL_TIME_HI_S))
256 #define RTC_CNTL_TIME_HI_V  0xFFFF
257 #define RTC_CNTL_TIME_HI_S  0
258 
259 #define RTC_CNTL_STATE0_REG          (DR_REG_RTCCNTL_BASE + 0x18)
260 /* RTC_CNTL_SLEEP_EN : R/W ;bitpos:[31] ;default: 1'd0 ; */
261 /*description: sleep enable bit*/
262 #define RTC_CNTL_SLEEP_EN  (BIT(31))
263 #define RTC_CNTL_SLEEP_EN_M  (BIT(31))
264 #define RTC_CNTL_SLEEP_EN_V  0x1
265 #define RTC_CNTL_SLEEP_EN_S  31
266 /* RTC_CNTL_SLP_REJECT : R/W ;bitpos:[30] ;default: 1'd0 ; */
267 /*description: sleep reject bit*/
268 #define RTC_CNTL_SLP_REJECT  (BIT(30))
269 #define RTC_CNTL_SLP_REJECT_M  (BIT(30))
270 #define RTC_CNTL_SLP_REJECT_V  0x1
271 #define RTC_CNTL_SLP_REJECT_S  30
272 /* RTC_CNTL_SLP_WAKEUP : R/W ;bitpos:[29] ;default: 1'd0 ; */
273 /*description: sleep wakeup bit*/
274 #define RTC_CNTL_SLP_WAKEUP  (BIT(29))
275 #define RTC_CNTL_SLP_WAKEUP_M  (BIT(29))
276 #define RTC_CNTL_SLP_WAKEUP_V  0x1
277 #define RTC_CNTL_SLP_WAKEUP_S  29
278 /* RTC_CNTL_SDIO_ACTIVE_IND : RO ;bitpos:[28] ;default: 1'd0 ; */
279 /*description: SDIO active indication*/
280 #define RTC_CNTL_SDIO_ACTIVE_IND  (BIT(28))
281 #define RTC_CNTL_SDIO_ACTIVE_IND_M  (BIT(28))
282 #define RTC_CNTL_SDIO_ACTIVE_IND_V  0x1
283 #define RTC_CNTL_SDIO_ACTIVE_IND_S  28
284 /* RTC_CNTL_ULP_CP_SLP_TIMER_EN : R/W ;bitpos:[24] ;default: 1'd0 ; */
285 /*description: ULP-coprocessor timer enable bit*/
286 #define RTC_CNTL_ULP_CP_SLP_TIMER_EN  (BIT(24))
287 #define RTC_CNTL_ULP_CP_SLP_TIMER_EN_M  (BIT(24))
288 #define RTC_CNTL_ULP_CP_SLP_TIMER_EN_V  0x1
289 #define RTC_CNTL_ULP_CP_SLP_TIMER_EN_S  24
290 /* RTC_CNTL_TOUCH_SLP_TIMER_EN : R/W ;bitpos:[23] ;default: 1'd0 ; */
291 /*description: touch timer enable bit*/
292 #define RTC_CNTL_TOUCH_SLP_TIMER_EN  (BIT(23))
293 #define RTC_CNTL_TOUCH_SLP_TIMER_EN_M  (BIT(23))
294 #define RTC_CNTL_TOUCH_SLP_TIMER_EN_V  0x1
295 #define RTC_CNTL_TOUCH_SLP_TIMER_EN_S  23
296 /* RTC_CNTL_APB2RTC_BRIDGE_SEL : R/W ;bitpos:[22] ;default: 1'd0 ; */
297 /*description: 1: APB to RTC using bridge   0: APB to RTC using sync*/
298 #define RTC_CNTL_APB2RTC_BRIDGE_SEL  (BIT(22))
299 #define RTC_CNTL_APB2RTC_BRIDGE_SEL_M  (BIT(22))
300 #define RTC_CNTL_APB2RTC_BRIDGE_SEL_V  0x1
301 #define RTC_CNTL_APB2RTC_BRIDGE_SEL_S  22
302 /* RTC_CNTL_ULP_CP_WAKEUP_FORCE_EN : R/W ;bitpos:[21] ;default: 1'd1 ; */
303 /*description: ULP-coprocessor force wake up*/
304 #define RTC_CNTL_ULP_CP_WAKEUP_FORCE_EN  (BIT(21))
305 #define RTC_CNTL_ULP_CP_WAKEUP_FORCE_EN_M  (BIT(21))
306 #define RTC_CNTL_ULP_CP_WAKEUP_FORCE_EN_V  0x1
307 #define RTC_CNTL_ULP_CP_WAKEUP_FORCE_EN_S  21
308 /* RTC_CNTL_TOUCH_WAKEUP_FORCE_EN : R/W ;bitpos:[20] ;default: 1'd1 ; */
309 /*description: touch controller force wake up*/
310 #define RTC_CNTL_TOUCH_WAKEUP_FORCE_EN  (BIT(20))
311 #define RTC_CNTL_TOUCH_WAKEUP_FORCE_EN_M  (BIT(20))
312 #define RTC_CNTL_TOUCH_WAKEUP_FORCE_EN_V  0x1
313 #define RTC_CNTL_TOUCH_WAKEUP_FORCE_EN_S  20
314 
315 #define RTC_CNTL_TIMER1_REG          (DR_REG_RTCCNTL_BASE + 0x1c)
316 /* RTC_CNTL_PLL_BUF_WAIT : R/W ;bitpos:[31:24] ;default: 8'd40 ; */
317 /*description: PLL wait cycles in slow_clk_rtc*/
318 #define RTC_CNTL_PLL_BUF_WAIT  0x000000FF
319 #define RTC_CNTL_PLL_BUF_WAIT_M  ((RTC_CNTL_PLL_BUF_WAIT_V)<<(RTC_CNTL_PLL_BUF_WAIT_S))
320 #define RTC_CNTL_PLL_BUF_WAIT_V  0xFF
321 #define RTC_CNTL_PLL_BUF_WAIT_S  24
322 #define RTC_CNTL_PLL_BUF_WAIT_DEFAULT  20
323 /* RTC_CNTL_XTL_BUF_WAIT : R/W ;bitpos:[23:14] ;default: 10'd80 ; */
324 /*description: XTAL wait cycles in slow_clk_rtc*/
325 #define RTC_CNTL_XTL_BUF_WAIT  0x000003FF
326 #define RTC_CNTL_XTL_BUF_WAIT_M  ((RTC_CNTL_XTL_BUF_WAIT_V)<<(RTC_CNTL_XTL_BUF_WAIT_S))
327 #define RTC_CNTL_XTL_BUF_WAIT_V  0x3FF
328 #define RTC_CNTL_XTL_BUF_WAIT_S  14
329 #define RTC_CNTL_XTL_BUF_WAIT_DEFAULT  20
330 /* RTC_CNTL_CK8M_WAIT : R/W ;bitpos:[13:6] ;default: 8'h10 ; */
331 /*description: CK8M wait cycles in slow_clk_rtc*/
332 #define RTC_CNTL_CK8M_WAIT  0x000000FF
333 #define RTC_CNTL_CK8M_WAIT_M  ((RTC_CNTL_CK8M_WAIT_V)<<(RTC_CNTL_CK8M_WAIT_S))
334 #define RTC_CNTL_CK8M_WAIT_V  0xFF
335 #define RTC_CNTL_CK8M_WAIT_S  6
336 /* RTC_CNTL_CPU_STALL_WAIT : R/W ;bitpos:[5:1] ;default: 5'd1 ; */
337 /*description: CPU stall wait cycles in fast_clk_rtc*/
338 #define RTC_CNTL_CPU_STALL_WAIT  0x0000001F
339 #define RTC_CNTL_CPU_STALL_WAIT_M  ((RTC_CNTL_CPU_STALL_WAIT_V)<<(RTC_CNTL_CPU_STALL_WAIT_S))
340 #define RTC_CNTL_CPU_STALL_WAIT_V  0x1F
341 #define RTC_CNTL_CPU_STALL_WAIT_S  1
342 /* RTC_CNTL_CPU_STALL_EN : R/W ;bitpos:[0] ;default: 1'd1 ; */
343 /*description: CPU stall enable bit*/
344 #define RTC_CNTL_CPU_STALL_EN  (BIT(0))
345 #define RTC_CNTL_CPU_STALL_EN_M  (BIT(0))
346 #define RTC_CNTL_CPU_STALL_EN_V  0x1
347 #define RTC_CNTL_CPU_STALL_EN_S  0
348 
349 #define RTC_CNTL_TIMER2_REG          (DR_REG_RTCCNTL_BASE + 0x20)
350 /* RTC_CNTL_MIN_TIME_CK8M_OFF : R/W ;bitpos:[31:24] ;default: 8'h1 ; */
351 /*description: minimal cycles in slow_clk_rtc for CK8M in power down state*/
352 #define RTC_CNTL_MIN_TIME_CK8M_OFF  0x000000FF
353 #define RTC_CNTL_MIN_TIME_CK8M_OFF_M  ((RTC_CNTL_MIN_TIME_CK8M_OFF_V)<<(RTC_CNTL_MIN_TIME_CK8M_OFF_S))
354 #define RTC_CNTL_MIN_TIME_CK8M_OFF_V  0xFF
355 #define RTC_CNTL_MIN_TIME_CK8M_OFF_S  24
356 /* RTC_CNTL_ULPCP_TOUCH_START_WAIT : R/W ;bitpos:[23:15] ;default: 9'h10 ; */
357 /*description: wait cycles in slow_clk_rtc before ULP-coprocessor / touch controller
358  start to work*/
359 #define RTC_CNTL_ULPCP_TOUCH_START_WAIT  0x000001FF
360 #define RTC_CNTL_ULPCP_TOUCH_START_WAIT_M  ((RTC_CNTL_ULPCP_TOUCH_START_WAIT_V)<<(RTC_CNTL_ULPCP_TOUCH_START_WAIT_S))
361 #define RTC_CNTL_ULPCP_TOUCH_START_WAIT_V  0x1FF
362 #define RTC_CNTL_ULPCP_TOUCH_START_WAIT_S  15
363 
364 #define RTC_CNTL_TIMER3_REG          (DR_REG_RTCCNTL_BASE + 0x24)
365 /* RTC_CNTL_ROM_RAM_POWERUP_TIMER : R/W ;bitpos:[31:25] ;default: 7'd10 ; */
366 /*description: */
367 #define RTC_CNTL_ROM_RAM_POWERUP_TIMER  0x0000007F
368 #define RTC_CNTL_ROM_RAM_POWERUP_TIMER_M  ((RTC_CNTL_ROM_RAM_POWERUP_TIMER_V)<<(RTC_CNTL_ROM_RAM_POWERUP_TIMER_S))
369 #define RTC_CNTL_ROM_RAM_POWERUP_TIMER_V  0x7F
370 #define RTC_CNTL_ROM_RAM_POWERUP_TIMER_S  25
371 /* RTC_CNTL_ROM_RAM_WAIT_TIMER : R/W ;bitpos:[24:16] ;default: 9'h16 ; */
372 /*description: */
373 #define RTC_CNTL_ROM_RAM_WAIT_TIMER  0x000001FF
374 #define RTC_CNTL_ROM_RAM_WAIT_TIMER_M  ((RTC_CNTL_ROM_RAM_WAIT_TIMER_V)<<(RTC_CNTL_ROM_RAM_WAIT_TIMER_S))
375 #define RTC_CNTL_ROM_RAM_WAIT_TIMER_V  0x1FF
376 #define RTC_CNTL_ROM_RAM_WAIT_TIMER_S  16
377 /* RTC_CNTL_WIFI_POWERUP_TIMER : R/W ;bitpos:[15:9] ;default: 7'h5 ; */
378 /*description: */
379 #define RTC_CNTL_WIFI_POWERUP_TIMER  0x0000007F
380 #define RTC_CNTL_WIFI_POWERUP_TIMER_M  ((RTC_CNTL_WIFI_POWERUP_TIMER_V)<<(RTC_CNTL_WIFI_POWERUP_TIMER_S))
381 #define RTC_CNTL_WIFI_POWERUP_TIMER_V  0x7F
382 #define RTC_CNTL_WIFI_POWERUP_TIMER_S  9
383 /* RTC_CNTL_WIFI_WAIT_TIMER : R/W ;bitpos:[8:0] ;default: 9'h8 ; */
384 /*description: */
385 #define RTC_CNTL_WIFI_WAIT_TIMER  0x000001FF
386 #define RTC_CNTL_WIFI_WAIT_TIMER_M  ((RTC_CNTL_WIFI_WAIT_TIMER_V)<<(RTC_CNTL_WIFI_WAIT_TIMER_S))
387 #define RTC_CNTL_WIFI_WAIT_TIMER_V  0x1FF
388 #define RTC_CNTL_WIFI_WAIT_TIMER_S  0
389 
390 #define RTC_CNTL_TIMER4_REG          (DR_REG_RTCCNTL_BASE + 0x28)
391 /* RTC_CNTL_DG_WRAP_POWERUP_TIMER : R/W ;bitpos:[31:25] ;default: 7'h8 ; */
392 /*description: */
393 #define RTC_CNTL_DG_WRAP_POWERUP_TIMER  0x0000007F
394 #define RTC_CNTL_DG_WRAP_POWERUP_TIMER_M  ((RTC_CNTL_DG_WRAP_POWERUP_TIMER_V)<<(RTC_CNTL_DG_WRAP_POWERUP_TIMER_S))
395 #define RTC_CNTL_DG_WRAP_POWERUP_TIMER_V  0x7F
396 #define RTC_CNTL_DG_WRAP_POWERUP_TIMER_S  25
397 /* RTC_CNTL_DG_WRAP_WAIT_TIMER : R/W ;bitpos:[24:16] ;default: 9'h20 ; */
398 /*description: */
399 #define RTC_CNTL_DG_WRAP_WAIT_TIMER  0x000001FF
400 #define RTC_CNTL_DG_WRAP_WAIT_TIMER_M  ((RTC_CNTL_DG_WRAP_WAIT_TIMER_V)<<(RTC_CNTL_DG_WRAP_WAIT_TIMER_S))
401 #define RTC_CNTL_DG_WRAP_WAIT_TIMER_V  0x1FF
402 #define RTC_CNTL_DG_WRAP_WAIT_TIMER_S  16
403 /* RTC_CNTL_POWERUP_TIMER : R/W ;bitpos:[15:9] ;default: 7'h5 ; */
404 /*description: */
405 #define RTC_CNTL_POWERUP_TIMER  0x0000007F
406 #define RTC_CNTL_POWERUP_TIMER_M  ((RTC_CNTL_POWERUP_TIMER_V)<<(RTC_CNTL_POWERUP_TIMER_S))
407 #define RTC_CNTL_POWERUP_TIMER_V  0x7F
408 #define RTC_CNTL_POWERUP_TIMER_S  9
409 /* RTC_CNTL_WAIT_TIMER : R/W ;bitpos:[8:0] ;default: 9'h8 ; */
410 /*description: */
411 #define RTC_CNTL_WAIT_TIMER  0x000001FF
412 #define RTC_CNTL_WAIT_TIMER_M  ((RTC_CNTL_WAIT_TIMER_V)<<(RTC_CNTL_WAIT_TIMER_S))
413 #define RTC_CNTL_WAIT_TIMER_V  0x1FF
414 #define RTC_CNTL_WAIT_TIMER_S  0
415 
416 #define RTC_CNTL_TIMER5_REG          (DR_REG_RTCCNTL_BASE + 0x2c)
417 /* RTC_CNTL_RTCMEM_POWERUP_TIMER : R/W ;bitpos:[31:25] ;default: 7'h9 ; */
418 /*description: */
419 #define RTC_CNTL_RTCMEM_POWERUP_TIMER  0x0000007F
420 #define RTC_CNTL_RTCMEM_POWERUP_TIMER_M  ((RTC_CNTL_RTCMEM_POWERUP_TIMER_V)<<(RTC_CNTL_RTCMEM_POWERUP_TIMER_S))
421 #define RTC_CNTL_RTCMEM_POWERUP_TIMER_V  0x7F
422 #define RTC_CNTL_RTCMEM_POWERUP_TIMER_S  25
423 /* RTC_CNTL_RTCMEM_WAIT_TIMER : R/W ;bitpos:[24:16] ;default: 9'h14 ; */
424 /*description: */
425 #define RTC_CNTL_RTCMEM_WAIT_TIMER  0x000001FF
426 #define RTC_CNTL_RTCMEM_WAIT_TIMER_M  ((RTC_CNTL_RTCMEM_WAIT_TIMER_V)<<(RTC_CNTL_RTCMEM_WAIT_TIMER_S))
427 #define RTC_CNTL_RTCMEM_WAIT_TIMER_V  0x1FF
428 #define RTC_CNTL_RTCMEM_WAIT_TIMER_S  16
429 /* RTC_CNTL_MIN_SLP_VAL : R/W ;bitpos:[15:8] ;default: 8'h80 ; */
430 /*description: minimal sleep cycles in slow_clk_rtc*/
431 #define RTC_CNTL_MIN_SLP_VAL  0x000000FF
432 #define RTC_CNTL_MIN_SLP_VAL_M  ((RTC_CNTL_MIN_SLP_VAL_V)<<(RTC_CNTL_MIN_SLP_VAL_S))
433 #define RTC_CNTL_MIN_SLP_VAL_V  0xFF
434 #define RTC_CNTL_MIN_SLP_VAL_S  8
435 /* RTC_CNTL_ULP_CP_SUBTIMER_PREDIV : R/W ;bitpos:[7:0] ;default: 8'd1 ; */
436 /*description: */
437 #define RTC_CNTL_ULP_CP_SUBTIMER_PREDIV  0x000000FF
438 #define RTC_CNTL_ULP_CP_SUBTIMER_PREDIV_M  ((RTC_CNTL_ULP_CP_SUBTIMER_PREDIV_V)<<(RTC_CNTL_ULP_CP_SUBTIMER_PREDIV_S))
439 #define RTC_CNTL_ULP_CP_SUBTIMER_PREDIV_V  0xFF
440 #define RTC_CNTL_ULP_CP_SUBTIMER_PREDIV_S  0
441 
442 #define RTC_CNTL_ANA_CONF_REG          (DR_REG_RTCCNTL_BASE + 0x30)
443 /* RTC_CNTL_PLL_I2C_PU : R/W ;bitpos:[31] ;default: 1'd0 ; */
444 /*description: 1: PLL_I2C power up   otherwise power down*/
445 #define RTC_CNTL_PLL_I2C_PU  (BIT(31))
446 #define RTC_CNTL_PLL_I2C_PU_M  (BIT(31))
447 #define RTC_CNTL_PLL_I2C_PU_V  0x1
448 #define RTC_CNTL_PLL_I2C_PU_S  31
449 /* RTC_CNTL_CKGEN_I2C_PU : R/W ;bitpos:[30] ;default: 1'd0 ; */
450 /*description: 1: CKGEN_I2C power up   otherwise power down*/
451 #define RTC_CNTL_CKGEN_I2C_PU  (BIT(30))
452 #define RTC_CNTL_CKGEN_I2C_PU_M  (BIT(30))
453 #define RTC_CNTL_CKGEN_I2C_PU_V  0x1
454 #define RTC_CNTL_CKGEN_I2C_PU_S  30
455 /* RTC_CNTL_RFRX_PBUS_PU : R/W ;bitpos:[28] ;default: 1'd0 ; */
456 /*description: 1: RFRX_PBUS power up   otherwise power down*/
457 #define RTC_CNTL_RFRX_PBUS_PU  (BIT(28))
458 #define RTC_CNTL_RFRX_PBUS_PU_M  (BIT(28))
459 #define RTC_CNTL_RFRX_PBUS_PU_V  0x1
460 #define RTC_CNTL_RFRX_PBUS_PU_S  28
461 /* RTC_CNTL_TXRF_I2C_PU : R/W ;bitpos:[27] ;default: 1'd0 ; */
462 /*description: 1: TXRF_I2C power up   otherwise power down*/
463 #define RTC_CNTL_TXRF_I2C_PU  (BIT(27))
464 #define RTC_CNTL_TXRF_I2C_PU_M  (BIT(27))
465 #define RTC_CNTL_TXRF_I2C_PU_V  0x1
466 #define RTC_CNTL_TXRF_I2C_PU_S  27
467 /* RTC_CNTL_PVTMON_PU : R/W ;bitpos:[26] ;default: 1'b0 ; */
468 /*description: 1: PVTMON power up   otherwise power down*/
469 #define RTC_CNTL_PVTMON_PU  (BIT(26))
470 #define RTC_CNTL_PVTMON_PU_M  (BIT(26))
471 #define RTC_CNTL_PVTMON_PU_V  0x1
472 #define RTC_CNTL_PVTMON_PU_S  26
473 /* RTC_CNTL_BBPLL_CAL_SLP_START : R/W ;bitpos:[25] ;default: 1'b0 ; */
474 /*description: start BBPLL calibration during sleep*/
475 #define RTC_CNTL_BBPLL_CAL_SLP_START  (BIT(25))
476 #define RTC_CNTL_BBPLL_CAL_SLP_START_M  (BIT(25))
477 #define RTC_CNTL_BBPLL_CAL_SLP_START_V  0x1
478 #define RTC_CNTL_BBPLL_CAL_SLP_START_S  25
479 /* RTC_CNTL_PLLA_FORCE_PU : R/W ;bitpos:[24] ;default: 1'b0 ; */
480 /*description: PLLA force power up*/
481 #define RTC_CNTL_PLLA_FORCE_PU  (BIT(24))
482 #define RTC_CNTL_PLLA_FORCE_PU_M  (BIT(24))
483 #define RTC_CNTL_PLLA_FORCE_PU_V  0x1
484 #define RTC_CNTL_PLLA_FORCE_PU_S  24
485 /* RTC_CNTL_PLLA_FORCE_PD : R/W ;bitpos:[23] ;default: 1'b1 ; */
486 /*description: PLLA force power down*/
487 #define RTC_CNTL_PLLA_FORCE_PD  (BIT(23))
488 #define RTC_CNTL_PLLA_FORCE_PD_M  (BIT(23))
489 #define RTC_CNTL_PLLA_FORCE_PD_V  0x1
490 #define RTC_CNTL_PLLA_FORCE_PD_S  23
491 
492 #define RTC_CNTL_RESET_STATE_REG          (DR_REG_RTCCNTL_BASE + 0x34)
493 /* RTC_CNTL_PROCPU_STAT_VECTOR_SEL : R/W ;bitpos:[13] ;default: 1'b1 ; */
494 /*description: PRO CPU state vector sel*/
495 #define RTC_CNTL_PROCPU_STAT_VECTOR_SEL  (BIT(13))
496 #define RTC_CNTL_PROCPU_STAT_VECTOR_SEL_M  (BIT(13))
497 #define RTC_CNTL_PROCPU_STAT_VECTOR_SEL_V  0x1
498 #define RTC_CNTL_PROCPU_STAT_VECTOR_SEL_S  13
499 /* RTC_CNTL_APPCPU_STAT_VECTOR_SEL : R/W ;bitpos:[12] ;default: 1'b1 ; */
500 /*description: APP CPU state vector sel*/
501 #define RTC_CNTL_APPCPU_STAT_VECTOR_SEL  (BIT(12))
502 #define RTC_CNTL_APPCPU_STAT_VECTOR_SEL_M  (BIT(12))
503 #define RTC_CNTL_APPCPU_STAT_VECTOR_SEL_V  0x1
504 #define RTC_CNTL_APPCPU_STAT_VECTOR_SEL_S  12
505 /* RTC_CNTL_RESET_CAUSE_APPCPU : RO ;bitpos:[11:6] ;default: 0 ; */
506 /*description: reset cause of APP CPU*/
507 #define RTC_CNTL_RESET_CAUSE_APPCPU  0x0000003F
508 #define RTC_CNTL_RESET_CAUSE_APPCPU_M  ((RTC_CNTL_RESET_CAUSE_APPCPU_V)<<(RTC_CNTL_RESET_CAUSE_APPCPU_S))
509 #define RTC_CNTL_RESET_CAUSE_APPCPU_V  0x3F
510 #define RTC_CNTL_RESET_CAUSE_APPCPU_S  6
511 /* RTC_CNTL_RESET_CAUSE_PROCPU : RO ;bitpos:[5:0] ;default: 0 ; */
512 /*description: reset cause of PRO CPU*/
513 #define RTC_CNTL_RESET_CAUSE_PROCPU  0x0000003F
514 #define RTC_CNTL_RESET_CAUSE_PROCPU_M  ((RTC_CNTL_RESET_CAUSE_PROCPU_V)<<(RTC_CNTL_RESET_CAUSE_PROCPU_S))
515 #define RTC_CNTL_RESET_CAUSE_PROCPU_V  0x3F
516 #define RTC_CNTL_RESET_CAUSE_PROCPU_S  0
517 
518 #define RTC_CNTL_WAKEUP_STATE_REG          (DR_REG_RTCCNTL_BASE + 0x38)
519 /* RTC_CNTL_GPIO_WAKEUP_FILTER : R/W ;bitpos:[22] ;default: 1'd0 ; */
520 /*description: enable filter for gpio wakeup event*/
521 #define RTC_CNTL_GPIO_WAKEUP_FILTER  (BIT(22))
522 #define RTC_CNTL_GPIO_WAKEUP_FILTER_M  (BIT(22))
523 #define RTC_CNTL_GPIO_WAKEUP_FILTER_V  0x1
524 #define RTC_CNTL_GPIO_WAKEUP_FILTER_S  22
525 /* RTC_CNTL_WAKEUP_ENA : R/W ;bitpos:[21:11] ;default: 11'b1100 ; */
526 /*description: wakeup enable bitmap*/
527 #define RTC_CNTL_WAKEUP_ENA  0x000007FF
528 #define RTC_CNTL_WAKEUP_ENA_M  ((RTC_CNTL_WAKEUP_ENA_V)<<(RTC_CNTL_WAKEUP_ENA_S))
529 #define RTC_CNTL_WAKEUP_ENA_V  0x7FF
530 #define RTC_CNTL_WAKEUP_ENA_S  11
531 /* RTC_CNTL_WAKEUP_CAUSE : RO ;bitpos:[10:0] ;default: 11'h0 ; */
532 /*description: wakeup cause*/
533 #define RTC_CNTL_WAKEUP_CAUSE  0x000007FF
534 #define RTC_CNTL_WAKEUP_CAUSE_M  ((RTC_CNTL_WAKEUP_CAUSE_V)<<(RTC_CNTL_WAKEUP_CAUSE_S))
535 #define RTC_CNTL_WAKEUP_CAUSE_V  0x7FF
536 #define RTC_CNTL_WAKEUP_CAUSE_S  0
537 
538 #define RTC_CNTL_INT_ENA_REG          (DR_REG_RTCCNTL_BASE + 0x3c)
539 /* RTC_CNTL_MAIN_TIMER_INT_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */
540 /*description: enable RTC main timer interrupt*/
541 #define RTC_CNTL_MAIN_TIMER_INT_ENA  (BIT(8))
542 #define RTC_CNTL_MAIN_TIMER_INT_ENA_M  (BIT(8))
543 #define RTC_CNTL_MAIN_TIMER_INT_ENA_V  0x1
544 #define RTC_CNTL_MAIN_TIMER_INT_ENA_S  8
545 /* RTC_CNTL_BROWN_OUT_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */
546 /*description: enable brown out interrupt*/
547 #define RTC_CNTL_BROWN_OUT_INT_ENA  (BIT(7))
548 #define RTC_CNTL_BROWN_OUT_INT_ENA_M  (BIT(7))
549 #define RTC_CNTL_BROWN_OUT_INT_ENA_V  0x1
550 #define RTC_CNTL_BROWN_OUT_INT_ENA_S  7
551 /* RTC_CNTL_TOUCH_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */
552 /*description: enable touch interrupt*/
553 #define RTC_CNTL_TOUCH_INT_ENA  (BIT(6))
554 #define RTC_CNTL_TOUCH_INT_ENA_M  (BIT(6))
555 #define RTC_CNTL_TOUCH_INT_ENA_V  0x1
556 #define RTC_CNTL_TOUCH_INT_ENA_S  6
557 /* RTC_CNTL_ULP_CP_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */
558 /*description: enable ULP-coprocessor interrupt*/
559 #define RTC_CNTL_ULP_CP_INT_ENA  (BIT(5))
560 #define RTC_CNTL_ULP_CP_INT_ENA_M  (BIT(5))
561 #define RTC_CNTL_ULP_CP_INT_ENA_V  0x1
562 #define RTC_CNTL_ULP_CP_INT_ENA_S  5
563 /* RTC_CNTL_TIME_VALID_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */
564 /*description: enable RTC time valid interrupt*/
565 #define RTC_CNTL_TIME_VALID_INT_ENA  (BIT(4))
566 #define RTC_CNTL_TIME_VALID_INT_ENA_M  (BIT(4))
567 #define RTC_CNTL_TIME_VALID_INT_ENA_V  0x1
568 #define RTC_CNTL_TIME_VALID_INT_ENA_S  4
569 /* RTC_CNTL_WDT_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */
570 /*description: enable RTC WDT interrupt*/
571 #define RTC_CNTL_WDT_INT_ENA  (BIT(3))
572 #define RTC_CNTL_WDT_INT_ENA_M  (BIT(3))
573 #define RTC_CNTL_WDT_INT_ENA_V  0x1
574 #define RTC_CNTL_WDT_INT_ENA_S  3
575 /* RTC_CNTL_SDIO_IDLE_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */
576 /*description: enable SDIO idle interrupt*/
577 #define RTC_CNTL_SDIO_IDLE_INT_ENA  (BIT(2))
578 #define RTC_CNTL_SDIO_IDLE_INT_ENA_M  (BIT(2))
579 #define RTC_CNTL_SDIO_IDLE_INT_ENA_V  0x1
580 #define RTC_CNTL_SDIO_IDLE_INT_ENA_S  2
581 /* RTC_CNTL_SLP_REJECT_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */
582 /*description: enable sleep reject interrupt*/
583 #define RTC_CNTL_SLP_REJECT_INT_ENA  (BIT(1))
584 #define RTC_CNTL_SLP_REJECT_INT_ENA_M  (BIT(1))
585 #define RTC_CNTL_SLP_REJECT_INT_ENA_V  0x1
586 #define RTC_CNTL_SLP_REJECT_INT_ENA_S  1
587 /* RTC_CNTL_SLP_WAKEUP_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */
588 /*description: enable sleep wakeup interrupt*/
589 #define RTC_CNTL_SLP_WAKEUP_INT_ENA  (BIT(0))
590 #define RTC_CNTL_SLP_WAKEUP_INT_ENA_M  (BIT(0))
591 #define RTC_CNTL_SLP_WAKEUP_INT_ENA_V  0x1
592 #define RTC_CNTL_SLP_WAKEUP_INT_ENA_S  0
593 
594 #define RTC_CNTL_INT_RAW_REG          (DR_REG_RTCCNTL_BASE + 0x40)
595 /* RTC_CNTL_MAIN_TIMER_INT_RAW : RO ;bitpos:[8] ;default: 1'b0 ; */
596 /*description: RTC main timer interrupt raw*/
597 #define RTC_CNTL_MAIN_TIMER_INT_RAW  (BIT(8))
598 #define RTC_CNTL_MAIN_TIMER_INT_RAW_M  (BIT(8))
599 #define RTC_CNTL_MAIN_TIMER_INT_RAW_V  0x1
600 #define RTC_CNTL_MAIN_TIMER_INT_RAW_S  8
601 /* RTC_CNTL_BROWN_OUT_INT_RAW : RO ;bitpos:[7] ;default: 1'b0 ; */
602 /*description: brown out interrupt raw*/
603 #define RTC_CNTL_BROWN_OUT_INT_RAW  (BIT(7))
604 #define RTC_CNTL_BROWN_OUT_INT_RAW_M  (BIT(7))
605 #define RTC_CNTL_BROWN_OUT_INT_RAW_V  0x1
606 #define RTC_CNTL_BROWN_OUT_INT_RAW_S  7
607 /* RTC_CNTL_TOUCH_INT_RAW : RO ;bitpos:[6] ;default: 1'b0 ; */
608 /*description: touch interrupt raw*/
609 #define RTC_CNTL_TOUCH_INT_RAW  (BIT(6))
610 #define RTC_CNTL_TOUCH_INT_RAW_M  (BIT(6))
611 #define RTC_CNTL_TOUCH_INT_RAW_V  0x1
612 #define RTC_CNTL_TOUCH_INT_RAW_S  6
613 /* RTC_CNTL_ULP_CP_INT_RAW : RO ;bitpos:[5] ;default: 1'b0 ; */
614 /*description: ULP-coprocessor interrupt raw*/
615 #define RTC_CNTL_ULP_CP_INT_RAW  (BIT(5))
616 #define RTC_CNTL_ULP_CP_INT_RAW_M  (BIT(5))
617 #define RTC_CNTL_ULP_CP_INT_RAW_V  0x1
618 #define RTC_CNTL_ULP_CP_INT_RAW_S  5
619 /* RTC_CNTL_TIME_VALID_INT_RAW : RO ;bitpos:[4] ;default: 1'b0 ; */
620 /*description: RTC time valid interrupt raw*/
621 #define RTC_CNTL_TIME_VALID_INT_RAW  (BIT(4))
622 #define RTC_CNTL_TIME_VALID_INT_RAW_M  (BIT(4))
623 #define RTC_CNTL_TIME_VALID_INT_RAW_V  0x1
624 #define RTC_CNTL_TIME_VALID_INT_RAW_S  4
625 /* RTC_CNTL_WDT_INT_RAW : RO ;bitpos:[3] ;default: 1'b0 ; */
626 /*description: RTC WDT interrupt raw*/
627 #define RTC_CNTL_WDT_INT_RAW  (BIT(3))
628 #define RTC_CNTL_WDT_INT_RAW_M  (BIT(3))
629 #define RTC_CNTL_WDT_INT_RAW_V  0x1
630 #define RTC_CNTL_WDT_INT_RAW_S  3
631 /* RTC_CNTL_SDIO_IDLE_INT_RAW : RO ;bitpos:[2] ;default: 1'b0 ; */
632 /*description: SDIO idle interrupt raw*/
633 #define RTC_CNTL_SDIO_IDLE_INT_RAW  (BIT(2))
634 #define RTC_CNTL_SDIO_IDLE_INT_RAW_M  (BIT(2))
635 #define RTC_CNTL_SDIO_IDLE_INT_RAW_V  0x1
636 #define RTC_CNTL_SDIO_IDLE_INT_RAW_S  2
637 /* RTC_CNTL_SLP_REJECT_INT_RAW : RO ;bitpos:[1] ;default: 1'b0 ; */
638 /*description: sleep reject interrupt raw*/
639 #define RTC_CNTL_SLP_REJECT_INT_RAW  (BIT(1))
640 #define RTC_CNTL_SLP_REJECT_INT_RAW_M  (BIT(1))
641 #define RTC_CNTL_SLP_REJECT_INT_RAW_V  0x1
642 #define RTC_CNTL_SLP_REJECT_INT_RAW_S  1
643 /* RTC_CNTL_SLP_WAKEUP_INT_RAW : RO ;bitpos:[0] ;default: 1'b0 ; */
644 /*description: sleep wakeup interrupt raw*/
645 #define RTC_CNTL_SLP_WAKEUP_INT_RAW  (BIT(0))
646 #define RTC_CNTL_SLP_WAKEUP_INT_RAW_M  (BIT(0))
647 #define RTC_CNTL_SLP_WAKEUP_INT_RAW_V  0x1
648 #define RTC_CNTL_SLP_WAKEUP_INT_RAW_S  0
649 
650 #define RTC_CNTL_INT_ST_REG          (DR_REG_RTCCNTL_BASE + 0x44)
651 /* RTC_CNTL_MAIN_TIMER_INT_ST : RO ;bitpos:[8] ;default: 1'b0 ; */
652 /*description: RTC main timer interrupt state*/
653 #define RTC_CNTL_MAIN_TIMER_INT_ST  (BIT(8))
654 #define RTC_CNTL_MAIN_TIMER_INT_ST_M  (BIT(8))
655 #define RTC_CNTL_MAIN_TIMER_INT_ST_V  0x1
656 #define RTC_CNTL_MAIN_TIMER_INT_ST_S  8
657 /* RTC_CNTL_BROWN_OUT_INT_ST : RO ;bitpos:[7] ;default: 1'b0 ; */
658 /*description: brown out interrupt state*/
659 #define RTC_CNTL_BROWN_OUT_INT_ST  (BIT(7))
660 #define RTC_CNTL_BROWN_OUT_INT_ST_M  (BIT(7))
661 #define RTC_CNTL_BROWN_OUT_INT_ST_V  0x1
662 #define RTC_CNTL_BROWN_OUT_INT_ST_S  7
663 /* RTC_CNTL_TOUCH_INT_ST : RO ;bitpos:[6] ;default: 1'b0 ; */
664 /*description: touch interrupt state*/
665 #define RTC_CNTL_TOUCH_INT_ST  (BIT(6))
666 #define RTC_CNTL_TOUCH_INT_ST_M  (BIT(6))
667 #define RTC_CNTL_TOUCH_INT_ST_V  0x1
668 #define RTC_CNTL_TOUCH_INT_ST_S  6
669 /* RTC_CNTL_SAR_INT_ST : RO ;bitpos:[5] ;default: 1'b0 ; */
670 /*description: ULP-coprocessor interrupt state*/
671 #define RTC_CNTL_SAR_INT_ST  (BIT(5))
672 #define RTC_CNTL_SAR_INT_ST_M  (BIT(5))
673 #define RTC_CNTL_SAR_INT_ST_V  0x1
674 #define RTC_CNTL_SAR_INT_ST_S  5
675 /* RTC_CNTL_TIME_VALID_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */
676 /*description: RTC time valid interrupt state*/
677 #define RTC_CNTL_TIME_VALID_INT_ST  (BIT(4))
678 #define RTC_CNTL_TIME_VALID_INT_ST_M  (BIT(4))
679 #define RTC_CNTL_TIME_VALID_INT_ST_V  0x1
680 #define RTC_CNTL_TIME_VALID_INT_ST_S  4
681 /* RTC_CNTL_WDT_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */
682 /*description: RTC WDT interrupt state*/
683 #define RTC_CNTL_WDT_INT_ST  (BIT(3))
684 #define RTC_CNTL_WDT_INT_ST_M  (BIT(3))
685 #define RTC_CNTL_WDT_INT_ST_V  0x1
686 #define RTC_CNTL_WDT_INT_ST_S  3
687 /* RTC_CNTL_SDIO_IDLE_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */
688 /*description: SDIO idle interrupt state*/
689 #define RTC_CNTL_SDIO_IDLE_INT_ST  (BIT(2))
690 #define RTC_CNTL_SDIO_IDLE_INT_ST_M  (BIT(2))
691 #define RTC_CNTL_SDIO_IDLE_INT_ST_V  0x1
692 #define RTC_CNTL_SDIO_IDLE_INT_ST_S  2
693 /* RTC_CNTL_SLP_REJECT_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */
694 /*description: sleep reject interrupt state*/
695 #define RTC_CNTL_SLP_REJECT_INT_ST  (BIT(1))
696 #define RTC_CNTL_SLP_REJECT_INT_ST_M  (BIT(1))
697 #define RTC_CNTL_SLP_REJECT_INT_ST_V  0x1
698 #define RTC_CNTL_SLP_REJECT_INT_ST_S  1
699 /* RTC_CNTL_SLP_WAKEUP_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */
700 /*description: sleep wakeup interrupt state*/
701 #define RTC_CNTL_SLP_WAKEUP_INT_ST  (BIT(0))
702 #define RTC_CNTL_SLP_WAKEUP_INT_ST_M  (BIT(0))
703 #define RTC_CNTL_SLP_WAKEUP_INT_ST_V  0x1
704 #define RTC_CNTL_SLP_WAKEUP_INT_ST_S  0
705 
706 #define RTC_CNTL_INT_CLR_REG          (DR_REG_RTCCNTL_BASE + 0x48)
707 /* RTC_CNTL_MAIN_TIMER_INT_CLR : WO ;bitpos:[8] ;default: 1'b0 ; */
708 /*description: Clear RTC main timer interrupt state*/
709 #define RTC_CNTL_MAIN_TIMER_INT_CLR  (BIT(8))
710 #define RTC_CNTL_MAIN_TIMER_INT_CLR_M  (BIT(8))
711 #define RTC_CNTL_MAIN_TIMER_INT_CLR_V  0x1
712 #define RTC_CNTL_MAIN_TIMER_INT_CLR_S  8
713 /* RTC_CNTL_BROWN_OUT_INT_CLR : WO ;bitpos:[7] ;default: 1'b0 ; */
714 /*description: Clear brown out interrupt state*/
715 #define RTC_CNTL_BROWN_OUT_INT_CLR  (BIT(7))
716 #define RTC_CNTL_BROWN_OUT_INT_CLR_M  (BIT(7))
717 #define RTC_CNTL_BROWN_OUT_INT_CLR_V  0x1
718 #define RTC_CNTL_BROWN_OUT_INT_CLR_S  7
719 /* RTC_CNTL_TOUCH_INT_CLR : WO ;bitpos:[6] ;default: 1'b0 ; */
720 /*description: Clear touch interrupt state*/
721 #define RTC_CNTL_TOUCH_INT_CLR  (BIT(6))
722 #define RTC_CNTL_TOUCH_INT_CLR_M  (BIT(6))
723 #define RTC_CNTL_TOUCH_INT_CLR_V  0x1
724 #define RTC_CNTL_TOUCH_INT_CLR_S  6
725 /* RTC_CNTL_SAR_INT_CLR : WO ;bitpos:[5] ;default: 1'b0 ; */
726 /*description: Clear ULP-coprocessor interrupt state*/
727 #define RTC_CNTL_SAR_INT_CLR  (BIT(5))
728 #define RTC_CNTL_SAR_INT_CLR_M  (BIT(5))
729 #define RTC_CNTL_SAR_INT_CLR_V  0x1
730 #define RTC_CNTL_SAR_INT_CLR_S  5
731 /* RTC_CNTL_TIME_VALID_INT_CLR : WO ;bitpos:[4] ;default: 1'b0 ; */
732 /*description: Clear RTC time valid interrupt state*/
733 #define RTC_CNTL_TIME_VALID_INT_CLR  (BIT(4))
734 #define RTC_CNTL_TIME_VALID_INT_CLR_M  (BIT(4))
735 #define RTC_CNTL_TIME_VALID_INT_CLR_V  0x1
736 #define RTC_CNTL_TIME_VALID_INT_CLR_S  4
737 /* RTC_CNTL_WDT_INT_CLR : WO ;bitpos:[3] ;default: 1'b0 ; */
738 /*description: Clear RTC WDT interrupt state*/
739 #define RTC_CNTL_WDT_INT_CLR  (BIT(3))
740 #define RTC_CNTL_WDT_INT_CLR_M  (BIT(3))
741 #define RTC_CNTL_WDT_INT_CLR_V  0x1
742 #define RTC_CNTL_WDT_INT_CLR_S  3
743 /* RTC_CNTL_SDIO_IDLE_INT_CLR : WO ;bitpos:[2] ;default: 1'b0 ; */
744 /*description: Clear SDIO idle interrupt state*/
745 #define RTC_CNTL_SDIO_IDLE_INT_CLR  (BIT(2))
746 #define RTC_CNTL_SDIO_IDLE_INT_CLR_M  (BIT(2))
747 #define RTC_CNTL_SDIO_IDLE_INT_CLR_V  0x1
748 #define RTC_CNTL_SDIO_IDLE_INT_CLR_S  2
749 /* RTC_CNTL_SLP_REJECT_INT_CLR : WO ;bitpos:[1] ;default: 1'b0 ; */
750 /*description: Clear sleep reject interrupt state*/
751 #define RTC_CNTL_SLP_REJECT_INT_CLR  (BIT(1))
752 #define RTC_CNTL_SLP_REJECT_INT_CLR_M  (BIT(1))
753 #define RTC_CNTL_SLP_REJECT_INT_CLR_V  0x1
754 #define RTC_CNTL_SLP_REJECT_INT_CLR_S  1
755 /* RTC_CNTL_SLP_WAKEUP_INT_CLR : WO ;bitpos:[0] ;default: 1'b0 ; */
756 /*description: Clear sleep wakeup interrupt state*/
757 #define RTC_CNTL_SLP_WAKEUP_INT_CLR  (BIT(0))
758 #define RTC_CNTL_SLP_WAKEUP_INT_CLR_M  (BIT(0))
759 #define RTC_CNTL_SLP_WAKEUP_INT_CLR_V  0x1
760 #define RTC_CNTL_SLP_WAKEUP_INT_CLR_S  0
761 
762 #define RTC_CNTL_STORE0_REG          (DR_REG_RTCCNTL_BASE + 0x4c)
763 /* RTC_CNTL_SCRATCH0 : R/W ;bitpos:[31:0] ;default: 0 ; */
764 /*description: 32-bit general purpose retention register*/
765 #define RTC_CNTL_SCRATCH0  0xFFFFFFFF
766 #define RTC_CNTL_SCRATCH0_M  ((RTC_CNTL_SCRATCH0_V)<<(RTC_CNTL_SCRATCH0_S))
767 #define RTC_CNTL_SCRATCH0_V  0xFFFFFFFF
768 #define RTC_CNTL_SCRATCH0_S  0
769 
770 #define RTC_CNTL_STORE1_REG          (DR_REG_RTCCNTL_BASE + 0x50)
771 /* RTC_CNTL_SCRATCH1 : R/W ;bitpos:[31:0] ;default: 0 ; */
772 /*description: 32-bit general purpose retention register*/
773 #define RTC_CNTL_SCRATCH1  0xFFFFFFFF
774 #define RTC_CNTL_SCRATCH1_M  ((RTC_CNTL_SCRATCH1_V)<<(RTC_CNTL_SCRATCH1_S))
775 #define RTC_CNTL_SCRATCH1_V  0xFFFFFFFF
776 #define RTC_CNTL_SCRATCH1_S  0
777 
778 #define RTC_CNTL_STORE2_REG          (DR_REG_RTCCNTL_BASE + 0x54)
779 /* RTC_CNTL_SCRATCH2 : R/W ;bitpos:[31:0] ;default: 0 ; */
780 /*description: 32-bit general purpose retention register*/
781 #define RTC_CNTL_SCRATCH2  0xFFFFFFFF
782 #define RTC_CNTL_SCRATCH2_M  ((RTC_CNTL_SCRATCH2_V)<<(RTC_CNTL_SCRATCH2_S))
783 #define RTC_CNTL_SCRATCH2_V  0xFFFFFFFF
784 #define RTC_CNTL_SCRATCH2_S  0
785 
786 #define RTC_CNTL_STORE3_REG          (DR_REG_RTCCNTL_BASE + 0x58)
787 /* RTC_CNTL_SCRATCH3 : R/W ;bitpos:[31:0] ;default: 0 ; */
788 /*description: 32-bit general purpose retention register*/
789 #define RTC_CNTL_SCRATCH3  0xFFFFFFFF
790 #define RTC_CNTL_SCRATCH3_M  ((RTC_CNTL_SCRATCH3_V)<<(RTC_CNTL_SCRATCH3_S))
791 #define RTC_CNTL_SCRATCH3_V  0xFFFFFFFF
792 #define RTC_CNTL_SCRATCH3_S  0
793 
794 #define RTC_CNTL_EXT_XTL_CONF_REG          (DR_REG_RTCCNTL_BASE + 0x5c)
795 /* RTC_CNTL_XTL_EXT_CTR_EN : R/W ;bitpos:[31] ;default: 1'b0 ; */
796 /*description: enable control XTAL by external pads*/
797 #define RTC_CNTL_XTL_EXT_CTR_EN  (BIT(31))
798 #define RTC_CNTL_XTL_EXT_CTR_EN_M  (BIT(31))
799 #define RTC_CNTL_XTL_EXT_CTR_EN_V  0x1
800 #define RTC_CNTL_XTL_EXT_CTR_EN_S  31
801 /* RTC_CNTL_XTL_EXT_CTR_LV : R/W ;bitpos:[30] ;default: 1'b0 ; */
802 /*description: 0: power down XTAL at high level  1: power down XTAL at low level*/
803 #define RTC_CNTL_XTL_EXT_CTR_LV  (BIT(30))
804 #define RTC_CNTL_XTL_EXT_CTR_LV_M  (BIT(30))
805 #define RTC_CNTL_XTL_EXT_CTR_LV_V  0x1
806 #define RTC_CNTL_XTL_EXT_CTR_LV_S  30
807 
808 #define RTC_CNTL_EXT_WAKEUP_CONF_REG          (DR_REG_RTCCNTL_BASE + 0x60)
809 /* RTC_CNTL_EXT_WAKEUP1_LV : R/W ;bitpos:[31] ;default: 1'b0 ; */
810 /*description: 0: external wakeup at low level  1: external wakeup at high level*/
811 #define RTC_CNTL_EXT_WAKEUP1_LV  (BIT(31))
812 #define RTC_CNTL_EXT_WAKEUP1_LV_M  (BIT(31))
813 #define RTC_CNTL_EXT_WAKEUP1_LV_V  0x1
814 #define RTC_CNTL_EXT_WAKEUP1_LV_S  31
815 /* RTC_CNTL_EXT_WAKEUP0_LV : R/W ;bitpos:[30] ;default: 1'b0 ; */
816 /*description: 0: external wakeup at low level  1: external wakeup at high level*/
817 #define RTC_CNTL_EXT_WAKEUP0_LV  (BIT(30))
818 #define RTC_CNTL_EXT_WAKEUP0_LV_M  (BIT(30))
819 #define RTC_CNTL_EXT_WAKEUP0_LV_V  0x1
820 #define RTC_CNTL_EXT_WAKEUP0_LV_S  30
821 
822 #define RTC_CNTL_SLP_REJECT_CONF_REG          (DR_REG_RTCCNTL_BASE + 0x64)
823 /* RTC_CNTL_REJECT_CAUSE : RO ;bitpos:[31:28] ;default: 4'b0 ; */
824 /*description: sleep reject cause*/
825 #define RTC_CNTL_REJECT_CAUSE  0x0000000F
826 #define RTC_CNTL_REJECT_CAUSE_M  ((RTC_CNTL_REJECT_CAUSE_V)<<(RTC_CNTL_REJECT_CAUSE_S))
827 #define RTC_CNTL_REJECT_CAUSE_V  0xF
828 #define RTC_CNTL_REJECT_CAUSE_S  28
829 /* RTC_CNTL_DEEP_SLP_REJECT_EN : R/W ;bitpos:[27] ;default: 1'b0 ; */
830 /*description: enable reject for deep sleep*/
831 #define RTC_CNTL_DEEP_SLP_REJECT_EN  (BIT(27))
832 #define RTC_CNTL_DEEP_SLP_REJECT_EN_M  (BIT(27))
833 #define RTC_CNTL_DEEP_SLP_REJECT_EN_V  0x1
834 #define RTC_CNTL_DEEP_SLP_REJECT_EN_S  27
835 /* RTC_CNTL_LIGHT_SLP_REJECT_EN : R/W ;bitpos:[26] ;default: 1'b0 ; */
836 /*description: enable reject for light sleep*/
837 #define RTC_CNTL_LIGHT_SLP_REJECT_EN  (BIT(26))
838 #define RTC_CNTL_LIGHT_SLP_REJECT_EN_M  (BIT(26))
839 #define RTC_CNTL_LIGHT_SLP_REJECT_EN_V  0x1
840 #define RTC_CNTL_LIGHT_SLP_REJECT_EN_S  26
841 /* RTC_CNTL_SDIO_REJECT_EN : R/W ;bitpos:[25] ;default: 1'b0 ; */
842 /*description: enable SDIO reject*/
843 #define RTC_CNTL_SDIO_REJECT_EN  (BIT(25))
844 #define RTC_CNTL_SDIO_REJECT_EN_M  (BIT(25))
845 #define RTC_CNTL_SDIO_REJECT_EN_V  0x1
846 #define RTC_CNTL_SDIO_REJECT_EN_S  25
847 /* RTC_CNTL_GPIO_REJECT_EN : R/W ;bitpos:[24] ;default: 1'b0 ; */
848 /*description: enable GPIO reject*/
849 #define RTC_CNTL_GPIO_REJECT_EN  (BIT(24))
850 #define RTC_CNTL_GPIO_REJECT_EN_M  (BIT(24))
851 #define RTC_CNTL_GPIO_REJECT_EN_V  0x1
852 #define RTC_CNTL_GPIO_REJECT_EN_S  24
853 
854 #define RTC_CNTL_CPU_PERIOD_CONF_REG          (DR_REG_RTCCNTL_BASE + 0x68)
855 /* RTC_CNTL_CPUPERIOD_SEL : R/W ;bitpos:[31:30] ;default: 2'b00 ; */
856 /*description: CPU period sel*/
857 #define RTC_CNTL_CPUPERIOD_SEL  0x00000003
858 #define RTC_CNTL_CPUPERIOD_SEL_M  ((RTC_CNTL_CPUPERIOD_SEL_V)<<(RTC_CNTL_CPUPERIOD_SEL_S))
859 #define RTC_CNTL_CPUPERIOD_SEL_V  0x3
860 #define RTC_CNTL_CPUPERIOD_SEL_S  30
861 /* RTC_CNTL_CPUSEL_CONF : R/W ;bitpos:[29] ;default: 1'b0 ; */
862 /*description: CPU sel option*/
863 #define RTC_CNTL_CPUSEL_CONF  (BIT(29))
864 #define RTC_CNTL_CPUSEL_CONF_M  (BIT(29))
865 #define RTC_CNTL_CPUSEL_CONF_V  0x1
866 #define RTC_CNTL_CPUSEL_CONF_S  29
867 
868 #define RTC_CNTL_SDIO_ACT_CONF_REG          (DR_REG_RTCCNTL_BASE + 0x6c)
869 /* RTC_CNTL_SDIO_ACT_DNUM : R/W ;bitpos:[31:22] ;default: 10'b0 ; */
870 /*description: */
871 #define RTC_CNTL_SDIO_ACT_DNUM  0x000003FF
872 #define RTC_CNTL_SDIO_ACT_DNUM_M  ((RTC_CNTL_SDIO_ACT_DNUM_V)<<(RTC_CNTL_SDIO_ACT_DNUM_S))
873 #define RTC_CNTL_SDIO_ACT_DNUM_V  0x3FF
874 #define RTC_CNTL_SDIO_ACT_DNUM_S  22
875 
876 #define RTC_CNTL_CLK_CONF_REG          (DR_REG_RTCCNTL_BASE + 0x70)
877 /* RTC_CNTL_ANA_CLK_RTC_SEL : R/W ;bitpos:[31:30] ;default: 2'd0 ; */
878 /*description: slow_clk_rtc sel. 0: SLOW_CK  1: CK_XTAL_32K  2: CK8M_D256_OUT*/
879 #define RTC_CNTL_ANA_CLK_RTC_SEL  0x00000003
880 #define RTC_CNTL_ANA_CLK_RTC_SEL_M  ((RTC_CNTL_ANA_CLK_RTC_SEL_V)<<(RTC_CNTL_ANA_CLK_RTC_SEL_S))
881 #define RTC_CNTL_ANA_CLK_RTC_SEL_V  0x3
882 #define RTC_CNTL_ANA_CLK_RTC_SEL_S  30
883 /* RTC_CNTL_FAST_CLK_RTC_SEL : R/W ;bitpos:[29] ;default: 1'b0 ; */
884 /*description: fast_clk_rtc sel. 0: XTAL div 4  1: CK8M*/
885 #define RTC_CNTL_FAST_CLK_RTC_SEL  (BIT(29))
886 #define RTC_CNTL_FAST_CLK_RTC_SEL_M  (BIT(29))
887 #define RTC_CNTL_FAST_CLK_RTC_SEL_V  0x1
888 #define RTC_CNTL_FAST_CLK_RTC_SEL_S  29
889 /* RTC_CNTL_SOC_CLK_SEL : R/W ;bitpos:[28:27] ;default: 2'd0 ; */
890 /*description: SOC clock sel. 0: XTAL  1: PLL  2: CK8M  3: APLL*/
891 #define RTC_CNTL_SOC_CLK_SEL  0x00000003
892 #define RTC_CNTL_SOC_CLK_SEL_M  ((RTC_CNTL_SOC_CLK_SEL_V)<<(RTC_CNTL_SOC_CLK_SEL_S))
893 #define RTC_CNTL_SOC_CLK_SEL_V  0x3
894 #define RTC_CNTL_SOC_CLK_SEL_S  27
895 /* RTC_CNTL_CK8M_FORCE_PU : R/W ;bitpos:[26] ;default: 1'd0 ; */
896 /*description: CK8M force power up*/
897 #define RTC_CNTL_CK8M_FORCE_PU  (BIT(26))
898 #define RTC_CNTL_CK8M_FORCE_PU_M  (BIT(26))
899 #define RTC_CNTL_CK8M_FORCE_PU_V  0x1
900 #define RTC_CNTL_CK8M_FORCE_PU_S  26
901 /* RTC_CNTL_CK8M_FORCE_PD : R/W ;bitpos:[25] ;default: 1'd0 ; */
902 /*description: CK8M force power down*/
903 #define RTC_CNTL_CK8M_FORCE_PD  (BIT(25))
904 #define RTC_CNTL_CK8M_FORCE_PD_M  (BIT(25))
905 #define RTC_CNTL_CK8M_FORCE_PD_V  0x1
906 #define RTC_CNTL_CK8M_FORCE_PD_S  25
907 /* RTC_CNTL_CK8M_DFREQ : R/W ;bitpos:[24:17] ;default: 8'd0 ; */
908 /*description: CK8M_DFREQ*/
909 #define RTC_CNTL_CK8M_DFREQ  0x000000FF
910 #define RTC_CNTL_CK8M_DFREQ_M  ((RTC_CNTL_CK8M_DFREQ_V)<<(RTC_CNTL_CK8M_DFREQ_S))
911 #define RTC_CNTL_CK8M_DFREQ_V  0xFF
912 #define RTC_CNTL_CK8M_DFREQ_S  17
913 #define RTC_CNTL_CK8M_DFREQ_DEFAULT 172
914 /* RTC_CNTL_CK8M_FORCE_NOGATING : R/W ;bitpos:[16] ;default: 1'd0 ; */
915 /*description: CK8M force no gating during sleep*/
916 #define RTC_CNTL_CK8M_FORCE_NOGATING  (BIT(16))
917 #define RTC_CNTL_CK8M_FORCE_NOGATING_M  (BIT(16))
918 #define RTC_CNTL_CK8M_FORCE_NOGATING_V  0x1
919 #define RTC_CNTL_CK8M_FORCE_NOGATING_S  16
920 /* RTC_CNTL_XTAL_FORCE_NOGATING : R/W ;bitpos:[15] ;default: 1'd0 ; */
921 /*description: XTAL force no gating during sleep*/
922 #define RTC_CNTL_XTAL_FORCE_NOGATING  (BIT(15))
923 #define RTC_CNTL_XTAL_FORCE_NOGATING_M  (BIT(15))
924 #define RTC_CNTL_XTAL_FORCE_NOGATING_V  0x1
925 #define RTC_CNTL_XTAL_FORCE_NOGATING_S  15
926 /* RTC_CNTL_CK8M_DIV_SEL : R/W ;bitpos:[14:12] ;default: 3'd2 ; */
927 /*description: divider = reg_ck8m_div_sel + 1*/
928 #define RTC_CNTL_CK8M_DIV_SEL  0x00000007
929 #define RTC_CNTL_CK8M_DIV_SEL_M  ((RTC_CNTL_CK8M_DIV_SEL_V)<<(RTC_CNTL_CK8M_DIV_SEL_S))
930 #define RTC_CNTL_CK8M_DIV_SEL_V  0x7
931 #define RTC_CNTL_CK8M_DIV_SEL_S  12
932 /* RTC_CNTL_CK8M_DFREQ_FORCE : R/W ;bitpos:[11] ;default: 1'd0 ; */
933 /*description: */
934 #define RTC_CNTL_CK8M_DFREQ_FORCE  (BIT(11))
935 #define RTC_CNTL_CK8M_DFREQ_FORCE_M  (BIT(11))
936 #define RTC_CNTL_CK8M_DFREQ_FORCE_V  0x1
937 #define RTC_CNTL_CK8M_DFREQ_FORCE_S  11
938 /* RTC_CNTL_DIG_CLK8M_EN : R/W ;bitpos:[10] ;default: 1'd0 ; */
939 /*description: enable CK8M for digital core (no relationship with RTC core)*/
940 #define RTC_CNTL_DIG_CLK8M_EN  (BIT(10))
941 #define RTC_CNTL_DIG_CLK8M_EN_M  (BIT(10))
942 #define RTC_CNTL_DIG_CLK8M_EN_V  0x1
943 #define RTC_CNTL_DIG_CLK8M_EN_S  10
944 /* RTC_CNTL_DIG_CLK8M_D256_EN : R/W ;bitpos:[9] ;default: 1'd1 ; */
945 /*description: enable CK8M_D256_OUT for digital core (no relationship with RTC core)*/
946 #define RTC_CNTL_DIG_CLK8M_D256_EN  (BIT(9))
947 #define RTC_CNTL_DIG_CLK8M_D256_EN_M  (BIT(9))
948 #define RTC_CNTL_DIG_CLK8M_D256_EN_V  0x1
949 #define RTC_CNTL_DIG_CLK8M_D256_EN_S  9
950 /* RTC_CNTL_DIG_XTAL32K_EN : R/W ;bitpos:[8] ;default: 1'd0 ; */
951 /*description: enable CK_XTAL_32K for digital core (no relationship with RTC core)*/
952 #define RTC_CNTL_DIG_XTAL32K_EN  (BIT(8))
953 #define RTC_CNTL_DIG_XTAL32K_EN_M  (BIT(8))
954 #define RTC_CNTL_DIG_XTAL32K_EN_V  0x1
955 #define RTC_CNTL_DIG_XTAL32K_EN_S  8
956 /* RTC_CNTL_ENB_CK8M_DIV : R/W ;bitpos:[7] ;default: 1'd0 ; */
957 /*description: 1: CK8M_D256_OUT is actually CK8M  0: CK8M_D256_OUT is CK8M divided by 256*/
958 #define RTC_CNTL_ENB_CK8M_DIV  (BIT(7))
959 #define RTC_CNTL_ENB_CK8M_DIV_M  (BIT(7))
960 #define RTC_CNTL_ENB_CK8M_DIV_V  0x1
961 #define RTC_CNTL_ENB_CK8M_DIV_S  7
962 /* RTC_CNTL_ENB_CK8M : R/W ;bitpos:[6] ;default: 1'd0 ; */
963 /*description: disable CK8M and CK8M_D256_OUT*/
964 #define RTC_CNTL_ENB_CK8M  (BIT(6))
965 #define RTC_CNTL_ENB_CK8M_M  (BIT(6))
966 #define RTC_CNTL_ENB_CK8M_V  0x1
967 #define RTC_CNTL_ENB_CK8M_S  6
968 /* RTC_CNTL_CK8M_DIV : R/W ;bitpos:[5:4] ;default: 2'b01 ; */
969 /*description: CK8M_D256_OUT divider. 00: div128  01: div256  10: div512  11: div1024.*/
970 #define RTC_CNTL_CK8M_DIV  0x00000003
971 #define RTC_CNTL_CK8M_DIV_M  ((RTC_CNTL_CK8M_DIV_V)<<(RTC_CNTL_CK8M_DIV_S))
972 #define RTC_CNTL_CK8M_DIV_V  0x3
973 #define RTC_CNTL_CK8M_DIV_S  4
974 
975 #define RTC_CNTL_SDIO_CONF_REG          (DR_REG_RTCCNTL_BASE + 0x74)
976 /* RTC_CNTL_XPD_SDIO_REG : R/W ;bitpos:[31] ;default: 1'd0 ; */
977 /*description: SW option for XPD_SDIO_REG. Only active when reg_sdio_force = 1*/
978 #define RTC_CNTL_XPD_SDIO_REG  (BIT(31))
979 #define RTC_CNTL_XPD_SDIO_REG_M  (BIT(31))
980 #define RTC_CNTL_XPD_SDIO_REG_V  0x1
981 #define RTC_CNTL_XPD_SDIO_REG_S  31
982 /* RTC_CNTL_DREFH_SDIO : R/W ;bitpos:[30:29] ;default: 2'b00 ; */
983 /*description: SW option for DREFH_SDIO. Only active when reg_sdio_force = 1*/
984 #define RTC_CNTL_DREFH_SDIO  0x00000003
985 #define RTC_CNTL_DREFH_SDIO_M  ((RTC_CNTL_DREFH_SDIO_V)<<(RTC_CNTL_DREFH_SDIO_S))
986 #define RTC_CNTL_DREFH_SDIO_V  0x3
987 #define RTC_CNTL_DREFH_SDIO_S  29
988 /* RTC_CNTL_DREFM_SDIO : R/W ;bitpos:[28:27] ;default: 2'b00 ; */
989 /*description: SW option for DREFM_SDIO. Only active when reg_sdio_force = 1*/
990 #define RTC_CNTL_DREFM_SDIO  0x00000003
991 #define RTC_CNTL_DREFM_SDIO_M  ((RTC_CNTL_DREFM_SDIO_V)<<(RTC_CNTL_DREFM_SDIO_S))
992 #define RTC_CNTL_DREFM_SDIO_V  0x3
993 #define RTC_CNTL_DREFM_SDIO_S  27
994 /* RTC_CNTL_DREFL_SDIO : R/W ;bitpos:[26:25] ;default: 2'b01 ; */
995 /*description: SW option for DREFL_SDIO. Only active when reg_sdio_force = 1*/
996 #define RTC_CNTL_DREFL_SDIO  0x00000003
997 #define RTC_CNTL_DREFL_SDIO_M  ((RTC_CNTL_DREFL_SDIO_V)<<(RTC_CNTL_DREFL_SDIO_S))
998 #define RTC_CNTL_DREFL_SDIO_V  0x3
999 #define RTC_CNTL_DREFL_SDIO_S  25
1000 /* RTC_CNTL_REG1P8_READY : RO ;bitpos:[24] ;default: 1'd0 ; */
1001 /*description: read only register for REG1P8_READY*/
1002 #define RTC_CNTL_REG1P8_READY  (BIT(24))
1003 #define RTC_CNTL_REG1P8_READY_M  (BIT(24))
1004 #define RTC_CNTL_REG1P8_READY_V  0x1
1005 #define RTC_CNTL_REG1P8_READY_S  24
1006 /* RTC_CNTL_SDIO_TIEH : R/W ;bitpos:[23] ;default: 1'd1 ; */
1007 /*description: SW option for SDIO_TIEH. Only active when reg_sdio_force = 1*/
1008 #define RTC_CNTL_SDIO_TIEH  (BIT(23))
1009 #define RTC_CNTL_SDIO_TIEH_M  (BIT(23))
1010 #define RTC_CNTL_SDIO_TIEH_V  0x1
1011 #define RTC_CNTL_SDIO_TIEH_S  23
1012 /* RTC_CNTL_SDIO_FORCE : R/W ;bitpos:[22] ;default: 1'd0 ; */
1013 /*description: 1: use SW option to control SDIO_REG  0: use state machine*/
1014 #define RTC_CNTL_SDIO_FORCE  (BIT(22))
1015 #define RTC_CNTL_SDIO_FORCE_M  (BIT(22))
1016 #define RTC_CNTL_SDIO_FORCE_V  0x1
1017 #define RTC_CNTL_SDIO_FORCE_S  22
1018 /* RTC_CNTL_SDIO_PD_EN : R/W ;bitpos:[21] ;default: 1'd1 ; */
1019 /*description: power down SDIO_REG in sleep. Only active when reg_sdio_force = 0*/
1020 #define RTC_CNTL_SDIO_PD_EN  (BIT(21))
1021 #define RTC_CNTL_SDIO_PD_EN_M  (BIT(21))
1022 #define RTC_CNTL_SDIO_PD_EN_V  0x1
1023 #define RTC_CNTL_SDIO_PD_EN_S  21
1024 
1025 #define RTC_CNTL_BIAS_CONF_REG          (DR_REG_RTCCNTL_BASE + 0x78)
1026 /* RTC_CNTL_RST_BIAS_I2C : R/W ;bitpos:[31] ;default: 1'd0 ; */
1027 /*description: RST_BIAS_I2C*/
1028 #define RTC_CNTL_RST_BIAS_I2C  (BIT(31))
1029 #define RTC_CNTL_RST_BIAS_I2C_M  (BIT(31))
1030 #define RTC_CNTL_RST_BIAS_I2C_V  0x1
1031 #define RTC_CNTL_RST_BIAS_I2C_S  31
1032 /* RTC_CNTL_DEC_HEARTBEAT_WIDTH : R/W ;bitpos:[30] ;default: 1'd0 ; */
1033 /*description: DEC_HEARTBEAT_WIDTH*/
1034 #define RTC_CNTL_DEC_HEARTBEAT_WIDTH  (BIT(30))
1035 #define RTC_CNTL_DEC_HEARTBEAT_WIDTH_M  (BIT(30))
1036 #define RTC_CNTL_DEC_HEARTBEAT_WIDTH_V  0x1
1037 #define RTC_CNTL_DEC_HEARTBEAT_WIDTH_S  30
1038 /* RTC_CNTL_INC_HEARTBEAT_PERIOD : R/W ;bitpos:[29] ;default: 1'd0 ; */
1039 /*description: INC_HEARTBEAT_PERIOD*/
1040 #define RTC_CNTL_INC_HEARTBEAT_PERIOD  (BIT(29))
1041 #define RTC_CNTL_INC_HEARTBEAT_PERIOD_M  (BIT(29))
1042 #define RTC_CNTL_INC_HEARTBEAT_PERIOD_V  0x1
1043 #define RTC_CNTL_INC_HEARTBEAT_PERIOD_S  29
1044 /* RTC_CNTL_DEC_HEARTBEAT_PERIOD : R/W ;bitpos:[28] ;default: 1'd0 ; */
1045 /*description: DEC_HEARTBEAT_PERIOD*/
1046 #define RTC_CNTL_DEC_HEARTBEAT_PERIOD  (BIT(28))
1047 #define RTC_CNTL_DEC_HEARTBEAT_PERIOD_M  (BIT(28))
1048 #define RTC_CNTL_DEC_HEARTBEAT_PERIOD_V  0x1
1049 #define RTC_CNTL_DEC_HEARTBEAT_PERIOD_S  28
1050 /* RTC_CNTL_INC_HEARTBEAT_REFRESH : R/W ;bitpos:[27] ;default: 1'd0 ; */
1051 /*description: INC_HEARTBEAT_REFRESH*/
1052 #define RTC_CNTL_INC_HEARTBEAT_REFRESH  (BIT(27))
1053 #define RTC_CNTL_INC_HEARTBEAT_REFRESH_M  (BIT(27))
1054 #define RTC_CNTL_INC_HEARTBEAT_REFRESH_V  0x1
1055 #define RTC_CNTL_INC_HEARTBEAT_REFRESH_S  27
1056 /* RTC_CNTL_ENB_SCK_XTAL : R/W ;bitpos:[26] ;default: 1'd0 ; */
1057 /*description: ENB_SCK_XTAL*/
1058 #define RTC_CNTL_ENB_SCK_XTAL  (BIT(26))
1059 #define RTC_CNTL_ENB_SCK_XTAL_M  (BIT(26))
1060 #define RTC_CNTL_ENB_SCK_XTAL_V  0x1
1061 #define RTC_CNTL_ENB_SCK_XTAL_S  26
1062 /* RTC_CNTL_DBG_ATTEN : R/W ;bitpos:[25:24] ;default: 2'b00 ; */
1063 /*description: DBG_ATTEN*/
1064 #define RTC_CNTL_DBG_ATTEN  0x00000003
1065 #define RTC_CNTL_DBG_ATTEN_M  ((RTC_CNTL_DBG_ATTEN_V)<<(RTC_CNTL_DBG_ATTEN_S))
1066 #define RTC_CNTL_DBG_ATTEN_V  0x3
1067 #define RTC_CNTL_DBG_ATTEN_S  24
1068 #define RTC_CNTL_DBG_ATTEN_DEFAULT  3
1069 #define RTC_CNTL_DBG_ATTEN_NODROP   0
1070 #define RTC_CNTL_REG          (DR_REG_RTCCNTL_BASE + 0x7c)
1071 /* RTC_CNTL_FORCE_PU : R/W ;bitpos:[31] ;default: 1'd1 ; */
1072 /*description: RTC_REG force power up*/
1073 #define RTC_CNTL_FORCE_PU  (BIT(31))
1074 #define RTC_CNTL_FORCE_PU_M  (BIT(31))
1075 #define RTC_CNTL_FORCE_PU_V  0x1
1076 #define RTC_CNTL_FORCE_PU_S  31
1077 /* RTC_CNTL_FORCE_PD : R/W ;bitpos:[30] ;default: 1'd0 ; */
1078 /*description: RTC_REG force power down (for RTC_REG power down means decrease
1079  the voltage to 0.8v or lower )*/
1080 #define RTC_CNTL_FORCE_PD  (BIT(30))
1081 #define RTC_CNTL_FORCE_PD_M  (BIT(30))
1082 #define RTC_CNTL_FORCE_PD_V  0x1
1083 #define RTC_CNTL_FORCE_PD_S  30
1084 /* RTC_CNTL_DBOOST_FORCE_PU : R/W ;bitpos:[29] ;default: 1'd1 ; */
1085 /*description: RTC_DBOOST force power up*/
1086 #define RTC_CNTL_DBOOST_FORCE_PU  (BIT(29))
1087 #define RTC_CNTL_DBOOST_FORCE_PU_M  (BIT(29))
1088 #define RTC_CNTL_DBOOST_FORCE_PU_V  0x1
1089 #define RTC_CNTL_DBOOST_FORCE_PU_S  29
1090 /* RTC_CNTL_DBOOST_FORCE_PD : R/W ;bitpos:[28] ;default: 1'd0 ; */
1091 /*description: RTC_DBOOST force power down*/
1092 #define RTC_CNTL_DBOOST_FORCE_PD  (BIT(28))
1093 #define RTC_CNTL_DBOOST_FORCE_PD_M  (BIT(28))
1094 #define RTC_CNTL_DBOOST_FORCE_PD_V  0x1
1095 #define RTC_CNTL_DBOOST_FORCE_PD_S  28
1096 /* RTC_CNTL_DBIAS_WAK : R/W ;bitpos:[27:25] ;default: 3'd4 ; */
1097 /*description: RTC_DBIAS during wakeup*/
1098 #define RTC_CNTL_DBIAS_WAK  0x00000007
1099 #define RTC_CNTL_DBIAS_WAK_M  ((RTC_CNTL_DBIAS_WAK_V)<<(RTC_CNTL_DBIAS_WAK_S))
1100 #define RTC_CNTL_DBIAS_WAK_V  0x7
1101 #define RTC_CNTL_DBIAS_WAK_S  25
1102 /* RTC_CNTL_DBIAS_SLP : R/W ;bitpos:[24:22] ;default: 3'd4 ; */
1103 /*description: RTC_DBIAS during sleep*/
1104 #define RTC_CNTL_DBIAS_SLP  0x00000007
1105 #define RTC_CNTL_DBIAS_SLP_M  ((RTC_CNTL_DBIAS_SLP_V)<<(RTC_CNTL_DBIAS_SLP_S))
1106 #define RTC_CNTL_DBIAS_SLP_V  0x7
1107 #define RTC_CNTL_DBIAS_SLP_S  22
1108 /* RTC_CNTL_SCK_DCAP : R/W ;bitpos:[21:14] ;default: 8'd0 ; */
1109 /*description: SCK_DCAP*/
1110 #define RTC_CNTL_SCK_DCAP  0x000000FF
1111 #define RTC_CNTL_SCK_DCAP_M  ((RTC_CNTL_SCK_DCAP_V)<<(RTC_CNTL_SCK_DCAP_S))
1112 #define RTC_CNTL_SCK_DCAP_V  0xFF
1113 #define RTC_CNTL_SCK_DCAP_S  14
1114 #define RTC_CNTL_SCK_DCAP_DEFAULT   255
1115 /* RTC_CNTL_DIG_DBIAS_WAK : R/W ;bitpos:[13:11] ;default: 3'd4 ; */
1116 /*description: DIG_REG_DBIAS during wakeup*/
1117 #define RTC_CNTL_DIG_DBIAS_WAK  0x00000007
1118 #define RTC_CNTL_DIG_DBIAS_WAK_M  ((RTC_CNTL_DIG_DBIAS_WAK_V)<<(RTC_CNTL_DIG_DBIAS_WAK_S))
1119 #define RTC_CNTL_DIG_DBIAS_WAK_V  0x7
1120 #define RTC_CNTL_DIG_DBIAS_WAK_S  11
1121 /* RTC_CNTL_DIG_DBIAS_SLP : R/W ;bitpos:[10:8] ;default: 3'd4 ; */
1122 /*description: DIG_REG_DBIAS during sleep*/
1123 #define RTC_CNTL_DIG_DBIAS_SLP  0x00000007
1124 #define RTC_CNTL_DIG_DBIAS_SLP_M  ((RTC_CNTL_DIG_DBIAS_SLP_V)<<(RTC_CNTL_DIG_DBIAS_SLP_S))
1125 #define RTC_CNTL_DIG_DBIAS_SLP_V  0x7
1126 #define RTC_CNTL_DIG_DBIAS_SLP_S  8
1127 /* RTC_CNTL_SCK_DCAP_FORCE : R/W ;bitpos:[7] ;default: 1'd0 ; */
1128 /*description: N/A*/
1129 #define RTC_CNTL_SCK_DCAP_FORCE  (BIT(7))
1130 #define RTC_CNTL_SCK_DCAP_FORCE_M  (BIT(7))
1131 #define RTC_CNTL_SCK_DCAP_FORCE_V  0x1
1132 #define RTC_CNTL_SCK_DCAP_FORCE_S  7
1133 
1134 /* Approximate mapping of voltages to RTC_CNTL_DBIAS_WAK, RTC_CNTL_DBIAS_SLP,
1135  * RTC_CNTL_DIG_DBIAS_WAK, RTC_CNTL_DIG_DBIAS_SLP values.
1136  * Valid if RTC_CNTL_DBG_ATTEN is 0.
1137  */
1138 #define RTC_CNTL_DBIAS_0V90 0
1139 #define RTC_CNTL_DBIAS_0V95 1
1140 #define RTC_CNTL_DBIAS_1V00 2
1141 #define RTC_CNTL_DBIAS_1V05 3
1142 #define RTC_CNTL_DBIAS_1V10 4
1143 #define RTC_CNTL_DBIAS_1V15 5
1144 #define RTC_CNTL_DBIAS_1V20 6
1145 #define RTC_CNTL_DBIAS_1V25 7
1146 
1147 #define RTC_CNTL_PWC_REG          (DR_REG_RTCCNTL_BASE + 0x80)
1148 /* RTC_CNTL_PD_EN : R/W ;bitpos:[20] ;default: 1'd0 ; */
1149 /*description: enable power down rtc_peri in sleep*/
1150 #define RTC_CNTL_PD_EN  (BIT(20))
1151 #define RTC_CNTL_PD_EN_M  (BIT(20))
1152 #define RTC_CNTL_PD_EN_V  0x1
1153 #define RTC_CNTL_PD_EN_S  20
1154 /* RTC_CNTL_FORCE_PU : R/W ;bitpos:[19] ;default: 1'd0 ; */
1155 /*description: rtc_peri force power up*/
1156 #define RTC_CNTL_PWC_FORCE_PU  (BIT(19))
1157 #define RTC_CNTL_PWC_FORCE_PU_M  (BIT(19))
1158 #define RTC_CNTL_PWC_FORCE_PU_V  0x1
1159 #define RTC_CNTL_PWC_FORCE_PU_S  19
1160 /* RTC_CNTL_FORCE_PD : R/W ;bitpos:[18] ;default: 1'b0 ; */
1161 /*description: rtc_peri force power down*/
1162 #define RTC_CNTL_PWC_FORCE_PD  (BIT(18))
1163 #define RTC_CNTL_PWC_FORCE_PD_M  (BIT(18))
1164 #define RTC_CNTL_PWC_FORCE_PD_V  0x1
1165 #define RTC_CNTL_PWC_FORCE_PD_S  18
1166 /* RTC_CNTL_SLOWMEM_PD_EN : R/W ;bitpos:[17] ;default: 1'b0 ; */
1167 /*description: enable power down RTC memory in sleep*/
1168 #define RTC_CNTL_SLOWMEM_PD_EN  (BIT(17))
1169 #define RTC_CNTL_SLOWMEM_PD_EN_M  (BIT(17))
1170 #define RTC_CNTL_SLOWMEM_PD_EN_V  0x1
1171 #define RTC_CNTL_SLOWMEM_PD_EN_S  17
1172 /* RTC_CNTL_SLOWMEM_FORCE_PU : R/W ;bitpos:[16] ;default: 1'b1 ; */
1173 /*description: RTC memory force power up*/
1174 #define RTC_CNTL_SLOWMEM_FORCE_PU  (BIT(16))
1175 #define RTC_CNTL_SLOWMEM_FORCE_PU_M  (BIT(16))
1176 #define RTC_CNTL_SLOWMEM_FORCE_PU_V  0x1
1177 #define RTC_CNTL_SLOWMEM_FORCE_PU_S  16
1178 /* RTC_CNTL_SLOWMEM_FORCE_PD : R/W ;bitpos:[15] ;default: 1'b0 ; */
1179 /*description: RTC memory force power down*/
1180 #define RTC_CNTL_SLOWMEM_FORCE_PD  (BIT(15))
1181 #define RTC_CNTL_SLOWMEM_FORCE_PD_M  (BIT(15))
1182 #define RTC_CNTL_SLOWMEM_FORCE_PD_V  0x1
1183 #define RTC_CNTL_SLOWMEM_FORCE_PD_S  15
1184 /* RTC_CNTL_FASTMEM_PD_EN : R/W ;bitpos:[14] ;default: 1'b0 ; */
1185 /*description: enable power down fast RTC memory in sleep*/
1186 #define RTC_CNTL_FASTMEM_PD_EN  (BIT(14))
1187 #define RTC_CNTL_FASTMEM_PD_EN_M  (BIT(14))
1188 #define RTC_CNTL_FASTMEM_PD_EN_V  0x1
1189 #define RTC_CNTL_FASTMEM_PD_EN_S  14
1190 /* RTC_CNTL_FASTMEM_FORCE_PU : R/W ;bitpos:[13] ;default: 1'b1 ; */
1191 /*description: Fast RTC memory force power up*/
1192 #define RTC_CNTL_FASTMEM_FORCE_PU  (BIT(13))
1193 #define RTC_CNTL_FASTMEM_FORCE_PU_M  (BIT(13))
1194 #define RTC_CNTL_FASTMEM_FORCE_PU_V  0x1
1195 #define RTC_CNTL_FASTMEM_FORCE_PU_S  13
1196 /* RTC_CNTL_FASTMEM_FORCE_PD : R/W ;bitpos:[12] ;default: 1'b0 ; */
1197 /*description: Fast RTC memory force power down*/
1198 #define RTC_CNTL_FASTMEM_FORCE_PD  (BIT(12))
1199 #define RTC_CNTL_FASTMEM_FORCE_PD_M  (BIT(12))
1200 #define RTC_CNTL_FASTMEM_FORCE_PD_V  0x1
1201 #define RTC_CNTL_FASTMEM_FORCE_PD_S  12
1202 /* RTC_CNTL_SLOWMEM_FORCE_LPU : R/W ;bitpos:[11] ;default: 1'b1 ; */
1203 /*description: RTC memory force no PD*/
1204 #define RTC_CNTL_SLOWMEM_FORCE_LPU  (BIT(11))
1205 #define RTC_CNTL_SLOWMEM_FORCE_LPU_M  (BIT(11))
1206 #define RTC_CNTL_SLOWMEM_FORCE_LPU_V  0x1
1207 #define RTC_CNTL_SLOWMEM_FORCE_LPU_S  11
1208 /* RTC_CNTL_SLOWMEM_FORCE_LPD : R/W ;bitpos:[10] ;default: 1'b0 ; */
1209 /*description: RTC memory force PD*/
1210 #define RTC_CNTL_SLOWMEM_FORCE_LPD  (BIT(10))
1211 #define RTC_CNTL_SLOWMEM_FORCE_LPD_M  (BIT(10))
1212 #define RTC_CNTL_SLOWMEM_FORCE_LPD_V  0x1
1213 #define RTC_CNTL_SLOWMEM_FORCE_LPD_S  10
1214 /* RTC_CNTL_SLOWMEM_FOLW_CPU : R/W ;bitpos:[9] ;default: 1'b0 ; */
1215 /*description: 1: RTC memory  PD following CPU  0: RTC memory PD following RTC state machine*/
1216 #define RTC_CNTL_SLOWMEM_FOLW_CPU  (BIT(9))
1217 #define RTC_CNTL_SLOWMEM_FOLW_CPU_M  (BIT(9))
1218 #define RTC_CNTL_SLOWMEM_FOLW_CPU_V  0x1
1219 #define RTC_CNTL_SLOWMEM_FOLW_CPU_S  9
1220 /* RTC_CNTL_FASTMEM_FORCE_LPU : R/W ;bitpos:[8] ;default: 1'b1 ; */
1221 /*description: Fast RTC memory force no PD*/
1222 #define RTC_CNTL_FASTMEM_FORCE_LPU  (BIT(8))
1223 #define RTC_CNTL_FASTMEM_FORCE_LPU_M  (BIT(8))
1224 #define RTC_CNTL_FASTMEM_FORCE_LPU_V  0x1
1225 #define RTC_CNTL_FASTMEM_FORCE_LPU_S  8
1226 /* RTC_CNTL_FASTMEM_FORCE_LPD : R/W ;bitpos:[7] ;default: 1'b0 ; */
1227 /*description: Fast RTC memory force PD*/
1228 #define RTC_CNTL_FASTMEM_FORCE_LPD  (BIT(7))
1229 #define RTC_CNTL_FASTMEM_FORCE_LPD_M  (BIT(7))
1230 #define RTC_CNTL_FASTMEM_FORCE_LPD_V  0x1
1231 #define RTC_CNTL_FASTMEM_FORCE_LPD_S  7
1232 /* RTC_CNTL_FASTMEM_FOLW_CPU : R/W ;bitpos:[6] ;default: 1'b0 ; */
1233 /*description: 1: Fast RTC memory PD following CPU  0: fast RTC memory PD following
1234  RTC state machine*/
1235 #define RTC_CNTL_FASTMEM_FOLW_CPU  (BIT(6))
1236 #define RTC_CNTL_FASTMEM_FOLW_CPU_M  (BIT(6))
1237 #define RTC_CNTL_FASTMEM_FOLW_CPU_V  0x1
1238 #define RTC_CNTL_FASTMEM_FOLW_CPU_S  6
1239 /* RTC_CNTL_FORCE_NOISO : R/W ;bitpos:[5] ;default: 1'd1 ; */
1240 /*description: rtc_peri force no ISO*/
1241 #define RTC_CNTL_FORCE_NOISO  (BIT(5))
1242 #define RTC_CNTL_FORCE_NOISO_M  (BIT(5))
1243 #define RTC_CNTL_FORCE_NOISO_V  0x1
1244 #define RTC_CNTL_FORCE_NOISO_S  5
1245 /* RTC_CNTL_FORCE_ISO : R/W ;bitpos:[4] ;default: 1'd0 ; */
1246 /*description: rtc_peri force ISO*/
1247 #define RTC_CNTL_FORCE_ISO  (BIT(4))
1248 #define RTC_CNTL_FORCE_ISO_M  (BIT(4))
1249 #define RTC_CNTL_FORCE_ISO_V  0x1
1250 #define RTC_CNTL_FORCE_ISO_S  4
1251 /* RTC_CNTL_SLOWMEM_FORCE_ISO : R/W ;bitpos:[3] ;default: 1'b0 ; */
1252 /*description: RTC memory force ISO*/
1253 #define RTC_CNTL_SLOWMEM_FORCE_ISO  (BIT(3))
1254 #define RTC_CNTL_SLOWMEM_FORCE_ISO_M  (BIT(3))
1255 #define RTC_CNTL_SLOWMEM_FORCE_ISO_V  0x1
1256 #define RTC_CNTL_SLOWMEM_FORCE_ISO_S  3
1257 /* RTC_CNTL_SLOWMEM_FORCE_NOISO : R/W ;bitpos:[2] ;default: 1'b1 ; */
1258 /*description: RTC memory force no ISO*/
1259 #define RTC_CNTL_SLOWMEM_FORCE_NOISO  (BIT(2))
1260 #define RTC_CNTL_SLOWMEM_FORCE_NOISO_M  (BIT(2))
1261 #define RTC_CNTL_SLOWMEM_FORCE_NOISO_V  0x1
1262 #define RTC_CNTL_SLOWMEM_FORCE_NOISO_S  2
1263 /* RTC_CNTL_FASTMEM_FORCE_ISO : R/W ;bitpos:[1] ;default: 1'b0 ; */
1264 /*description: Fast RTC memory force ISO*/
1265 #define RTC_CNTL_FASTMEM_FORCE_ISO  (BIT(1))
1266 #define RTC_CNTL_FASTMEM_FORCE_ISO_M  (BIT(1))
1267 #define RTC_CNTL_FASTMEM_FORCE_ISO_V  0x1
1268 #define RTC_CNTL_FASTMEM_FORCE_ISO_S  1
1269 /* RTC_CNTL_FASTMEM_FORCE_NOISO : R/W ;bitpos:[0] ;default: 1'b1 ; */
1270 /*description: Fast RTC memory force no ISO*/
1271 #define RTC_CNTL_FASTMEM_FORCE_NOISO  (BIT(0))
1272 #define RTC_CNTL_FASTMEM_FORCE_NOISO_M  (BIT(0))
1273 #define RTC_CNTL_FASTMEM_FORCE_NOISO_V  0x1
1274 #define RTC_CNTL_FASTMEM_FORCE_NOISO_S  0
1275 
1276 /* Useful groups of RTC_CNTL_PWC_REG bits */
1277 #define RTC_CNTL_MEM_FORCE_ISO    \
1278     (RTC_CNTL_SLOWMEM_FORCE_ISO | RTC_CNTL_FASTMEM_FORCE_ISO)
1279 #define RTC_CNTL_MEM_FORCE_NOISO  \
1280     (RTC_CNTL_SLOWMEM_FORCE_NOISO | RTC_CNTL_FASTMEM_FORCE_NOISO)
1281 #define RTC_CNTL_MEM_PD_EN        \
1282     (RTC_CNTL_SLOWMEM_PD_EN | RTC_CNTL_FASTMEM_PD_EN)
1283 #define RTC_CNTL_MEM_FORCE_PU     \
1284     (RTC_CNTL_SLOWMEM_FORCE_PU | RTC_CNTL_FASTMEM_FORCE_PU)
1285 #define RTC_CNTL_MEM_FORCE_PD     \
1286     (RTC_CNTL_SLOWMEM_FORCE_PD | RTC_CNTL_FASTMEM_FORCE_PD)
1287 #define RTC_CNTL_MEM_FOLW_CPU     \
1288     (RTC_CNTL_SLOWMEM_FOLW_CPU | RTC_CNTL_FASTMEM_FOLW_CPU)
1289 #define RTC_CNTL_MEM_FORCE_LPU    \
1290     (RTC_CNTL_SLOWMEM_FORCE_LPU | RTC_CNTL_FASTMEM_FORCE_LPU)
1291 #define RTC_CNTL_MEM_FORCE_LPD    \
1292     (RTC_CNTL_SLOWMEM_FORCE_LPD | RTC_CNTL_FASTMEM_FORCE_LPD)
1293 
1294 #define RTC_CNTL_DIG_PWC_REG          (DR_REG_RTCCNTL_BASE + 0x84)
1295 /* RTC_CNTL_DG_WRAP_PD_EN : R/W ;bitpos:[31] ;default: 0 ; */
1296 /*description: enable power down digital core in sleep*/
1297 #define RTC_CNTL_DG_WRAP_PD_EN  (BIT(31))
1298 #define RTC_CNTL_DG_WRAP_PD_EN_M  (BIT(31))
1299 #define RTC_CNTL_DG_WRAP_PD_EN_V  0x1
1300 #define RTC_CNTL_DG_WRAP_PD_EN_S  31
1301 /* RTC_CNTL_WIFI_PD_EN : R/W ;bitpos:[30] ;default: 0 ; */
1302 /*description: enable power down wifi in sleep*/
1303 #define RTC_CNTL_WIFI_PD_EN  (BIT(30))
1304 #define RTC_CNTL_WIFI_PD_EN_M  (BIT(30))
1305 #define RTC_CNTL_WIFI_PD_EN_V  0x1
1306 #define RTC_CNTL_WIFI_PD_EN_S  30
1307 /* RTC_CNTL_INTER_RAM4_PD_EN : R/W ;bitpos:[29] ;default: 0 ; */
1308 /*description: enable power down internal SRAM 4 in sleep*/
1309 #define RTC_CNTL_INTER_RAM4_PD_EN  (BIT(29))
1310 #define RTC_CNTL_INTER_RAM4_PD_EN_M  (BIT(29))
1311 #define RTC_CNTL_INTER_RAM4_PD_EN_V  0x1
1312 #define RTC_CNTL_INTER_RAM4_PD_EN_S  29
1313 /* RTC_CNTL_INTER_RAM3_PD_EN : R/W ;bitpos:[28] ;default: 0 ; */
1314 /*description: enable power down internal SRAM 3 in sleep*/
1315 #define RTC_CNTL_INTER_RAM3_PD_EN  (BIT(28))
1316 #define RTC_CNTL_INTER_RAM3_PD_EN_M  (BIT(28))
1317 #define RTC_CNTL_INTER_RAM3_PD_EN_V  0x1
1318 #define RTC_CNTL_INTER_RAM3_PD_EN_S  28
1319 /* RTC_CNTL_INTER_RAM2_PD_EN : R/W ;bitpos:[27] ;default: 0 ; */
1320 /*description: enable power down internal SRAM 2 in sleep*/
1321 #define RTC_CNTL_INTER_RAM2_PD_EN  (BIT(27))
1322 #define RTC_CNTL_INTER_RAM2_PD_EN_M  (BIT(27))
1323 #define RTC_CNTL_INTER_RAM2_PD_EN_V  0x1
1324 #define RTC_CNTL_INTER_RAM2_PD_EN_S  27
1325 /* RTC_CNTL_INTER_RAM1_PD_EN : R/W ;bitpos:[26] ;default: 0 ; */
1326 /*description: enable power down internal SRAM 1 in sleep*/
1327 #define RTC_CNTL_INTER_RAM1_PD_EN  (BIT(26))
1328 #define RTC_CNTL_INTER_RAM1_PD_EN_M  (BIT(26))
1329 #define RTC_CNTL_INTER_RAM1_PD_EN_V  0x1
1330 #define RTC_CNTL_INTER_RAM1_PD_EN_S  26
1331 /* RTC_CNTL_INTER_RAM0_PD_EN : R/W ;bitpos:[25] ;default: 0 ; */
1332 /*description: enable power down internal SRAM 0 in sleep*/
1333 #define RTC_CNTL_INTER_RAM0_PD_EN  (BIT(25))
1334 #define RTC_CNTL_INTER_RAM0_PD_EN_M  (BIT(25))
1335 #define RTC_CNTL_INTER_RAM0_PD_EN_V  0x1
1336 #define RTC_CNTL_INTER_RAM0_PD_EN_S  25
1337 /* RTC_CNTL_ROM0_PD_EN : R/W ;bitpos:[24] ;default: 0 ; */
1338 /*description: enable power down ROM in sleep*/
1339 #define RTC_CNTL_ROM0_PD_EN  (BIT(24))
1340 #define RTC_CNTL_ROM0_PD_EN_M  (BIT(24))
1341 #define RTC_CNTL_ROM0_PD_EN_V  0x1
1342 #define RTC_CNTL_ROM0_PD_EN_S  24
1343 /* RTC_CNTL_DG_WRAP_FORCE_PU : R/W ;bitpos:[20] ;default: 1'd1 ; */
1344 /*description: digital core force power up*/
1345 #define RTC_CNTL_DG_WRAP_FORCE_PU  (BIT(20))
1346 #define RTC_CNTL_DG_WRAP_FORCE_PU_M  (BIT(20))
1347 #define RTC_CNTL_DG_WRAP_FORCE_PU_V  0x1
1348 #define RTC_CNTL_DG_WRAP_FORCE_PU_S  20
1349 /* RTC_CNTL_DG_WRAP_FORCE_PD : R/W ;bitpos:[19] ;default: 1'b0 ; */
1350 /*description: digital core force power down*/
1351 #define RTC_CNTL_DG_WRAP_FORCE_PD  (BIT(19))
1352 #define RTC_CNTL_DG_WRAP_FORCE_PD_M  (BIT(19))
1353 #define RTC_CNTL_DG_WRAP_FORCE_PD_V  0x1
1354 #define RTC_CNTL_DG_WRAP_FORCE_PD_S  19
1355 /* RTC_CNTL_WIFI_FORCE_PU : R/W ;bitpos:[18] ;default: 1'd1 ; */
1356 /*description: wifi force power up*/
1357 #define RTC_CNTL_WIFI_FORCE_PU  (BIT(18))
1358 #define RTC_CNTL_WIFI_FORCE_PU_M  (BIT(18))
1359 #define RTC_CNTL_WIFI_FORCE_PU_V  0x1
1360 #define RTC_CNTL_WIFI_FORCE_PU_S  18
1361 /* RTC_CNTL_WIFI_FORCE_PD : R/W ;bitpos:[17] ;default: 1'b0 ; */
1362 /*description: wifi force power down*/
1363 #define RTC_CNTL_WIFI_FORCE_PD  (BIT(17))
1364 #define RTC_CNTL_WIFI_FORCE_PD_M  (BIT(17))
1365 #define RTC_CNTL_WIFI_FORCE_PD_V  0x1
1366 #define RTC_CNTL_WIFI_FORCE_PD_S  17
1367 /* RTC_CNTL_INTER_RAM4_FORCE_PU : R/W ;bitpos:[16] ;default: 1'd1 ; */
1368 /*description: internal SRAM 4 force power up*/
1369 #define RTC_CNTL_INTER_RAM4_FORCE_PU  (BIT(16))
1370 #define RTC_CNTL_INTER_RAM4_FORCE_PU_M  (BIT(16))
1371 #define RTC_CNTL_INTER_RAM4_FORCE_PU_V  0x1
1372 #define RTC_CNTL_INTER_RAM4_FORCE_PU_S  16
1373 /* RTC_CNTL_INTER_RAM4_FORCE_PD : R/W ;bitpos:[15] ;default: 1'b0 ; */
1374 /*description: internal SRAM 4 force power down*/
1375 #define RTC_CNTL_INTER_RAM4_FORCE_PD  (BIT(15))
1376 #define RTC_CNTL_INTER_RAM4_FORCE_PD_M  (BIT(15))
1377 #define RTC_CNTL_INTER_RAM4_FORCE_PD_V  0x1
1378 #define RTC_CNTL_INTER_RAM4_FORCE_PD_S  15
1379 /* RTC_CNTL_INTER_RAM3_FORCE_PU : R/W ;bitpos:[14] ;default: 1'd1 ; */
1380 /*description: internal SRAM 3 force power up*/
1381 #define RTC_CNTL_INTER_RAM3_FORCE_PU  (BIT(14))
1382 #define RTC_CNTL_INTER_RAM3_FORCE_PU_M  (BIT(14))
1383 #define RTC_CNTL_INTER_RAM3_FORCE_PU_V  0x1
1384 #define RTC_CNTL_INTER_RAM3_FORCE_PU_S  14
1385 /* RTC_CNTL_INTER_RAM3_FORCE_PD : R/W ;bitpos:[13] ;default: 1'b0 ; */
1386 /*description: internal SRAM 3 force power down*/
1387 #define RTC_CNTL_INTER_RAM3_FORCE_PD  (BIT(13))
1388 #define RTC_CNTL_INTER_RAM3_FORCE_PD_M  (BIT(13))
1389 #define RTC_CNTL_INTER_RAM3_FORCE_PD_V  0x1
1390 #define RTC_CNTL_INTER_RAM3_FORCE_PD_S  13
1391 /* RTC_CNTL_INTER_RAM2_FORCE_PU : R/W ;bitpos:[12] ;default: 1'd1 ; */
1392 /*description: internal SRAM 2 force power up*/
1393 #define RTC_CNTL_INTER_RAM2_FORCE_PU  (BIT(12))
1394 #define RTC_CNTL_INTER_RAM2_FORCE_PU_M  (BIT(12))
1395 #define RTC_CNTL_INTER_RAM2_FORCE_PU_V  0x1
1396 #define RTC_CNTL_INTER_RAM2_FORCE_PU_S  12
1397 /* RTC_CNTL_INTER_RAM2_FORCE_PD : R/W ;bitpos:[11] ;default: 1'b0 ; */
1398 /*description: internal SRAM 2 force power down*/
1399 #define RTC_CNTL_INTER_RAM2_FORCE_PD  (BIT(11))
1400 #define RTC_CNTL_INTER_RAM2_FORCE_PD_M  (BIT(11))
1401 #define RTC_CNTL_INTER_RAM2_FORCE_PD_V  0x1
1402 #define RTC_CNTL_INTER_RAM2_FORCE_PD_S  11
1403 /* RTC_CNTL_INTER_RAM1_FORCE_PU : R/W ;bitpos:[10] ;default: 1'd1 ; */
1404 /*description: internal SRAM 1 force power up*/
1405 #define RTC_CNTL_INTER_RAM1_FORCE_PU  (BIT(10))
1406 #define RTC_CNTL_INTER_RAM1_FORCE_PU_M  (BIT(10))
1407 #define RTC_CNTL_INTER_RAM1_FORCE_PU_V  0x1
1408 #define RTC_CNTL_INTER_RAM1_FORCE_PU_S  10
1409 /* RTC_CNTL_INTER_RAM1_FORCE_PD : R/W ;bitpos:[9] ;default: 1'b0 ; */
1410 /*description: internal SRAM 1 force power down*/
1411 #define RTC_CNTL_INTER_RAM1_FORCE_PD  (BIT(9))
1412 #define RTC_CNTL_INTER_RAM1_FORCE_PD_M  (BIT(9))
1413 #define RTC_CNTL_INTER_RAM1_FORCE_PD_V  0x1
1414 #define RTC_CNTL_INTER_RAM1_FORCE_PD_S  9
1415 /* RTC_CNTL_INTER_RAM0_FORCE_PU : R/W ;bitpos:[8] ;default: 1'd1 ; */
1416 /*description: internal SRAM 0 force power up*/
1417 #define RTC_CNTL_INTER_RAM0_FORCE_PU  (BIT(8))
1418 #define RTC_CNTL_INTER_RAM0_FORCE_PU_M  (BIT(8))
1419 #define RTC_CNTL_INTER_RAM0_FORCE_PU_V  0x1
1420 #define RTC_CNTL_INTER_RAM0_FORCE_PU_S  8
1421 /* RTC_CNTL_INTER_RAM0_FORCE_PD : R/W ;bitpos:[7] ;default: 1'b0 ; */
1422 /*description: internal SRAM 0 force power down*/
1423 #define RTC_CNTL_INTER_RAM0_FORCE_PD  (BIT(7))
1424 #define RTC_CNTL_INTER_RAM0_FORCE_PD_M  (BIT(7))
1425 #define RTC_CNTL_INTER_RAM0_FORCE_PD_V  0x1
1426 #define RTC_CNTL_INTER_RAM0_FORCE_PD_S  7
1427 /* RTC_CNTL_ROM0_FORCE_PU : R/W ;bitpos:[6] ;default: 1'd1 ; */
1428 /*description: ROM force power up*/
1429 #define RTC_CNTL_ROM0_FORCE_PU  (BIT(6))
1430 #define RTC_CNTL_ROM0_FORCE_PU_M  (BIT(6))
1431 #define RTC_CNTL_ROM0_FORCE_PU_V  0x1
1432 #define RTC_CNTL_ROM0_FORCE_PU_S  6
1433 /* RTC_CNTL_ROM0_FORCE_PD : R/W ;bitpos:[5] ;default: 1'b0 ; */
1434 /*description: ROM force power down*/
1435 #define RTC_CNTL_ROM0_FORCE_PD  (BIT(5))
1436 #define RTC_CNTL_ROM0_FORCE_PD_M  (BIT(5))
1437 #define RTC_CNTL_ROM0_FORCE_PD_V  0x1
1438 #define RTC_CNTL_ROM0_FORCE_PD_S  5
1439 /* RTC_CNTL_LSLP_MEM_FORCE_PU : R/W ;bitpos:[4] ;default: 1'b1 ; */
1440 /*description: memories in digital core force no PD in sleep*/
1441 #define RTC_CNTL_LSLP_MEM_FORCE_PU  (BIT(4))
1442 #define RTC_CNTL_LSLP_MEM_FORCE_PU_M  (BIT(4))
1443 #define RTC_CNTL_LSLP_MEM_FORCE_PU_V  0x1
1444 #define RTC_CNTL_LSLP_MEM_FORCE_PU_S  4
1445 /* RTC_CNTL_LSLP_MEM_FORCE_PD : R/W ;bitpos:[3] ;default: 1'b0 ; */
1446 /*description: memories in digital core force PD in sleep*/
1447 #define RTC_CNTL_LSLP_MEM_FORCE_PD  (BIT(3))
1448 #define RTC_CNTL_LSLP_MEM_FORCE_PD_M  (BIT(3))
1449 #define RTC_CNTL_LSLP_MEM_FORCE_PD_V  0x1
1450 #define RTC_CNTL_LSLP_MEM_FORCE_PD_S  3
1451 
1452 /* Useful groups of RTC_CNTL_DIG_PWC_REG bits */
1453 #define RTC_CNTL_CPU_ROM_RAM_PD_EN \
1454     (RTC_CNTL_INTER_RAM4_PD_EN | RTC_CNTL_INTER_RAM3_PD_EN |\
1455      RTC_CNTL_INTER_RAM2_PD_EN | RTC_CNTL_INTER_RAM1_PD_EN |\
1456      RTC_CNTL_INTER_RAM0_PD_EN | RTC_CNTL_ROM0_PD_EN)
1457 #define RTC_CNTL_CPU_ROM_RAM_FORCE_PU \
1458     (RTC_CNTL_INTER_RAM4_FORCE_PU | RTC_CNTL_INTER_RAM3_FORCE_PU |\
1459      RTC_CNTL_INTER_RAM2_FORCE_PU | RTC_CNTL_INTER_RAM1_FORCE_PU |\
1460      RTC_CNTL_INTER_RAM0_FORCE_PU | RTC_CNTL_ROM0_FORCE_PU)
1461 #define RTC_CNTL_CPU_ROM_RAM_FORCE_PD \
1462     (RTC_CNTL_INTER_RAM4_FORCE_PD | RTC_CNTL_INTER_RAM3_FORCE_PD |\
1463      RTC_CNTL_INTER_RAM2_FORCE_PD | RTC_CNTL_INTER_RAM1_FORCE_PD |\
1464      RTC_CNTL_INTER_RAM0_FORCE_PD | RTC_CNTL_ROM0_FORCE_PD
1465 
1466 #define RTC_CNTL_DIG_ISO_REG          (DR_REG_RTCCNTL_BASE + 0x88)
1467 /* RTC_CNTL_DG_WRAP_FORCE_NOISO : R/W ;bitpos:[31] ;default: 1'd1 ; */
1468 /*description: digital core force no ISO*/
1469 #define RTC_CNTL_DG_WRAP_FORCE_NOISO  (BIT(31))
1470 #define RTC_CNTL_DG_WRAP_FORCE_NOISO_M  (BIT(31))
1471 #define RTC_CNTL_DG_WRAP_FORCE_NOISO_V  0x1
1472 #define RTC_CNTL_DG_WRAP_FORCE_NOISO_S  31
1473 /* RTC_CNTL_DG_WRAP_FORCE_ISO : R/W ;bitpos:[30] ;default: 1'd0 ; */
1474 /*description: digital core force ISO*/
1475 #define RTC_CNTL_DG_WRAP_FORCE_ISO  (BIT(30))
1476 #define RTC_CNTL_DG_WRAP_FORCE_ISO_M  (BIT(30))
1477 #define RTC_CNTL_DG_WRAP_FORCE_ISO_V  0x1
1478 #define RTC_CNTL_DG_WRAP_FORCE_ISO_S  30
1479 /* RTC_CNTL_WIFI_FORCE_NOISO : R/W ;bitpos:[29] ;default: 1'd1 ; */
1480 /*description: wifi force no ISO*/
1481 #define RTC_CNTL_WIFI_FORCE_NOISO  (BIT(29))
1482 #define RTC_CNTL_WIFI_FORCE_NOISO_M  (BIT(29))
1483 #define RTC_CNTL_WIFI_FORCE_NOISO_V  0x1
1484 #define RTC_CNTL_WIFI_FORCE_NOISO_S  29
1485 /* RTC_CNTL_WIFI_FORCE_ISO : R/W ;bitpos:[28] ;default: 1'd0 ; */
1486 /*description: wifi force ISO*/
1487 #define RTC_CNTL_WIFI_FORCE_ISO  (BIT(28))
1488 #define RTC_CNTL_WIFI_FORCE_ISO_M  (BIT(28))
1489 #define RTC_CNTL_WIFI_FORCE_ISO_V  0x1
1490 #define RTC_CNTL_WIFI_FORCE_ISO_S  28
1491 /* RTC_CNTL_INTER_RAM4_FORCE_NOISO : R/W ;bitpos:[27] ;default: 1'd1 ; */
1492 /*description: internal SRAM 4 force no ISO*/
1493 #define RTC_CNTL_INTER_RAM4_FORCE_NOISO  (BIT(27))
1494 #define RTC_CNTL_INTER_RAM4_FORCE_NOISO_M  (BIT(27))
1495 #define RTC_CNTL_INTER_RAM4_FORCE_NOISO_V  0x1
1496 #define RTC_CNTL_INTER_RAM4_FORCE_NOISO_S  27
1497 /* RTC_CNTL_INTER_RAM4_FORCE_ISO : R/W ;bitpos:[26] ;default: 1'd0 ; */
1498 /*description: internal SRAM 4 force ISO*/
1499 #define RTC_CNTL_INTER_RAM4_FORCE_ISO  (BIT(26))
1500 #define RTC_CNTL_INTER_RAM4_FORCE_ISO_M  (BIT(26))
1501 #define RTC_CNTL_INTER_RAM4_FORCE_ISO_V  0x1
1502 #define RTC_CNTL_INTER_RAM4_FORCE_ISO_S  26
1503 /* RTC_CNTL_INTER_RAM3_FORCE_NOISO : R/W ;bitpos:[25] ;default: 1'd1 ; */
1504 /*description: internal SRAM 3 force no ISO*/
1505 #define RTC_CNTL_INTER_RAM3_FORCE_NOISO  (BIT(25))
1506 #define RTC_CNTL_INTER_RAM3_FORCE_NOISO_M  (BIT(25))
1507 #define RTC_CNTL_INTER_RAM3_FORCE_NOISO_V  0x1
1508 #define RTC_CNTL_INTER_RAM3_FORCE_NOISO_S  25
1509 /* RTC_CNTL_INTER_RAM3_FORCE_ISO : R/W ;bitpos:[24] ;default: 1'd0 ; */
1510 /*description: internal SRAM 3 force ISO*/
1511 #define RTC_CNTL_INTER_RAM3_FORCE_ISO  (BIT(24))
1512 #define RTC_CNTL_INTER_RAM3_FORCE_ISO_M  (BIT(24))
1513 #define RTC_CNTL_INTER_RAM3_FORCE_ISO_V  0x1
1514 #define RTC_CNTL_INTER_RAM3_FORCE_ISO_S  24
1515 /* RTC_CNTL_INTER_RAM2_FORCE_NOISO : R/W ;bitpos:[23] ;default: 1'd1 ; */
1516 /*description: internal SRAM 2 force no ISO*/
1517 #define RTC_CNTL_INTER_RAM2_FORCE_NOISO  (BIT(23))
1518 #define RTC_CNTL_INTER_RAM2_FORCE_NOISO_M  (BIT(23))
1519 #define RTC_CNTL_INTER_RAM2_FORCE_NOISO_V  0x1
1520 #define RTC_CNTL_INTER_RAM2_FORCE_NOISO_S  23
1521 /* RTC_CNTL_INTER_RAM2_FORCE_ISO : R/W ;bitpos:[22] ;default: 1'd0 ; */
1522 /*description: internal SRAM 2 force ISO*/
1523 #define RTC_CNTL_INTER_RAM2_FORCE_ISO  (BIT(22))
1524 #define RTC_CNTL_INTER_RAM2_FORCE_ISO_M  (BIT(22))
1525 #define RTC_CNTL_INTER_RAM2_FORCE_ISO_V  0x1
1526 #define RTC_CNTL_INTER_RAM2_FORCE_ISO_S  22
1527 /* RTC_CNTL_INTER_RAM1_FORCE_NOISO : R/W ;bitpos:[21] ;default: 1'd1 ; */
1528 /*description: internal SRAM 1 force no ISO*/
1529 #define RTC_CNTL_INTER_RAM1_FORCE_NOISO  (BIT(21))
1530 #define RTC_CNTL_INTER_RAM1_FORCE_NOISO_M  (BIT(21))
1531 #define RTC_CNTL_INTER_RAM1_FORCE_NOISO_V  0x1
1532 #define RTC_CNTL_INTER_RAM1_FORCE_NOISO_S  21
1533 /* RTC_CNTL_INTER_RAM1_FORCE_ISO : R/W ;bitpos:[20] ;default: 1'd0 ; */
1534 /*description: internal SRAM 1 force ISO*/
1535 #define RTC_CNTL_INTER_RAM1_FORCE_ISO  (BIT(20))
1536 #define RTC_CNTL_INTER_RAM1_FORCE_ISO_M  (BIT(20))
1537 #define RTC_CNTL_INTER_RAM1_FORCE_ISO_V  0x1
1538 #define RTC_CNTL_INTER_RAM1_FORCE_ISO_S  20
1539 /* RTC_CNTL_INTER_RAM0_FORCE_NOISO : R/W ;bitpos:[19] ;default: 1'd1 ; */
1540 /*description: internal SRAM 0 force no ISO*/
1541 #define RTC_CNTL_INTER_RAM0_FORCE_NOISO  (BIT(19))
1542 #define RTC_CNTL_INTER_RAM0_FORCE_NOISO_M  (BIT(19))
1543 #define RTC_CNTL_INTER_RAM0_FORCE_NOISO_V  0x1
1544 #define RTC_CNTL_INTER_RAM0_FORCE_NOISO_S  19
1545 /* RTC_CNTL_INTER_RAM0_FORCE_ISO : R/W ;bitpos:[18] ;default: 1'd0 ; */
1546 /*description: internal SRAM 0 force ISO*/
1547 #define RTC_CNTL_INTER_RAM0_FORCE_ISO  (BIT(18))
1548 #define RTC_CNTL_INTER_RAM0_FORCE_ISO_M  (BIT(18))
1549 #define RTC_CNTL_INTER_RAM0_FORCE_ISO_V  0x1
1550 #define RTC_CNTL_INTER_RAM0_FORCE_ISO_S  18
1551 /* RTC_CNTL_ROM0_FORCE_NOISO : R/W ;bitpos:[17] ;default: 1'd1 ; */
1552 /*description: ROM force no ISO*/
1553 #define RTC_CNTL_ROM0_FORCE_NOISO  (BIT(17))
1554 #define RTC_CNTL_ROM0_FORCE_NOISO_M  (BIT(17))
1555 #define RTC_CNTL_ROM0_FORCE_NOISO_V  0x1
1556 #define RTC_CNTL_ROM0_FORCE_NOISO_S  17
1557 /* RTC_CNTL_ROM0_FORCE_ISO : R/W ;bitpos:[16] ;default: 1'd0 ; */
1558 /*description: ROM force ISO*/
1559 #define RTC_CNTL_ROM0_FORCE_ISO  (BIT(16))
1560 #define RTC_CNTL_ROM0_FORCE_ISO_M  (BIT(16))
1561 #define RTC_CNTL_ROM0_FORCE_ISO_V  0x1
1562 #define RTC_CNTL_ROM0_FORCE_ISO_S  16
1563 /* RTC_CNTL_DG_PAD_FORCE_HOLD : R/W ;bitpos:[15] ;default: 1'd0 ; */
1564 /*description: digital pad force hold*/
1565 #define RTC_CNTL_DG_PAD_FORCE_HOLD  (BIT(15))
1566 #define RTC_CNTL_DG_PAD_FORCE_HOLD_M  (BIT(15))
1567 #define RTC_CNTL_DG_PAD_FORCE_HOLD_V  0x1
1568 #define RTC_CNTL_DG_PAD_FORCE_HOLD_S  15
1569 /* RTC_CNTL_DG_PAD_FORCE_UNHOLD : R/W ;bitpos:[14] ;default: 1'd1 ; */
1570 /*description: digital pad force un-hold*/
1571 #define RTC_CNTL_DG_PAD_FORCE_UNHOLD  (BIT(14))
1572 #define RTC_CNTL_DG_PAD_FORCE_UNHOLD_M  (BIT(14))
1573 #define RTC_CNTL_DG_PAD_FORCE_UNHOLD_V  0x1
1574 #define RTC_CNTL_DG_PAD_FORCE_UNHOLD_S  14
1575 /* RTC_CNTL_DG_PAD_FORCE_ISO : R/W ;bitpos:[13] ;default: 1'd0 ; */
1576 /*description: digital pad force ISO*/
1577 #define RTC_CNTL_DG_PAD_FORCE_ISO  (BIT(13))
1578 #define RTC_CNTL_DG_PAD_FORCE_ISO_M  (BIT(13))
1579 #define RTC_CNTL_DG_PAD_FORCE_ISO_V  0x1
1580 #define RTC_CNTL_DG_PAD_FORCE_ISO_S  13
1581 /* RTC_CNTL_DG_PAD_FORCE_NOISO : R/W ;bitpos:[12] ;default: 1'd1 ; */
1582 /*description: digital pad force no ISO*/
1583 #define RTC_CNTL_DG_PAD_FORCE_NOISO  (BIT(12))
1584 #define RTC_CNTL_DG_PAD_FORCE_NOISO_M  (BIT(12))
1585 #define RTC_CNTL_DG_PAD_FORCE_NOISO_V  0x1
1586 #define RTC_CNTL_DG_PAD_FORCE_NOISO_S  12
1587 /* RTC_CNTL_DG_PAD_AUTOHOLD_EN : R/W ;bitpos:[11] ;default: 1'd0 ; */
1588 /*description: digital pad enable auto-hold*/
1589 #define RTC_CNTL_DG_PAD_AUTOHOLD_EN  (BIT(11))
1590 #define RTC_CNTL_DG_PAD_AUTOHOLD_EN_M  (BIT(11))
1591 #define RTC_CNTL_DG_PAD_AUTOHOLD_EN_V  0x1
1592 #define RTC_CNTL_DG_PAD_AUTOHOLD_EN_S  11
1593 /* RTC_CNTL_CLR_DG_PAD_AUTOHOLD : WO ;bitpos:[10] ;default: 1'd0 ; */
1594 /*description: wtite only register to clear digital pad auto-hold*/
1595 #define RTC_CNTL_CLR_DG_PAD_AUTOHOLD  (BIT(10))
1596 #define RTC_CNTL_CLR_DG_PAD_AUTOHOLD_M  (BIT(10))
1597 #define RTC_CNTL_CLR_DG_PAD_AUTOHOLD_V  0x1
1598 #define RTC_CNTL_CLR_DG_PAD_AUTOHOLD_S  10
1599 /* RTC_CNTL_DG_PAD_AUTOHOLD : RO ;bitpos:[9] ;default: 1'd0 ; */
1600 /*description: read only register to indicate digital pad auto-hold status*/
1601 #define RTC_CNTL_DG_PAD_AUTOHOLD  (BIT(9))
1602 #define RTC_CNTL_DG_PAD_AUTOHOLD_M  (BIT(9))
1603 #define RTC_CNTL_DG_PAD_AUTOHOLD_V  0x1
1604 #define RTC_CNTL_DG_PAD_AUTOHOLD_S  9
1605 /* RTC_CNTL_DIG_ISO_FORCE_ON : R/W ;bitpos:[8] ;default: 1'd0 ; */
1606 /*description: */
1607 #define RTC_CNTL_DIG_ISO_FORCE_ON  (BIT(8))
1608 #define RTC_CNTL_DIG_ISO_FORCE_ON_M  (BIT(8))
1609 #define RTC_CNTL_DIG_ISO_FORCE_ON_V  0x1
1610 #define RTC_CNTL_DIG_ISO_FORCE_ON_S  8
1611 /* RTC_CNTL_DIG_ISO_FORCE_OFF : R/W ;bitpos:[7] ;default: 1'd0 ; */
1612 /*description: */
1613 #define RTC_CNTL_DIG_ISO_FORCE_OFF  (BIT(7))
1614 #define RTC_CNTL_DIG_ISO_FORCE_OFF_M  (BIT(7))
1615 #define RTC_CNTL_DIG_ISO_FORCE_OFF_V  0x1
1616 #define RTC_CNTL_DIG_ISO_FORCE_OFF_S  7
1617 
1618 /* Useful groups of RTC_CNTL_DIG_ISO_REG bits */
1619 #define RTC_CNTL_CPU_ROM_RAM_FORCE_ISO   \
1620     (RTC_CNTL_INTER_RAM4_FORCE_ISO | RTC_CNTL_INTER_RAM3_FORCE_ISO |\
1621      RTC_CNTL_INTER_RAM2_FORCE_ISO | RTC_CNTL_INTER_RAM1_FORCE_ISO |\
1622      RTC_CNTL_INTER_RAM0_FORCE_ISO | RTC_CNTL_ROM0_FORCE_ISO)
1623 #define RTC_CNTL_CPU_ROM_RAM_FORCE_NOISO \
1624     (RTC_CNTL_INTER_RAM4_FORCE_NOISO | RTC_CNTL_INTER_RAM3_FORCE_NOISO |\
1625      RTC_CNTL_INTER_RAM2_FORCE_NOISO | RTC_CNTL_INTER_RAM1_FORCE_NOISO |\
1626      RTC_CNTL_INTER_RAM0_FORCE_NOISO | RTC_CNTL_ROM0_FORCE_NOISO)
1627 
1628 #define RTC_CNTL_WDTCONFIG0_REG          (DR_REG_RTCCNTL_BASE + 0x8c)
1629 /* RTC_CNTL_WDT_EN : R/W ;bitpos:[31] ;default: 1'h0 ; */
1630 /*description: enable RTC WDT*/
1631 #define RTC_CNTL_WDT_EN  (BIT(31))
1632 #define RTC_CNTL_WDT_EN_M  (BIT(31))
1633 #define RTC_CNTL_WDT_EN_V  0x1
1634 #define RTC_CNTL_WDT_EN_S  31
1635 /* RTC_CNTL_WDT_STG0 : R/W ;bitpos:[30:28] ;default: 3'h0 ; */
1636 /*description: 1: interrupt stage en  2: CPU reset stage en  3: system reset
1637  stage en  4: RTC reset stage en*/
1638 #define RTC_CNTL_WDT_STG0  0x00000007
1639 #define RTC_CNTL_WDT_STG0_M  ((RTC_CNTL_WDT_STG0_V)<<(RTC_CNTL_WDT_STG0_S))
1640 #define RTC_CNTL_WDT_STG0_V  0x7
1641 #define RTC_CNTL_WDT_STG0_S  28
1642 /* RTC_CNTL_WDT_STG1 : R/W ;bitpos:[27:25] ;default: 3'h0 ; */
1643 /*description: 1: interrupt stage en  2: CPU reset stage en  3: system reset
1644  stage en  4: RTC reset stage en*/
1645 #define RTC_CNTL_WDT_STG1  0x00000007
1646 #define RTC_CNTL_WDT_STG1_M  ((RTC_CNTL_WDT_STG1_V)<<(RTC_CNTL_WDT_STG1_S))
1647 #define RTC_CNTL_WDT_STG1_V  0x7
1648 #define RTC_CNTL_WDT_STG1_S  25
1649 /* RTC_CNTL_WDT_STG2 : R/W ;bitpos:[24:22] ;default: 3'h0 ; */
1650 /*description: 1: interrupt stage en  2: CPU reset stage en  3: system reset
1651  stage en  4: RTC reset stage en*/
1652 #define RTC_CNTL_WDT_STG2  0x00000007
1653 #define RTC_CNTL_WDT_STG2_M  ((RTC_CNTL_WDT_STG2_V)<<(RTC_CNTL_WDT_STG2_S))
1654 #define RTC_CNTL_WDT_STG2_V  0x7
1655 #define RTC_CNTL_WDT_STG2_S  22
1656 /* RTC_CNTL_WDT_STG3 : R/W ;bitpos:[21:19] ;default: 3'h0 ; */
1657 /*description: 1: interrupt stage en  2: CPU reset stage en  3: system reset
1658  stage en  4: RTC reset stage en*/
1659 #define RTC_CNTL_WDT_STG3  0x00000007
1660 #define RTC_CNTL_WDT_STG3_M  ((RTC_CNTL_WDT_STG3_V)<<(RTC_CNTL_WDT_STG3_S))
1661 #define RTC_CNTL_WDT_STG3_V  0x7
1662 #define RTC_CNTL_WDT_STG3_S  19
1663 /* RTC_CNTL_WDT_EDGE_INT_EN : R/W ;bitpos:[18] ;default: 1'h0 ; */
1664 /*description: N/A*/
1665 #define RTC_CNTL_WDT_EDGE_INT_EN  (BIT(18))
1666 #define RTC_CNTL_WDT_EDGE_INT_EN_M  (BIT(18))
1667 #define RTC_CNTL_WDT_EDGE_INT_EN_V  0x1
1668 #define RTC_CNTL_WDT_EDGE_INT_EN_S  18
1669 /* RTC_CNTL_WDT_LEVEL_INT_EN : R/W ;bitpos:[17] ;default: 1'h0 ; */
1670 /*description: N/A*/
1671 #define RTC_CNTL_WDT_LEVEL_INT_EN  (BIT(17))
1672 #define RTC_CNTL_WDT_LEVEL_INT_EN_M  (BIT(17))
1673 #define RTC_CNTL_WDT_LEVEL_INT_EN_V  0x1
1674 #define RTC_CNTL_WDT_LEVEL_INT_EN_S  17
1675 /* RTC_CNTL_WDT_CPU_RESET_LENGTH : R/W ;bitpos:[16:14] ;default: 3'h1 ; */
1676 /*description: CPU reset counter length*/
1677 #define RTC_CNTL_WDT_CPU_RESET_LENGTH  0x00000007
1678 #define RTC_CNTL_WDT_CPU_RESET_LENGTH_M  ((RTC_CNTL_WDT_CPU_RESET_LENGTH_V)<<(RTC_CNTL_WDT_CPU_RESET_LENGTH_S))
1679 #define RTC_CNTL_WDT_CPU_RESET_LENGTH_V  0x7
1680 #define RTC_CNTL_WDT_CPU_RESET_LENGTH_S  14
1681 /* RTC_CNTL_WDT_SYS_RESET_LENGTH : R/W ;bitpos:[13:11] ;default: 3'h1 ; */
1682 /*description: system reset counter length*/
1683 #define RTC_CNTL_WDT_SYS_RESET_LENGTH  0x00000007
1684 #define RTC_CNTL_WDT_SYS_RESET_LENGTH_M  ((RTC_CNTL_WDT_SYS_RESET_LENGTH_V)<<(RTC_CNTL_WDT_SYS_RESET_LENGTH_S))
1685 #define RTC_CNTL_WDT_SYS_RESET_LENGTH_V  0x7
1686 #define RTC_CNTL_WDT_SYS_RESET_LENGTH_S  11
1687 /* RTC_CNTL_WDT_FLASHBOOT_MOD_EN : R/W ;bitpos:[10] ;default: 1'h1 ; */
1688 /*description: enable WDT in flash boot*/
1689 #define RTC_CNTL_WDT_FLASHBOOT_MOD_EN  (BIT(10))
1690 #define RTC_CNTL_WDT_FLASHBOOT_MOD_EN_M  (BIT(10))
1691 #define RTC_CNTL_WDT_FLASHBOOT_MOD_EN_V  0x1
1692 #define RTC_CNTL_WDT_FLASHBOOT_MOD_EN_S  10
1693 /* RTC_CNTL_WDT_PROCPU_RESET_EN : R/W ;bitpos:[9] ;default: 1'd0 ; */
1694 /*description: enable WDT reset PRO CPU*/
1695 #define RTC_CNTL_WDT_PROCPU_RESET_EN  (BIT(9))
1696 #define RTC_CNTL_WDT_PROCPU_RESET_EN_M  (BIT(9))
1697 #define RTC_CNTL_WDT_PROCPU_RESET_EN_V  0x1
1698 #define RTC_CNTL_WDT_PROCPU_RESET_EN_S  9
1699 /* RTC_CNTL_WDT_APPCPU_RESET_EN : R/W ;bitpos:[8] ;default: 1'd0 ; */
1700 /*description: enable WDT reset APP CPU*/
1701 #define RTC_CNTL_WDT_APPCPU_RESET_EN  (BIT(8))
1702 #define RTC_CNTL_WDT_APPCPU_RESET_EN_M  (BIT(8))
1703 #define RTC_CNTL_WDT_APPCPU_RESET_EN_V  0x1
1704 #define RTC_CNTL_WDT_APPCPU_RESET_EN_S  8
1705 /* RTC_CNTL_WDT_PAUSE_IN_SLP : R/W ;bitpos:[7] ;default: 1'd1 ; */
1706 /*description: pause WDT in sleep*/
1707 #define RTC_CNTL_WDT_PAUSE_IN_SLP  (BIT(7))
1708 #define RTC_CNTL_WDT_PAUSE_IN_SLP_M  (BIT(7))
1709 #define RTC_CNTL_WDT_PAUSE_IN_SLP_V  0x1
1710 #define RTC_CNTL_WDT_PAUSE_IN_SLP_S  7
1711 /* RTC_CNTL_WDT_STGX : */
1712 /*description: stage action selection values */
1713 #define RTC_WDT_STG_SEL_OFF             0
1714 #define RTC_WDT_STG_SEL_INT             1
1715 #define RTC_WDT_STG_SEL_RESET_CPU       2
1716 #define RTC_WDT_STG_SEL_RESET_SYSTEM    3
1717 #define RTC_WDT_STG_SEL_RESET_RTC       4
1718 
1719 #define RTC_CNTL_WDTCONFIG1_REG          (DR_REG_RTCCNTL_BASE + 0x90)
1720 /* RTC_CNTL_WDT_STG0_HOLD : R/W ;bitpos:[31:0] ;default: 32'd128000 ; */
1721 /*description: */
1722 #define RTC_CNTL_WDT_STG0_HOLD  0xFFFFFFFF
1723 #define RTC_CNTL_WDT_STG0_HOLD_M  ((RTC_CNTL_WDT_STG0_HOLD_V)<<(RTC_CNTL_WDT_STG0_HOLD_S))
1724 #define RTC_CNTL_WDT_STG0_HOLD_V  0xFFFFFFFF
1725 #define RTC_CNTL_WDT_STG0_HOLD_S  0
1726 
1727 #define RTC_CNTL_WDTCONFIG2_REG          (DR_REG_RTCCNTL_BASE + 0x94)
1728 /* RTC_CNTL_WDT_STG1_HOLD : R/W ;bitpos:[31:0] ;default: 32'd80000 ; */
1729 /*description: */
1730 #define RTC_CNTL_WDT_STG1_HOLD  0xFFFFFFFF
1731 #define RTC_CNTL_WDT_STG1_HOLD_M  ((RTC_CNTL_WDT_STG1_HOLD_V)<<(RTC_CNTL_WDT_STG1_HOLD_S))
1732 #define RTC_CNTL_WDT_STG1_HOLD_V  0xFFFFFFFF
1733 #define RTC_CNTL_WDT_STG1_HOLD_S  0
1734 
1735 #define RTC_CNTL_WDTCONFIG3_REG          (DR_REG_RTCCNTL_BASE + 0x98)
1736 /* RTC_CNTL_WDT_STG2_HOLD : R/W ;bitpos:[31:0] ;default: 32'hfff ; */
1737 /*description: */
1738 #define RTC_CNTL_WDT_STG2_HOLD  0xFFFFFFFF
1739 #define RTC_CNTL_WDT_STG2_HOLD_M  ((RTC_CNTL_WDT_STG2_HOLD_V)<<(RTC_CNTL_WDT_STG2_HOLD_S))
1740 #define RTC_CNTL_WDT_STG2_HOLD_V  0xFFFFFFFF
1741 #define RTC_CNTL_WDT_STG2_HOLD_S  0
1742 
1743 #define RTC_CNTL_WDTCONFIG4_REG          (DR_REG_RTCCNTL_BASE + 0x9c)
1744 /* RTC_CNTL_WDT_STG3_HOLD : R/W ;bitpos:[31:0] ;default: 32'hfff ; */
1745 /*description: */
1746 #define RTC_CNTL_WDT_STG3_HOLD  0xFFFFFFFF
1747 #define RTC_CNTL_WDT_STG3_HOLD_M  ((RTC_CNTL_WDT_STG3_HOLD_V)<<(RTC_CNTL_WDT_STG3_HOLD_S))
1748 #define RTC_CNTL_WDT_STG3_HOLD_V  0xFFFFFFFF
1749 #define RTC_CNTL_WDT_STG3_HOLD_S  0
1750 
1751 #define RTC_CNTL_WDTFEED_REG          (DR_REG_RTCCNTL_BASE + 0xa0)
1752 /* RTC_CNTL_WDT_FEED : WO ;bitpos:[31] ;default: 1'd0 ; */
1753 /*description: */
1754 #define RTC_CNTL_WDT_FEED  (BIT(31))
1755 #define RTC_CNTL_WDT_FEED_M  (BIT(31))
1756 #define RTC_CNTL_WDT_FEED_V  0x1
1757 #define RTC_CNTL_WDT_FEED_S  31
1758 
1759 #define RTC_CNTL_WDTWPROTECT_REG          (DR_REG_RTCCNTL_BASE + 0xa4)
1760 /* RTC_CNTL_WDT_WKEY : R/W ;bitpos:[31:0] ;default: 32'h50d83aa1 ; */
1761 /*description: */
1762 #define RTC_CNTL_WDT_WKEY  0xFFFFFFFF
1763 #define RTC_CNTL_WDT_WKEY_M  ((RTC_CNTL_WDT_WKEY_V)<<(RTC_CNTL_WDT_WKEY_S))
1764 #define RTC_CNTL_WDT_WKEY_V  0xFFFFFFFF
1765 #define RTC_CNTL_WDT_WKEY_S  0
1766 
1767 #define RTC_CNTL_TEST_MUX_REG          (DR_REG_RTCCNTL_BASE + 0xa8)
1768 /* RTC_CNTL_DTEST_RTC : R/W ;bitpos:[31:30] ;default: 2'd0 ; */
1769 /*description: DTEST_RTC*/
1770 #define RTC_CNTL_DTEST_RTC  0x00000003
1771 #define RTC_CNTL_DTEST_RTC_M  ((RTC_CNTL_DTEST_RTC_V)<<(RTC_CNTL_DTEST_RTC_S))
1772 #define RTC_CNTL_DTEST_RTC_V  0x3
1773 #define RTC_CNTL_DTEST_RTC_S  30
1774 /* RTC_CNTL_ENT_RTC : R/W ;bitpos:[29] ;default: 1'd0 ; */
1775 /*description: ENT_RTC*/
1776 #define RTC_CNTL_ENT_RTC  (BIT(29))
1777 #define RTC_CNTL_ENT_RTC_M  (BIT(29))
1778 #define RTC_CNTL_ENT_RTC_V  0x1
1779 #define RTC_CNTL_ENT_RTC_S  29
1780 
1781 #define RTC_CNTL_SW_CPU_STALL_REG          (DR_REG_RTCCNTL_BASE + 0xac)
1782 /* RTC_CNTL_SW_STALL_PROCPU_C1 : R/W ;bitpos:[31:26] ;default: 6'b0 ; */
1783 /*description: {reg_sw_stall_procpu_c1[5:0]   reg_sw_stall_procpu_c0[1:0]} ==
1784  0x86 will stall PRO CPU*/
1785 #define RTC_CNTL_SW_STALL_PROCPU_C1  0x0000003F
1786 #define RTC_CNTL_SW_STALL_PROCPU_C1_M  ((RTC_CNTL_SW_STALL_PROCPU_C1_V)<<(RTC_CNTL_SW_STALL_PROCPU_C1_S))
1787 #define RTC_CNTL_SW_STALL_PROCPU_C1_V  0x3F
1788 #define RTC_CNTL_SW_STALL_PROCPU_C1_S  26
1789 /* RTC_CNTL_SW_STALL_APPCPU_C1 : R/W ;bitpos:[25:20] ;default: 6'b0 ; */
1790 /*description: {reg_sw_stall_appcpu_c1[5:0]   reg_sw_stall_appcpu_c0[1:0]} ==
1791  0x86 will stall APP CPU*/
1792 #define RTC_CNTL_SW_STALL_APPCPU_C1  0x0000003F
1793 #define RTC_CNTL_SW_STALL_APPCPU_C1_M  ((RTC_CNTL_SW_STALL_APPCPU_C1_V)<<(RTC_CNTL_SW_STALL_APPCPU_C1_S))
1794 #define RTC_CNTL_SW_STALL_APPCPU_C1_V  0x3F
1795 #define RTC_CNTL_SW_STALL_APPCPU_C1_S  20
1796 
1797 #define RTC_CNTL_STORE4_REG          (DR_REG_RTCCNTL_BASE + 0xb0)
1798 /* RTC_CNTL_SCRATCH4 : R/W ;bitpos:[31:0] ;default: 0 ; */
1799 /*description: 32-bit general purpose retention register*/
1800 #define RTC_CNTL_SCRATCH4  0xFFFFFFFF
1801 #define RTC_CNTL_SCRATCH4_M  ((RTC_CNTL_SCRATCH4_V)<<(RTC_CNTL_SCRATCH4_S))
1802 #define RTC_CNTL_SCRATCH4_V  0xFFFFFFFF
1803 #define RTC_CNTL_SCRATCH4_S  0
1804 
1805 #define RTC_CNTL_STORE5_REG          (DR_REG_RTCCNTL_BASE + 0xb4)
1806 /* RTC_CNTL_SCRATCH5 : R/W ;bitpos:[31:0] ;default: 0 ; */
1807 /*description: 32-bit general purpose retention register*/
1808 #define RTC_CNTL_SCRATCH5  0xFFFFFFFF
1809 #define RTC_CNTL_SCRATCH5_M  ((RTC_CNTL_SCRATCH5_V)<<(RTC_CNTL_SCRATCH5_S))
1810 #define RTC_CNTL_SCRATCH5_V  0xFFFFFFFF
1811 #define RTC_CNTL_SCRATCH5_S  0
1812 
1813 #define RTC_CNTL_STORE6_REG          (DR_REG_RTCCNTL_BASE + 0xb8)
1814 /* RTC_CNTL_SCRATCH6 : R/W ;bitpos:[31:0] ;default: 0 ; */
1815 /*description: 32-bit general purpose retention register*/
1816 #define RTC_CNTL_SCRATCH6  0xFFFFFFFF
1817 #define RTC_CNTL_SCRATCH6_M  ((RTC_CNTL_SCRATCH6_V)<<(RTC_CNTL_SCRATCH6_S))
1818 #define RTC_CNTL_SCRATCH6_V  0xFFFFFFFF
1819 #define RTC_CNTL_SCRATCH6_S  0
1820 
1821 #define RTC_CNTL_STORE7_REG          (DR_REG_RTCCNTL_BASE + 0xbc)
1822 /* RTC_CNTL_SCRATCH7 : R/W ;bitpos:[31:0] ;default: 0 ; */
1823 /*description: 32-bit general purpose retention register*/
1824 #define RTC_CNTL_SCRATCH7  0xFFFFFFFF
1825 #define RTC_CNTL_SCRATCH7_M  ((RTC_CNTL_SCRATCH7_V)<<(RTC_CNTL_SCRATCH7_S))
1826 #define RTC_CNTL_SCRATCH7_V  0xFFFFFFFF
1827 #define RTC_CNTL_SCRATCH7_S  0
1828 
1829 #define RTC_CNTL_LOW_POWER_ST_REG          (DR_REG_RTCCNTL_BASE + 0xc0)
1830 /* RTC_CNTL_RDY_FOR_WAKEUP : R/0; bitpos:[19]; default: 0 */
1831 /*description: 1 if RTC controller is ready to execute WAKE instruction, 0 otherwise */
1832 #define RTC_CNTL_RDY_FOR_WAKEUP  (BIT(19))
1833 #define RTC_CNTL_RDY_FOR_WAKEUP_M  (BIT(19))
1834 #define RTC_CNTL_RDY_FOR_WAKEUP_V  0x1
1835 #define RTC_CNTL_RDY_FOR_WAKEUP_S  19
1836 
1837 /* Compatibility definition */
1838 #define RTC_CNTL_DIAG0_REG RTC_CNTL_LOW_POWER_ST_REG
1839 /* RTC_CNTL_LOW_POWER_DIAG0 : RO ;bitpos:[31:0] ;default: 0 ; */
1840 /*description: */
1841 #define RTC_CNTL_LOW_POWER_DIAG0  0xFFFFFFFF
1842 #define RTC_CNTL_LOW_POWER_DIAG0_M  ((RTC_CNTL_LOW_POWER_DIAG0_V)<<(RTC_CNTL_LOW_POWER_DIAG0_S))
1843 #define RTC_CNTL_LOW_POWER_DIAG0_V  0xFFFFFFFF
1844 #define RTC_CNTL_LOW_POWER_DIAG0_S  0
1845 
1846 #define RTC_CNTL_DIAG1_REG          (DR_REG_RTCCNTL_BASE + 0xc4)
1847 /* RTC_CNTL_LOW_POWER_DIAG1 : RO ;bitpos:[31:0] ;default: 0 ; */
1848 /*description: */
1849 #define RTC_CNTL_LOW_POWER_DIAG1  0xFFFFFFFF
1850 #define RTC_CNTL_LOW_POWER_DIAG1_M  ((RTC_CNTL_LOW_POWER_DIAG1_V)<<(RTC_CNTL_LOW_POWER_DIAG1_S))
1851 #define RTC_CNTL_LOW_POWER_DIAG1_V  0xFFFFFFFF
1852 #define RTC_CNTL_LOW_POWER_DIAG1_S  0
1853 
1854 #define RTC_CNTL_HOLD_FORCE_REG          (DR_REG_RTCCNTL_BASE + 0xc8)
1855 /* RTC_CNTL_X32N_HOLD_FORCE : R/W ;bitpos:[17] ;default: 1'b0 ; */
1856 /*description: */
1857 #define RTC_CNTL_X32N_HOLD_FORCE  (BIT(17))
1858 #define RTC_CNTL_X32N_HOLD_FORCE_M  (BIT(17))
1859 #define RTC_CNTL_X32N_HOLD_FORCE_V  0x1
1860 #define RTC_CNTL_X32N_HOLD_FORCE_S  17
1861 /* RTC_CNTL_X32P_HOLD_FORCE : R/W ;bitpos:[16] ;default: 1'b0 ; */
1862 /*description: */
1863 #define RTC_CNTL_X32P_HOLD_FORCE  (BIT(16))
1864 #define RTC_CNTL_X32P_HOLD_FORCE_M  (BIT(16))
1865 #define RTC_CNTL_X32P_HOLD_FORCE_V  0x1
1866 #define RTC_CNTL_X32P_HOLD_FORCE_S  16
1867 /* RTC_CNTL_TOUCH_PAD7_HOLD_FORCE : R/W ;bitpos:[15] ;default: 1'b0 ; */
1868 /*description: */
1869 #define RTC_CNTL_TOUCH_PAD7_HOLD_FORCE  (BIT(15))
1870 #define RTC_CNTL_TOUCH_PAD7_HOLD_FORCE_M  (BIT(15))
1871 #define RTC_CNTL_TOUCH_PAD7_HOLD_FORCE_V  0x1
1872 #define RTC_CNTL_TOUCH_PAD7_HOLD_FORCE_S  15
1873 /* RTC_CNTL_TOUCH_PAD6_HOLD_FORCE : R/W ;bitpos:[14] ;default: 1'b0 ; */
1874 /*description: */
1875 #define RTC_CNTL_TOUCH_PAD6_HOLD_FORCE  (BIT(14))
1876 #define RTC_CNTL_TOUCH_PAD6_HOLD_FORCE_M  (BIT(14))
1877 #define RTC_CNTL_TOUCH_PAD6_HOLD_FORCE_V  0x1
1878 #define RTC_CNTL_TOUCH_PAD6_HOLD_FORCE_S  14
1879 /* RTC_CNTL_TOUCH_PAD5_HOLD_FORCE : R/W ;bitpos:[13] ;default: 1'b0 ; */
1880 /*description: */
1881 #define RTC_CNTL_TOUCH_PAD5_HOLD_FORCE  (BIT(13))
1882 #define RTC_CNTL_TOUCH_PAD5_HOLD_FORCE_M  (BIT(13))
1883 #define RTC_CNTL_TOUCH_PAD5_HOLD_FORCE_V  0x1
1884 #define RTC_CNTL_TOUCH_PAD5_HOLD_FORCE_S  13
1885 /* RTC_CNTL_TOUCH_PAD4_HOLD_FORCE : R/W ;bitpos:[12] ;default: 1'b0 ; */
1886 /*description: */
1887 #define RTC_CNTL_TOUCH_PAD4_HOLD_FORCE  (BIT(12))
1888 #define RTC_CNTL_TOUCH_PAD4_HOLD_FORCE_M  (BIT(12))
1889 #define RTC_CNTL_TOUCH_PAD4_HOLD_FORCE_V  0x1
1890 #define RTC_CNTL_TOUCH_PAD4_HOLD_FORCE_S  12
1891 /* RTC_CNTL_TOUCH_PAD3_HOLD_FORCE : R/W ;bitpos:[11] ;default: 1'b0 ; */
1892 /*description: */
1893 #define RTC_CNTL_TOUCH_PAD3_HOLD_FORCE  (BIT(11))
1894 #define RTC_CNTL_TOUCH_PAD3_HOLD_FORCE_M  (BIT(11))
1895 #define RTC_CNTL_TOUCH_PAD3_HOLD_FORCE_V  0x1
1896 #define RTC_CNTL_TOUCH_PAD3_HOLD_FORCE_S  11
1897 /* RTC_CNTL_TOUCH_PAD2_HOLD_FORCE : R/W ;bitpos:[10] ;default: 1'b0 ; */
1898 /*description: */
1899 #define RTC_CNTL_TOUCH_PAD2_HOLD_FORCE  (BIT(10))
1900 #define RTC_CNTL_TOUCH_PAD2_HOLD_FORCE_M  (BIT(10))
1901 #define RTC_CNTL_TOUCH_PAD2_HOLD_FORCE_V  0x1
1902 #define RTC_CNTL_TOUCH_PAD2_HOLD_FORCE_S  10
1903 /* RTC_CNTL_TOUCH_PAD1_HOLD_FORCE : R/W ;bitpos:[9] ;default: 1'b0 ; */
1904 /*description: */
1905 #define RTC_CNTL_TOUCH_PAD1_HOLD_FORCE  (BIT(9))
1906 #define RTC_CNTL_TOUCH_PAD1_HOLD_FORCE_M  (BIT(9))
1907 #define RTC_CNTL_TOUCH_PAD1_HOLD_FORCE_V  0x1
1908 #define RTC_CNTL_TOUCH_PAD1_HOLD_FORCE_S  9
1909 /* RTC_CNTL_TOUCH_PAD0_HOLD_FORCE : R/W ;bitpos:[8] ;default: 1'b0 ; */
1910 /*description: */
1911 #define RTC_CNTL_TOUCH_PAD0_HOLD_FORCE  (BIT(8))
1912 #define RTC_CNTL_TOUCH_PAD0_HOLD_FORCE_M  (BIT(8))
1913 #define RTC_CNTL_TOUCH_PAD0_HOLD_FORCE_V  0x1
1914 #define RTC_CNTL_TOUCH_PAD0_HOLD_FORCE_S  8
1915 /* RTC_CNTL_SENSE4_HOLD_FORCE : R/W ;bitpos:[7] ;default: 1'b0 ; */
1916 /*description: */
1917 #define RTC_CNTL_SENSE4_HOLD_FORCE  (BIT(7))
1918 #define RTC_CNTL_SENSE4_HOLD_FORCE_M  (BIT(7))
1919 #define RTC_CNTL_SENSE4_HOLD_FORCE_V  0x1
1920 #define RTC_CNTL_SENSE4_HOLD_FORCE_S  7
1921 /* RTC_CNTL_SENSE3_HOLD_FORCE : R/W ;bitpos:[6] ;default: 1'b0 ; */
1922 /*description: */
1923 #define RTC_CNTL_SENSE3_HOLD_FORCE  (BIT(6))
1924 #define RTC_CNTL_SENSE3_HOLD_FORCE_M  (BIT(6))
1925 #define RTC_CNTL_SENSE3_HOLD_FORCE_V  0x1
1926 #define RTC_CNTL_SENSE3_HOLD_FORCE_S  6
1927 /* RTC_CNTL_SENSE2_HOLD_FORCE : R/W ;bitpos:[5] ;default: 1'b0 ; */
1928 /*description: */
1929 #define RTC_CNTL_SENSE2_HOLD_FORCE  (BIT(5))
1930 #define RTC_CNTL_SENSE2_HOLD_FORCE_M  (BIT(5))
1931 #define RTC_CNTL_SENSE2_HOLD_FORCE_V  0x1
1932 #define RTC_CNTL_SENSE2_HOLD_FORCE_S  5
1933 /* RTC_CNTL_SENSE1_HOLD_FORCE : R/W ;bitpos:[4] ;default: 1'b0 ; */
1934 /*description: */
1935 #define RTC_CNTL_SENSE1_HOLD_FORCE  (BIT(4))
1936 #define RTC_CNTL_SENSE1_HOLD_FORCE_M  (BIT(4))
1937 #define RTC_CNTL_SENSE1_HOLD_FORCE_V  0x1
1938 #define RTC_CNTL_SENSE1_HOLD_FORCE_S  4
1939 /* RTC_CNTL_PDAC2_HOLD_FORCE : R/W ;bitpos:[3] ;default: 1'b0 ; */
1940 /*description: */
1941 #define RTC_CNTL_PDAC2_HOLD_FORCE  (BIT(3))
1942 #define RTC_CNTL_PDAC2_HOLD_FORCE_M  (BIT(3))
1943 #define RTC_CNTL_PDAC2_HOLD_FORCE_V  0x1
1944 #define RTC_CNTL_PDAC2_HOLD_FORCE_S  3
1945 /* RTC_CNTL_PDAC1_HOLD_FORCE : R/W ;bitpos:[2] ;default: 1'b0 ; */
1946 /*description: */
1947 #define RTC_CNTL_PDAC1_HOLD_FORCE  (BIT(2))
1948 #define RTC_CNTL_PDAC1_HOLD_FORCE_M  (BIT(2))
1949 #define RTC_CNTL_PDAC1_HOLD_FORCE_V  0x1
1950 #define RTC_CNTL_PDAC1_HOLD_FORCE_S  2
1951 /* RTC_CNTL_ADC2_HOLD_FORCE : R/W ;bitpos:[1] ;default: 1'b0 ; */
1952 /*description: */
1953 #define RTC_CNTL_ADC2_HOLD_FORCE  (BIT(1))
1954 #define RTC_CNTL_ADC2_HOLD_FORCE_M  (BIT(1))
1955 #define RTC_CNTL_ADC2_HOLD_FORCE_V  0x1
1956 #define RTC_CNTL_ADC2_HOLD_FORCE_S  1
1957 /* RTC_CNTL_ADC1_HOLD_FORCE : R/W ;bitpos:[0] ;default: 1'b0 ; */
1958 /*description: */
1959 #define RTC_CNTL_ADC1_HOLD_FORCE  (BIT(0))
1960 #define RTC_CNTL_ADC1_HOLD_FORCE_M  (BIT(0))
1961 #define RTC_CNTL_ADC1_HOLD_FORCE_V  0x1
1962 #define RTC_CNTL_ADC1_HOLD_FORCE_S  0
1963 
1964 #define RTC_CNTL_EXT_WAKEUP1_REG          (DR_REG_RTCCNTL_BASE + 0xcc)
1965 /* RTC_CNTL_EXT_WAKEUP1_STATUS_CLR : WO ;bitpos:[18] ;default: 1'd0 ; */
1966 /*description: clear ext wakeup1 status*/
1967 #define RTC_CNTL_EXT_WAKEUP1_STATUS_CLR  (BIT(18))
1968 #define RTC_CNTL_EXT_WAKEUP1_STATUS_CLR_M  (BIT(18))
1969 #define RTC_CNTL_EXT_WAKEUP1_STATUS_CLR_V  0x1
1970 #define RTC_CNTL_EXT_WAKEUP1_STATUS_CLR_S  18
1971 /* RTC_CNTL_EXT_WAKEUP1_SEL : R/W ;bitpos:[17:0] ;default: 18'd0 ; */
1972 /*description: Bitmap to select RTC pads for ext wakeup1*/
1973 #define RTC_CNTL_EXT_WAKEUP1_SEL  0x0003FFFF
1974 #define RTC_CNTL_EXT_WAKEUP1_SEL_M  ((RTC_CNTL_EXT_WAKEUP1_SEL_V)<<(RTC_CNTL_EXT_WAKEUP1_SEL_S))
1975 #define RTC_CNTL_EXT_WAKEUP1_SEL_V  0x3FFFF
1976 #define RTC_CNTL_EXT_WAKEUP1_SEL_S  0
1977 
1978 #define RTC_CNTL_EXT_WAKEUP1_STATUS_REG          (DR_REG_RTCCNTL_BASE + 0xd0)
1979 /* RTC_CNTL_EXT_WAKEUP1_STATUS : RO ;bitpos:[17:0] ;default: 18'd0 ; */
1980 /*description: ext wakeup1 status*/
1981 #define RTC_CNTL_EXT_WAKEUP1_STATUS  0x0003FFFF
1982 #define RTC_CNTL_EXT_WAKEUP1_STATUS_M  ((RTC_CNTL_EXT_WAKEUP1_STATUS_V)<<(RTC_CNTL_EXT_WAKEUP1_STATUS_S))
1983 #define RTC_CNTL_EXT_WAKEUP1_STATUS_V  0x3FFFF
1984 #define RTC_CNTL_EXT_WAKEUP1_STATUS_S  0
1985 
1986 #define RTC_CNTL_BROWN_OUT_REG          (DR_REG_RTCCNTL_BASE + 0xd4)
1987 /* RTC_CNTL_BROWN_OUT_DET : RO ;bitpos:[31] ;default: 1'b0 ; */
1988 /*description: brown out detect*/
1989 #define RTC_CNTL_BROWN_OUT_DET  (BIT(31))
1990 #define RTC_CNTL_BROWN_OUT_DET_M  (BIT(31))
1991 #define RTC_CNTL_BROWN_OUT_DET_V  0x1
1992 #define RTC_CNTL_BROWN_OUT_DET_S  31
1993 /* RTC_CNTL_BROWN_OUT_ENA : R/W ;bitpos:[30] ;default: 1'b0 ; */
1994 /*description: enable brown out*/
1995 #define RTC_CNTL_BROWN_OUT_ENA  (BIT(30))
1996 #define RTC_CNTL_BROWN_OUT_ENA_M  (BIT(30))
1997 #define RTC_CNTL_BROWN_OUT_ENA_V  0x1
1998 #define RTC_CNTL_BROWN_OUT_ENA_S  30
1999 /* RTC_CNTL_DBROWN_OUT_THRES : R/W ;bitpos:[29:27] ;default: 3'b010 ; */
2000 /*description: brown out threshold*/
2001 #define RTC_CNTL_DBROWN_OUT_THRES  0x00000007
2002 #define RTC_CNTL_DBROWN_OUT_THRES_M  ((RTC_CNTL_DBROWN_OUT_THRES_V)<<(RTC_CNTL_DBROWN_OUT_THRES_S))
2003 #define RTC_CNTL_DBROWN_OUT_THRES_V  0x7
2004 #define RTC_CNTL_DBROWN_OUT_THRES_S  27
2005 /* RTC_CNTL_BROWN_OUT_RST_ENA : R/W ;bitpos:[26] ;default: 1'b0 ; */
2006 /*description: enable brown out reset*/
2007 #define RTC_CNTL_BROWN_OUT_RST_ENA  (BIT(26))
2008 #define RTC_CNTL_BROWN_OUT_RST_ENA_M  (BIT(26))
2009 #define RTC_CNTL_BROWN_OUT_RST_ENA_V  0x1
2010 #define RTC_CNTL_BROWN_OUT_RST_ENA_S  26
2011 /* RTC_CNTL_BROWN_OUT_RST_WAIT : R/W ;bitpos:[25:16] ;default: 10'h3ff ; */
2012 /*description: brown out reset wait cycles*/
2013 #define RTC_CNTL_BROWN_OUT_RST_WAIT  0x000003FF
2014 #define RTC_CNTL_BROWN_OUT_RST_WAIT_M  ((RTC_CNTL_BROWN_OUT_RST_WAIT_V)<<(RTC_CNTL_BROWN_OUT_RST_WAIT_S))
2015 #define RTC_CNTL_BROWN_OUT_RST_WAIT_V  0x3FF
2016 #define RTC_CNTL_BROWN_OUT_RST_WAIT_S  16
2017 /* RTC_CNTL_BROWN_OUT_PD_RF_ENA : R/W ;bitpos:[15] ;default: 1'b0 ; */
2018 /*description: enable power down RF when brown out happens*/
2019 #define RTC_CNTL_BROWN_OUT_PD_RF_ENA  (BIT(15))
2020 #define RTC_CNTL_BROWN_OUT_PD_RF_ENA_M  (BIT(15))
2021 #define RTC_CNTL_BROWN_OUT_PD_RF_ENA_V  0x1
2022 #define RTC_CNTL_BROWN_OUT_PD_RF_ENA_S  15
2023 /* RTC_CNTL_BROWN_OUT_CLOSE_FLASH_ENA : R/W ;bitpos:[14] ;default: 1'b0 ; */
2024 /*description: enable close flash when brown out happens*/
2025 #define RTC_CNTL_BROWN_OUT_CLOSE_FLASH_ENA  (BIT(14))
2026 #define RTC_CNTL_BROWN_OUT_CLOSE_FLASH_ENA_M  (BIT(14))
2027 #define RTC_CNTL_BROWN_OUT_CLOSE_FLASH_ENA_V  0x1
2028 #define RTC_CNTL_BROWN_OUT_CLOSE_FLASH_ENA_S  14
2029 
2030 #define RTC_MEM_CONF            (DR_REG_RTCCNTL_BASE + 0x40 * 4)
2031 #define RTC_MEM_CRC_FINISH      (BIT(31))
2032 #define RTC_MEM_CRC_FINISH_M    (BIT(31))
2033 #define RTC_MEM_CRC_FINISH_V    0x1
2034 #define RTC_MEM_CRC_FINISH_S    31
2035 #define RTC_MEM_CRC_LEN         (0x7ff)
2036 #define RTC_MEM_CRC_LEN_M       ((RTC_MEM_CRC_LEN_V)<<(RTC_MEM_CRC_LEN_S))
2037 #define RTC_MEM_CRC_LEN_V       0x7ff
2038 #define RTC_MEM_CRC_LEN_S       20
2039 #define RTC_MEM_CRC_ADDR        0x7ff
2040 #define RTC_MEM_CRC_ADDR_M      ((RTC_MEM_CRC_ADDR_V)<<(RTC_MEM_CRC_ADDR_S))
2041 #define RTC_MEM_CRC_ADDR_V      0x7ff
2042 #define RTC_MEM_CRC_ADDR_S      9
2043 #define RTC_MEM_CRC_START       (BIT(8))
2044 #define RTC_MEM_CRC_START_M     (BIT(8))
2045 #define RTC_MEM_CRC_START_V     0x1
2046 #define RTC_MEM_CRC_START_S     8
2047 #define RTC_MEM_PID_CONF        0xff
2048 #define RTC_MEM_PID_CONF_M      0xff
2049 #define RTC_MEM_PID_CONF_V      0xff
2050 #define RTC_MEM_PID_CONF_S      0
2051 
2052 #define RTC_MEM_CRC_RES         (DR_REG_RTCCNTL_BASE + 0x41 * 4)
2053 
2054 #define RTC_CNTL_DATE_REG          (DR_REG_RTCCNTL_BASE + 0x13c)
2055 /* RTC_CNTL_CNTL_DATE : R/W ;bitpos:[27:0] ;default: 28'h1604280 ; */
2056 /*description: */
2057 #define RTC_CNTL_CNTL_DATE  0x0FFFFFFF
2058 #define RTC_CNTL_CNTL_DATE_M  ((RTC_CNTL_CNTL_DATE_V)<<(RTC_CNTL_CNTL_DATE_S))
2059 #define RTC_CNTL_CNTL_DATE_V  0xFFFFFFF
2060 #define RTC_CNTL_CNTL_DATE_S  0
2061 #define RTC_CNTL_RTC_CNTL_DATE_VERSION 0x1604280
2062 
2063 
2064 
2065 
2066 #endif /*_SOC_RTC_CNTL_REG_H_ */
2067