1 /**************************************************************************//** 2 * @file rtc_reg.h 3 * @version V1.00 4 * @brief RTC register definition header file 5 * 6 * @copyright SPDX-License-Identifier: Apache-2.0 7 * @copyright Copyright (C) 2017-2020 Nuvoton Technology Corp. All rights reserved. 8 *****************************************************************************/ 9 #ifndef __RTC_REG_H__ 10 #define __RTC_REG_H__ 11 12 /** @addtogroup REGISTER Control Register 13 14 @{ 15 16 */ 17 18 /*---------------------- Real Time Clock Controller -------------------------*/ 19 /** 20 @addtogroup RTC Real Time Clock Controller(RTC) 21 Memory Mapped Structure for RTC Controller 22 @{ */ 23 24 typedef struct 25 { 26 27 28 /** 29 * @var RTC_T::INIT 30 * Offset: 0x00 RTC Initiation Register 31 * --------------------------------------------------------------------------------------------------- 32 * |Bits |Field |Descriptions 33 * | :----: | :----: | :---- | 34 * |[0] |INIT_ACTIVE|RTC Active Status (Read Only) 35 * | | |0 = RTC is at reset state. 36 * | | |1 = RTC is at normal active state. 37 * |[31:1] |INIT |RTC Initiation 38 * | | |When RTC block is powered on, RTC is at reset state 39 * | | |User has to write a number (0x a5eb1357) to INIT to make RTC leaving reset state 40 * | | |Once the INIT is written as 0xa5eb1357, the RTC will be in un-reset state permanently. 41 * | | |The INIT is a write-only field and read value will be always 0. 42 * @var RTC_T::RWEN 43 * Offset: 0x04 RTC Access Enable Register 44 * --------------------------------------------------------------------------------------------------- 45 * |Bits |Field |Descriptions 46 * | :----: | :----: | :---- | 47 * |[15:0] |RWEN |RTC Register Access Enable Password (Write Only) 48 * | | |Writing 0xA965 to this field will enable RTC accessible period keeps 1024 RTC clocks. 49 * | | |Note: Writing other value will clear RWENF and disable RTC register access function immediately. 50 * |[16] |RWENF |RTC Register Access Enable Flag (Read Only) 51 * | | |0 = RTC register read/write Disabled. 52 * | | |1 = RTC register read/write Enabled. 53 * | | |This bit will be set after RTC_RWEN[15:0] register is load a 0xA965, and be cleared automatically after 1024 RTC clocks expired. 54 * | | |Note: RWENF will be mask to 0 during RTCBUSY is 1, and first turn on RTCCKEN (CLK_APBCLK[1]) also. 55 * |[24] |RTCBUSY |RTC Write Busy Flag 56 * | | |This bit indicates RTC registers are busy or not. RTC register R/W is invalid during RTCBUSY. 57 * | | |0: RTC registers are readable and writable. 58 * | | |1: RTC registers can't R/W, RTC under Busy Status. 59 * | | |Note: RTCBUSY flag will be set when execute write RTC register command exceed 6 times within 1120 PCLK cycles or PCLKRTC switch on first few cycles. 60 * | | |Note: The bit reflect RWENF (RWENF = 0 when RTCBUSY). 61 * @var RTC_T::FREQADJ 62 * Offset: 0x08 RTC Frequency Compensation Register 63 * --------------------------------------------------------------------------------------------------- 64 * |Bits |Field |Descriptions 65 * | :----: | :----: | :---- | 66 * |[21:0] |FREQADJ |Frequency Compensation Register 67 * | | |User must to get actual LXT frequency for RTC application. 68 * | | |FCR = 0x200000 * (32768 / LXT frequency). 69 * | | |Note: This formula is suitable only when RTC clock source is from LXT, RTCSEL (CLK_CLKSEL3[8]) is 0. 70 * | | |If set RTCSEL (CLK_CLKSEL3[8]) to 1, RTC clock source is from LIRC. 71 * | | |User can set FREQADJ to execute LIRC compensation for RTC counter more accurate and the formula as below, 72 * | | |FCR = 0x80000 * (32768 / LIRC frequency). 73 * @var RTC_T::TIME 74 * Offset: 0x0C RTC Time Loading Register 75 * --------------------------------------------------------------------------------------------------- 76 * |Bits |Field |Descriptions 77 * | :----: | :----: | :---- | 78 * |[3:0] |SEC |1-Sec Time Digit (0~9) 79 * |[6:4] |TENSEC |10-Sec Time Digit (0~5) 80 * |[11:8] |MIN |1-Min Time Digit (0~9) 81 * |[14:12] |TENMIN |10-Min Time Digit (0~5) 82 * |[19:16] |HR |1-Hour Time Digit (0~9) 83 * |[21:20] |TENHR |10-Hour Time Digit (0~2) 84 * | | |When RTC runs as 12-hour time scale mode, RTC_TIME[21] (the high bit of TENHR[1:0]) means AM/PM indication (If RTC_TIME[21] is 1, it indicates PM time message.) 85 * |[30:24] |HZCNT |Index of sub-second counter(0x00 ~0x7F) 86 * @var RTC_T::CAL 87 * Offset: 0x10 RTC Calendar Loading Register 88 * --------------------------------------------------------------------------------------------------- 89 * |Bits |Field |Descriptions 90 * | :----: | :----: | :---- | 91 * |[3:0] |DAY |1-Day Calendar Digit (0~9) 92 * |[5:4] |TENDAY |10-Day Calendar Digit (0~3) 93 * |[11:8] |MON |1-Month Calendar Digit (0~9) 94 * |[12] |TENMON |10-Month Calendar Digit (0~1) 95 * |[19:16] |YEAR |1-Year Calendar Digit (0~9) 96 * |[23:20] |TENYEAR |10-Year Calendar Digit (0~9) 97 * @var RTC_T::CLKFMT 98 * Offset: 0x14 RTC Time Scale Selection Register 99 * --------------------------------------------------------------------------------------------------- 100 * |Bits |Field |Descriptions 101 * | :----: | :----: | :---- | 102 * |[0] |24HEN |24-hour / 12-hour Time Scale Selection 103 * | | |Indicates that RTC_TIME and RTC_TALM are in 24-hour time scale or 12-hour time scale 104 * | | |0 = 12-hour time scale with AM and PM indication selected. 105 * | | |1 = 24-hour time scale selected. 106 * |[8] |HZCNTEN |Sub-second Counter Enable Bit 107 * | | |0 = HZCNT disabled in RTC_TIME and RTC_TALM. 108 * | | |1 = HZCNT enabled in RTC_TIME and RTC_TALM . 109 * @var RTC_T::WEEKDAY 110 * Offset: 0x18 RTC Day of the Week Register 111 * --------------------------------------------------------------------------------------------------- 112 * |Bits |Field |Descriptions 113 * | :----: | :----: | :---- | 114 * |[2:0] |WEEKDAY |Day of the Week Register 115 * | | |000 = Sunday. 116 * | | |001 = Monday. 117 * | | |010 = Tuesday. 118 * | | |011 = Wednesday. 119 * | | |100 = Thursday. 120 * | | |101 = Friday. 121 * | | |110 = Saturday. 122 * | | |111 = Reserved. 123 * @var RTC_T::TALM 124 * Offset: 0x1C RTC Time Alarm Register 125 * --------------------------------------------------------------------------------------------------- 126 * |Bits |Field |Descriptions 127 * | :----: | :----: | :---- | 128 * |[3:0] |SEC |1-Sec Time Digit of Alarm Setting (0~9) 129 * |[6:4] |TENSEC |10-Sec Time Digit of Alarm Setting (0~5) 130 * |[11:8] |MIN |1-Min Time Digit of Alarm Setting (0~9) 131 * |[14:12] |TENMIN |10-Min Time Digit of Alarm Setting (0~5) 132 * |[19:16] |HR |1-Hour Time Digit of Alarm Setting (0~9) 133 * |[21:20] |TENHR |10-Hour Time Digit of Alarm Setting (0~2) 134 * | | |When RTC runs as 12-hour time scale mode, RTC_TIME[21] (the high bit of TENHR[1:0]) means AM/PM indication (If RTC_TIME[21] is 1, it indicates PM time message.) 135 * |[30:24] |HZCNT |Index of sub-second counter(0x00 ~0x7F) 136 * @var RTC_T::CALM 137 * Offset: 0x20 RTC Calendar Alarm Register 138 * --------------------------------------------------------------------------------------------------- 139 * |Bits |Field |Descriptions 140 * | :----: | :----: | :---- | 141 * |[3:0] |DAY |1-Day Calendar Digit of Alarm Setting (0~9) 142 * |[5:4] |TENDAY |10-Day Calendar Digit of Alarm Setting (0~3) 143 * |[11:8] |MON |1-Month Calendar Digit of Alarm Setting (0~9) 144 * |[12] |TENMON |10-Month Calendar Digit of Alarm Setting (0~1) 145 * |[19:16] |YEAR |1-Year Calendar Digit of Alarm Setting (0~9) 146 * |[23:20] |TENYEAR |10-Year Calendar Digit of Alarm Setting (0~9) 147 * @var RTC_T::LEAPYEAR 148 * Offset: 0x24 RTC Leap Year Indicator Register 149 * --------------------------------------------------------------------------------------------------- 150 * |Bits |Field |Descriptions 151 * | :----: | :----: | :---- | 152 * |[0] |LEAPYEAR |Leap Year Indication Register (Read Only) 153 * | | |0 = This year is not a leap year. 154 * | | |1 = This year is leap year. 155 * @var RTC_T::INTEN 156 * Offset: 0x28 RTC Interrupt Enable Register 157 * --------------------------------------------------------------------------------------------------- 158 * |Bits |Field |Descriptions 159 * | :----: | :----: | :---- | 160 * |[0] |ALMIEN |Alarm Interrupt Enable Bit 161 * | | |Set ALMIEN to 1 can also enable chip wake-up function when RTC alarm interrupt event is generated. 162 * | | |0 = RTC Alarm interrupt Disabled. 163 * | | |1 = RTC Alarm interrupt Enabled. 164 * |[1] |TICKIEN |Time Tick Interrupt Enable Bit 165 * | | |Set TICKIEN to 1 can also enable chip wake-up function when RTC tick interrupt event is generated. 166 * | | |0 = RTC Time Tick interrupt Disabled. 167 * | | |1 = RTC Time Tick interrupt Enabled. 168 * |[8] |TAMP0IEN |Tamper 0 Interrupt Enable Bit 169 * | | |Set TAMP0IEN to 1 can also enable chip wake-up function when tamper 0 interrupt event is generated. 170 * | | |0 = Tamper 0 interrupt Disabled. 171 * | | |1 = Tamper 0 interrupt Enabled. 172 * |[9] |TAMP1IEN |Tamper 1 or Pair 0 Interrupt Enable Bit 173 * | | |Set TAMP1IEN to 1 can also enable chip wake-up function when tamper 1 interrupt event is generated. 174 * | | |0 = Tamper 1 or Pair 0 interrupt Disabled. 175 * | | |1 = Tamper 1 or Pair 0 interrupt Enabled. 176 * |[10] |TAMP2IEN |Tamper 2 Interrupt Enable Bit 177 * | | |Set TAMP2IEN to 1 can also enable chip wake-up function when tamper 2 interrupt event is generated. 178 * | | |0 = Tamper 2 interrupt Disabled. 179 * | | |1 = Tamper 2 interrupt Enabled. 180 * |[11] |TAMP3IEN |Tamper 3 or Pair 1 Interrupt Enable Bit 181 * | | |Set TAMP3IEN to 1 can also enable chip wake-up function when tamper 3 interrupt event is generated. 182 * | | |0 = Tamper 3 or Pair 1 interrupt Disabled. 183 * | | |1 = Tamper 3 or Pair 1 interrupt Enabled. 184 * |[12] |TAMP4IEN |Tamper 4 Interrupt Enable Bit 185 * | | |Set TAMP4IEN to 1 can also enable chip wake-up function when tamper 4 interrupt event is generated. 186 * | | |0 = Tamper 4 interrupt Disabled. 187 * | | |1 = Tamper 4 interrupt Enabled. 188 * |[13] |TAMP5IEN |Tamper 5 or Pair 2 Interrupt Enable Bit 189 * | | |Set TAMP5IEN to 1 can also enable chip wake-up function when tamper 5 interrupt event is generated. 190 * | | |0 = Tamper 5 or Pair 2 interrupt Disabled. 191 * | | |1 = Tamper 5 or Pair 2 interrupt Enabled. 192 * |[24] |CLKFIEN |LXT Clock Frequency Monitor Fail Interrupt Enable Bit 193 * | | |0 = LXT Frequency Fail interrupt Disabled. 194 * | | |1 = LXT Frequency Fail interrupt Enabled. 195 * |[25] |CLKSPIEN |LXT Clock Frequency Monitor Stop Interrupt Enable Bit 196 * | | |0 = LXT Frequency Stop interrupt Disabled. 197 * | | |1 = LXT Frequency Stop interrupt Enabled. 198 * @var RTC_T::INTSTS 199 * Offset: 0x2C RTC Interrupt Status Register 200 * --------------------------------------------------------------------------------------------------- 201 * |Bits |Field |Descriptions 202 * | :----: | :----: | :---- | 203 * |[0] |ALMIF |RTC Alarm Interrupt Flag 204 * | | |0 = Alarm condition is not matched. 205 * | | |1 = Alarm condition is matched. 206 * | | |Note: Write 1 to clear this bit. 207 * |[1] |TICKIF |RTC Time Tick Interrupt Flag 208 * | | |0 = Tick condition does not occur. 209 * | | |1 = Tick condition occur. 210 * | | |Note: Write 1 to clear this bit. 211 * |[8] |TAMP0IF |Tamper 0 Interrupt Flag 212 * | | |0 = No Tamper 0 interrupt flag is generated. 213 * | | |1 = Tamper 0 interrupt flag is generated. 214 * | | |Note1: Write 1 to clear this bit. 215 * | | |Note2: Clear all TAPMxIF will clear RTC_TAMPTIME and RTC_TAMPCAL automatically. 216 * |[9] |TAMP1IF |Tamper 1 or Pair 0 Interrupt Flag 217 * | | |0 = No Tamper 1 or Pair 0 interrupt flag is generated. 218 * | | |1 = Tamper 1 or Pair 0 interrupt flag is generated. 219 * | | |Note1: Write 1 to clear this bit. 220 * | | |Note2: Clear all TAPMxIF will clear RTC_TAMPTIME and RTC_TAMPCAL automatically. 221 * |[10] |TAMP2IF |Tamper 2 Interrupt Flag 222 * | | |0 = No Tamper 2 interrupt flag is generated. 223 * | | |1 = Tamper 2 interrupt flag is generated. 224 * | | |Note1: Write 1 to clear this bit. 225 * | | |Note2: Clear all TAPMxIF will clear RTC_TAMPTIME and RTC_TAMPCAL automatically. 226 * |[11] |TAMP3IF |Tamper 3 or Pair 1 Interrupt Flag 227 * | | |0 = No Tamper 3 or Pair 1 interrupt flag is generated. 228 * | | |1 = Tamper 3 or Pair 1 interrupt flag is generated. 229 * | | |Note1: Write 1 to clear this bit. 230 * | | |Note2: Clear all TAPMxIF will clear RTC_TAMPTIME and RTC_TAMPCAL automatically. 231 * |[12] |TAMP4IF |Tamper 4 Interrupt Flag 232 * | | |0 = No Tamper 4 interrupt flag is generated. 233 * | | |1 = Tamper 4 interrupt flag is generated. 234 * | | |Note1: Write 1 to clear this bit. 235 * | | |Note2: Clear all TAPMxIF will clear RTC_TAMPTIME and RTC_TAMPCAL automatically. 236 * |[13] |TAMP5IF |Tamper 5 or Pair 2 Interrupt Flag 237 * | | |0 = No Tamper 5 or Pair 2 interrupt flag is generated. 238 * | | |1 = Tamper 5 or Pair 2 interrupt flag is generated. 239 * | | |Note1: Write 1 to clear this bit. 240 * | | |Note2: Clear all TAPMxIF will clear RTC_TAMPTIME and RTC_TAMPCAL automatically. 241 * |[24] |CLKFIF |LXT Clock Frequency Monitor Fail Interrupt Flag 242 * | | |0 = LXT frequency is normal. 243 * | | |1 = LXT frequency is abnormal. 244 * | | |Note1: Write 1 to clear the bit to 0. 245 * | | |Note2: LXT detector will automatic disable when Fail/Stop Flag rise, resume after Fail/Stop Flag clear. 246 * |[25] |CLKSPIF |LXT Clock Frequency Monitor Stop Interrupt Flag 247 * | | |0 = LXT frequency is normal. 248 * | | |1 = LXT frequency is almost stop .. 249 * | | |Note1: Write 1 to clear the bit to 0. 250 * | | |Note2: LXT detector will automatic disable when Fail/Stop Flag rise, resume after Fail/Stop Flag clear. 251 * @var RTC_T::TICK 252 * Offset: 0x30 RTC Time Tick Register 253 * --------------------------------------------------------------------------------------------------- 254 * |Bits |Field |Descriptions 255 * | :----: | :----: | :---- | 256 * |[2:0] |TICK |Time Tick Register 257 * | | |These bits are used to select RTC time tick period for Periodic Time Tick Interrupt request. 258 * | | |000 = Time tick is 1 second. 259 * | | |001 = Time tick is 1/2 second. 260 * | | |010 = Time tick is 1/4 second. 261 * | | |011 = Time tick is 1/8 second. 262 * | | |100 = Time tick is 1/16 second. 263 * | | |101 = Time tick is 1/32 second. 264 * | | |110 = Time tick is 1/64 second. 265 * | | |111 = Time tick is 1/128 second. 266 * | | |Note: This register can be read back after the RTC register access enable bit RWENF (RTC_RWEN[16]) is active. 267 * @var RTC_T::TAMSK 268 * Offset: 0x34 RTC Time Alarm Mask Register 269 * --------------------------------------------------------------------------------------------------- 270 * |Bits |Field |Descriptions 271 * | :----: | :----: | :---- | 272 * |[0] |MSEC |Mask 1-Sec Time Digit of Alarm Setting (0~9) 273 * |[1] |MTENSEC |Mask 10-Sec Time Digit of Alarm Setting (0~5) 274 * |[2] |MMIN |Mask 1-Min Time Digit of Alarm Setting (0~9) 275 * |[3] |MTENMIN |Mask 10-Min Time Digit of Alarm Setting (0~5) 276 * |[4] |MHR |Mask 1-Hour Time Digit of Alarm Setting (0~9) 277 * | | |Note: MHR function is only for 24-hour time scale mode. 278 * |[5] |MTENHR |Mask 10-Hour Time Digit of Alarm Setting (0~2) 279 * | | |Note: MTENHR function is only for 24-hour time scale mode. 280 * @var RTC_T::CAMSK 281 * Offset: 0x38 RTC Calendar Alarm Mask Register 282 * --------------------------------------------------------------------------------------------------- 283 * |Bits |Field |Descriptions 284 * | :----: | :----: | :---- | 285 * |[0] |MDAY |Mask 1-Day Calendar Digit of Alarm Setting (0~9) 286 * |[1] |MTENDAY |Mask 10-Day Calendar Digit of Alarm Setting (0~3) 287 * |[2] |MMON |Mask 1-Month Calendar Digit of Alarm Setting (0~9) 288 * |[3] |MTENMON |Mask 10-Month Calendar Digit of Alarm Setting (0~1) 289 * |[4] |MYEAR |Mask 1-Year Calendar Digit of Alarm Setting (0~9) 290 * |[5] |MTENYEAR |Mask 10-Year Calendar Digit of Alarm Setting (0~9) 291 * @var RTC_T::SPRCTL 292 * Offset: 0x3C RTC Spare Functional Control Register 293 * --------------------------------------------------------------------------------------------------- 294 * |Bits |Field |Descriptions 295 * | :----: | :----: | :---- | 296 * |[2] |SPRRWEN |Spare Register Enable Bit 297 * | | |0 = Spare register is Disabled. 298 * | | |1 = Spare register is Enabled. 299 * | | |Note: When spare register is disabled, RTC_SPR0 ~ RTC_SPR19 cannot be accessed. 300 * |[5] |SPRCSTS |SPR Clear Flag 301 * | | |This bit indicates if the RTC_SPR0 ~RTC_SPR19 content is cleared when specify snoop event is detected. 302 * | | |0 = Spare register content is not cleared. 303 * | | |1 = Spare register content is cleared. 304 * | | |Writes 1 to clear this bit. 305 * | | |Note: This bit keep 1 when RTC_INTSTS[13:8] or RTC_INTSTS[25:24] are not equal zero. 306 * |[16] |LXTFCLR |LXT Clock Monitor Fail/Stop to Clear Spare Enable Bit 307 * | | |0 = LXT monitor Fail/Stop to clear Spare register content is Disabled.. 308 * | | |1 = LXT monitor Fail/Stop to clear Spare register content is Enabled. 309 * @var RTC_T::SPR[20] 310 * Offset: 0x40 ~ 0x8C RTC Spare Register 0 ~ 19 311 * --------------------------------------------------------------------------------------------------- 312 * |Bits |Field |Descriptions 313 * | :----: | :----: | :---- | 314 * |[31:0] |SPARE |Spare Register 315 * | | |This field is used to store back-up information defined by user. 316 * | | |This field will be cleared by hardware automatically once a tamper pin event is detected. 317 * | | |Before storing back-up information in to RTC_SPRx register, user should write 0xA965 to RTC_RWEN[15:0] to make sure register read/write enable bit REWNF (RTC_RWEN[16]) is enabled. 318 * @var RTC_T::LXTCTL 319 * Offset: 0x100 RTC 32.768 kHz Oscillator Control Register 320 * --------------------------------------------------------------------------------------------------- 321 * |Bits |Field |Descriptions 322 * | :----: | :----: | :---- | 323 * |[0] |LIRC32KEN |LIRC 32K Source Enable Bit 324 * | | |0 = LIRC32K Disabled. 325 * | | |1 = LIRC32K.Enabled. 326 * |[3:1] |GAIN |Oscillator Gain Option 327 * | | |User can select oscillator gain according to crystal external loading and operating temperature range 328 * | | |The larger gain value corresponding to stronger driving capability and higher power consumption. 329 * | | |000 = L0 mode. 330 * | | |001 = L1 mode. 331 * | | |010 = L2 mode. 332 * | | |011 = L3 mode. 333 * | | |100 = L4 mode. 334 * | | |101 = L5 mode. 335 * | | |110 = L6 mode. 336 * | | |111 = L7 mode (Default). 337 * |[7] |C32KS |Clock 32K Source Selection: 338 * | | |0 = Internal 32K clock is from 32K crystal . 339 * | | |1 = Internal 32K clock is from LIRC32K. 340 * @var RTC_T::GPIOCTL0 341 * Offset: 0x104 RTC GPIO Control 0 Register 342 * --------------------------------------------------------------------------------------------------- 343 * |Bits |Field |Descriptions 344 * | :----: | :----: | :---- | 345 * |[1:0] |OPMODE0 |IO Operation Mode 346 * | | |00 = PF.0 is input only mode, without pull-up resistor. 347 * | | |01 = PF.0 is output push pull mode. 348 * | | |10 = PF.0 is open drain mode. 349 * | | |11 = PF.0 is quasi-bidirectional mode with internal pull up. 350 * |[2] |DOUT0 |IO Output Data 351 * | | |0 = PF.0 output low. 352 * | | |1 = PF.0 output high. 353 * |[3] |CTLSEL0 |IO Pin State Backup Selection 354 * | | |When low speed 32 kHz oscillator is disabled, PF.0 pin (X32KO pin) can be used as GPIO function 355 * | | |User can program CTLSEL0 to decide PF.0 I/O function is controlled by system power domain GPIO module or VBAT power domain RTC_GPIOCTL0 control register. 356 * | | |0 = PF.0 pin I/O function is controlled by GPIO module. 357 * | | |Hardware auto becomes CTLSEL0 = 1 when system power is turned off. 358 * | | |1 = PF.0 pin I/O function is controlled by VBAT power domain. 359 * | | |PF.0 pin function and I/O status are controlled by OPMODE0[1:0] and DOUT0 after CTLSEL0 is set to 1. 360 * | | |Note: CTLSEL0 will automatically be set by hardware to 1 when system power is off and RTC_INIT[0] (RTC Active Status) is 1. 361 * |[5:4] |PUSEL0 |IO Pull-up and Pull-down Enable Bit 362 * | | |Determine PF.0 I/O pull-up or pull-down. 363 * | | |00 = PF.0 pull-up and pull-up disable. 364 * | | |01 = PF.0 pull-down enable. 365 * | | |10 = PF.0 pull-up enable. 366 * | | |11 = PF.0 pull-up and pull-up disable. 367 * | | |Note: 368 * | | |Basically, the pull-up control and pull-down control has following behavior limitation. 369 * | | |The independent pull-up control register only valid when OPMODE0 set as input tri-state and open-drain mode. 370 * | | |The independent pull-down control register only valid when OPMODE0 set as input tri-state mode. 371 * |[9:8] |OPMODE1 |IO Operation Mode 372 * | | |00 = PF.1 is input only mode, without pull-up resistor. 373 * | | |01 = PF.1 is output push pull mode. 374 * | | |10 = PF.1 is open drain mode. 375 * | | |11 = PF.1 is quasi-bidirectional mode with internal pull up. 376 * |[10] |DOUT1 |IO Output Data 377 * | | |0 = PF.1 output low. 378 * | | |1 = PF.1 output high. 379 * |[11] |CTLSEL1 |IO Pin State Backup Selection 380 * | | |When low speed 32 kHz oscillator is disabled, PF.1 pin (X32KI pin) can be used as GPIO function 381 * | | |User can program CTLSEL1 to decide PF.1 I/O function is controlled by system power domain GPIO module or VBAT power domain RTC_GPIOCTL0 control register. 382 * | | |0 = PF.1 pin I/O function is controlled by GPIO module. 383 * | | |Hardware auto becomes CTLSEL1 = 1 when system power is turned off. 384 * | | |1 = PF.1 pin I/O function is controlled by VBAT power domain. 385 * | | |PF.1 pin function and I/O status are controlled by OPMODE1[1:0] and DOUT1 after CTLSEL1 is set to 1. 386 * | | |Note: CTLSEL1 will automatically be set by hardware to 1 when system power is off and RTC_INIT[0] (RTC Active Status) is 1. 387 * |[13:12] |PUSEL1 |IO Pull-up and Pull-down Enable Bit 388 * | | |Determine PF.1 I/O pull-up or pull-down. 389 * | | |00 = PF.1 pull-up and pull-up disable. 390 * | | |01 = PF.1 pull-down enable. 391 * | | |10 = PF.1 pull-up enable. 392 * | | |11 = PF.1 pull-up and pull-up disable. 393 * | | |Note: 394 * | | |Basically, the pull-up control and pull-down control has following behavior limitation. 395 * | | |The independent pull-up control register only valid when OPMODE1 set as input tri-state and open-drain mode. 396 * | | |The independent pull-down control register only valid when OPMODE1 set as input tri-state mode. 397 * |[17:16] |OPMODE2 |IO Operation Mode 398 * | | |00 = PF.2 is input only mode, without pull-up resistor. 399 * | | |01 = PF.2 is output push pull mode. 400 * | | |10 = PF.2 is open drain mode. 401 * | | |11 = PF.2 is quasi-bidirectional mode with internal pull up. 402 * |[18] |DOUT2 |IO Output Data 403 * | | |0 = PF.2 output low. 404 * | | |1 = PF.2 output high. 405 * |[19] |CTLSEL2 |IO Pin State Backup Selection 406 * | | |When TAMP0EN is disabled, PF.2 pin (TAMPER0 pin) can be used as GPIO function 407 * | | |User can program CTLSEL2 to decide PF.2 I/O function is controlled by system power domain GPIO module or VBAT power domain RTC_GPIOCTL0 control register. 408 * | | |0 = PF.2 pin I/O function is controlled by GPIO module. 409 * | | |Hardware auto becomes CTLSEL2 = 1 when system power is turned off. 410 * | | |1 = PF.2 pin I/O function is controlled by VBAT power domain. 411 * | | |PF.2 pin function and I/O status are controlled by OPMODE2[1:0] and DOUT2 after CTLSEL2 is set to 1. 412 * | | |Note: CTLSEL2 will automatically be set by hardware to 1 when system power is off and RTC_INIT[0] (RTC Active Status) is 1. 413 * |[21:20] |PUSEL2 |IO Pull-up and Pull-down Enable Bit 414 * | | |Determine PF.2 I/O pull-up or pull-down. 415 * | | |00 = PF.2 pull-up and pull-up disable. 416 * | | |01 = PF.2 pull-down enable. 417 * | | |10 = PF.2 pull-up enable. 418 * | | |11 = PF.2 pull-up and pull-up disable. 419 * | | |Note1: 420 * | | |Basically, the pull-up control and pull-down control has following behavior limitation. 421 * | | |The independent pull-up control register only valid when OPMODE2 set as input tri-state and open-drain mode. 422 * | | |The independent pull-down control register only valid when OPMODE2 set as input tri-state mode. 423 * |[25:24] |OPMODE3 |IO Operation Mode 424 * | | |00 = PF.7 is input only mode, without pull-up resistor. 425 * | | |01 = PF.7 is output push pull mode. 426 * | | |10 = PF.7 is open drain mode. 427 * | | |11 = PF.7 is quasi-bidirectional mode with with internal pull up. 428 * |[26] |DOUT3 |IO Output Data 429 * | | |0 = PF.7 output low. 430 * | | |1 = PF.7 output high. 431 * |[27] |CTLSEL3 |IO Pin State Backup Selection 432 * | | |When TAMP1EN is disabled, PF.7 pin (TAMPER1 pin) can be used as GPIO function 433 * | | |User can program CTLSEL3 to decide PF.7 I/O function is controlled by system power domain GPIO module or VBAT power domain RTC_GPIOCTL0 control register. 434 * | | |0 = PF.7 pin I/O function is controlled by GPIO module. 435 * | | |Hardware auto becomes CTLSEL3 = 1 when system power is turned off. 436 * | | |1 = PF.7 pin I/O function is controlled by VBAT power domain. 437 * | | |PF.7 pin function and I/O status are controlled by OPMODE3[1:0] and DOUT3 after CTLSEL3 is set to 1. 438 * | | |Note: CTLSEL3 will automatically be set by hardware to 1 when system power is off and RTC_INIT[0] (RTC Active Status) is 1. 439 * |[29:28] |PUSEL3 |IO Pull-up and Pull-down Enable Bit 440 * | | |Determine PF.7 I/O pull-up or pull-down. 441 * | | |00 = PF.7 pull-up and pull-down disable. 442 * | | |01 = PF.7 pull-down enable. 443 * | | |10 = PF.7 pull-up enable. 444 * | | |11 = PF.7 pull-up and pull-down disable. 445 * | | |Note: 446 * | | |Basically, the pull-up control and pull-down control has following behavior limitation. 447 * | | |The independent pull-up control register only valid when OPMODE3 set as input tri-state and open-drain mode. 448 * | | |The independent pull-down control register only valid when OPMODE3 set as input tri-state mode. 449 * @var RTC_T::GPIOCTL1 450 * Offset: 0x108 RTC GPIO Control 1 Register 451 * --------------------------------------------------------------------------------------------------- 452 * |Bits |Field |Descriptions 453 * | :----: | :----: | :---- | 454 * |[1:0] |OPMODE4 |IO Operation Mode 455 * | | |00 = PF.8 is input only mode, without pull-up resistor. 456 * | | |01 = PF.8 is output push pull mode. 457 * | | |10 = PF.8 is open drain mode. 458 * | | |11 = PF.8 is quasi-bidirectional mode with with internal pull up. 459 * |[2] |DOUT4 |IO Output Data 460 * | | |0 = PF.8 output low. 461 * | | |1 = PF.8 output high. 462 * |[3] |CTLSEL4 |IO Pin State Backup Selection 463 * | | |When TAMP2EN is disabled, PF.8 pin (TAMPER2 pin) can be used as GPIO function 464 * | | |User can program CTLSEL4 to decide PF.8 I/O function is controlled by system power domain GPIO module or VBAT power domain RTC_GPIOCTL1 control register. 465 * | | |0 = PF.8 pin I/O function is controlled by GPIO module. 466 * | | |Hardware auto becomes CTLSEL4 = 1 when system power is turned off. 467 * | | |1 = PF.8 pin I/O function is controlled by VBAT power domain. 468 * | | |PF.8 pin function and I/O status are controlled by OPMODE4[1:0] and DOUT4 after CTLSEL4 is set to 1. 469 * | | |Note: CTLSEL4 will automatically be set by hardware to 1 when system power is off and RTC_INIT[0] (RTC Active Status) is 1. 470 * |[5:4] |PUSEL4 |IO Pull-up and Pull-down Enable Bit 471 * | | |Determine PF.8 I/O pull-up or pull-down. 472 * | | |00 = PF.8 pull-up and pull-down disable. 473 * | | |01 = PF.8 pull-down enable. 474 * | | |10 = PF.8 pull-up enable. 475 * | | |11 = PF.8 pull-up and pull-down disable. 476 * | | |Note: 477 * | | |Basically, the pull-up control and pull-down control has following behavior limitation. 478 * | | |The independent pull-up control register only valid when OPMODE4 set as input tri-state and open-drain mode. 479 * | | |The independent pull-down control register only valid when OPMODE4 set as input tri-state mode. 480 * |[9:8] |OPMODE5 |IO Operation Mode 481 * | | |00 = PF.9 is input only mode, without pull-up resistor. 482 * | | |01 = PF.9 is output push pull mode. 483 * | | |10 = PF.9 is open drain mode. 484 * | | |11 = PF.9 is quasi-bidirectional mode with with internal pull up. 485 * |[10] |DOUT5 |IO Output Data 486 * | | |0 = PF.9 output low. 487 * | | |1 = PF.9 output high. 488 * |[11] |CTLSEL5 |IO Pin State Backup Selection 489 * | | |When TAMP3EN is disabled, PF.9 pin (TAMPER3 pin) can be used as GPIO function 490 * | | |User can program CTLSEL5 to decide PF.9 I/O function is controlled by system power domain GPIO module or VBAT power domain RTC_GPIOCTL1 control register. 491 * | | |0 = PF.9 pin I/O function is controlled by GPIO module. 492 * | | |Hardware auto becomes CTLSEL5 = 1 when system power is turned off. 493 * | | |1 = PF.9 pin I/O function is controlled by VBAT power domain. 494 * | | |PF.9 pin function and I/O status are controlled by OPMODE5[1:0] and DOUT5 after CTLSEL5 is set to 1. 495 * | | |Note: CTLSEL5 will automatically be set by hardware to 1 when system power is off and RTC_INIT[0] (RTC Active Status) is 1. 496 * |[13:12] |PUSEL5 |IO Pull-up and Pull-down Enable Bit 497 * | | |Determine PF.9 I/O pull-up or pull-down. 498 * | | |00 = PF.9 pull-up and pull-down disable. 499 * | | |01 = PF.9 pull-down enable. 500 * | | |10 = PF.9 pull-up enable. 501 * | | |11 = PF.9 pull-up and pull-down disable. 502 * | | |.Note: 503 * | | |Basically, the pull-up control and pull-down control has following behavior limitation. 504 * | | |The independent pull-up control register only valid when OPMODE5 set as input tri-state and open-drain mode. 505 * | | |The independent pull-down control register only valid when OPMODE5 set as input tri-state mode. 506 * |[17:16] |OPMODE6 |IO Operation Mode 507 * | | |00 = PF.10 is input only mode, without pull-up resistor. 508 * | | |01 = PF.10 is output push pull mode. 509 * | | |10 = PF.10 is open drain mode. 510 * | | |11 = PF.10 is quasi-bidirectional mode with with internal pull up. 511 * |[18] |DOUT6 |IO Output Data 512 * | | |0 = PF.10 output low. 513 * | | |1 = PF.10 output high. 514 * |[19] |CTLSEL6 |IO Pin State Backup Selection 515 * | | |When TAMP4EN is disabled, PF.10 pin (TAMPER4 pin) can be used as GPIO function 516 * | | |User can program CTLSEL6 to decide PF.10 I/O function is controlled by system power domain GPIO module or VBAT power domain RTC_GPIOCTL1 control register. 517 * | | |0 = PF.10 pin I/O function is controlled by GPIO module. 518 * | | |Hardware auto becomes CTLSEL6 = 1 when system power is turned off. 519 * | | |1 = PF.10 pin I/O function is controlled by VBAT power domain. 520 * | | |PF.10 pin function and I/O status are controlled by OPMODE6[1:0] and DOUT6 after CTLSEL6 is set to 1. 521 * | | |Note: CTLSEL6 will automatically be set by hardware to 1 when system power is off and RTC_INIT[0] (RTC Active Status) is 1. 522 * |[21:20] |PUSEL6 |IO Pull-up and Pull-down Enable Bit 523 * | | |Determine PF.10 I/O pull-up or pull-down. 524 * | | |00 = PF.10 pull-up and pull-down disable. 525 * | | |01 = PF.10 pull-down enable. 526 * | | |10 = PF.10 pull-up enable. 527 * | | |11 = PF.10 pull-up and pull-down disable. 528 * | | |Note: 529 * | | |Basically, the pull-up control and pull-down control has following behavior limitation. 530 * | | |The independent pull-up control register only valid when OPMODE6 set as input tri-state and open-drain mode. 531 * | | |The independent pull-down control register only valid when OPMODE6 set as input tri-state mode. 532 * |[25:24] |OPMODE7 |IO Operation Mode 533 * | | |00 = PF.11 is input only mode, without pull-up resistor. 534 * | | |01 = PF.11 is output push pull mode. 535 * | | |10 = PF.11 is open drain mode. 536 * | | |11 = PF.11 is quasi-bidirectional mode with with internal pull up. 537 * |[26] |DOUT7 |IO Output Data 538 * | | |0 = PF.11 output low. 539 * | | |1 = PF.11 output high. 540 * |[27] |CTLSEL7 |IO Pin State Backup Selection 541 * | | |When TAMP5EN is disabled, PF.11 pin (TAMPER5 pin) can be used as GPIO function 542 * | | |User can program CTLSEL7 to decide PF.11 I/O function is controlled by system power domain GPIO module or VBAT power domain RTC_GPIOCTL1 control register. 543 * | | |0 = PF.11 pin I/O function is controlled by GPIO module. 544 * | | |Hardware auto becomes CTLSEL7 = 1 when system power is turned off. 545 * | | |1 = PF.11 pin I/O function is controlled by VBAT power domain. 546 * | | |PF.11 pin function and I/O status are controlled by OPMODE7[1:0] and DOUT7 after CTLSEL7 is set to 1. 547 * | | |Note: CTLSEL7 will automatically be set by hardware to 1 when system power is off and RTC_INIT[0] (RTC Active Status) is 1. 548 * |[29:28] |PUSEL7 |IO Pull-up and Pull-down Enable Bit 549 * | | |Determine PF.11 I/O pull-up or pull-down. 550 * | | |00 = PF.11 pull-up and pull-down disable. 551 * | | |01 = PF.11 pull-down enable. 552 * | | |10 = PF.11 pull-up enable. 553 * | | |11 = PF.11 pull-up and pull-down disable. 554 * | | |Note: 555 * | | |Basically, the pull-up control and pull-down control has following behavior limitation. 556 * | | |The independent pull-up control register only valid when OPMODE7 set as input tri-state and open-drain mode. 557 * | | |The independent pull-down control register only valid when OPMODE7 set as input tri-state mode. 558 * @var RTC_T::DSTCTL 559 * Offset: 0x110 RTC Daylight Saving Time Control Register 560 * --------------------------------------------------------------------------------------------------- 561 * |Bits |Field |Descriptions 562 * | :----: | :----: | :---- | 563 * |[0] |ADDHR |Add 1 Hour 564 * | | |0 = No effect. 565 * | | |1 = Indicates RTC hour digit has been added one hour for summer time change. 566 * |[1] |SUBHR |Subtract 1 Hour 567 * | | |0 = No effect. 568 * | | |1 = Indicates RTC hour digit has been subtracted one hour for winter time change. 569 * |[2] |DSBAK |Daylight Saving Back 570 * | | |0= Daylight Saving Change is not performed. 571 * | | |1= Daylight Saving Change is performed. 572 * @var RTC_T::TAMPCTL 573 * Offset: 0x120 RTC Tamper Pin Control Register 574 * --------------------------------------------------------------------------------------------------- 575 * |Bits |Field |Descriptions 576 * | :----: | :----: | :---- | 577 * |[0] |DYN1ISS |Dynamic Pair 1 Input Source Select 578 * | | |This bit determine Tamper 3 input is from Tamper 2 or Tamper 0 in dynamic mode. 579 * | | |0 = Tamper input is from Tamper 2. 580 * | | |1 = Tamper input is from Tamper 0. 581 * | | |Note: This bit has effect only when DYNPR1EN (RTC_TAMPCTL[16]) and DYNPR0EN (RTC_TAMPCTL[15]) are set 582 * |[1] |DYN2ISS |Dynamic Pair 2 Input Source Select 583 * | | |This bit determine Tamper 5 input is from Tamper 4 or Tamper 0 in dynamic mode. 584 * | | |0 = Tamper input is from Tamper 4. 585 * | | |1 = Tamper input is from Tamper 0. 586 * | | |Note: This bit has effect only when DYNPR2EN (RTC_TAMPCTL[24]) and DYNPR0EN (RTC_TAMPCTL[15]) are set 587 * |[3:2] |DYNSRC |Dynamic Reference Pattern 588 * | | |This fields determine the new reference pattern when current pattern run out in dynamic pair mode. 589 * | | |00 or 10 = The new reference pattern is generated by random number generator when the reference pattern run out. 590 * | | |01 = The new reference pattern is repeated previous random value when the reference pattern run out. 591 * | | |11 = The new reference pattern is repeated from SEED (RTC_TAMPSEED[31:0]) when the reference pattern run out. 592 * | | |Note: After revise this bit, the SEEDRLD (RTC_TAMPCTL[4]) should be set. 593 * |[4] |SEEDRLD |Reload New Seed for PRNG Engine 594 * | | |Setting this bit, the tamper configuration will be reload. 595 * | | |0 = Generating key based on the current seed. 596 * | | |1 = Reload new seed. 597 * | | |Note: Before set this bit, the tamper configuration should be set to complete. 598 * |[7:5] |DYNRATE |Dynamic Change Rate 599 * | | |This item is choice the dynamic tamper output change rate. 600 * | | |000 = 2^10 * RTC_CLK. 601 * | | |001 = 2^11 * RTC_CLK. 602 * | | |010 = 2^12 * RTC_CLK. 603 * | | |011 = 2^13 * RTC_CLK. 604 * | | |100 = 2^14 * RTC_CLK. 605 * | | |101 = 2^15 * RTC_CLK. 606 * | | |110 = 2^16 * RTC_CLK. 607 * | | |111 = 2^17 * RTC_CLK. 608 * | | |Note: After revise this field, set SEEDRLD (RTC_TAMPCTL[4]) can reload chage rate immediately. 609 * |[8] |TAMP0EN |Tamper0 Detect Enable Bit 610 * | | |0 = Tamper 0 detect Disabled. 611 * | | |1 = Tamper 0 detect Enabled. 612 * | | |Note1: The reference is RTC-clock . Tamper detector need sync 2 ~ 3 RTC-clock. 613 * |[9] |TAMP0LV |Tamper 0 Level 614 * | | |This bit depend on level attribute of tamper pin for static tamper detection. 615 * | | |0 = Detect voltage level is low. 616 * | | |1 = Detect voltage level is high. 617 * |[10] |TAMP0DBEN |Tamper 0 De-bounce Enable Bit 618 * | | |0 = Tamper 0 de-bounce Disabled. 619 * | | |1 = Tamper 0 de-bounce Enabled. 620 * |[12] |TAMP1EN |Tamper 1 Detect Enable Bit 621 * | | |0 = Tamper 1 detect Disabled. 622 * | | |1 = Tamper 1 detect Enabled. 623 * | | |Note1: The reference is RTC-clock . Tamper detector need sync 2 ~ 3 RTC-clock. 624 * |[13] |TAMP1LV |Tamper 1 Level 625 * | | |This bit depend on level attribute of tamper pin for static tamper detection. 626 * | | |0 = Detect voltage level is low. 627 * | | |1 = Detect voltage level is high. 628 * |[14] |TAMP1DBEN |Tamper 1 De-bounce Enable Bit 629 * | | |0 = Tamper 1 de-bounce Disabled. 630 * | | |1 = Tamper 1 de-bounce Enabled. 631 * |[15] |DYNPR0EN |Dynamic Pair 0 Enable Bit 632 * | | |0 = Static detect. 633 * | | |1 = Dynamic detect. 634 * |[16] |TAMP2EN |Tamper 2 Detect Enable Bit 635 * | | |0 = Tamper 2 detect Disabled. 636 * | | |1 = Tamper 2 detect Enabled. 637 * | | |Note1: The reference is RTC-clock . Tamper detector need sync 2 ~ 3 RTC-clock. 638 * |[17] |TAMP2LV |Tamper 2 Level 639 * | | |This bit depend on level attribute of tamper pin for static tamper detection. 640 * | | |0 = Detect voltage level is low. 641 * | | |1 = Detect voltage level is high. 642 * |[18] |TAMP2DBEN |Tamper 2 De-bounce Enable Bit 643 * | | |0 = Tamper 2 de-bounce Disabled. 644 * | | |1 = Tamper 2 de-bounce Enabled. 645 * |[20] |TAMP3EN |Tamper 3 Detect Enable Bit 646 * | | |0 = Tamper 3 detect Disabled. 647 * | | |1 = Tamper 3 detect Enabled. 648 * | | |Note1: The reference is RTC-clock . Tamper detector need sync 2 ~ 3 RTC-clock. 649 * |[21] |TAMP3LV |Tamper 3 Level 650 * | | |This bit depend on level attribute of tamper pin for static tamper detection. 651 * | | |0 = Detect voltage level is low. 652 * | | |1 = Detect voltage level is high. 653 * |[22] |TAMP3DBEN |Tamper 3 De-bounce Enable Bit 654 * | | |0 = Tamper 3 de-bounce Disabled. 655 * | | |1 = Tamper 3 de-bounce Enabled. 656 * |[23] |DYNPR1EN |Dynamic Pair 1 Enable Bit 657 * | | |0 = Static detect. 658 * | | |1 = Dynamic detect. 659 * |[24] |TAMP4EN |Tamper4 Detect Enable Bit 660 * | | |0 = Tamper 4 detect Disabled. 661 * | | |1 = Tamper 4 detect Enabled. 662 * | | |Note1: The reference is RTC-clock . Tamper detector need sync 2 ~ 3 RTC-clock. 663 * |[25] |TAMP4LV |Tamper 4 Level 664 * | | |This bit depend on level attribute of tamper pin for static tamper detection. 665 * | | |0 = Detect voltage level is low. 666 * | | |1 = Detect voltage level is high. 667 * |[26] |TAMP4DBEN |Tamper 4 De-bounce Enable Bit 668 * | | |0 = Tamper 4 de-bounce Disabled. 669 * | | |1 = Tamper 4 de-bounce Enabled. 670 * |[28] |TAMP5EN |Tamper 5 Detect Enable Bit 671 * | | |0 = Tamper 5 detect Disabled. 672 * | | |1 = Tamper 5 detect Enabled. 673 * | | |Note1: The reference is RTC-clock . Tamper detector need sync 2 ~ 3 RTC-clock. 674 * |[29] |TAMP5LV |Tamper 5 Level 675 * | | |This bit depend on level attribute of tamper pin for static tamper detection. 676 * | | |0 = Detect voltage level is low. 677 * | | |1 = Detect voltage level is high. 678 * |[30] |TAMP5DBEN |Tamper 5 De-bounce Enable Bit 679 * | | |0 = Tamper 5 de-bounce Disabled. 680 * | | |1 = Tamper 5 de-bounce Enabled. 681 * |[31] |DYNPR2EN |Dynamic Pair 2 Enable Bit 682 * | | |0 = Static detect. 683 * | | |1 = Dynamic detect. 684 * @var RTC_T::TAMPSEED 685 * Offset: 0x128 RTC Tamper Dynamic Seed Register 686 * --------------------------------------------------------------------------------------------------- 687 * |Bits |Field |Descriptions 688 * | :----: | :----: | :---- | 689 * |[31:0] |SEED |Seed Value 690 * @var RTC_T::TAMPTIME 691 * Offset: 0x130 RTC Tamper Time Register 692 * --------------------------------------------------------------------------------------------------- 693 * |Bits |Field |Descriptions 694 * | :----: | :----: | :---- | 695 * |[3:0] |SEC |1-Sec Time Digit of TAMPER Time (0~9) 696 * |[6:4] |TENSEC |10-Sec Time Digit of TAMPER Time (0~5) 697 * |[11:8] |MIN |1-Min Time Digit of TAMPER Time (0~9) 698 * |[14:12] |TENMIN |10-Min Time Digit of TAMPER Time (0~5) 699 * |[19:16] |HR |1-Hour Time Digit of TAMPER Time (0~9) 700 * |[21:20] |TENHR |10-Hour Time Digit of TAMPER Time (0~2) Note: 24-hour time scale only . 701 * |[30:24] |HZCNT |Index of sub-second counter(0x00 ~0x7F) 702 * @var RTC_T::TAMPCAL 703 * Offset: 0x134 RTC Tamper Calendar Register 704 * --------------------------------------------------------------------------------------------------- 705 * |Bits |Field |Descriptions 706 * | :----: | :----: | :---- | 707 * |[3:0] |DAY |1-Day Calendar Digit of TAMPER Calendar (0~9) 708 * |[5:4] |TENDAY |10-Day Calendar Digit of TAMPER Calendar (0~3) 709 * |[11:8] |MON |1-Month Calendar Digit of TAMPER Calendar (0~9) 710 * |[12] |TENMON |10-Month Calendar Digit of TAMPER Calendar (0~1) 711 * |[19:16] |YEAR |1-Year Calendar Digit of TAMPER Calendar (0~9) 712 * |[23:20] |TENYEAR |10-Year Calendar Digit of TAMPER Calendar (0~9) 713 * @var RTC_T::CLKDCTL 714 * Offset: 0x140 Clock Fail Detector Control Register 715 * --------------------------------------------------------------------------------------------------- 716 * |Bits |Field |Descriptions 717 * | :----: | :----: | :---- | 718 * |[0] |LXTFDEN |LXT Clock Fail/Stop Detector Enable Bit 719 * | | |0 = LXT clock fail/stop detector Disabled. 720 * | | |1 = LXT clock fail/stop detector Enabled. 721 * | | |Note: 722 * |[1] |LXTFSW |LXT Clock Fail Detector Switch LIRC32K Enable Bit 723 * | | |0 = LXT Clock Fail Detector Switch LIRC32K Disabled. 724 * | | |1 = Enabled 725 * | | |If LXT clock fail detector flag CLKFIF (RTC_INTSTS[24]) is generated, RTC clock source will switch to LIRC32K automatically. 726 * |[2] |LXTSPSW |LXT Clock Stop Detector Switch LIRC32K Enable Bit 727 * | | |0 = LXT Clock Stop Detector Switch LIRC32K Disabled. 728 * | | |1 = Enabled 729 * | | |If LXT clock stop detector flag CLKSPIF (RTC_INTSTS[25]) is generated, RTC clock source will switch to LIRC32K automatically 730 * |[16] |CLKSWLIRCF|LXT Clock Detector Fail/Stop Switch LIRC32K Flag (Read Only) 731 * | | |0 = RTC clock source from LXT. 732 * | | |1 = RTC clock source from LIRC32K . 733 * |[17] |LXTFASTF |LXT Faster Than LIRX32K Flag (Read Only) 734 * | | |0 = LXT frequency is slowly. 735 * | | |1 = LXT frequency faster than LIRC32K. 736 * @var RTC_T::CDBR 737 * Offset: 0x144 Clock Frequency Detector Boundary Register 738 * --------------------------------------------------------------------------------------------------- 739 * |Bits |Field |Descriptions 740 * | :----: | :----: | :---- | 741 * |[7:0] |STOPBD |LXT Clock Frequency Detector Stop Boundary 742 * | | |The bits define the stop value of frequency monitor window. 743 * | | |When LXT frequency monitor counter lower than Clock Frequency Detector Stop Boundary , the LXT frequency detect Stop interrupt flag will set to 1. 744 * | | |Note: The boundary is defined as the maximum value of LXT among 256 LIRC32K clock time. 745 * |[23:16] |FAILBD |LXT Clock Frequency Detector Fail Boundary 746 * | | |The bits define the fail value of frequency monitor window. 747 * | | |When LXT frequency monitor counter lower than Clock Frequency Detector fail Boundary , the LXT frequency detect fail interrupt flag will set to 1. 748 * | | |Note: The boundary is defined as the minimum value of LXT among 256 LIRC32K clock time. 749 */ 750 __IO uint32_t INIT; /*!< [0x0000] RTC Initiation Register */ 751 __IO uint32_t RWEN; /*!< [0x0004] RTC Access Enable Register */ 752 __IO uint32_t FREQADJ; /*!< [0x0008] RTC Frequency Compensation Register */ 753 __IO uint32_t TIME; /*!< [0x000c] RTC Time Loading Register */ 754 __IO uint32_t CAL; /*!< [0x0010] RTC Calendar Loading Register */ 755 __IO uint32_t CLKFMT; /*!< [0x0014] RTC Time Scale Selection Register */ 756 __IO uint32_t WEEKDAY; /*!< [0x0018] RTC Day of the Week Register */ 757 __IO uint32_t TALM; /*!< [0x001c] RTC Time Alarm Register */ 758 __IO uint32_t CALM; /*!< [0x0020] RTC Calendar Alarm Register */ 759 __I uint32_t LEAPYEAR; /*!< [0x0024] RTC Leap Year Indicator Register */ 760 __IO uint32_t INTEN; /*!< [0x0028] RTC Interrupt Enable Register */ 761 __IO uint32_t INTSTS; /*!< [0x002c] RTC Interrupt Status Register */ 762 __IO uint32_t TICK; /*!< [0x0030] RTC Time Tick Register */ 763 __IO uint32_t TAMSK; /*!< [0x0034] RTC Time Alarm Mask Register */ 764 __IO uint32_t CAMSK; /*!< [0x0038] RTC Calendar Alarm Mask Register */ 765 __IO uint32_t SPRCTL; /*!< [0x003c] RTC Spare Functional Control Register */ 766 __IO uint32_t SPR[20]; /*!< [0x0040] ~ [0x008C] RTC Spare Register 0 ~ 19 */ 767 __I uint32_t RESERVE0[28]; /* 0x90 ~ 0xFC */ 768 __IO uint32_t LXTCTL; /*!< [0x0100] RTC 32.768 kHz Oscillator Control Register */ 769 __IO uint32_t GPIOCTL0; /*!< [0x0104] RTC GPIO Control 0 Register */ 770 __IO uint32_t GPIOCTL1; /*!< [0x0108] RTC GPIO Control 1 Register */ 771 __I uint32_t RESERVE1[1]; 772 __IO uint32_t DSTCTL; /*!< [0x0110] RTC Daylight Saving Time Control Register */ 773 __I uint32_t RESERVE2[3]; 774 __IO uint32_t TAMPCTL; /*!< [0x0120] RTC Tamper Pin Control Register */ 775 __I uint32_t RESERVE3[1]; 776 __IO uint32_t TAMPSEED; /*!< [0x0128] RTC Tamper Dynamic Seed Register */ 777 __I uint32_t RESERVE4[1]; 778 __I uint32_t TAMPTIME; /*!< [0x0130] RTC Tamper Time Register */ 779 __I uint32_t TAMPCAL; /*!< [0x0134] RTC Tamper Calendar Register */ 780 __I uint32_t RESERVE5[2]; 781 __IO uint32_t CLKDCTL; /*!< [0x0140] Clock Fail Detector Control Register */ 782 __IO uint32_t CDBR; /*!< [0x0144] Clock Frequency Detector Boundary Register */ 783 784 } RTC_T; 785 786 /** 787 @addtogroup RTC_CONST RTC Bit Field Definition 788 Constant Definitions for RTC Controller 789 @{ */ 790 791 #define RTC_INIT_ACTIVE_Pos (0) /*!< RTC_T::INIT: ACTIVE Position */ 792 #define RTC_INIT_ACTIVE_Msk (0x1ul << RTC_INIT_ACTIVE_Pos) /*!< RTC_T::INIT: ACTIVE Mask */ 793 794 #define RTC_INIT_INIT_Pos (1) /*!< RTC_T::INIT: INIT Position */ 795 #define RTC_INIT_INIT_Msk (0x7ffffffful << RTC_INIT_INIT_Pos) /*!< RTC_T::INIT: INIT Mask */ 796 797 #define RTC_RWEN_RWEN_Pos (0) /*!< RTC_T::RWEN: RWEN Position */ 798 #define RTC_RWEN_RWEN_Msk (0xfffful << RTC_RWEN_RWEN_Pos) /*!< RTC_T::RWEN: RWEN Mask */ 799 800 #define RTC_RWEN_RWENF_Pos (16) /*!< RTC_T::RWEN: RWENF Position */ 801 #define RTC_RWEN_RWENF_Msk (0x1ul << RTC_RWEN_RWENF_Pos) /*!< RTC_T::RWEN: RWENF Mask */ 802 803 #define RTC_RWEN_RTCBUSY_Pos (24) /*!< RTC_T::RWEN: RTCBUSY Position */ 804 #define RTC_RWEN_RTCBUSY_Msk (0x1ul << RTC_RWEN_RTCBUSY_Pos) /*!< RTC_T::RWEN: RTCBUSY Mask */ 805 806 #define RTC_FREQADJ_FREQADJ_Pos (0) /*!< RTC_T::FREQADJ: FREQADJ Position */ 807 #define RTC_FREQADJ_FREQADJ_Msk (0x3ffffful << RTC_FREQADJ_FREQADJ_Pos) /*!< RTC_T::FREQADJ: FREQADJ Mask */ 808 809 #define RTC_TIME_SEC_Pos (0) /*!< RTC_T::TIME: SEC Position */ 810 #define RTC_TIME_SEC_Msk (0xful << RTC_TIME_SEC_Pos) /*!< RTC_T::TIME: SEC Mask */ 811 812 #define RTC_TIME_TENSEC_Pos (4) /*!< RTC_T::TIME: TENSEC Position */ 813 #define RTC_TIME_TENSEC_Msk (0x7ul << RTC_TIME_TENSEC_Pos) /*!< RTC_T::TIME: TENSEC Mask */ 814 815 #define RTC_TIME_MIN_Pos (8) /*!< RTC_T::TIME: MIN Position */ 816 #define RTC_TIME_MIN_Msk (0xful << RTC_TIME_MIN_Pos) /*!< RTC_T::TIME: MIN Mask */ 817 818 #define RTC_TIME_TENMIN_Pos (12) /*!< RTC_T::TIME: TENMIN Position */ 819 #define RTC_TIME_TENMIN_Msk (0x7ul << RTC_TIME_TENMIN_Pos) /*!< RTC_T::TIME: TENMIN Mask */ 820 821 #define RTC_TIME_HR_Pos (16) /*!< RTC_T::TIME: HR Position */ 822 #define RTC_TIME_HR_Msk (0xful << RTC_TIME_HR_Pos) /*!< RTC_T::TIME: HR Mask */ 823 824 #define RTC_TIME_TENHR_Pos (20) /*!< RTC_T::TIME: TENHR Position */ 825 #define RTC_TIME_TENHR_Msk (0x3ul << RTC_TIME_TENHR_Pos) /*!< RTC_T::TIME: TENHR Mask */ 826 827 #define RTC_TIME_HZCNT_Pos (24) /*!< RTC_T::TIME: HZCNT Position */ 828 #define RTC_TIME_HZCNT_Msk (0x7ful << RTC_TIME_HZCNT_Pos) /*!< RTC_T::TIME: HZCNT Mask */ 829 830 #define RTC_CAL_DAY_Pos (0) /*!< RTC_T::CAL: DAY Position */ 831 #define RTC_CAL_DAY_Msk (0xful << RTC_CAL_DAY_Pos) /*!< RTC_T::CAL: DAY Mask */ 832 833 #define RTC_CAL_TENDAY_Pos (4) /*!< RTC_T::CAL: TENDAY Position */ 834 #define RTC_CAL_TENDAY_Msk (0x3ul << RTC_CAL_TENDAY_Pos) /*!< RTC_T::CAL: TENDAY Mask */ 835 836 #define RTC_CAL_MON_Pos (8) /*!< RTC_T::CAL: MON Position */ 837 #define RTC_CAL_MON_Msk (0xful << RTC_CAL_MON_Pos) /*!< RTC_T::CAL: MON Mask */ 838 839 #define RTC_CAL_TENMON_Pos (12) /*!< RTC_T::CAL: TENMON Position */ 840 #define RTC_CAL_TENMON_Msk (0x1ul << RTC_CAL_TENMON_Pos) /*!< RTC_T::CAL: TENMON Mask */ 841 842 #define RTC_CAL_YEAR_Pos (16) /*!< RTC_T::CAL: YEAR Position */ 843 #define RTC_CAL_YEAR_Msk (0xful << RTC_CAL_YEAR_Pos) /*!< RTC_T::CAL: YEAR Mask */ 844 845 #define RTC_CAL_TENYEAR_Pos (20) /*!< RTC_T::CAL: TENYEAR Position */ 846 #define RTC_CAL_TENYEAR_Msk (0xful << RTC_CAL_TENYEAR_Pos) /*!< RTC_T::CAL: TENYEAR Mask */ 847 848 #define RTC_CLKFMT_24HEN_Pos (0) /*!< RTC_T::CLKFMT: 24HEN Position */ 849 #define RTC_CLKFMT_24HEN_Msk (0x1ul << RTC_CLKFMT_24HEN_Pos) /*!< RTC_T::CLKFMT: 24HEN Mask */ 850 851 #define RTC_CLKFMT_HZCNTEN_Pos (8) /*!< RTC_T::CLKFMT: HZCNTEN Position */ 852 #define RTC_CLKFMT_HZCNTEN_Msk (0x1ul << RTC_CLKFMT_HZCNTEN_Pos) /*!< RTC_T::CLKFMT: HZCNTEN Mask */ 853 854 #define RTC_WEEKDAY_WEEKDAY_Pos (0) /*!< RTC_T::WEEKDAY: WEEKDAY Position */ 855 #define RTC_WEEKDAY_WEEKDAY_Msk (0x7ul << RTC_WEEKDAY_WEEKDAY_Pos) /*!< RTC_T::WEEKDAY: WEEKDAY Mask */ 856 857 #define RTC_TALM_SEC_Pos (0) /*!< RTC_T::TALM: SEC Position */ 858 #define RTC_TALM_SEC_Msk (0xful << RTC_TALM_SEC_Pos) /*!< RTC_T::TALM: SEC Mask */ 859 860 #define RTC_TALM_TENSEC_Pos (4) /*!< RTC_T::TALM: TENSEC Position */ 861 #define RTC_TALM_TENSEC_Msk (0x7ul << RTC_TALM_TENSEC_Pos) /*!< RTC_T::TALM: TENSEC Mask */ 862 863 #define RTC_TALM_MIN_Pos (8) /*!< RTC_T::TALM: MIN Position */ 864 #define RTC_TALM_MIN_Msk (0xful << RTC_TALM_MIN_Pos) /*!< RTC_T::TALM: MIN Mask */ 865 866 #define RTC_TALM_TENMIN_Pos (12) /*!< RTC_T::TALM: TENMIN Position */ 867 #define RTC_TALM_TENMIN_Msk (0x7ul << RTC_TALM_TENMIN_Pos) /*!< RTC_T::TALM: TENMIN Mask */ 868 869 #define RTC_TALM_HR_Pos (16) /*!< RTC_T::TALM: HR Position */ 870 #define RTC_TALM_HR_Msk (0xful << RTC_TALM_HR_Pos) /*!< RTC_T::TALM: HR Mask */ 871 872 #define RTC_TALM_TENHR_Pos (20) /*!< RTC_T::TALM: TENHR Position */ 873 #define RTC_TALM_TENHR_Msk (0x3ul << RTC_TALM_TENHR_Pos) /*!< RTC_T::TALM: TENHR Mask */ 874 875 #define RTC_TALM_HZCNT_Pos (24) /*!< RTC_T::TALM: HZCNT Position */ 876 #define RTC_TALM_HZCNT_Msk (0x7ful << RTC_TALM_HZCNT_Pos) /*!< RTC_T::TALM: HZCNT Mask */ 877 878 #define RTC_CALM_DAY_Pos (0) /*!< RTC_T::CALM: DAY Position */ 879 #define RTC_CALM_DAY_Msk (0xful << RTC_CALM_DAY_Pos) /*!< RTC_T::CALM: DAY Mask */ 880 881 #define RTC_CALM_TENDAY_Pos (4) /*!< RTC_T::CALM: TENDAY Position */ 882 #define RTC_CALM_TENDAY_Msk (0x3ul << RTC_CALM_TENDAY_Pos) /*!< RTC_T::CALM: TENDAY Mask */ 883 884 #define RTC_CALM_MON_Pos (8) /*!< RTC_T::CALM: MON Position */ 885 #define RTC_CALM_MON_Msk (0xful << RTC_CALM_MON_Pos) /*!< RTC_T::CALM: MON Mask */ 886 887 #define RTC_CALM_TENMON_Pos (12) /*!< RTC_T::CALM: TENMON Position */ 888 #define RTC_CALM_TENMON_Msk (0x1ul << RTC_CALM_TENMON_Pos) /*!< RTC_T::CALM: TENMON Mask */ 889 890 #define RTC_CALM_YEAR_Pos (16) /*!< RTC_T::CALM: YEAR Position */ 891 #define RTC_CALM_YEAR_Msk (0xful << RTC_CALM_YEAR_Pos) /*!< RTC_T::CALM: YEAR Mask */ 892 893 #define RTC_CALM_TENYEAR_Pos (20) /*!< RTC_T::CALM: TENYEAR Position */ 894 #define RTC_CALM_TENYEAR_Msk (0xful << RTC_CALM_TENYEAR_Pos) /*!< RTC_T::CALM: TENYEAR Mask */ 895 896 #define RTC_LEAPYEAR_LEAPYEAR_Pos (0) /*!< RTC_T::LEAPYEAR: LEAPYEAR Position */ 897 #define RTC_LEAPYEAR_LEAPYEAR_Msk (0x1ul << RTC_LEAPYEAR_LEAPYEAR_Pos) /*!< RTC_T::LEAPYEAR: LEAPYEAR Mask */ 898 899 #define RTC_INTEN_ALMIEN_Pos (0) /*!< RTC_T::INTEN: ALMIEN Position */ 900 #define RTC_INTEN_ALMIEN_Msk (0x1ul << RTC_INTEN_ALMIEN_Pos) /*!< RTC_T::INTEN: ALMIEN Mask */ 901 902 #define RTC_INTEN_TICKIEN_Pos (1) /*!< RTC_T::INTEN: TICKIEN Position */ 903 #define RTC_INTEN_TICKIEN_Msk (0x1ul << RTC_INTEN_TICKIEN_Pos) /*!< RTC_T::INTEN: TICKIEN Mask */ 904 905 #define RTC_INTEN_TAMP0IEN_Pos (8) /*!< RTC_T::INTEN: TAMP0IEN Position */ 906 #define RTC_INTEN_TAMP0IEN_Msk (0x1ul << RTC_INTEN_TAMP0IEN_Pos) /*!< RTC_T::INTEN: TAMP0IEN Mask */ 907 908 #define RTC_INTEN_TAMP1IEN_Pos (9) /*!< RTC_T::INTEN: TAMP1IEN Position */ 909 #define RTC_INTEN_TAMP1IEN_Msk (0x1ul << RTC_INTEN_TAMP1IEN_Pos) /*!< RTC_T::INTEN: TAMP1IEN Mask */ 910 911 #define RTC_INTEN_TAMP2IEN_Pos (10) /*!< RTC_T::INTEN: TAMP2IEN Position */ 912 #define RTC_INTEN_TAMP2IEN_Msk (0x1ul << RTC_INTEN_TAMP2IEN_Pos) /*!< RTC_T::INTEN: TAMP2IEN Mask */ 913 914 #define RTC_INTEN_TAMP3IEN_Pos (11) /*!< RTC_T::INTEN: TAMP3IEN Position */ 915 #define RTC_INTEN_TAMP3IEN_Msk (0x1ul << RTC_INTEN_TAMP3IEN_Pos) /*!< RTC_T::INTEN: TAMP3IEN Mask */ 916 917 #define RTC_INTEN_TAMP4IEN_Pos (12) /*!< RTC_T::INTEN: TAMP4IEN Position */ 918 #define RTC_INTEN_TAMP4IEN_Msk (0x1ul << RTC_INTEN_TAMP4IEN_Pos) /*!< RTC_T::INTEN: TAMP4IEN Mask */ 919 920 #define RTC_INTEN_TAMP5IEN_Pos (13) /*!< RTC_T::INTEN: TAMP5IEN Position */ 921 #define RTC_INTEN_TAMP5IEN_Msk (0x1ul << RTC_INTEN_TAMP5IEN_Pos) /*!< RTC_T::INTEN: TAMP5IEN Mask */ 922 923 #define RTC_INTEN_CLKFIEN_Pos (24) /*!< RTC_T::INTEN: CLKFIEN Position */ 924 #define RTC_INTEN_CLKFIEN_Msk (0x1ul << RTC_INTEN_CLKFIEN_Pos) /*!< RTC_T::INTEN: CLKFIEN Mask */ 925 926 #define RTC_INTEN_CLKSPIEN_Pos (25) /*!< RTC_T::INTEN: CLKSPIEN Position */ 927 #define RTC_INTEN_CLKSPIEN_Msk (0x1ul << RTC_INTEN_CLKSPIEN_Pos) /*!< RTC_T::INTEN: CLKSPIEN Mask */ 928 929 #define RTC_INTSTS_ALMIF_Pos (0) /*!< RTC_T::INTSTS: ALMIF Position */ 930 #define RTC_INTSTS_ALMIF_Msk (0x1ul << RTC_INTSTS_ALMIF_Pos) /*!< RTC_T::INTSTS: ALMIF Mask */ 931 932 #define RTC_INTSTS_TICKIF_Pos (1) /*!< RTC_T::INTSTS: TICKIF Position */ 933 #define RTC_INTSTS_TICKIF_Msk (0x1ul << RTC_INTSTS_TICKIF_Pos) /*!< RTC_T::INTSTS: TICKIF Mask */ 934 935 #define RTC_INTSTS_TAMP0IF_Pos (8) /*!< RTC_T::INTSTS: TAMP0IF Position */ 936 #define RTC_INTSTS_TAMP0IF_Msk (0x1ul << RTC_INTSTS_TAMP0IF_Pos) /*!< RTC_T::INTSTS: TAMP0IF Mask */ 937 938 #define RTC_INTSTS_TAMP1IF_Pos (9) /*!< RTC_T::INTSTS: TAMP1IF Position */ 939 #define RTC_INTSTS_TAMP1IF_Msk (0x1ul << RTC_INTSTS_TAMP1IF_Pos) /*!< RTC_T::INTSTS: TAMP1IF Mask */ 940 941 #define RTC_INTSTS_TAMP2IF_Pos (10) /*!< RTC_T::INTSTS: TAMP2IF Position */ 942 #define RTC_INTSTS_TAMP2IF_Msk (0x1ul << RTC_INTSTS_TAMP2IF_Pos) /*!< RTC_T::INTSTS: TAMP2IF Mask */ 943 944 #define RTC_INTSTS_TAMP3IF_Pos (11) /*!< RTC_T::INTSTS: TAMP3IF Position */ 945 #define RTC_INTSTS_TAMP3IF_Msk (0x1ul << RTC_INTSTS_TAMP3IF_Pos) /*!< RTC_T::INTSTS: TAMP3IF Mask */ 946 947 #define RTC_INTSTS_TAMP4IF_Pos (12) /*!< RTC_T::INTSTS: TAMP4IF Position */ 948 #define RTC_INTSTS_TAMP4IF_Msk (0x1ul << RTC_INTSTS_TAMP4IF_Pos) /*!< RTC_T::INTSTS: TAMP4IF Mask */ 949 950 #define RTC_INTSTS_TAMP5IF_Pos (13) /*!< RTC_T::INTSTS: TAMP5IF Position */ 951 #define RTC_INTSTS_TAMP5IF_Msk (0x1ul << RTC_INTSTS_TAMP5IF_Pos) /*!< RTC_T::INTSTS: TAMP5IF Mask */ 952 953 #define RTC_INTSTS_CLKFIF_Pos (24) /*!< RTC_T::INTSTS: CLKFIF Position */ 954 #define RTC_INTSTS_CLKFIF_Msk (0x1ul << RTC_INTSTS_CLKFIF_Pos) /*!< RTC_T::INTSTS: CLKFIF Mask */ 955 956 #define RTC_INTSTS_CLKSPIF_Pos (25) /*!< RTC_T::INTSTS: CLKSPIF Position */ 957 #define RTC_INTSTS_CLKSPIF_Msk (0x1ul << RTC_INTSTS_CLKSPIF_Pos) /*!< RTC_T::INTSTS: CLKSPIF Mask */ 958 959 #define RTC_TICK_TICK_Pos (0) /*!< RTC_T::TICK: TICK Position */ 960 #define RTC_TICK_TICK_Msk (0x7ul << RTC_TICK_TICK_Pos) /*!< RTC_T::TICK: TICK Mask */ 961 962 #define RTC_TAMSK_MSEC_Pos (0) /*!< RTC_T::TAMSK: MSEC Position */ 963 #define RTC_TAMSK_MSEC_Msk (0x1ul << RTC_TAMSK_MSEC_Pos) /*!< RTC_T::TAMSK: MSEC Mask */ 964 965 #define RTC_TAMSK_MTENSEC_Pos (1) /*!< RTC_T::TAMSK: MTENSEC Position */ 966 #define RTC_TAMSK_MTENSEC_Msk (0x1ul << RTC_TAMSK_MTENSEC_Pos) /*!< RTC_T::TAMSK: MTENSEC Mask */ 967 968 #define RTC_TAMSK_MMIN_Pos (2) /*!< RTC_T::TAMSK: MMIN Position */ 969 #define RTC_TAMSK_MMIN_Msk (0x1ul << RTC_TAMSK_MMIN_Pos) /*!< RTC_T::TAMSK: MMIN Mask */ 970 971 #define RTC_TAMSK_MTENMIN_Pos (3) /*!< RTC_T::TAMSK: MTENMIN Position */ 972 #define RTC_TAMSK_MTENMIN_Msk (0x1ul << RTC_TAMSK_MTENMIN_Pos) /*!< RTC_T::TAMSK: MTENMIN Mask */ 973 974 #define RTC_TAMSK_MHR_Pos (4) /*!< RTC_T::TAMSK: MHR Position */ 975 #define RTC_TAMSK_MHR_Msk (0x1ul << RTC_TAMSK_MHR_Pos) /*!< RTC_T::TAMSK: MHR Mask */ 976 977 #define RTC_TAMSK_MTENHR_Pos (5) /*!< RTC_T::TAMSK: MTENHR Position */ 978 #define RTC_TAMSK_MTENHR_Msk (0x1ul << RTC_TAMSK_MTENHR_Pos) /*!< RTC_T::TAMSK: MTENHR Mask */ 979 980 #define RTC_CAMSK_MDAY_Pos (0) /*!< RTC_T::CAMSK: MDAY Position */ 981 #define RTC_CAMSK_MDAY_Msk (0x1ul << RTC_CAMSK_MDAY_Pos) /*!< RTC_T::CAMSK: MDAY Mask */ 982 983 #define RTC_CAMSK_MTENDAY_Pos (1) /*!< RTC_T::CAMSK: MTENDAY Position */ 984 #define RTC_CAMSK_MTENDAY_Msk (0x1ul << RTC_CAMSK_MTENDAY_Pos) /*!< RTC_T::CAMSK: MTENDAY Mask */ 985 986 #define RTC_CAMSK_MMON_Pos (2) /*!< RTC_T::CAMSK: MMON Position */ 987 #define RTC_CAMSK_MMON_Msk (0x1ul << RTC_CAMSK_MMON_Pos) /*!< RTC_T::CAMSK: MMON Mask */ 988 989 #define RTC_CAMSK_MTENMON_Pos (3) /*!< RTC_T::CAMSK: MTENMON Position */ 990 #define RTC_CAMSK_MTENMON_Msk (0x1ul << RTC_CAMSK_MTENMON_Pos) /*!< RTC_T::CAMSK: MTENMON Mask */ 991 992 #define RTC_CAMSK_MYEAR_Pos (4) /*!< RTC_T::CAMSK: MYEAR Position */ 993 #define RTC_CAMSK_MYEAR_Msk (0x1ul << RTC_CAMSK_MYEAR_Pos) /*!< RTC_T::CAMSK: MYEAR Mask */ 994 995 #define RTC_CAMSK_MTENYEAR_Pos (5) /*!< RTC_T::CAMSK: MTENYEAR Position */ 996 #define RTC_CAMSK_MTENYEAR_Msk (0x1ul << RTC_CAMSK_MTENYEAR_Pos) /*!< RTC_T::CAMSK: MTENYEAR Mask */ 997 998 #define RTC_SPRCTL_SPRRWEN_Pos (2) /*!< RTC_T::SPRCTL: SPRRWEN Position */ 999 #define RTC_SPRCTL_SPRRWEN_Msk (0x1ul << RTC_SPRCTL_SPRRWEN_Pos) /*!< RTC_T::SPRCTL: SPRRWEN Mask */ 1000 1001 #define RTC_SPRCTL_SPRCSTS_Pos (5) /*!< RTC_T::SPRCTL: SPRCSTS Position */ 1002 #define RTC_SPRCTL_SPRCSTS_Msk (0x1ul << RTC_SPRCTL_SPRCSTS_Pos) /*!< RTC_T::SPRCTL: SPRCSTS Mask */ 1003 1004 #define RTC_SPRCTL_LXTFCLR_Pos (16) /*!< RTC_T::SPRCTL: LXTFCLR Position */ 1005 #define RTC_SPRCTL_LXTFCLR_Msk (0x1ul << RTC_SPRCTL_LXTFCLR_Pos) /*!< RTC_T::SPRCTL: LXTFCLR Mask */ 1006 1007 #define RTC_SPR0_SPARE_Pos (0) /*!< RTC_T::SPR0: SPARE Position */ 1008 #define RTC_SPR0_SPARE_Msk (0xfffffffful << RTC_SPR0_SPARE_Pos) /*!< RTC_T::SPR0: SPARE Mask */ 1009 1010 #define RTC_SPR1_SPARE_Pos (0) /*!< RTC_T::SPR1: SPARE Position */ 1011 #define RTC_SPR1_SPARE_Msk (0xfffffffful << RTC_SPR1_SPARE_Pos) /*!< RTC_T::SPR1: SPARE Mask */ 1012 1013 #define RTC_SPR2_SPARE_Pos (0) /*!< RTC_T::SPR2: SPARE Position */ 1014 #define RTC_SPR2_SPARE_Msk (0xfffffffful << RTC_SPR2_SPARE_Pos) /*!< RTC_T::SPR2: SPARE Mask */ 1015 1016 #define RTC_SPR3_SPARE_Pos (0) /*!< RTC_T::SPR3: SPARE Position */ 1017 #define RTC_SPR3_SPARE_Msk (0xfffffffful << RTC_SPR3_SPARE_Pos) /*!< RTC_T::SPR3: SPARE Mask */ 1018 1019 #define RTC_SPR4_SPARE_Pos (0) /*!< RTC_T::SPR4: SPARE Position */ 1020 #define RTC_SPR4_SPARE_Msk (0xfffffffful << RTC_SPR4_SPARE_Pos) /*!< RTC_T::SPR4: SPARE Mask */ 1021 1022 #define RTC_SPR5_SPARE_Pos (0) /*!< RTC_T::SPR5: SPARE Position */ 1023 #define RTC_SPR5_SPARE_Msk (0xfffffffful << RTC_SPR5_SPARE_Pos) /*!< RTC_T::SPR5: SPARE Mask */ 1024 1025 #define RTC_SPR6_SPARE_Pos (0) /*!< RTC_T::SPR6: SPARE Position */ 1026 #define RTC_SPR6_SPARE_Msk (0xfffffffful << RTC_SPR6_SPARE_Pos) /*!< RTC_T::SPR6: SPARE Mask */ 1027 1028 #define RTC_SPR7_SPARE_Pos (0) /*!< RTC_T::SPR7: SPARE Position */ 1029 #define RTC_SPR7_SPARE_Msk (0xfffffffful << RTC_SPR7_SPARE_Pos) /*!< RTC_T::SPR7: SPARE Mask */ 1030 1031 #define RTC_SPR8_SPARE_Pos (0) /*!< RTC_T::SPR8: SPARE Position */ 1032 #define RTC_SPR8_SPARE_Msk (0xfffffffful << RTC_SPR8_SPARE_Pos) /*!< RTC_T::SPR8: SPARE Mask */ 1033 1034 #define RTC_SPR9_SPARE_Pos (0) /*!< RTC_T::SPR9: SPARE Position */ 1035 #define RTC_SPR9_SPARE_Msk (0xfffffffful << RTC_SPR9_SPARE_Pos) /*!< RTC_T::SPR9: SPARE Mask */ 1036 1037 #define RTC_SPR10_SPARE_Pos (0) /*!< RTC_T::SPR10: SPARE Position */ 1038 #define RTC_SPR10_SPARE_Msk (0xfffffffful << RTC_SPR10_SPARE_Pos) /*!< RTC_T::SPR10: SPARE Mask */ 1039 1040 #define RTC_SPR11_SPARE_Pos (0) /*!< RTC_T::SPR11: SPARE Position */ 1041 #define RTC_SPR11_SPARE_Msk (0xfffffffful << RTC_SPR11_SPARE_Pos) /*!< RTC_T::SPR11: SPARE Mask */ 1042 1043 #define RTC_SPR12_SPARE_Pos (0) /*!< RTC_T::SPR12: SPARE Position */ 1044 #define RTC_SPR12_SPARE_Msk (0xfffffffful << RTC_SPR12_SPARE_Pos) /*!< RTC_T::SPR12: SPARE Mask */ 1045 1046 #define RTC_SPR13_SPARE_Pos (0) /*!< RTC_T::SPR13: SPARE Position */ 1047 #define RTC_SPR13_SPARE_Msk (0xfffffffful << RTC_SPR13_SPARE_Pos) /*!< RTC_T::SPR13: SPARE Mask */ 1048 1049 #define RTC_SPR14_SPARE_Pos (0) /*!< RTC_T::SPR14: SPARE Position */ 1050 #define RTC_SPR14_SPARE_Msk (0xfffffffful << RTC_SPR14_SPARE_Pos) /*!< RTC_T::SPR14: SPARE Mask */ 1051 1052 #define RTC_SPR15_SPARE_Pos (0) /*!< RTC_T::SPR15: SPARE Position */ 1053 #define RTC_SPR15_SPARE_Msk (0xfffffffful << RTC_SPR15_SPARE_Pos) /*!< RTC_T::SPR15: SPARE Mask */ 1054 1055 #define RTC_SPR16_SPARE_Pos (0) /*!< RTC_T::SPR16: SPARE Position */ 1056 #define RTC_SPR16_SPARE_Msk (0xfffffffful << RTC_SPR16_SPARE_Pos) /*!< RTC_T::SPR16: SPARE Mask */ 1057 1058 #define RTC_SPR17_SPARE_Pos (0) /*!< RTC_T::SPR17: SPARE Position */ 1059 #define RTC_SPR17_SPARE_Msk (0xfffffffful << RTC_SPR17_SPARE_Pos) /*!< RTC_T::SPR17: SPARE Mask */ 1060 1061 #define RTC_SPR18_SPARE_Pos (0) /*!< RTC_T::SPR18: SPARE Position */ 1062 #define RTC_SPR18_SPARE_Msk (0xfffffffful << RTC_SPR18_SPARE_Pos) /*!< RTC_T::SPR18: SPARE Mask */ 1063 1064 #define RTC_SPR19_SPARE_Pos (0) /*!< RTC_T::SPR19: SPARE Position */ 1065 #define RTC_SPR19_SPARE_Msk (0xfffffffful << RTC_SPR19_SPARE_Pos) /*!< RTC_T::SPR19: SPARE Mask */ 1066 1067 #define RTC_LXTCTL_LIRC32KEN_Pos (0) /*!< RTC_T::LXTCTL: LIRC32KEN Position */ 1068 #define RTC_LXTCTL_LIRC32KEN_Msk (0x1ul << RTC_LXTCTL_LIRC32KEN_Pos) /*!< RTC_T::LXTCTL: LIRC32KEN Mask */ 1069 1070 #define RTC_LXTCTL_GAIN_Pos (1) /*!< RTC_T::LXTCTL: GAIN Position */ 1071 #define RTC_LXTCTL_GAIN_Msk (0x7ul << RTC_LXTCTL_GAIN_Pos) /*!< RTC_T::LXTCTL: GAIN Mask */ 1072 1073 #define RTC_LXTCTL_C32KS_Pos (7) /*!< RTC_T::LXTCTL: C32KS Position */ 1074 #define RTC_LXTCTL_C32KS_Msk (0x1ul << RTC_LXTCTL_C32KS_Pos) /*!< RTC_T::LXTCTL: C32KS Mask */ 1075 1076 #define RTC_GPIOCTL0_OPMODE0_Pos (0) /*!< RTC_T::GPIOCTL0: OPMODE0 Position */ 1077 #define RTC_GPIOCTL0_OPMODE0_Msk (0x3ul << RTC_GPIOCTL0_OPMODE0_Pos) /*!< RTC_T::GPIOCTL0: OPMODE0 Mask */ 1078 1079 #define RTC_GPIOCTL0_DOUT0_Pos (2) /*!< RTC_T::GPIOCTL0: DOUT0 Position */ 1080 #define RTC_GPIOCTL0_DOUT0_Msk (0x1ul << RTC_GPIOCTL0_DOUT0_Pos) /*!< RTC_T::GPIOCTL0: DOUT0 Mask */ 1081 1082 #define RTC_GPIOCTL0_CTLSEL0_Pos (3) /*!< RTC_T::GPIOCTL0: CTLSEL0 Position */ 1083 #define RTC_GPIOCTL0_CTLSEL0_Msk (0x1ul << RTC_GPIOCTL0_CTLSEL0_Pos) /*!< RTC_T::GPIOCTL0: CTLSEL0 Mask */ 1084 1085 #define RTC_GPIOCTL0_PUSEL0_Pos (4) /*!< RTC_T::GPIOCTL0: PUSEL0 Position */ 1086 #define RTC_GPIOCTL0_PUSEL0_Msk (0x3ul << RTC_GPIOCTL0_PUSEL0_Pos) /*!< RTC_T::GPIOCTL0: PUSEL0 Mask */ 1087 1088 #define RTC_GPIOCTL0_OPMODE1_Pos (8) /*!< RTC_T::GPIOCTL0: OPMODE1 Position */ 1089 #define RTC_GPIOCTL0_OPMODE1_Msk (0x3ul << RTC_GPIOCTL0_OPMODE1_Pos) /*!< RTC_T::GPIOCTL0: OPMODE1 Mask */ 1090 1091 #define RTC_GPIOCTL0_DOUT1_Pos (10) /*!< RTC_T::GPIOCTL0: DOUT1 Position */ 1092 #define RTC_GPIOCTL0_DOUT1_Msk (0x1ul << RTC_GPIOCTL0_DOUT1_Pos) /*!< RTC_T::GPIOCTL0: DOUT1 Mask */ 1093 1094 #define RTC_GPIOCTL0_CTLSEL1_Pos (11) /*!< RTC_T::GPIOCTL0: CTLSEL1 Position */ 1095 #define RTC_GPIOCTL0_CTLSEL1_Msk (0x1ul << RTC_GPIOCTL0_CTLSEL1_Pos) /*!< RTC_T::GPIOCTL0: CTLSEL1 Mask */ 1096 1097 #define RTC_GPIOCTL0_PUSEL1_Pos (12) /*!< RTC_T::GPIOCTL0: PUSEL1 Position */ 1098 #define RTC_GPIOCTL0_PUSEL1_Msk (0x3ul << RTC_GPIOCTL0_PUSEL1_Pos) /*!< RTC_T::GPIOCTL0: PUSEL1 Mask */ 1099 1100 #define RTC_GPIOCTL0_OPMODE2_Pos (16) /*!< RTC_T::GPIOCTL0: OPMODE2 Position */ 1101 #define RTC_GPIOCTL0_OPMODE2_Msk (0x3ul << RTC_GPIOCTL0_OPMODE2_Pos) /*!< RTC_T::GPIOCTL0: OPMODE2 Mask */ 1102 1103 #define RTC_GPIOCTL0_DOUT2_Pos (18) /*!< RTC_T::GPIOCTL0: DOUT2 Position */ 1104 #define RTC_GPIOCTL0_DOUT2_Msk (0x1ul << RTC_GPIOCTL0_DOUT2_Pos) /*!< RTC_T::GPIOCTL0: DOUT2 Mask */ 1105 1106 #define RTC_GPIOCTL0_CTLSEL2_Pos (19) /*!< RTC_T::GPIOCTL0: CTLSEL2 Position */ 1107 #define RTC_GPIOCTL0_CTLSEL2_Msk (0x1ul << RTC_GPIOCTL0_CTLSEL2_Pos) /*!< RTC_T::GPIOCTL0: CTLSEL2 Mask */ 1108 1109 #define RTC_GPIOCTL0_PUSEL2_Pos (20) /*!< RTC_T::GPIOCTL0: PUSEL2 Position */ 1110 #define RTC_GPIOCTL0_PUSEL2_Msk (0x3ul << RTC_GPIOCTL0_PUSEL2_Pos) /*!< RTC_T::GPIOCTL0: PUSEL2 Mask */ 1111 1112 #define RTC_GPIOCTL0_OPMODE3_Pos (24) /*!< RTC_T::GPIOCTL0: OPMODE3 Position */ 1113 #define RTC_GPIOCTL0_OPMODE3_Msk (0x3ul << RTC_GPIOCTL0_OPMODE3_Pos) /*!< RTC_T::GPIOCTL0: OPMODE3 Mask */ 1114 1115 #define RTC_GPIOCTL0_DOUT3_Pos (26) /*!< RTC_T::GPIOCTL0: DOUT3 Position */ 1116 #define RTC_GPIOCTL0_DOUT3_Msk (0x1ul << RTC_GPIOCTL0_DOUT3_Pos) /*!< RTC_T::GPIOCTL0: DOUT3 Mask */ 1117 1118 #define RTC_GPIOCTL0_CTLSEL3_Pos (27) /*!< RTC_T::GPIOCTL0: CTLSEL3 Position */ 1119 #define RTC_GPIOCTL0_CTLSEL3_Msk (0x1ul << RTC_GPIOCTL0_CTLSEL3_Pos) /*!< RTC_T::GPIOCTL0: CTLSEL3 Mask */ 1120 1121 #define RTC_GPIOCTL0_PUSEL3_Pos (28) /*!< RTC_T::GPIOCTL0: PUSEL3 Position */ 1122 #define RTC_GPIOCTL0_PUSEL3_Msk (0x3ul << RTC_GPIOCTL0_PUSEL3_Pos) /*!< RTC_T::GPIOCTL0: PUSEL3 Mask */ 1123 1124 #define RTC_GPIOCTL1_OPMODE4_Pos (0) /*!< RTC_T::GPIOCTL1: OPMODE4 Position */ 1125 #define RTC_GPIOCTL1_OPMODE4_Msk (0x3ul << RTC_GPIOCTL1_OPMODE4_Pos) /*!< RTC_T::GPIOCTL1: OPMODE4 Mask */ 1126 1127 #define RTC_GPIOCTL1_DOUT4_Pos (2) /*!< RTC_T::GPIOCTL1: DOUT4 Position */ 1128 #define RTC_GPIOCTL1_DOUT4_Msk (0x1ul << RTC_GPIOCTL1_DOUT4_Pos) /*!< RTC_T::GPIOCTL1: DOUT4 Mask */ 1129 1130 #define RTC_GPIOCTL1_CTLSEL4_Pos (3) /*!< RTC_T::GPIOCTL1: CTLSEL4 Position */ 1131 #define RTC_GPIOCTL1_CTLSEL4_Msk (0x1ul << RTC_GPIOCTL1_CTLSEL4_Pos) /*!< RTC_T::GPIOCTL1: CTLSEL4 Mask */ 1132 1133 #define RTC_GPIOCTL1_PUSEL4_Pos (4) /*!< RTC_T::GPIOCTL1: PUSEL4 Position */ 1134 #define RTC_GPIOCTL1_PUSEL4_Msk (0x3ul << RTC_GPIOCTL1_PUSEL4_Pos) /*!< RTC_T::GPIOCTL1: PUSEL4 Mask */ 1135 1136 #define RTC_GPIOCTL1_OPMODE5_Pos (8) /*!< RTC_T::GPIOCTL1: OPMODE5 Position */ 1137 #define RTC_GPIOCTL1_OPMODE5_Msk (0x3ul << RTC_GPIOCTL1_OPMODE5_Pos) /*!< RTC_T::GPIOCTL1: OPMODE5 Mask */ 1138 1139 #define RTC_GPIOCTL1_DOUT5_Pos (10) /*!< RTC_T::GPIOCTL1: DOUT5 Position */ 1140 #define RTC_GPIOCTL1_DOUT5_Msk (0x1ul << RTC_GPIOCTL1_DOUT5_Pos) /*!< RTC_T::GPIOCTL1: DOUT5 Mask */ 1141 1142 #define RTC_GPIOCTL1_CTLSEL5_Pos (11) /*!< RTC_T::GPIOCTL1: CTLSEL5 Position */ 1143 #define RTC_GPIOCTL1_CTLSEL5_Msk (0x1ul << RTC_GPIOCTL1_CTLSEL5_Pos) /*!< RTC_T::GPIOCTL1: CTLSEL5 Mask */ 1144 1145 #define RTC_GPIOCTL1_PUSEL5_Pos (12) /*!< RTC_T::GPIOCTL1: PUSEL5 Position */ 1146 #define RTC_GPIOCTL1_PUSEL5_Msk (0x3ul << RTC_GPIOCTL1_PUSEL5_Pos) /*!< RTC_T::GPIOCTL1: PUSEL5 Mask */ 1147 1148 #define RTC_GPIOCTL1_OPMODE6_Pos (16) /*!< RTC_T::GPIOCTL1: OPMODE6 Position */ 1149 #define RTC_GPIOCTL1_OPMODE6_Msk (0x3ul << RTC_GPIOCTL1_OPMODE6_Pos) /*!< RTC_T::GPIOCTL1: OPMODE6 Mask */ 1150 1151 #define RTC_GPIOCTL1_DOUT6_Pos (18) /*!< RTC_T::GPIOCTL1: DOUT6 Position */ 1152 #define RTC_GPIOCTL1_DOUT6_Msk (0x1ul << RTC_GPIOCTL1_DOUT6_Pos) /*!< RTC_T::GPIOCTL1: DOUT6 Mask */ 1153 1154 #define RTC_GPIOCTL1_CTLSEL6_Pos (19) /*!< RTC_T::GPIOCTL1: CTLSEL6 Position */ 1155 #define RTC_GPIOCTL1_CTLSEL6_Msk (0x1ul << RTC_GPIOCTL1_CTLSEL6_Pos) /*!< RTC_T::GPIOCTL1: CTLSEL6 Mask */ 1156 1157 #define RTC_GPIOCTL1_PUSEL6_Pos (20) /*!< RTC_T::GPIOCTL1: PUSEL6 Position */ 1158 #define RTC_GPIOCTL1_PUSEL6_Msk (0x3ul << RTC_GPIOCTL1_PUSEL6_Pos) /*!< RTC_T::GPIOCTL1: PUSEL6 Mask */ 1159 1160 #define RTC_GPIOCTL1_OPMODE7_Pos (24) /*!< RTC_T::GPIOCTL1: OPMODE7 Position */ 1161 #define RTC_GPIOCTL1_OPMODE7_Msk (0x3ul << RTC_GPIOCTL1_OPMODE7_Pos) /*!< RTC_T::GPIOCTL1: OPMODE7 Mask */ 1162 1163 #define RTC_GPIOCTL1_DOUT7_Pos (26) /*!< RTC_T::GPIOCTL1: DOUT7 Position */ 1164 #define RTC_GPIOCTL1_DOUT7_Msk (0x1ul << RTC_GPIOCTL1_DOUT7_Pos) /*!< RTC_T::GPIOCTL1: DOUT7 Mask */ 1165 1166 #define RTC_GPIOCTL1_CTLSEL7_Pos (27) /*!< RTC_T::GPIOCTL1: CTLSEL7 Position */ 1167 #define RTC_GPIOCTL1_CTLSEL7_Msk (0x1ul << RTC_GPIOCTL1_CTLSEL7_Pos) /*!< RTC_T::GPIOCTL1: CTLSEL7 Mask */ 1168 1169 #define RTC_GPIOCTL1_PUSEL7_Pos (28) /*!< RTC_T::GPIOCTL1: PUSEL7 Position */ 1170 #define RTC_GPIOCTL1_PUSEL7_Msk (0x3ul << RTC_GPIOCTL1_PUSEL7_Pos) /*!< RTC_T::GPIOCTL1: PUSEL7 Mask */ 1171 1172 #define RTC_DSTCTL_ADDHR_Pos (0) /*!< RTC_T::DSTCTL: ADDHR Position */ 1173 #define RTC_DSTCTL_ADDHR_Msk (0x1ul << RTC_DSTCTL_ADDHR_Pos) /*!< RTC_T::DSTCTL: ADDHR Mask */ 1174 1175 #define RTC_DSTCTL_SUBHR_Pos (1) /*!< RTC_T::DSTCTL: SUBHR Position */ 1176 #define RTC_DSTCTL_SUBHR_Msk (0x1ul << RTC_DSTCTL_SUBHR_Pos) /*!< RTC_T::DSTCTL: SUBHR Mask */ 1177 1178 #define RTC_DSTCTL_DSBAK_Pos (2) /*!< RTC_T::DSTCTL: DSBAK Position */ 1179 #define RTC_DSTCTL_DSBAK_Msk (0x1ul << RTC_DSTCTL_DSBAK_Pos) /*!< RTC_T::DSTCTL: DSBAK Mask */ 1180 1181 #define RTC_TAMPCTL_DYN1ISS_Pos (0) /*!< RTC_T::TAMPCTL: DYN1ISS Position */ 1182 #define RTC_TAMPCTL_DYN1ISS_Msk (0x1ul << RTC_TAMPCTL_DYN1ISS_Pos) /*!< RTC_T::TAMPCTL: DYN1ISS Mask */ 1183 1184 #define RTC_TAMPCTL_DYN2ISS_Pos (1) /*!< RTC_T::TAMPCTL: DYN2ISS Position */ 1185 #define RTC_TAMPCTL_DYN2ISS_Msk (0x1ul << RTC_TAMPCTL_DYN2ISS_Pos) /*!< RTC_T::TAMPCTL: DYN2ISS Mask */ 1186 1187 #define RTC_TAMPCTL_DYNSRC_Pos (2) /*!< RTC_T::TAMPCTL: DYNSRC Position */ 1188 #define RTC_TAMPCTL_DYNSRC_Msk (0x3ul << RTC_TAMPCTL_DYNSRC_Pos) /*!< RTC_T::TAMPCTL: DYNSRC Mask */ 1189 1190 #define RTC_TAMPCTL_SEEDRLD_Pos (4) /*!< RTC_T::TAMPCTL: SEEDRLD Position */ 1191 #define RTC_TAMPCTL_SEEDRLD_Msk (0x1ul << RTC_TAMPCTL_SEEDRLD_Pos) /*!< RTC_T::TAMPCTL: SEEDRLD Mask */ 1192 1193 #define RTC_TAMPCTL_DYNRATE_Pos (5) /*!< RTC_T::TAMPCTL: DYNRATE Position */ 1194 #define RTC_TAMPCTL_DYNRATE_Msk (0x7ul << RTC_TAMPCTL_DYNRATE_Pos) /*!< RTC_T::TAMPCTL: DYNRATE Mask */ 1195 1196 #define RTC_TAMPCTL_TAMP0EN_Pos (8) /*!< RTC_T::TAMPCTL: TAMP0EN Position */ 1197 #define RTC_TAMPCTL_TAMP0EN_Msk (0x1ul << RTC_TAMPCTL_TAMP0EN_Pos) /*!< RTC_T::TAMPCTL: TAMP0EN Mask */ 1198 1199 #define RTC_TAMPCTL_TAMP0LV_Pos (9) /*!< RTC_T::TAMPCTL: TAMP0LV Position */ 1200 #define RTC_TAMPCTL_TAMP0LV_Msk (0x1ul << RTC_TAMPCTL_TAMP0LV_Pos) /*!< RTC_T::TAMPCTL: TAMP0LV Mask */ 1201 1202 #define RTC_TAMPCTL_TAMP0DBEN_Pos (10) /*!< RTC_T::TAMPCTL: TAMP0DBEN Position */ 1203 #define RTC_TAMPCTL_TAMP0DBEN_Msk (0x1ul << RTC_TAMPCTL_TAMP0DBEN_Pos) /*!< RTC_T::TAMPCTL: TAMP0DBEN Mask */ 1204 1205 #define RTC_TAMPCTL_TAMP1EN_Pos (12) /*!< RTC_T::TAMPCTL: TAMP1EN Position */ 1206 #define RTC_TAMPCTL_TAMP1EN_Msk (0x1ul << RTC_TAMPCTL_TAMP1EN_Pos) /*!< RTC_T::TAMPCTL: TAMP1EN Mask */ 1207 1208 #define RTC_TAMPCTL_TAMP1LV_Pos (13) /*!< RTC_T::TAMPCTL: TAMP1LV Position */ 1209 #define RTC_TAMPCTL_TAMP1LV_Msk (0x1ul << RTC_TAMPCTL_TAMP1LV_Pos) /*!< RTC_T::TAMPCTL: TAMP1LV Mask */ 1210 1211 #define RTC_TAMPCTL_TAMP1DBEN_Pos (14) /*!< RTC_T::TAMPCTL: TAMP1DBEN Position */ 1212 #define RTC_TAMPCTL_TAMP1DBEN_Msk (0x1ul << RTC_TAMPCTL_TAMP1DBEN_Pos) /*!< RTC_T::TAMPCTL: TAMP1DBEN Mask */ 1213 1214 #define RTC_TAMPCTL_DYNPR0EN_Pos (15) /*!< RTC_T::TAMPCTL: DYNPR0EN Position */ 1215 #define RTC_TAMPCTL_DYNPR0EN_Msk (0x1ul << RTC_TAMPCTL_DYNPR0EN_Pos) /*!< RTC_T::TAMPCTL: DYNPR0EN Mask */ 1216 1217 #define RTC_TAMPCTL_TAMP2EN_Pos (16) /*!< RTC_T::TAMPCTL: TAMP2EN Position */ 1218 #define RTC_TAMPCTL_TAMP2EN_Msk (0x1ul << RTC_TAMPCTL_TAMP2EN_Pos) /*!< RTC_T::TAMPCTL: TAMP2EN Mask */ 1219 1220 #define RTC_TAMPCTL_TAMP2LV_Pos (17) /*!< RTC_T::TAMPCTL: TAMP2LV Position */ 1221 #define RTC_TAMPCTL_TAMP2LV_Msk (0x1ul << RTC_TAMPCTL_TAMP2LV_Pos) /*!< RTC_T::TAMPCTL: TAMP2LV Mask */ 1222 1223 #define RTC_TAMPCTL_TAMP2DBEN_Pos (18) /*!< RTC_T::TAMPCTL: TAMP2DBEN Position */ 1224 #define RTC_TAMPCTL_TAMP2DBEN_Msk (0x1ul << RTC_TAMPCTL_TAMP2DBEN_Pos) /*!< RTC_T::TAMPCTL: TAMP2DBEN Mask */ 1225 1226 #define RTC_TAMPCTL_TAMP3EN_Pos (20) /*!< RTC_T::TAMPCTL: TAMP3EN Position */ 1227 #define RTC_TAMPCTL_TAMP3EN_Msk (0x1ul << RTC_TAMPCTL_TAMP3EN_Pos) /*!< RTC_T::TAMPCTL: TAMP3EN Mask */ 1228 1229 #define RTC_TAMPCTL_TAMP3LV_Pos (21) /*!< RTC_T::TAMPCTL: TAMP3LV Position */ 1230 #define RTC_TAMPCTL_TAMP3LV_Msk (0x1ul << RTC_TAMPCTL_TAMP3LV_Pos) /*!< RTC_T::TAMPCTL: TAMP3LV Mask */ 1231 1232 #define RTC_TAMPCTL_TAMP3DBEN_Pos (22) /*!< RTC_T::TAMPCTL: TAMP3DBEN Position */ 1233 #define RTC_TAMPCTL_TAMP3DBEN_Msk (0x1ul << RTC_TAMPCTL_TAMP3DBEN_Pos) /*!< RTC_T::TAMPCTL: TAMP3DBEN Mask */ 1234 1235 #define RTC_TAMPCTL_DYNPR1EN_Pos (23) /*!< RTC_T::TAMPCTL: DYNPR1EN Position */ 1236 #define RTC_TAMPCTL_DYNPR1EN_Msk (0x1ul << RTC_TAMPCTL_DYNPR1EN_Pos) /*!< RTC_T::TAMPCTL: DYNPR1EN Mask */ 1237 1238 #define RTC_TAMPCTL_TAMP4EN_Pos (24) /*!< RTC_T::TAMPCTL: TAMP4EN Position */ 1239 #define RTC_TAMPCTL_TAMP4EN_Msk (0x1ul << RTC_TAMPCTL_TAMP4EN_Pos) /*!< RTC_T::TAMPCTL: TAMP4EN Mask */ 1240 1241 #define RTC_TAMPCTL_TAMP4LV_Pos (25) /*!< RTC_T::TAMPCTL: TAMP4LV Position */ 1242 #define RTC_TAMPCTL_TAMP4LV_Msk (0x1ul << RTC_TAMPCTL_TAMP4LV_Pos) /*!< RTC_T::TAMPCTL: TAMP4LV Mask */ 1243 1244 #define RTC_TAMPCTL_TAMP4DBEN_Pos (26) /*!< RTC_T::TAMPCTL: TAMP4DBEN Position */ 1245 #define RTC_TAMPCTL_TAMP4DBEN_Msk (0x1ul << RTC_TAMPCTL_TAMP4DBEN_Pos) /*!< RTC_T::TAMPCTL: TAMP4DBEN Mask */ 1246 1247 #define RTC_TAMPCTL_TAMP5EN_Pos (28) /*!< RTC_T::TAMPCTL: TAMP5EN Position */ 1248 #define RTC_TAMPCTL_TAMP5EN_Msk (0x1ul << RTC_TAMPCTL_TAMP5EN_Pos) /*!< RTC_T::TAMPCTL: TAMP5EN Mask */ 1249 1250 #define RTC_TAMPCTL_TAMP5LV_Pos (29) /*!< RTC_T::TAMPCTL: TAMP5LV Position */ 1251 #define RTC_TAMPCTL_TAMP5LV_Msk (0x1ul << RTC_TAMPCTL_TAMP5LV_Pos) /*!< RTC_T::TAMPCTL: TAMP5LV Mask */ 1252 1253 #define RTC_TAMPCTL_TAMP5DBEN_Pos (30) /*!< RTC_T::TAMPCTL: TAMP5DBEN Position */ 1254 #define RTC_TAMPCTL_TAMP5DBEN_Msk (0x1ul << RTC_TAMPCTL_TAMP5DBEN_Pos) /*!< RTC_T::TAMPCTL: TAMP5DBEN Mask */ 1255 1256 #define RTC_TAMPCTL_DYNPR2EN_Pos (31) /*!< RTC_T::TAMPCTL: DYNPR2EN Position */ 1257 #define RTC_TAMPCTL_DYNPR2EN_Msk (0x1ul << RTC_TAMPCTL_DYNPR2EN_Pos) /*!< RTC_T::TAMPCTL: DYNPR2EN Mask */ 1258 1259 #define RTC_TAMPSEED_SEED_Pos (0) /*!< RTC_T::TAMPSEED: SEED Position */ 1260 #define RTC_TAMPSEED_SEED_Msk (0xfffffffful << RTC_TAMPSEED_SEED_Pos) /*!< RTC_T::TAMPSEED: SEED Mask */ 1261 1262 #define RTC_TAMPTIME_SEC_Pos (0) /*!< RTC_T::TAMPTIME: SEC Position */ 1263 #define RTC_TAMPTIME_SEC_Msk (0xful << RTC_TAMPTIME_SEC_Pos) /*!< RTC_T::TAMPTIME: SEC Mask */ 1264 1265 #define RTC_TAMPTIME_TENSEC_Pos (4) /*!< RTC_T::TAMPTIME: TENSEC Position */ 1266 #define RTC_TAMPTIME_TENSEC_Msk (0x7ul << RTC_TAMPTIME_TENSEC_Pos) /*!< RTC_T::TAMPTIME: TENSEC Mask */ 1267 1268 #define RTC_TAMPTIME_MIN_Pos (8) /*!< RTC_T::TAMPTIME: MIN Position */ 1269 #define RTC_TAMPTIME_MIN_Msk (0xful << RTC_TAMPTIME_MIN_Pos) /*!< RTC_T::TAMPTIME: MIN Mask */ 1270 1271 #define RTC_TAMPTIME_TENMIN_Pos (12) /*!< RTC_T::TAMPTIME: TENMIN Position */ 1272 #define RTC_TAMPTIME_TENMIN_Msk (0x7ul << RTC_TAMPTIME_TENMIN_Pos) /*!< RTC_T::TAMPTIME: TENMIN Mask */ 1273 1274 #define RTC_TAMPTIME_HR_Pos (16) /*!< RTC_T::TAMPTIME: HR Position */ 1275 #define RTC_TAMPTIME_HR_Msk (0xful << RTC_TAMPTIME_HR_Pos) /*!< RTC_T::TAMPTIME: HR Mask */ 1276 1277 #define RTC_TAMPTIME_TENHR_Pos (20) /*!< RTC_T::TAMPTIME: TENHR Position */ 1278 #define RTC_TAMPTIME_TENHR_Msk (0x3ul << RTC_TAMPTIME_TENHR_Pos) /*!< RTC_T::TAMPTIME: TENHR Mask */ 1279 1280 #define RTC_TAMPTIME_HZCNT_Pos (24) /*!< RTC_T::TAMPTIME: HZCNT Position */ 1281 #define RTC_TAMPTIME_HZCNT_Msk (0x7ful << RTC_TAMPTIME_HZCNT_Pos) /*!< RTC_T::TAMPTIME: HZCNT Mask */ 1282 1283 #define RTC_TAMPCAL_DAY_Pos (0) /*!< RTC_T::TAMPCAL: DAY Position */ 1284 #define RTC_TAMPCAL_DAY_Msk (0xful << RTC_TAMPCAL_DAY_Pos) /*!< RTC_T::TAMPCAL: DAY Mask */ 1285 1286 #define RTC_TAMPCAL_TENDAY_Pos (4) /*!< RTC_T::TAMPCAL: TENDAY Position */ 1287 #define RTC_TAMPCAL_TENDAY_Msk (0x3ul << RTC_TAMPCAL_TENDAY_Pos) /*!< RTC_T::TAMPCAL: TENDAY Mask */ 1288 1289 #define RTC_TAMPCAL_MON_Pos (8) /*!< RTC_T::TAMPCAL: MON Position */ 1290 #define RTC_TAMPCAL_MON_Msk (0xful << RTC_TAMPCAL_MON_Pos) /*!< RTC_T::TAMPCAL: MON Mask */ 1291 1292 #define RTC_TAMPCAL_TENMON_Pos (12) /*!< RTC_T::TAMPCAL: TENMON Position */ 1293 #define RTC_TAMPCAL_TENMON_Msk (0x1ul << RTC_TAMPCAL_TENMON_Pos) /*!< RTC_T::TAMPCAL: TENMON Mask */ 1294 1295 #define RTC_TAMPCAL_YEAR_Pos (16) /*!< RTC_T::TAMPCAL: YEAR Position */ 1296 #define RTC_TAMPCAL_YEAR_Msk (0xful << RTC_TAMPCAL_YEAR_Pos) /*!< RTC_T::TAMPCAL: YEAR Mask */ 1297 1298 #define RTC_TAMPCAL_TENYEAR_Pos (20) /*!< RTC_T::TAMPCAL: TENYEAR Position */ 1299 #define RTC_TAMPCAL_TENYEAR_Msk (0xful << RTC_TAMPCAL_TENYEAR_Pos) /*!< RTC_T::TAMPCAL: TENYEAR Mask */ 1300 1301 #define RTC_CLKDCTL_LXTFDEN_Pos (0) /*!< RTC_T::CLKDCTL: LXTFDEN Position */ 1302 #define RTC_CLKDCTL_LXTFDEN_Msk (0x1ul << RTC_CLKDCTL_LXTFDEN_Pos) /*!< RTC_T::CLKDCTL: LXTFDEN Mask */ 1303 1304 #define RTC_CLKDCTL_LXTFSW_Pos (1) /*!< RTC_T::CLKDCTL: LXTFSW Position */ 1305 #define RTC_CLKDCTL_LXTFSW_Msk (0x1ul << RTC_CLKDCTL_LXTFSW_Pos) /*!< RTC_T::CLKDCTL: LXTFSW Mask */ 1306 1307 #define RTC_CLKDCTL_LXTSPSW_Pos (2) /*!< RTC_T::CLKDCTL: LXTSPSW Position */ 1308 #define RTC_CLKDCTL_LXTSPSW_Msk (0x1ul << RTC_CLKDCTL_LXTSPSW_Pos) /*!< RTC_T::CLKDCTL: LXTSPSW Mask */ 1309 1310 #define RTC_CLKDCTL_CLKSWLIRCF_Pos (16) /*!< RTC_T::CLKDCTL: CLKSWLIRCF Position */ 1311 #define RTC_CLKDCTL_CLKSWLIRCF_Msk (0x1ul << RTC_CLKDCTL_CLKSWLIRCF_Pos) /*!< RTC_T::CLKDCTL: CLKSWLIRCF Mask */ 1312 1313 #define RTC_CLKDCTL_LXTFASTF_Pos (17) /*!< RTC_T::CLKDCTL: LXTFASTF Position */ 1314 #define RTC_CLKDCTL_LXTFASTF_Msk (0x1ul << RTC_CLKDCTL_LXTFASTF_Pos) /*!< RTC_T::CLKDCTL: LXTFASTF Mask */ 1315 1316 #define RTC_CDBR_STOPBD_Pos (0) /*!< RTC_T::CDBR: STOPBD Position */ 1317 #define RTC_CDBR_STOPBD_Msk (0xfful << RTC_CDBR_STOPBD_Pos) /*!< RTC_T::CDBR: STOPBD Mask */ 1318 1319 #define RTC_CDBR_FAILBD_Pos (16) /*!< RTC_T::CDBR: FAILBD Position */ 1320 #define RTC_CDBR_FAILBD_Msk (0xfful << RTC_CDBR_FAILBD_Pos) /*!< RTC_T::CDBR: FAILBD Mask */ 1321 1322 /**@}*/ /* RTC_CONST */ 1323 /**@}*/ /* end of RTC register group */ 1324 /**@}*/ /* end of REGISTER group */ 1325 1326 #endif /* __RTC_REG_H__ */ 1327
