1 /**************************************************************************//** 2 * @file rtc_reg.h 3 * @version V1.00 4 * @brief RTC register definition header file 5 * 6 * @copyright SPDX-License-Identifier: Apache-2.0 7 * @copyright Copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. 8 *****************************************************************************/ 9 #ifndef __RTC_REG_H__ 10 #define __RTC_REG_H__ 11 12 /** @addtogroup REGISTER Control Register 13 14 @{ 15 16 */ 17 18 /*---------------------- Real Time Clock Controller -------------------------*/ 19 /** 20 @addtogroup RTC Real Time Clock Controller(RTC) 21 Memory Mapped Structure for RTC Controller 22 @{ 23 */ 24 25 typedef struct 26 { 27 28 29 /** 30 * @var RTC_T::INIT 31 * Offset: 0x00 RTC Initiation Register 32 * --------------------------------------------------------------------------------------------------- 33 * |Bits |Field |Descriptions 34 * | :----: | :----: | :---- | 35 * |[0] |INIT_ACTIVE|RTC Active Status (Read Only) 36 * | | |0 = RTC is at reset state. 37 * | | |1 = RTC is at normal active state. 38 * |[31:1] |INIT |RTC Initiation (Write Only) 39 * | | |When RTC block is powered on, RTC is at reset state. 40 * | | |User has to write a number (0xa5eb1357) to INIT to make RTC leave reset state. 41 * | | |Once the INIT is written as 0xa5eb1357, the RTC will be in un-reset state permanently. 42 * | | |The INIT is a write-only field and read value will be always 0. 43 * @var RTC_T::FREQADJ 44 * Offset: 0x08 RTC Frequency Compensation Register 45 * --------------------------------------------------------------------------------------------------- 46 * |Bits |Field |Descriptions 47 * | :----: | :----: | :---- | 48 * |[5:0] |FRACTION |Fraction Part 49 * | | |Formula: FRACTION = (fraction part of detected value) X 64. 50 * | | |Note: Digit in FCR must be expressed as hexadecimal number. 51 * |[12:8] |INTEGER |Integer Part 52 * | | |00000 = Integer part of detected value is 32752. 53 * | | |00001 = Integer part of detected value is 32753. 54 * | | |00010 = Integer part of detected value is 32754. 55 * | | |00011 = Integer part of detected value is 32755. 56 * | | |00100 = Integer part of detected value is 32756. 57 * | | |00101 = Integer part of detected value is 32757. 58 * | | |00110 = Integer part of detected value is 32758. 59 * | | |00111 = Integer part of detected value is 32759. 60 * | | |01000 = Integer part of detected value is 32760. 61 * | | |01001 = Integer part of detected value is 32761. 62 * | | |01010 = Integer part of detected value is 32762. 63 * | | |01011 = Integer part of detected value is 32763. 64 * | | |01100 = Integer part of detected value is 32764. 65 * | | |01101 = Integer part of detected value is 32765. 66 * | | |01110 = Integer part of detected value is 32766. 67 * | | |01111 = Integer part of detected value is 32767. 68 * | | |10000 = Integer part of detected value is 32768. 69 * | | |10001 = Integer part of detected value is 32769. 70 * | | |10010 = Integer part of detected value is 32770. 71 * | | |10011 = Integer part of detected value is 32771. 72 * | | |10100 = Integer part of detected value is 32772. 73 * | | |10101 = Integer part of detected value is 32773. 74 * | | |10110 = Integer part of detected value is 32774. 75 * | | |10111 = Integer part of detected value is 32775. 76 * | | |11000 = Integer part of detected value is 32776. 77 * | | |11001 = Integer part of detected value is 32777. 78 * | | |11010 = Integer part of detected value is 32778. 79 * | | |11011 = Integer part of detected value is 32779. 80 * | | |11100 = Integer part of detected value is 32780. 81 * | | |11101 = Integer part of detected value is 32781. 82 * | | |11110 = Integer part of detected value is 32782. 83 * | | |11111 = Integer part of detected value is 32783. 84 * |[31] |FCRBUSY |Frequency Compensation Register Write Operation Busy (Read Only) 85 * | | |0 = The new register write operation is acceptable. 86 * | | |1 = The last write operation is in progress and new register write operation prohibited. 87 * | | |Note: This bit is only used when DCOMPEN(RTC_CLKFMT[16]) is enabled. 88 * @var RTC_T::TIME 89 * Offset: 0x0C RTC Time Loading Register 90 * --------------------------------------------------------------------------------------------------- 91 * |Bits |Field |Descriptions 92 * | :----: | :----: | :---- | 93 * |[3:0] |SEC |1-Sec Time Digit (0~9) 94 * |[6:4] |TENSEC |10-Sec Time Digit (0~5) 95 * |[11:8] |MIN |1-Min Time Digit (0~9) 96 * |[14:12] |TENMIN |10-Min Time Digit (0~5) 97 * |[19:16] |HR |1-Hour Time Digit (0~9) 98 * |[21:20] |TENHR |10-Hour Time Digit (0~2) 99 * | | |When RTC runs as 12-hour time scale mode, RTC_TIME[21] (the high bit of TENHR[1:0]) means AM/PM indication (If RTC_TIME[21] is 1, it indicates PM time message.) 100 * @var RTC_T::CAL 101 * Offset: 0x10 RTC Calendar Loading Register 102 * --------------------------------------------------------------------------------------------------- 103 * |Bits |Field |Descriptions 104 * | :----: | :----: | :---- | 105 * |[3:0] |DAY |1-Day Calendar Digit (0~9) 106 * |[5:4] |TENDAY |10-Day Calendar Digit (0~3) 107 * |[11:8] |MON |1-Month Calendar Digit (0~9) 108 * |[12] |TENMON |10-Month Calendar Digit (0~1) 109 * |[19:16] |YEAR |1-Year Calendar Digit (0~9) 110 * |[23:20] |TENYEAR |10-Year Calendar Digit (0~9) 111 * @var RTC_T::CLKFMT 112 * Offset: 0x14 RTC Time Scale Selection Register 113 * --------------------------------------------------------------------------------------------------- 114 * |Bits |Field |Descriptions 115 * | :----: | :----: | :---- | 116 * |[0] |24HEN |24-hour / 12-hour Time Scale Selection 117 * | | |The RTC_TIME and RTC_TALM are in 24-hour time scale or 12-hour time scale. 118 * | | |0 = 12-hour time scale with AM and PM indication selected. 119 * | | |1 = 24-hour time scale selected. 120 * |[16] |DCOMPEN |Dynamic Compensation Enable Bit 121 * | | |0 = Dynamic Compensation Disabled. 122 * | | |1 = Dynamic Compensation Enabled. 123 * @var RTC_T::WEEKDAY 124 * Offset: 0x18 RTC Day of the Week Register 125 * --------------------------------------------------------------------------------------------------- 126 * |Bits |Field |Descriptions 127 * | :----: | :----: | :---- | 128 * |[2:0] |WEEKDAY |Day of the Week Register 129 * | | |000 = Sunday. 130 * | | |001 = Monday. 131 * | | |010 = Tuesday. 132 * | | |011 = Wednesday. 133 * | | |100 = Thursday. 134 * | | |101 = Friday. 135 * | | |110 = Saturday. 136 * | | |111 = Reserved. 137 * @var RTC_T::TALM 138 * Offset: 0x1C RTC Time Alarm Register 139 * --------------------------------------------------------------------------------------------------- 140 * |Bits |Field |Descriptions 141 * | :----: | :----: | :---- | 142 * |[3:0] |SEC |1-Sec Time Digit of Alarm Setting (0~9) 143 * |[6:4] |TENSEC |10-Sec Time Digit of Alarm Setting (0~5) 144 * |[11:8] |MIN |1-Min Time Digit of Alarm Setting (0~9) 145 * |[14:12] |TENMIN |10-Min Time Digit of Alarm Setting (0~5) 146 * |[19:16] |HR |1-Hour Time Digit of Alarm Setting (0~9) 147 * |[21:20] |TENHR |10-Hour Time Digit of Alarm Setting (0~2) 148 * | | |When RTC runs as 12-hour time scale mode, RTC_TIME[21] (the high bit of TENHR[1:0]) means AM/PM indication (If RTC_TIME[21] is 1, it indicates PM time message.) 149 * @var RTC_T::CALM 150 * Offset: 0x20 RTC Calendar Alarm Register 151 * --------------------------------------------------------------------------------------------------- 152 * |Bits |Field |Descriptions 153 * | :----: | :----: | :---- | 154 * |[3:0] |DAY |1-Day Calendar Digit of Alarm Setting (0~9) 155 * |[5:4] |TENDAY |10-Day Calendar Digit of Alarm Setting (0~3) 156 * |[11:8] |MON |1-Month Calendar Digit of Alarm Setting (0~9) 157 * |[12] |TENMON |10-Month Calendar Digit of Alarm Setting (0~1) 158 * |[19:16] |YEAR |1-Year Calendar Digit of Alarm Setting (0~9) 159 * |[23:20] |TENYEAR |10-Year Calendar Digit of Alarm Setting (0~9) 160 * @var RTC_T::LEAPYEAR 161 * Offset: 0x24 RTC Leap Year Indicator Register 162 * --------------------------------------------------------------------------------------------------- 163 * |Bits |Field |Descriptions 164 * | :----: | :----: | :---- | 165 * |[0] |LEAPYEAR |Leap Year Indication (Read Only) 166 * | | |0 = This year is not a leap year. 167 * | | |1 = This year is leap year. 168 * @var RTC_T::INTEN 169 * Offset: 0x28 RTC Interrupt Enable Register 170 * --------------------------------------------------------------------------------------------------- 171 * |Bits |Field |Descriptions 172 * | :----: | :----: | :---- | 173 * |[0] |ALMIEN |Alarm Interrupt Enable Bit 174 * | | |Set ALMIEN to 1 can also enable chip wake-up function when RTC alarm interrupt event is generated. 175 * | | |0 = RTC Alarm interrupt Disabled. 176 * | | |1 = RTC Alarm interrupt Enabled. 177 * |[1] |TICKIEN |Time Tick Interrupt Enable Bit 178 * | | |Set TICKIEN to 1 can also enable chip wake-up function when RTC tick interrupt event is generated. 179 * | | |0 = RTC Time Tick interrupt Disabled. 180 * | | |1 = RTC Time Tick interrupt Enabled. 181 * |[8] |TAMP0IEN |Tamper 0 Interrupt Enable Bit 182 * | | |Set TAMP0IEN to 1 can also enable chip wake-up function when tamper 0 interrupt event is generated. 183 * | | |0 = Tamper 0 interrupt Disabled. 184 * | | |1 = Tamper 0 interrupt Enabled. 185 * |[9] |TAMP1IEN |Tamper 1 or Pair 0 Interrupt Enable Bit 186 * | | |Set TAMP1IEN to 1 can also enable chip wake-up function when tamper 1 interrupt event is generated. 187 * | | |0 = Tamper 1 or Pair 0 interrupt Disabled. 188 * | | |1 = Tamper 1 or Pair 0 interrupt Enabled. 189 * |[10] |TAMP2IEN |Tamper 2 Interrupt Enable Bit 190 * | | |Set TAMP2IEN to 1 can also enable chip wake-up function when tamper 2 interrupt event is generated. 191 * | | |0 = Tamper 2 interrupt Disabled. 192 * | | |1 = Tamper 2 interrupt Enabled. 193 * |[11] |TAMP3IEN |Tamper 3 or Pair 1 Interrupt Enable Bit 194 * | | |Set TAMP3IEN to 1 can also enable chip wake-up function when tamper 3 interrupt event is generated. 195 * | | |0 = Tamper 3 or Pair 1 interrupt Disabled. 196 * | | |1 = Tamper 3 or Pair 1 interrupt Enabled. 197 * |[12] |TAMP4IEN |Tamper 4 Interrupt Enable Bit 198 * | | |Set TAMP4IEN to 1 can also enable chip wake-up function when tamper 4 interrupt event is generated. 199 * | | |0 = Tamper 4 interrupt Disabled. 200 * | | |1 = Tamper 4 interrupt Enabled. 201 * |[13] |TAMP5IEN |Tamper 5 or Pair 2 Interrupt Enable Bit 202 * | | |Set TAMP5IEN to 1 can also enable chip wake-up function when tamper 5 interrupt event is generated. 203 * | | |0 = Tamper 5 or Pair 2 interrupt Disabled. 204 * | | |1 = Tamper 5 or Pair 2 interrupt Enabled. 205 * |[24] |CLKFIEN |LXT Clock Frequency Monitor Fail Interrupt Enable Bit 206 * | | |0 = LXT Frequency Fail interrupt Disabled. 207 * | | |1 = LXT Frequency Fail interrupt Enabled. 208 * |[25] |CLKSTIEN |LXT Clock Frequency Monitor Stop Interrupt Enable Bit 209 * | | |0 = LXT Frequency Stop interrupt Disabled. 210 * | | |1 = LXT Frequency Stop interrupt Enabled. 211 * @var RTC_T::INTSTS 212 * Offset: 0x2C RTC Interrupt Status Register 213 * --------------------------------------------------------------------------------------------------- 214 * |Bits |Field |Descriptions 215 * | :----: | :----: | :---- | 216 * |[0] |ALMIF |RTC Alarm Interrupt Flag 217 * | | |0 = Alarm condition is not matched. 218 * | | |1 = Alarm condition is matched. 219 * | | |Note: Write 1 to clear this bit. 220 * |[1] |TICKIF |RTC Time Tick Interrupt Flag 221 * | | |0 = Tick condition does not occur. 222 * | | |1 = Tick condition occur. 223 * | | |Note: Write 1 to clear this bit. 224 * |[8] |TAMP0IF |Tamper 0 Interrupt Flag 225 * | | |This bit is set when TAMP0_PIN detected level non-equal TAMP0LV (RTC_TAMPCTL[9]). 226 * | | |0 = No Tamper 0 interrupt flag is generated. 227 * | | |1 = Tamper 0 interrupt flag is generated. 228 * | | |Note1: Write 1 to clear this bit. 229 * | | |Note2: This interrupt flag will be generated again when Tamper setting condition is not restoration. 230 * | | |Note3: Need to clear all TAMPxIF, after that, new RTC_TAMPTIME and RTC_TAMPCAL values are loaded while a tamper event occurred. 231 * |[9] |TAMP1IF |Tamper 1 or Pair 0 Interrupt Flag 232 * | | |This bit is set when TAMP1_PIN detected level non-equal TAMP1LV (RTC_TAMPCTL[13]) or TAMP0_PIN and TAMP1_PIN disconnected during DYNPR0EN (RTC_TAMPCTL[15]) is activated. 233 * | | |0 = No Tamper 1 or Pair 0 interrupt flag is generated. 234 * | | |1 = Tamper 1 or Pair 0 interrupt flag is generated. 235 * | | |Note1: Write 1 to clear this bit. 236 * | | |Note2: This interrupt flag will be generated again when Tamper setting condition is not restoration. 237 * | | |Note3: Need to clear all TAMPxIF, after that, new RTC_TAMPTIME and RTC_TAMPCAL values are loaded while a tamper event occurred. 238 * |[10] |TAMP2IF |Tamper 2 Interrupt Flag 239 * | | |This bit is set when TAMP2_PIN detected level non-equal TAMP2LV (RTC_TAMPCTL[17]). 240 * | | |0 = No Tamper 2 interrupt flag is generated. 241 * | | |1 = Tamper 2 interrupt flag is generated. 242 * | | |Note1: Write 1 to clear this bit. 243 * | | |Note2: This interrupt flag will be generated again when Tamper setting condition is not restoration. 244 * | | |Note3: Need to clear all TAMPxIF, after that, new RTC_TAMPTIME and RTC_TAMPCAL values are loaded while a tamper event occurred. 245 * |[11] |TAMP3IF |Tamper 3 or Pair 1 Interrupt Flag 246 * | | |This bit is set when TAMP3_PIN detected level non-equal TAMP3LV (RTC_TAMPCTL[21]) or TAMP2_PIN and TAMP3_PIN disconnected during DYNPR1EN (RTC_TAMPCTL[23]) is activated or 247 * | | |TAMP0_PIN and TAMP3_PIN disconnected during DYNPR1EN (RTC_TAMPCTL[23]) and DYN1ISS (RTC_TAMPCTL[0]) are activated. 248 * | | |0 = No Tamper 3 or Pair 1 interrupt flag is generated. 249 * | | |1 = Tamper 3 or Pair 1 interrupt flag is generated. 250 * | | |Note1: Write 1 to clear this bit. 251 * | | |Note2: This interrupt flag will be generated again when Tamper setting condition is not restoration. 252 * | | |Note3: Need to clear all TAMPxIF, after that, new RTC_TAMPTIME and RTC_TAMPCAL values are loaded while a tamper event occurred. 253 * |[12] |TAMP4IF |Tamper 4 Interrupt Flag 254 * | | |This bit is set when TAMP4_PIN detected level non-equal TAMP4LV (RTC_TAMPCTL[25]). 255 * | | |0 = No Tamper 4 interrupt flag is generated. 256 * | | |1 = Tamper 4 interrupt flag is generated. 257 * | | |Note1: Write 1 to clear this bit. 258 * | | |Note2: This interrupt flag will be generated again when Tamper setting condition is not restoration. 259 * | | |Note3: Need to clear all TAMPxIF, after that, new RTC_TAMPTIME and RTC_TAMPCAL values are loaded while a tamper event occurred. 260 * |[13] |TAMP5IF |Tamper 5 or Pair 2 Interrupt Flag 261 * | | |This bit is set when TAMP5_PIN detected level non-equal TAMP5LV (RTC_TAMPCTL[29]) or TAMP4_PIN and TAMP5_PIN disconnected during DYNPR2EN (RTC_TAMPCTL[31]) is activated or 262 * | | |TAMP0_PIN and TAMP5_PIN disconnected during DYNPR2EN (RTC_TAMPCTL[31]) and DYN2ISS (RTC_TAMPCTL[1]) are activated. 263 * | | |0 = No Tamper 5 or Pair 2 interrupt flag is generated. 264 * | | |1 = Tamper 5 or Pair 2 interrupt flag is generated. 265 * | | |Note1: Write 1 to clear this bit. 266 * | | |Note2: This interrupt flag will be generated again when Tamper setting condition is not restoration. 267 * | | |Note3: Need to clear all TAMPxIF, after that, new RTC_TAMPTIME and RTC_TAMPCAL values are loaded while a tamper event occurred. 268 * |[24] |CLKFIF |LXT Clock Frequency Monitor Fail Interrupt Flag 269 * | | |0 = LXT frequency is normal. 270 * | | |1 = LXT frequency is abnormal. 271 * | | |Note1: Write 1 to clear the bit to 0. 272 * | | |Note2: LXT detector will automatic disable when Fail/Stop Flag rise, resume after Fail/Stop Flag clear. 273 * |[25] |CLKSTIF |LXT Clock Frequency Monitor Stop Interrupt Flag 274 * | | |0 = LXT frequency is normal. 275 * | | |1 = LXT frequency is almost stop. 276 * | | |Note1: Write 1 to clear the bit to 0. 277 * | | |Note2: LXT detector will automatic disable when Fail/Stop Flag rise, resume after Fail/Stop Flag clear. 278 * @var RTC_T::TICK 279 * Offset: 0x30 RTC Time Tick Register 280 * --------------------------------------------------------------------------------------------------- 281 * |Bits |Field |Descriptions 282 * | :----: | :----: | :---- | 283 * |[2:0] |TICK |Time Tick Register 284 * | | |These bits are used to select RTC time tick period for Periodic Time Tick Interrupt request. 285 * | | |000 = Time tick is 1 second. 286 * | | |001 = Time tick is 1/2 second. 287 * | | |010 = Time tick is 1/4 second. 288 * | | |011 = Time tick is 1/8 second. 289 * | | |100 = Time tick is 1/16 second. 290 * | | |101 = Time tick is 1/32 second. 291 * | | |110 = Time tick is 1/64 second. 292 * | | |111 = Time tick is 1/128 second. 293 * @var RTC_T::TAMSK 294 * Offset: 0x34 RTC Time Alarm Mask Register 295 * --------------------------------------------------------------------------------------------------- 296 * |Bits |Field |Descriptions 297 * | :----: | :----: | :---- | 298 * |[0] |MSEC |Mask 1-Sec Time Digit of Alarm Setting (0~9) 299 * |[1] |MTENSEC |Mask 10-Sec Time Digit of Alarm Setting (0~5) 300 * |[2] |MMIN |Mask 1-Min Time Digit of Alarm Setting (0~9) 301 * |[3] |MTENMIN |Mask 10-Min Time Digit of Alarm Setting (0~5) 302 * |[4] |MHR |Mask 1-Hour Time Digit of Alarm Setting (0~9) 303 * | | |Note: MHR function is only for 24-hour time scale mode. 304 * |[5] |MTENHR |Mask 10-Hour Time Digit of Alarm Setting (0~2) 305 * | | |Note: MTENHR function is only for 24-hour time scale mode. 306 * @var RTC_T::CAMSK 307 * Offset: 0x38 RTC Calendar Alarm Mask Register 308 * --------------------------------------------------------------------------------------------------- 309 * |Bits |Field |Descriptions 310 * | :----: | :----: | :---- | 311 * |[0] |MDAY |Mask 1-Day Calendar Digit of Alarm Setting (0~9) 312 * |[1] |MTENDAY |Mask 10-Day Calendar Digit of Alarm Setting (0~3) 313 * |[2] |MMON |Mask 1-Month Calendar Digit of Alarm Setting (0~9) 314 * |[3] |MTENMON |Mask 10-Month Calendar Digit of Alarm Setting (0~1) 315 * |[4] |MYEAR |Mask 1-Year Calendar Digit of Alarm Setting (0~9) 316 * |[5] |MTENYEAR |Mask 10-Year Calendar Digit of Alarm Setting (0~9) 317 * @var RTC_T::SPRCTL 318 * Offset: 0x3C RTC Spare Functional Control Register 319 * --------------------------------------------------------------------------------------------------- 320 * |Bits |Field |Descriptions 321 * | :----: | :----: | :---- | 322 * |[2] |SPRRWEN |Spare Register Enable Bit 323 * | | |0 = Spare register Disabled. 324 * | | |1 = Spare register Enabled. 325 * | | |Note: When spare register is disabled, RTC_SPR0 ~ RTC_SPR19 cannot be accessed. 326 * |[5] |SPRCSTS |SPR Clear Flag 327 * | | |This bit indicates if the RTC_SPR0 ~ RTC_SPR19 content is cleared when specify tamper event is detected. 328 * | | |0 = Spare register content is not cleared. 329 * | | |1 = Spare register content is cleared. 330 * | | |Note 1: Writes 1 to clear this bit. 331 * | | |Note 2: This bit keep 1 when RTC_INTSTS[13:8] or RTC_INTSTS[25:24] are not equal zero. 332 * |[16] |LXTFCLR |LXT Clock Fail/Stop to Clear Spare Enable Bit 333 * | | |0 = LXT Fail/Stop to clear Spare register content Disabled. 334 * | | |1 = LXT Fail/Stop to clear Spare register content Enabled. 335 * @var RTC_T::SPR[20] 336 * Offset: 0x40 ~ 0x8C RTC Spare Register 0 ~ 19 337 * --------------------------------------------------------------------------------------------------- 338 * |Bits |Field |Descriptions 339 * | :----: | :----: | :---- | 340 * |[31:0] |SPARE |Spare Register 341 * | | |This field is used to store back-up information defined by user. 342 * | | |This field will be cleared by hardware automatically in the following conditions, a tamper pin event is detected, 343 * | | |LXT clock fail/stop event occurs if LXTFCLR(RTC_SPRCTL[16]) is 1, or after Flash mass operation. 344 * @var RTC_T::LXTCTL 345 * Offset: 0x100 RTC 32.768 kHz Oscillator Control Register 346 * --------------------------------------------------------------------------------------------------- 347 * |Bits |Field |Descriptions 348 * | :----: | :----: | :---- | 349 * |[0] |LIRC32KEN |Enable LIRC32K Source 350 * | | |0 = LIRC32K Disabled. 351 * | | |1 = LIRC32K Enabled. 352 * |[3:1] |GAIN |Oscillator Gain Option 353 * | | |User can select oscillator gain according to crystal external loading and operating temperature range. 354 * | | |The larger gain value corresponding to stronger driving capability and higher power consumption. 355 * | | |000 = L0 mode. 356 * | | |001 = L1 mode. 357 * | | |010 = L2 mode. 358 * | | |011 = L3 mode. 359 * | | |100 = L4 mode. 360 * | | |101 = L5 mode. 361 * | | |110 = L6 mode. 362 * | | |111 = L7 mode (Default). 363 * |[6] |C32KSEL |Clock 32K Source Selection 364 * | | |0 = Clock source from external low speed crystal oscillator (LXT). 365 * | | |1 = Clock source from internal low speed RC 32K oscillator (LIRC32K). 366 * |[7] |RTCCKSEL |RTC Clock Source Selection 367 * | | |0 = Clock source from external low speed crystal oscillator (LXT) or internal low speed RC 32K oscillator (LIRC32K) depended on C32KSEL value. 368 * | | |1 = Clock source from internal low speed RC oscillator (LIRC). 369 * |[8] |IOCTLSEL |IO Pin Backup Control Selection 370 * | | |When low speed 32 kHz oscillator is disabled or TAMPxEN is disabled, 371 * | | |PF.4 pin (X32KO pin), PF.5 pin (X32KI pin) or PF.6~11 pin (TAMPERx pin) can be used as GPIO function. 372 * | | |User can program IOCTLSEL to decide PF.4~11 I/O function is controlled by system power domain GPIO module or VBAT power domain RTC_GPIOCTL0/1 control register. 373 * | | |0 = PF.4~11 pin I/O function is controlled by GPIO module. 374 * | | |1 = PF.4~11 pin I/O function is controlled by VBAT power domain. 375 * | | |Note: IOCTLSEL will automatically be set by hardware to 1 when system power is off and any writable RTC registers has been written at RTCCKEN(CLK_APBCLK0[1]) enabled. 376 * @var RTC_T::GPIOCTL0 377 * Offset: 0x104 RTC GPIO Control 0 Register 378 * --------------------------------------------------------------------------------------------------- 379 * |Bits |Field |Descriptions 380 * | :----: | :----: | :---- | 381 * |[1:0] |OPMODE0 |IO Operation Mode 382 * | | |00 = PF.4 is input only mode. 383 * | | |01 = PF.4 is output push pull mode. 384 * | | |10 = PF.4 is open drain mode. 385 * | | |11 = PF.4 is quasi-bidirectional mod. 386 * |[2] |DOUT0 |IO Output Data 387 * | | |0 = PF.4 output low. 388 * | | |1 = PF.4 output high. 389 * |[3] |DINOFF0 |IO Pin Digital Input Path Disable Bit 390 * | | |0 = PF.4 digital input path Enabled. 391 * | | |1 = PF.4 digital input path Disabled (digital input tied to low). 392 * |[5:4] |PUSEL0 |IO Pull-up and Pull-down Enable Bits 393 * | | |Determine PF.4 I/O pull-up or pull-down. 394 * | | |00 = PF.4 pull-up and pull-down Disabled. 395 * | | |01 = PF.4 pull-up Enabled. 396 * | | |10 = PF.4 pull-down Enabled. 397 * | | |11 = PF.4 pull-up and pull-down Disabled. 398 * | | |Note: Basically, the pull-up control and pull-down control has following behavior limitation. 399 * | | |The independent pull-up/pull-down control register is only valid when OPMODE0 is set as input tri-state and open-drain mode. 400 * |[9:8] |OPMODE1 |IO Operation Mode 401 * | | |00 = PF.5 is input only mode. 402 * | | |01 = PF.5 is output push pull mode. 403 * | | |10 = PF.5 is open drain mode. 404 * | | |11 = PF.5 is quasi-bidirectional mod. 405 * |[10] |DOUT1 |IO Output Data 406 * | | |0 = PF.5 output low. 407 * | | |1 = PF.5 output high. 408 * |[11 |DINOFF1 |IO Pin Digital Input Path Disable Bit 409 * | | |0 = PF.5 digital input path Enabled. 410 * | | |1 = PF.5 digital input path Disabled (digital input tied to low). 411 * |[13:12] |PUSEL1 |IO Pull-up and Pull-down Enable Bits 412 * | | |Determine PF.5 I/O pull-up or pull-down. 413 * | | |00 = PF.5 pull-up and pull-down Disabled. 414 * | | |01 = PF.5 pull-up Enabled. 415 * | | |10 = PF.5 pull-down Enabled. 416 * | | |11 = PF.5 pull-up and pull-down Disabled. 417 * | | |Note: Basically, the pull-up control and pull-down control has following behavior limitation. 418 * | | |The independent pull-up/pull-down control register is only valid when OPMODE1 is set as input tri-state and open-drain mode. 419 * |[17:16] |OPMODE2 |IO Operation Mode 420 * | | |00 = PF.6 is input only mode. 421 * | | |01 = PF.6 is output push pull mode. 422 * | | |10 = PF.6 is open drain mode. 423 * | | |11 = PF.6 is quasi-bidirectional mod. 424 * |[18] |DOUT2 |IO Output Data 425 * | | |0 = PF.6 output low. 426 * | | |1 = PF.6 output high. 427 * |[19 |DINOFF2 |IO Pin Digital Input Path Disable Bit 428 * | | |0 = PF.6 digital input path Enabled. 429 * | | |1 = PF.6 digital input path Disabled (digital input tied to low). 430 * |[21:20] |PUSEL2 |IO Pull-up and Pull-down Enable Bits 431 * | | |Determine PF.6 I/O pull-up or pull-down. 432 * | | |00 = PF.6 pull-up and pull-down Disabled. 433 * | | |01 = PF.6 pull-up Enabled. 434 * | | |10 = PF.6 pull-down Enabled. 435 * | | |11 = PF.6 pull-up and pull-down Disabled. 436 * | | |Note: Basically, the pull-up control and pull-down control has following behavior limitation. 437 * | | |The independent pull-up/pull-down control register is only valid when OPMODE2 is set as input tri-state and open-drain mode. 438 * |[25:24] |OPMODE3 |IO Operation Mode 439 * | | |00 = PF.7 is input only mode. 440 * | | |01 = PF.7 is output push pull mode. 441 * | | |10 = PF.7 is open drain mode. 442 * | | |11 = PF.7 is quasi-bidirectional mod. 443 * |[26] |DOUT3 |IO Output Data 444 * | | |0 = PF.7 output low. 445 * | | |1 = PF.7 output high. 446 * |[27 |DINOFF3 |IO Pin Digital Input Path Disable Bit 447 * | | |0 = PF.7 digital input path Enabled. 448 * | | |1 = PF.7 digital input path Disabled (digital input tied to low). 449 * |[29:28] |PUSEL3 |IO Pull-up and Pull-down Enable Bits 450 * | | |Determine PF.7 I/O pull-up or pull-down. 451 * | | |00 = PF.7 pull-up and pull-down Disabled. 452 * | | |01 = PF.7 pull-up Enabled. 453 * | | |10 = PF.7 pull-down Enabled. 454 * | | |11 = PF.7 pull-up and pull-down Disabled. 455 * | | |Note: Basically, the pull-up control and pull-down control has following behavior limitation. 456 * | | |The independent pull-up/pull-down control register is only valid when OPMODE3 is set as input tri-state and open-drain mode. 457 * @var RTC_T::GPIOCTL1 458 * Offset: 0x108 RTC GPIO Control 1 Register 459 * --------------------------------------------------------------------------------------------------- 460 * |Bits |Field |Descriptions 461 * | :----: | :----: | :---- | 462 * |[1:0] |OPMODE4 |IO Operation Mode 463 * | | |00 = PF.8 is input only mode. 464 * | | |01 = PF.8 is output push pull mode. 465 * | | |10 = PF.8 is open drain mode. 466 * | | |11 = PF.8 is quasi-bidirectional mod. 467 * |[2] |DOUT4 |IO Output Data 468 * | | |0 = PF.8 output low. 469 * | | |1 = PF.8 output high. 470 * |[3] |DINOFF4 |IO Pin Digital Input Path Disable Bit 471 * | | |0 = PF.8 digital input path Enabled. 472 * | | |1 = PF.8 digital input path Disabled (digital input tied to low). 473 * |[5:4] |PUSEL4 |IO Pull-up and Pull-down Enable Bits 474 * | | |Determine PF.8 I/O pull-up or pull-down. 475 * | | |00 = PF.8 pull-up and pull-down Disabled. 476 * | | |01 = PF.8 pull-up Enabled. 477 * | | |10 = PF.8 pull-down Enabled. 478 * | | |11 = PF.8 pull-up and pull-down Disabled. 479 * | | |Note: Basically, the pull-up control and pull-down control has following behavior limitation. 480 * | | |The independent pull-up/pull-down control register is only valid when OPMODE4 is set as input tri-state and open-drain mode. 481 * |[9:8] |OPMODE5 |IO Operation Mode 482 * | | |00 = PF.9 is input only mode. 483 * | | |01 = PF.9 is output push pull mode. 484 * | | |10 = PF.9 is open drain mode. 485 * | | |11 = PF.9 is quasi-bidirectional mod. 486 * |[10] |DOUT5 |IO Output Data 487 * | | |0 = PF.9 output low. 488 * | | |1 = PF.9 output high. 489 * |[11 |DINOFF5 |IO Pin Digital Input Path Disable Bit 490 * | | |0 = PF.9 digital input path Enabled. 491 * | | |1 = PF.9 digital input path Disabled (digital input tied to low). 492 * |[13:12] |PUSEL5 |IO Pull-up and Pull-down Enable Bits 493 * | | |Determine PF.9 I/O pull-up or pull-down. 494 * | | |00 = PF.9 pull-up and pull-down Disabled. 495 * | | |01 = PF.9 pull-up Enabled. 496 * | | |10 = PF.9 pull-down Enabled. 497 * | | |11 = PF.9 pull-up and pull-down Disabled. 498 * | | |Note: Basically, the pull-up control and pull-down control has following behavior limitation. 499 * | | |The independent pull-up/pull-down control register is only valid when OPMODE5 is set as input tri-state and open-drain mode. 500 * |[17:16] |OPMODE6 |IO Operation Mode 501 * | | |00 = PF.10 is input only mode. 502 * | | |01 = PF.10 is output push pull mode. 503 * | | |10 = PF.10 is open drain mode. 504 * | | |11 = PF.10 is quasi-bidirectional mod. 505 * |[18] |DOUT6 |IO Output Data 506 * | | |0 = PF.10 output low. 507 * | | |1 = PF.10 output high. 508 * |[19 |DINOFF6 |IO Pin Digital Input Path Disable Bit 509 * | | |0 = PF.10 digital input path Enabled. 510 * | | |1 = PF.10 digital input path Disabled (digital input tied to low). 511 * |[21:20] |PUSEL6 |IO Pull-up and Pull-down Enable Bits 512 * | | |Determine PF.10 I/O pull-up or pull-down. 513 * | | |00 = PF.10 pull-up and pull-down Disabled. 514 * | | |01 = PF.10 pull-up Enabled. 515 * | | |10 = PF.10 pull-down Enabled. 516 * | | |11 = PF.10 pull-up and pull-down Disabled. 517 * | | |Note: Basically, the pull-up control and pull-down control has following behavior limitation. 518 * | | |The independent pull-up/pull-down control register is only valid when OPMODE6 is set as input tri-state and open-drain mode. 519 * |[25:24] |OPMODE7 |IO Operation Mode 520 * | | |00 = PF.11 is input only mode. 521 * | | |01 = PF.11 is output push pull mode. 522 * | | |10 = PF.11 is open drain mode. 523 * | | |11 = PF.11 is quasi-bidirectional mod. 524 * |[26] |DOUT7 |IO Output Data 525 * | | |0 = PF.11 output low. 526 * | | |1 = PF.11 output high. 527 * |[27 |DINOFF7 |IO Pin Digital Input Path Disable Bit 528 * | | |0 = PF.11 digital input path Enabled. 529 * | | |1 = PF.11 digital input path Disabled (digital input tied to low). 530 * |[29:28] |PUSEL7 |IO Pull-up and Pull-down Enable Bits 531 * | | |Determine PF.11 I/O pull-up or pull-down. 532 * | | |00 = PF.11 pull-up and pull-down Disabled. 533 * | | |01 = PF.11 pull-up Enabled. 534 * | | |10 = PF.11 pull-down Enabled. 535 * | | |11 = PF.11 pull-up and pull-down Disabled. 536 * | | |Note: Basically, the pull-up control and pull-down control has following behavior limitation. 537 * | | |The independent pull-up/pull-down control register is only valid when OPMODE7 is set as input tri-state and open-drain mode. 538 * @var RTC_T::DSTCTL 539 * Offset: 0x110 RTC Daylight Saving Time Control Register 540 * --------------------------------------------------------------------------------------------------- 541 * |Bits |Field |Descriptions 542 * | :----: | :----: | :---- | 543 * |[0] |ADDHR |Add 1 Hour 544 * | | |0 = No effect. 545 * | | |1 = Indicates RTC hour digit has been added one hour for summer time change. 546 * |[1] |SUBHR |Subtract 1 Hour 547 * | | |0 = No effect. 548 * | | |1 = Indicates RTC hour digit has been subtracted one hour for winter time change. 549 * |[2] |DSBAK |Daylight Saving Back 550 * | | |0 = Daylight Saving Change is not performed. 551 * | | |1 = Daylight Saving Change is performed. 552 * @var RTC_T::TAMPCTL 553 * Offset: 0x120 RTC Tamper Pin Control Register 554 * --------------------------------------------------------------------------------------------------- 555 * |Bits |Field |Descriptions 556 * | :----: | :----: | :---- | 557 * |[0] |DYN1ISS |Dynamic Pair 1 Input Source Select 558 * | | |This bit determine Tamper 3 input is from Tamper 2 or Tamper 0 in dynamic mode. 559 * | | |0 = Tamper input is from Tamper 2. 560 * | | |1 = Tamper input is from Tamper 0. 561 * | | |Note: This bit is effective only when DYNPR1EN (RTC_TAMPCTL[23]) and DYNPR0EN (RTC_TAMPCTL[15]) are set. 562 * |[1] |DYN2ISS |Dynamic Pair 2 Input Source Select 563 * | | |This bit determine Tamper 5 input is from Tamper 4 or Tamper 0 in dynamic mode. 564 * | | |0 = Tamper input is from Tamper 4. 565 * | | |1 = Tamper input is from Tamper 0. 566 * | | |Note: This bit is effective only when DYNPR2EN (RTC_TAMPCTL[31]) and DYNPR0EN (RTC_TAMPCTL[15]) are set. 567 * |[3] |DYNSRC |Dynamic Reference Pattern 568 * | | |This fields determine the new reference pattern when current pattern run out in dynamic pair mode. 569 * | | |0 = The new reference pattern is generated by random number generator when the reference pattern run out. 570 * | | |1 = The new reference pattern is repeated from SEED (RTC_TAMPSEED[31:0]) when the reference pattern run out. 571 * | | |Note: After this bit is modified, the SEEDRLD (RTC_TAMPCTL[4]) should be set. 572 * |[4] |SEEDRLD |Reload New Seed for PRNG Engine 573 * | | |Setting this bit, the tamper configuration will be reload. 574 * | | |0 = Generating key based on the current seed. 575 * | | |1 = Reload new seed. 576 * | | |Note 1: Before this bit is set, the tamper configuration should be set to complete and this bit will be auto clear to 0 after reload new seed completed. 577 * | | |Note 2: The reference is RTC clock. Tamper detector need sync 2 ~ 3 RTC clock. 578 * |[7:5] |DYNRATE |Dynamic Change Rate 579 * | | |This item is choice the dynamic tamper output change rate. 580 * | | |000 = 2^10 * RTC_CLK. 581 * | | |001 = 2^11 * RTC_CLK. 582 * | | |010 = 2^12 * RTC_CLK. 583 * | | |011 = 2^13 * RTC_CLK. 584 * | | |100 = 2^14 * RTC_CLK. 585 * | | |101 = 2^15 * RTC_CLK. 586 * | | |110 = 2^16 * RTC_CLK. 587 * | | |111 = 2^17 * RTC_CLK. 588 * | | |Note: After revising this field, set SEEDRLD (RTC_TAMPCTL[4]) can reload change rate immediately. 589 * |[8] |TAMP0EN |Tamper0 Detect Enable Bit 590 * | | |0 = Tamper 0 detect Disabled. 591 * | | |1 = Tamper 0 detect Enabled. 592 * | | |Note1: The reference is RTC clock. Tamper detector need sync 2 ~ 3 RTC clock. 593 * |[9] |TAMP0LV |Tamper 0 Level 594 * | | |This bit depend on level attribute of tamper pin for static tamper detection. 595 * | | |0 = Detect voltage level is low. 596 * | | |1 = Detect voltage level is high. 597 * |[10] |TAMP0DBEN |Tamper 0 De-bounce Enable Bit 598 * | | |0 = Tamper 0 de-bounce Disabled. 599 * | | |1 = Tamper 0 de-bounce Enabled. 600 * |[12] |TAMP1EN |Tamper 1 Detect Enable Bit 601 * | | |0 = Tamper 1 detect Disabled. 602 * | | |1 = Tamper 1 detect Enabled. 603 * | | |Note1: The reference is RTC clock. Tamper detector need sync 2 ~ 3 RTC clock. 604 * |[13] |TAMP1LV |Tamper 1 Level 605 * | | |This bit depend on level attribute of tamper pin for static tamper detection. 606 * | | |0 = Detect voltage level is low. 607 * | | |1 = Detect voltage level is high. 608 * |[14] |TAMP1DBEN |Tamper 1 De-bounce Enable Bit 609 * | | |0 = Tamper 1 de-bounce Disabled. 610 * | | |1 = Tamper 1 de-bounce Enabled. 611 * |[15] |DYNPR0EN |Dynamic Pair 0 Enable Bit 612 * | | |0 = Static detect. 613 * | | |1 = Dynamic detect. 614 * |[16] |TAMP2EN |Tamper 2 Detect Enable Bit 615 * | | |0 = Tamper 2 detect Disabled. 616 * | | |1 = Tamper 2 detect Enabled. 617 * | | |Note1: The reference is RTC clock. Tamper detector need sync 2 ~ 3 RTC clock. 618 * |[17] |TAMP2LV |Tamper 2 Level 619 * | | |This bit depend on level attribute of tamper pin for static tamper detection. 620 * | | |0 = Detect voltage level is low. 621 * | | |1 = Detect voltage level is high. 622 * |[18] |TAMP2DBEN |Tamper 2 De-bounce Enable Bit 623 * | | |0 = Tamper 2 de-bounce Disabled. 624 * | | |1 = Tamper 2 de-bounce Enabled. 625 * |[20] |TAMP3EN |Tamper 3 Detect Enable Bit 626 * | | |0 = Tamper 3 detect Disabled. 627 * | | |1 = Tamper 3 detect Enabled. 628 * | | |Note1: The reference is RTC clock. Tamper detector need sync 2 ~ 3 RTC clock. 629 * |[21] |TAMP3LV |Tamper 3 Level 630 * | | |This bit depend on level attribute of tamper pin for static tamper detection. 631 * | | |0 = Detect voltage level is low. 632 * | | |1 = Detect voltage level is high. 633 * |[22] |TAMP3DBEN |Tamper 3 De-bounce Enable Bit 634 * | | |0 = Tamper 3 de-bounce Disabled. 635 * | | |1 = Tamper 3 de-bounce Enabled. 636 * |[23] |DYNPR1EN |Dynamic Pair 1 Enable Bit 637 * | | |0 = Static detect. 638 * | | |1 = Dynamic detect. 639 * |[24] |TAMP4EN |Tamper4 Detect Enable Bit 640 * | | |0 = Tamper 4 detect Disabled. 641 * | | |1 = Tamper 4 detect Enabled. 642 * | | |Note1: The reference is RTC clock. Tamper detector need sync 2 ~ 3 RTC clock. 643 * |[25] |TAMP4LV |Tamper 4 Level 644 * | | |This bit depend on level attribute of tamper pin for static tamper detection. 645 * | | |0 = Detect voltage level is low. 646 * | | |1 = Detect voltage level is high. 647 * |[26] |TAMP4DBEN |Tamper 4 De-bounce Enable Bit 648 * | | |0 = Tamper 4 de-bounce Disabled. 649 * | | |1 = Tamper 4 de-bounce Enabled. 650 * |[28] |TAMP5EN |Tamper 5 Detect Enable Bit 651 * | | |0 = Tamper 5 detect Disabled. 652 * | | |1 = Tamper 5 detect Enabled. 653 * | | |Note1: The reference is RTC clock. Tamper detector need sync 2 ~ 3 RTC clock. 654 * |[29] |TAMP5LV |Tamper 5 Level 655 * | | |This bit depend on level attribute of tamper pin for static tamper detection. 656 * | | |0 = Detect voltage level is low. 657 * | | |1 = Detect voltage level is high. 658 * |[30] |TAMP5DBEN |Tamper 5 De-bounce Enable Bit 659 * | | |0 = Tamper 5 de-bounce Disabled. 660 * | | |1 = Tamper 5 de-bounce Enabled. 661 * |[31] |DYNPR2EN |Dynamic Pair 2 Enable Bit 662 * | | |0 = Static detect. 663 * | | |1 = Dynamic detect. 664 * @var RTC_T::TAMPSEED 665 * Offset: 0x128 RTC Tamper Dynamic Seed Register 666 * --------------------------------------------------------------------------------------------------- 667 * |Bits |Field |Descriptions 668 * | :----: | :----: | :---- | 669 * |[31:0] |SEED |Seed Value 670 * @var RTC_T::TAMPTIME 671 * Offset: 0x130 RTC Tamper Time Register 672 * --------------------------------------------------------------------------------------------------- 673 * |Bits |Field |Descriptions 674 * | :----: | :----: | :---- | 675 * |[3:0] |SEC |1-Sec Time Digit of TAMPER Time (0~9) 676 * |[6:4] |TENSEC |10-Sec Time Digit of TAMPER Time (0~5) 677 * |[11:8] |MIN |1-Min Time Digit of TAMPER Time (0~9) 678 * |[14:12] |TENMIN |10-Min Time Digit of TAMPER Time (0~5) 679 * |[19:16] |HR |1-Hour Time Digit of TAMPER Time (0~9) 680 * |[21:20] |TENHR |10-Hour Time Digit of TAMPER Time (0~2) 681 * | | |Note: 24-hour time scale only. 682 * @var RTC_T::TAMPCAL 683 * Offset: 0x134 RTC Tamper Calendar Register 684 * --------------------------------------------------------------------------------------------------- 685 * |Bits |Field |Descriptions 686 * | :----: | :----: | :---- | 687 * |[3:0] |DAY |1-Day Calendar Digit of TAMPER Calendar (0~9) 688 * |[5:4] |TENDAY |10-Day Calendar Digit of TAMPER Calendar (0~3) 689 * |[11:8] |MON |1-Month Calendar Digit of TAMPER Calendar (0~9) 690 * |[12] |TENMON |10-Month Calendar Digit of TAMPER Calendar (0~1) 691 * |[19:16] |YEAR |1-Year Calendar Digit of TAMPER Calendar (0~9) 692 * |[23:20] |TENYEAR |10-Year Calendar Digit of TAMPER Calendar (0~9) 693 * @var RTC_T::CLKDCTL 694 * Offset: 0x140 RTC Clock Fail Detector Control Register 695 * --------------------------------------------------------------------------------------------------- 696 * |Bits |Field |Descriptions 697 * | :----: | :----: | :---- | 698 * |[0] |LXTFDEN |LXT Clock Fail/Stop Detector Enable Bit 699 * | | |0 = LXT clock Fail/Stop detector Disabled. 700 * | | |1 = LXT clock Fail/Stop detector Enabled. 701 * | | |Note: LXT detector will automatic disable when Fail/Stop Flag rise, resume after Fail/Stop Flag clear. 702 * |[1] |LXTFSW |LXT Clock Fail Detector Switch LIRC32K Enable Bit 703 * | | |0 = LXT clock Fail switch LIRC32K Disabled. 704 * | | |1 = LXT clock Fail detector rise, RTC clock source switch from LIRC32K. 705 * | | |If LXT clock fail detector flag CLKFIF (RTC_INTSTS[24]) is generated, RTC clock source will switch to LIRC32K automatically. 706 * |[2] |LXTSTSW |LXT Clock Stop Detector Switch LIRC32K Enable Bit 707 * | | |0 = LXT clock Stop switch LIRC32K Disabled. 708 * | | |1 = LXT clock Stop detector rise, RTC clock source switch from LIRC32K. 709 * | | |If LXT clock stop detector flag CLKSTIF (RTC_INTSTS[25]) is generated, RTC clock source will switch to LIRC32K automatically 710 * |[16] |SWLIRCF |LXT Clock Detector Fail/Stop Switch LIRC32K Flag (Read Only) 711 * | | |0 = Indicate RTC clock source from LXT. 712 * | | |1 = Indicate RTC clock source from LIRC32K. 713 * |[17] |LXTSLOWF |LXT Slower Than LIRC32K Flag (Read Only) 714 * | | |0 = LXT frequency faster than LIRC32K. 715 * | | |1 = LXT frequency is slowly. 716 * | | |Note: LXTSLOWF is vaild during CLKSTIF (RTC_INTSTS[25]) or CLKFIF (RTC_INTSTS[24]) rising. 717 * @var RTC_T::CDBR 718 * Offset: 0x144 RTC Clock Frequency Detector Boundary Register 719 * --------------------------------------------------------------------------------------------------- 720 * |Bits |Field |Descriptions 721 * | :----: | :----: | :---- | 722 * |[7:0] |STOPBD |LXT Clock Stop Frequency Detector Stop Boundary 723 * | | |These bits define the stop value of frequency monitor window. 724 * | | |When LXT frequency monitor counter lower than STOPBD, the LXT frequency detect Stop interrupt flag will set to 1. 725 * | | |Note: The boundary is defined as the maximum value of LXT among 256 LIRC32K clock time. 726 * |[23:16] |FAILBD |LXT Clock Frequency Detector Fail Boundary 727 * | | |These bits define the fail value of frequency monitor window. 728 * | | |When LXT frequency monitor counter lower than FAILBD, the LXT frequency detect fail interrupt flag will set to 1. 729 * | | |Note: The boundary is defined as the maximum value of LXT among 256 LIRC32K clock time. 730 */ 731 __IO uint32_t INIT; /*!< [0x0000] RTC Initiation Register */ 732 __I uint32_t RESERVE0[1]; /* 0x4 */ 733 __IO uint32_t FREQADJ; /*!< [0x0008] RTC Frequency Compensation Register */ 734 __IO uint32_t TIME; /*!< [0x000c] RTC Time Loading Register */ 735 __IO uint32_t CAL; /*!< [0x0010] RTC Calendar Loading Register */ 736 __IO uint32_t CLKFMT; /*!< [0x0014] RTC Time Scale Selection Register */ 737 __IO uint32_t WEEKDAY; /*!< [0x0018] RTC Day of the Week Register */ 738 __IO uint32_t TALM; /*!< [0x001c] RTC Time Alarm Register */ 739 __IO uint32_t CALM; /*!< [0x0020] RTC Calendar Alarm Register */ 740 __I uint32_t LEAPYEAR; /*!< [0x0024] RTC Leap Year Indicator Register */ 741 __IO uint32_t INTEN; /*!< [0x0028] RTC Interrupt Enable Register */ 742 __IO uint32_t INTSTS; /*!< [0x002c] RTC Interrupt Status Register */ 743 __IO uint32_t TICK; /*!< [0x0030] RTC Time Tick Register */ 744 __IO uint32_t TAMSK; /*!< [0x0034] RTC Time Alarm Mask Register */ 745 __IO uint32_t CAMSK; /*!< [0x0038] RTC Calendar Alarm Mask Register */ 746 __IO uint32_t SPRCTL; /*!< [0x003c] RTC Spare Functional Control Register */ 747 __IO uint32_t SPR[20]; /*!< [0x0040] ~ [0x008C] RTC Spare Register 0 ~ 19 */ 748 __I uint32_t RESERVE1[28]; /* 0x90 ~ 0xfc */ 749 __IO uint32_t LXTCTL; /*!< [0x0100] RTC 32.768 kHz Oscillator Control Register */ 750 __IO uint32_t GPIOCTL0; /*!< [0x0104] RTC GPIO Control 0 Register */ 751 __IO uint32_t GPIOCTL1; /*!< [0x0108] RTC GPIO Control 1 Register */ 752 __I uint32_t RESERVE2[1]; /* 0x10c */ 753 __IO uint32_t DSTCTL; /*!< [0x0110] RTC Daylight Saving Time Control Register */ 754 __I uint32_t RESERVE3[3]; /* 0x114 ~ 0x11c */ 755 __IO uint32_t TAMPCTL; /*!< [0x0120] RTC Tamper Pin Control Register */ 756 __I uint32_t RESERVE4[1]; /* 0x124 */ 757 __IO uint32_t TAMPSEED; /*!< [0x0128] RTC Tamper Dynamic Seed Register */ 758 __I uint32_t RESERVE5[1]; /* 0x12c */ 759 __I uint32_t TAMPTIME; /*!< [0x0130] RTC Tamper Time Register */ 760 __I uint32_t TAMPCAL; /*!< [0x0134] RTC Tamper Calendar Register */ 761 __I uint32_t RESERVE6[2]; /* 0x138 ~ 0x13c */ 762 __IO uint32_t CLKDCTL; /*!< [0x0140] RTC Clock Fail Detector Control Register */ 763 __IO uint32_t CDBR; /*!< [0x0144] RTC Clock Frequency Detector Boundary Register */ 764 765 } RTC_T; 766 767 /** 768 @addtogroup RTC_CONST RTC Bit Field Definition 769 Constant Definitions for RTC Controller 770 @{ 771 */ 772 773 #define RTC_INIT_ACTIVE_Pos (0) /*!< RTC_T::INIT: ACTIVE Position */ 774 #define RTC_INIT_ACTIVE_Msk (0x1ul << RTC_INIT_ACTIVE_Pos) /*!< RTC_T::INIT: ACTIVE Mask */ 775 776 #define RTC_INIT_INIT_Pos (1) /*!< RTC_T::INIT: INIT Position */ 777 #define RTC_INIT_INIT_Msk (0x7ffffffful << RTC_INIT_INIT_Pos) /*!< RTC_T::INIT: INIT Mask */ 778 779 #define RTC_FREQADJ_FRACTION_Pos (0) /*!< RTC_T::FREQADJ: FRACTION Position */ 780 #define RTC_FREQADJ_FRACTION_Msk (0x3ful << RTC_FREQADJ_FRACTION_Pos) /*!< RTC_T::FREQADJ: FRACTION Mask */ 781 782 #define RTC_FREQADJ_INTEGER_Pos (8) /*!< RTC_T::FREQADJ: INTEGER Position */ 783 #define RTC_FREQADJ_INTEGER_Msk (0x1ful << RTC_FREQADJ_INTEGER_Pos) /*!< RTC_T::FREQADJ: INTEGER Mask */ 784 785 #define RTC_FREQADJ_FCRBUSY_Pos (31) /*!< RTC_T::FREQADJ: FCRBUSY Position */ 786 #define RTC_FREQADJ_FCRBUSY_Msk (0x1ul << RTC_FREQADJ_FCRBUSY_Pos) /*!< RTC_T::FREQADJ: FCRBUSY Mask */ 787 788 #define RTC_TIME_SEC_Pos (0) /*!< RTC_T::TIME: SEC Position */ 789 #define RTC_TIME_SEC_Msk (0xful << RTC_TIME_SEC_Pos) /*!< RTC_T::TIME: SEC Mask */ 790 791 #define RTC_TIME_TENSEC_Pos (4) /*!< RTC_T::TIME: TENSEC Position */ 792 #define RTC_TIME_TENSEC_Msk (0x7ul << RTC_TIME_TENSEC_Pos) /*!< RTC_T::TIME: TENSEC Mask */ 793 794 #define RTC_TIME_MIN_Pos (8) /*!< RTC_T::TIME: MIN Position */ 795 #define RTC_TIME_MIN_Msk (0xful << RTC_TIME_MIN_Pos) /*!< RTC_T::TIME: MIN Mask */ 796 797 #define RTC_TIME_TENMIN_Pos (12) /*!< RTC_T::TIME: TENMIN Position */ 798 #define RTC_TIME_TENMIN_Msk (0x7ul << RTC_TIME_TENMIN_Pos) /*!< RTC_T::TIME: TENMIN Mask */ 799 800 #define RTC_TIME_HR_Pos (16) /*!< RTC_T::TIME: HR Position */ 801 #define RTC_TIME_HR_Msk (0xful << RTC_TIME_HR_Pos) /*!< RTC_T::TIME: HR Mask */ 802 803 #define RTC_TIME_TENHR_Pos (20) /*!< RTC_T::TIME: TENHR Position */ 804 #define RTC_TIME_TENHR_Msk (0x3ul << RTC_TIME_TENHR_Pos) /*!< RTC_T::TIME: TENHR Mask */ 805 806 #define RTC_CAL_DAY_Pos (0) /*!< RTC_T::CAL: DAY Position */ 807 #define RTC_CAL_DAY_Msk (0xful << RTC_CAL_DAY_Pos) /*!< RTC_T::CAL: DAY Mask */ 808 809 #define RTC_CAL_TENDAY_Pos (4) /*!< RTC_T::CAL: TENDAY Position */ 810 #define RTC_CAL_TENDAY_Msk (0x3ul << RTC_CAL_TENDAY_Pos) /*!< RTC_T::CAL: TENDAY Mask */ 811 812 #define RTC_CAL_MON_Pos (8) /*!< RTC_T::CAL: MON Position */ 813 #define RTC_CAL_MON_Msk (0xful << RTC_CAL_MON_Pos) /*!< RTC_T::CAL: MON Mask */ 814 815 #define RTC_CAL_TENMON_Pos (12) /*!< RTC_T::CAL: TENMON Position */ 816 #define RTC_CAL_TENMON_Msk (0x1ul << RTC_CAL_TENMON_Pos) /*!< RTC_T::CAL: TENMON Mask */ 817 818 #define RTC_CAL_YEAR_Pos (16) /*!< RTC_T::CAL: YEAR Position */ 819 #define RTC_CAL_YEAR_Msk (0xful << RTC_CAL_YEAR_Pos) /*!< RTC_T::CAL: YEAR Mask */ 820 821 #define RTC_CAL_TENYEAR_Pos (20) /*!< RTC_T::CAL: TENYEAR Position */ 822 #define RTC_CAL_TENYEAR_Msk (0xful << RTC_CAL_TENYEAR_Pos) /*!< RTC_T::CAL: TENYEAR Mask */ 823 824 #define RTC_CLKFMT_24HEN_Pos (0) /*!< RTC_T::CLKFMT: 24HEN Position */ 825 #define RTC_CLKFMT_24HEN_Msk (0x1ul << RTC_CLKFMT_24HEN_Pos) /*!< RTC_T::CLKFMT: 24HEN Mask */ 826 827 #define RTC_CLKFMT_DCOMPEN_Pos (16) /*!< RTC_T::CLKFMT: DCOMPEN Position */ 828 #define RTC_CLKFMT_DCOMPEN_Msk (0x1ul << RTC_CLKFMT_DCOMPEN_Pos) /*!< RTC_T::CLKFMT: DCOMPEN Mask */ 829 830 #define RTC_WEEKDAY_WEEKDAY_Pos (0) /*!< RTC_T::WEEKDAY: WEEKDAY Position */ 831 #define RTC_WEEKDAY_WEEKDAY_Msk (0x7ul << RTC_WEEKDAY_WEEKDAY_Pos) /*!< RTC_T::WEEKDAY: WEEKDAY Mask */ 832 833 #define RTC_TALM_SEC_Pos (0) /*!< RTC_T::TALM: SEC Position */ 834 #define RTC_TALM_SEC_Msk (0xful << RTC_TALM_SEC_Pos) /*!< RTC_T::TALM: SEC Mask */ 835 836 #define RTC_TALM_TENSEC_Pos (4) /*!< RTC_T::TALM: TENSEC Position */ 837 #define RTC_TALM_TENSEC_Msk (0x7ul << RTC_TALM_TENSEC_Pos) /*!< RTC_T::TALM: TENSEC Mask */ 838 839 #define RTC_TALM_MIN_Pos (8) /*!< RTC_T::TALM: MIN Position */ 840 #define RTC_TALM_MIN_Msk (0xful << RTC_TALM_MIN_Pos) /*!< RTC_T::TALM: MIN Mask */ 841 842 #define RTC_TALM_TENMIN_Pos (12) /*!< RTC_T::TALM: TENMIN Position */ 843 #define RTC_TALM_TENMIN_Msk (0x7ul << RTC_TALM_TENMIN_Pos) /*!< RTC_T::TALM: TENMIN Mask */ 844 845 #define RTC_TALM_HR_Pos (16) /*!< RTC_T::TALM: HR Position */ 846 #define RTC_TALM_HR_Msk (0xful << RTC_TALM_HR_Pos) /*!< RTC_T::TALM: HR Mask */ 847 848 #define RTC_TALM_TENHR_Pos (20) /*!< RTC_T::TALM: TENHR Position */ 849 #define RTC_TALM_TENHR_Msk (0x3ul << RTC_TALM_TENHR_Pos) /*!< RTC_T::TALM: TENHR Mask */ 850 851 #define RTC_CALM_DAY_Pos (0) /*!< RTC_T::CALM: DAY Position */ 852 #define RTC_CALM_DAY_Msk (0xful << RTC_CALM_DAY_Pos) /*!< RTC_T::CALM: DAY Mask */ 853 854 #define RTC_CALM_TENDAY_Pos (4) /*!< RTC_T::CALM: TENDAY Position */ 855 #define RTC_CALM_TENDAY_Msk (0x3ul << RTC_CALM_TENDAY_Pos) /*!< RTC_T::CALM: TENDAY Mask */ 856 857 #define RTC_CALM_MON_Pos (8) /*!< RTC_T::CALM: MON Position */ 858 #define RTC_CALM_MON_Msk (0xful << RTC_CALM_MON_Pos) /*!< RTC_T::CALM: MON Mask */ 859 860 #define RTC_CALM_TENMON_Pos (12) /*!< RTC_T::CALM: TENMON Position */ 861 #define RTC_CALM_TENMON_Msk (0x1ul << RTC_CALM_TENMON_Pos) /*!< RTC_T::CALM: TENMON Mask */ 862 863 #define RTC_CALM_YEAR_Pos (16) /*!< RTC_T::CALM: YEAR Position */ 864 #define RTC_CALM_YEAR_Msk (0xful << RTC_CALM_YEAR_Pos) /*!< RTC_T::CALM: YEAR Mask */ 865 866 #define RTC_CALM_TENYEAR_Pos (20) /*!< RTC_T::CALM: TENYEAR Position */ 867 #define RTC_CALM_TENYEAR_Msk (0xful << RTC_CALM_TENYEAR_Pos) /*!< RTC_T::CALM: TENYEAR Mask */ 868 869 #define RTC_LEAPYEAR_LEAPYEAR_Pos (0) /*!< RTC_T::LEAPYEAR: LEAPYEAR Position */ 870 #define RTC_LEAPYEAR_LEAPYEAR_Msk (0x1ul << RTC_LEAPYEAR_LEAPYEAR_Pos) /*!< RTC_T::LEAPYEAR: LEAPYEAR Mask */ 871 872 #define RTC_INTEN_ALMIEN_Pos (0) /*!< RTC_T::INTEN: ALMIEN Position */ 873 #define RTC_INTEN_ALMIEN_Msk (0x1ul << RTC_INTEN_ALMIEN_Pos) /*!< RTC_T::INTEN: ALMIEN Mask */ 874 875 #define RTC_INTEN_TICKIEN_Pos (1) /*!< RTC_T::INTEN: TICKIEN Position */ 876 #define RTC_INTEN_TICKIEN_Msk (0x1ul << RTC_INTEN_TICKIEN_Pos) /*!< RTC_T::INTEN: TICKIEN Mask */ 877 878 #define RTC_INTEN_TAMP0IEN_Pos (8) /*!< RTC_T::INTEN: TAMP0IEN Position */ 879 #define RTC_INTEN_TAMP0IEN_Msk (0x1ul << RTC_INTEN_TAMP0IEN_Pos) /*!< RTC_T::INTEN: TAMP0IEN Mask */ 880 881 #define RTC_INTEN_TAMP1IEN_Pos (9) /*!< RTC_T::INTEN: TAMP1IEN Position */ 882 #define RTC_INTEN_TAMP1IEN_Msk (0x1ul << RTC_INTEN_TAMP1IEN_Pos) /*!< RTC_T::INTEN: TAMP1IEN Mask */ 883 884 #define RTC_INTEN_TAMP2IEN_Pos (10) /*!< RTC_T::INTEN: TAMP2IEN Position */ 885 #define RTC_INTEN_TAMP2IEN_Msk (0x1ul << RTC_INTEN_TAMP2IEN_Pos) /*!< RTC_T::INTEN: TAMP2IEN Mask */ 886 887 #define RTC_INTEN_TAMP3IEN_Pos (11) /*!< RTC_T::INTEN: TAMP3IEN Position */ 888 #define RTC_INTEN_TAMP3IEN_Msk (0x1ul << RTC_INTEN_TAMP3IEN_Pos) /*!< RTC_T::INTEN: TAMP3IEN Mask */ 889 890 #define RTC_INTEN_TAMP4IEN_Pos (12) /*!< RTC_T::INTEN: TAMP4IEN Position */ 891 #define RTC_INTEN_TAMP4IEN_Msk (0x1ul << RTC_INTEN_TAMP4IEN_Pos) /*!< RTC_T::INTEN: TAMP4IEN Mask */ 892 893 #define RTC_INTEN_TAMP5IEN_Pos (13) /*!< RTC_T::INTEN: TAMP5IEN Position */ 894 #define RTC_INTEN_TAMP5IEN_Msk (0x1ul << RTC_INTEN_TAMP5IEN_Pos) /*!< RTC_T::INTEN: TAMP5IEN Mask */ 895 896 #define RTC_INTEN_CLKFIEN_Pos (24) /*!< RTC_T::INTEN: CLKFIEN Position */ 897 #define RTC_INTEN_CLKFIEN_Msk (0x1ul << RTC_INTEN_CLKFIEN_Pos) /*!< RTC_T::INTEN: CLKFIEN Mask */ 898 899 #define RTC_INTEN_CLKSTIEN_Pos (25) /*!< RTC_T::INTEN: CLKSTIEN Position */ 900 #define RTC_INTEN_CLKSTIEN_Msk (0x1ul << RTC_INTEN_CLKSTIEN_Pos) /*!< RTC_T::INTEN: CLKSTIEN Mask */ 901 902 #define RTC_INTSTS_ALMIF_Pos (0) /*!< RTC_T::INTSTS: ALMIF Position */ 903 #define RTC_INTSTS_ALMIF_Msk (0x1ul << RTC_INTSTS_ALMIF_Pos) /*!< RTC_T::INTSTS: ALMIF Mask */ 904 905 #define RTC_INTSTS_TICKIF_Pos (1) /*!< RTC_T::INTSTS: TICKIF Position */ 906 #define RTC_INTSTS_TICKIF_Msk (0x1ul << RTC_INTSTS_TICKIF_Pos) /*!< RTC_T::INTSTS: TICKIF Mask */ 907 908 #define RTC_INTSTS_TAMP0IF_Pos (8) /*!< RTC_T::INTSTS: TAMP0IF Position */ 909 #define RTC_INTSTS_TAMP0IF_Msk (0x1ul << RTC_INTSTS_TAMP0IF_Pos) /*!< RTC_T::INTSTS: TAMP0IF Mask */ 910 911 #define RTC_INTSTS_TAMP1IF_Pos (9) /*!< RTC_T::INTSTS: TAMP1IF Position */ 912 #define RTC_INTSTS_TAMP1IF_Msk (0x1ul << RTC_INTSTS_TAMP1IF_Pos) /*!< RTC_T::INTSTS: TAMP1IF Mask */ 913 914 #define RTC_INTSTS_TAMP2IF_Pos (10) /*!< RTC_T::INTSTS: TAMP2IF Position */ 915 #define RTC_INTSTS_TAMP2IF_Msk (0x1ul << RTC_INTSTS_TAMP2IF_Pos) /*!< RTC_T::INTSTS: TAMP2IF Mask */ 916 917 #define RTC_INTSTS_TAMP3IF_Pos (11) /*!< RTC_T::INTSTS: TAMP3IF Position */ 918 #define RTC_INTSTS_TAMP3IF_Msk (0x1ul << RTC_INTSTS_TAMP3IF_Pos) /*!< RTC_T::INTSTS: TAMP3IF Mask */ 919 920 #define RTC_INTSTS_TAMP4IF_Pos (12) /*!< RTC_T::INTSTS: TAMP4IF Position */ 921 #define RTC_INTSTS_TAMP4IF_Msk (0x1ul << RTC_INTSTS_TAMP4IF_Pos) /*!< RTC_T::INTSTS: TAMP4IF Mask */ 922 923 #define RTC_INTSTS_TAMP5IF_Pos (13) /*!< RTC_T::INTSTS: TAMP5IF Position */ 924 #define RTC_INTSTS_TAMP5IF_Msk (0x1ul << RTC_INTSTS_TAMP5IF_Pos) /*!< RTC_T::INTSTS: TAMP5IF Mask */ 925 926 #define RTC_INTSTS_CLKFIF_Pos (24) /*!< RTC_T::INTSTS: CLKFIF Position */ 927 #define RTC_INTSTS_CLKFIF_Msk (0x1ul << RTC_INTSTS_CLKFIF_Pos) /*!< RTC_T::INTSTS: CLKFIF Mask */ 928 929 #define RTC_INTSTS_CLKSTIF_Pos (25) /*!< RTC_T::INTSTS: CLKSTIF Position */ 930 #define RTC_INTSTS_CLKSTIF_Msk (0x1ul << RTC_INTSTS_CLKSTIF_Pos) /*!< RTC_T::INTSTS: CLKSTIF Mask */ 931 932 #define RTC_TICK_TICK_Pos (0) /*!< RTC_T::TICK: TICK Position */ 933 #define RTC_TICK_TICK_Msk (0x7ul << RTC_TICK_TICK_Pos) /*!< RTC_T::TICK: TICK Mask */ 934 935 #define RTC_TAMSK_MSEC_Pos (0) /*!< RTC_T::TAMSK: MSEC Position */ 936 #define RTC_TAMSK_MSEC_Msk (0x1ul << RTC_TAMSK_MSEC_Pos) /*!< RTC_T::TAMSK: MSEC Mask */ 937 938 #define RTC_TAMSK_MTENSEC_Pos (1) /*!< RTC_T::TAMSK: MTENSEC Position */ 939 #define RTC_TAMSK_MTENSEC_Msk (0x1ul << RTC_TAMSK_MTENSEC_Pos) /*!< RTC_T::TAMSK: MTENSEC Mask */ 940 941 #define RTC_TAMSK_MMIN_Pos (2) /*!< RTC_T::TAMSK: MMIN Position */ 942 #define RTC_TAMSK_MMIN_Msk (0x1ul << RTC_TAMSK_MMIN_Pos) /*!< RTC_T::TAMSK: MMIN Mask */ 943 944 #define RTC_TAMSK_MTENMIN_Pos (3) /*!< RTC_T::TAMSK: MTENMIN Position */ 945 #define RTC_TAMSK_MTENMIN_Msk (0x1ul << RTC_TAMSK_MTENMIN_Pos) /*!< RTC_T::TAMSK: MTENMIN Mask */ 946 947 #define RTC_TAMSK_MHR_Pos (4) /*!< RTC_T::TAMSK: MHR Position */ 948 #define RTC_TAMSK_MHR_Msk (0x1ul << RTC_TAMSK_MHR_Pos) /*!< RTC_T::TAMSK: MHR Mask */ 949 950 #define RTC_TAMSK_MTENHR_Pos (5) /*!< RTC_T::TAMSK: MTENHR Position */ 951 #define RTC_TAMSK_MTENHR_Msk (0x1ul << RTC_TAMSK_MTENHR_Pos) /*!< RTC_T::TAMSK: MTENHR Mask */ 952 953 #define RTC_CAMSK_MDAY_Pos (0) /*!< RTC_T::CAMSK: MDAY Position */ 954 #define RTC_CAMSK_MDAY_Msk (0x1ul << RTC_CAMSK_MDAY_Pos) /*!< RTC_T::CAMSK: MDAY Mask */ 955 956 #define RTC_CAMSK_MTENDAY_Pos (1) /*!< RTC_T::CAMSK: MTENDAY Position */ 957 #define RTC_CAMSK_MTENDAY_Msk (0x1ul << RTC_CAMSK_MTENDAY_Pos) /*!< RTC_T::CAMSK: MTENDAY Mask */ 958 959 #define RTC_CAMSK_MMON_Pos (2) /*!< RTC_T::CAMSK: MMON Position */ 960 #define RTC_CAMSK_MMON_Msk (0x1ul << RTC_CAMSK_MMON_Pos) /*!< RTC_T::CAMSK: MMON Mask */ 961 962 #define RTC_CAMSK_MTENMON_Pos (3) /*!< RTC_T::CAMSK: MTENMON Position */ 963 #define RTC_CAMSK_MTENMON_Msk (0x1ul << RTC_CAMSK_MTENMON_Pos) /*!< RTC_T::CAMSK: MTENMON Mask */ 964 965 #define RTC_CAMSK_MYEAR_Pos (4) /*!< RTC_T::CAMSK: MYEAR Position */ 966 #define RTC_CAMSK_MYEAR_Msk (0x1ul << RTC_CAMSK_MYEAR_Pos) /*!< RTC_T::CAMSK: MYEAR Mask */ 967 968 #define RTC_CAMSK_MTENYEAR_Pos (5) /*!< RTC_T::CAMSK: MTENYEAR Position */ 969 #define RTC_CAMSK_MTENYEAR_Msk (0x1ul << RTC_CAMSK_MTENYEAR_Pos) /*!< RTC_T::CAMSK: MTENYEAR Mask */ 970 971 #define RTC_SPRCTL_SPRRWEN_Pos (2) /*!< RTC_T::SPRCTL: SPRRWEN Position */ 972 #define RTC_SPRCTL_SPRRWEN_Msk (0x1ul << RTC_SPRCTL_SPRRWEN_Pos) /*!< RTC_T::SPRCTL: SPRRWEN Mask */ 973 974 #define RTC_SPRCTL_SPRCSTS_Pos (5) /*!< RTC_T::SPRCTL: SPRCSTS Position */ 975 #define RTC_SPRCTL_SPRCSTS_Msk (0x1ul << RTC_SPRCTL_SPRCSTS_Pos) /*!< RTC_T::SPRCTL: SPRCSTS Mask */ 976 977 #define RTC_SPRCTL_LXTFCLR_Pos (16) /*!< RTC_T::SPRCTL: LXTFCLR Position */ 978 #define RTC_SPRCTL_LXTFCLR_Msk (0x1ul << RTC_SPRCTL_LXTFCLR_Pos) /*!< RTC_T::SPRCTL: LXTFCLR Mask */ 979 980 #define RTC_SPR0_SPARE_Pos (0) /*!< RTC_T::SPR0: SPARE Position */ 981 #define RTC_SPR0_SPARE_Msk (0xfffffffful << RTC_SPR0_SPARE_Pos) /*!< RTC_T::SPR0: SPARE Mask */ 982 983 #define RTC_SPR1_SPARE_Pos (0) /*!< RTC_T::SPR1: SPARE Position */ 984 #define RTC_SPR1_SPARE_Msk (0xfffffffful << RTC_SPR1_SPARE_Pos) /*!< RTC_T::SPR1: SPARE Mask */ 985 986 #define RTC_SPR2_SPARE_Pos (0) /*!< RTC_T::SPR2: SPARE Position */ 987 #define RTC_SPR2_SPARE_Msk (0xfffffffful << RTC_SPR2_SPARE_Pos) /*!< RTC_T::SPR2: SPARE Mask */ 988 989 #define RTC_SPR3_SPARE_Pos (0) /*!< RTC_T::SPR3: SPARE Position */ 990 #define RTC_SPR3_SPARE_Msk (0xfffffffful << RTC_SPR3_SPARE_Pos) /*!< RTC_T::SPR3: SPARE Mask */ 991 992 #define RTC_SPR4_SPARE_Pos (0) /*!< RTC_T::SPR4: SPARE Position */ 993 #define RTC_SPR4_SPARE_Msk (0xfffffffful << RTC_SPR4_SPARE_Pos) /*!< RTC_T::SPR4: SPARE Mask */ 994 995 #define RTC_SPR5_SPARE_Pos (0) /*!< RTC_T::SPR5: SPARE Position */ 996 #define RTC_SPR5_SPARE_Msk (0xfffffffful << RTC_SPR5_SPARE_Pos) /*!< RTC_T::SPR5: SPARE Mask */ 997 998 #define RTC_SPR6_SPARE_Pos (0) /*!< RTC_T::SPR6: SPARE Position */ 999 #define RTC_SPR6_SPARE_Msk (0xfffffffful << RTC_SPR6_SPARE_Pos) /*!< RTC_T::SPR6: SPARE Mask */ 1000 1001 #define RTC_SPR7_SPARE_Pos (0) /*!< RTC_T::SPR7: SPARE Position */ 1002 #define RTC_SPR7_SPARE_Msk (0xfffffffful << RTC_SPR7_SPARE_Pos) /*!< RTC_T::SPR7: SPARE Mask */ 1003 1004 #define RTC_SPR8_SPARE_Pos (0) /*!< RTC_T::SPR8: SPARE Position */ 1005 #define RTC_SPR8_SPARE_Msk (0xfffffffful << RTC_SPR8_SPARE_Pos) /*!< RTC_T::SPR8: SPARE Mask */ 1006 1007 #define RTC_SPR9_SPARE_Pos (0) /*!< RTC_T::SPR9: SPARE Position */ 1008 #define RTC_SPR9_SPARE_Msk (0xfffffffful << RTC_SPR9_SPARE_Pos) /*!< RTC_T::SPR9: SPARE Mask */ 1009 1010 #define RTC_SPR10_SPARE_Pos (0) /*!< RTC_T::SPR10: SPARE Position */ 1011 #define RTC_SPR10_SPARE_Msk (0xfffffffful << RTC_SPR10_SPARE_Pos) /*!< RTC_T::SPR10: SPARE Mask */ 1012 1013 #define RTC_SPR11_SPARE_Pos (0) /*!< RTC_T::SPR11: SPARE Position */ 1014 #define RTC_SPR11_SPARE_Msk (0xfffffffful << RTC_SPR11_SPARE_Pos) /*!< RTC_T::SPR11: SPARE Mask */ 1015 1016 #define RTC_SPR12_SPARE_Pos (0) /*!< RTC_T::SPR12: SPARE Position */ 1017 #define RTC_SPR12_SPARE_Msk (0xfffffffful << RTC_SPR12_SPARE_Pos) /*!< RTC_T::SPR12: SPARE Mask */ 1018 1019 #define RTC_SPR13_SPARE_Pos (0) /*!< RTC_T::SPR13: SPARE Position */ 1020 #define RTC_SPR13_SPARE_Msk (0xfffffffful << RTC_SPR13_SPARE_Pos) /*!< RTC_T::SPR13: SPARE Mask */ 1021 1022 #define RTC_SPR14_SPARE_Pos (0) /*!< RTC_T::SPR14: SPARE Position */ 1023 #define RTC_SPR14_SPARE_Msk (0xfffffffful << RTC_SPR14_SPARE_Pos) /*!< RTC_T::SPR14: SPARE Mask */ 1024 1025 #define RTC_SPR15_SPARE_Pos (0) /*!< RTC_T::SPR15: SPARE Position */ 1026 #define RTC_SPR15_SPARE_Msk (0xfffffffful << RTC_SPR15_SPARE_Pos) /*!< RTC_T::SPR15: SPARE Mask */ 1027 1028 #define RTC_SPR16_SPARE_Pos (0) /*!< RTC_T::SPR16: SPARE Position */ 1029 #define RTC_SPR16_SPARE_Msk (0xfffffffful << RTC_SPR16_SPARE_Pos) /*!< RTC_T::SPR16: SPARE Mask */ 1030 1031 #define RTC_SPR17_SPARE_Pos (0) /*!< RTC_T::SPR17: SPARE Position */ 1032 #define RTC_SPR17_SPARE_Msk (0xfffffffful << RTC_SPR17_SPARE_Pos) /*!< RTC_T::SPR17: SPARE Mask */ 1033 1034 #define RTC_SPR18_SPARE_Pos (0) /*!< RTC_T::SPR18: SPARE Position */ 1035 #define RTC_SPR18_SPARE_Msk (0xfffffffful << RTC_SPR18_SPARE_Pos) /*!< RTC_T::SPR18: SPARE Mask */ 1036 1037 #define RTC_SPR19_SPARE_Pos (0) /*!< RTC_T::SPR19: SPARE Position */ 1038 #define RTC_SPR19_SPARE_Msk (0xfffffffful << RTC_SPR19_SPARE_Pos) /*!< RTC_T::SPR19: SPARE Mask */ 1039 1040 #define RTC_LXTCTL_LIRC32KEN_Pos (0) /*!< RTC_T::LXTCTL: LIRC32KEN Position */ 1041 #define RTC_LXTCTL_LIRC32KEN_Msk (0x1ul << RTC_LXTCTL_LIRC32KEN_Pos) /*!< RTC_T::LXTCTL: LIRC32KEN Mask */ 1042 1043 #define RTC_LXTCTL_GAIN_Pos (1) /*!< RTC_T::LXTCTL: GAIN Position */ 1044 #define RTC_LXTCTL_GAIN_Msk (0x7ul << RTC_LXTCTL_GAIN_Pos) /*!< RTC_T::LXTCTL: GAIN Mask */ 1045 1046 #define RTC_LXTCTL_C32KSEL_Pos (6) /*!< RTC_T::LXTCTL: C32KSEL Position */ 1047 #define RTC_LXTCTL_C32KSEL_Msk (0x1ul << RTC_LXTCTL_C32KSEL_Pos) /*!< RTC_T::LXTCTL: C32KSEL Mask */ 1048 1049 #define RTC_LXTCTL_RTCCKSEL_Pos (7) /*!< RTC_T::LXTCTL: RTCCKSEL Position */ 1050 #define RTC_LXTCTL_RTCCKSEL_Msk (0x1ul << RTC_LXTCTL_RTCCKSEL_Pos) /*!< RTC_T::LXTCTL: RTCCKSEL Mask */ 1051 1052 #define RTC_LXTCTL_IOCTLSEL_Pos (8) /*!< RTC_T::LXTCTL: IOCTLSEL Position */ 1053 #define RTC_LXTCTL_IOCTLSEL_Msk (0x1ul << RTC_LXTCTL_IOCTLSEL_Pos) /*!< RTC_T::LXTCTL: IOCTLSEL Mask */ 1054 1055 #define RTC_GPIOCTL0_OPMODE0_Pos (0) /*!< RTC_T::GPIOCTL0: OPMODE0 Position */ 1056 #define RTC_GPIOCTL0_OPMODE0_Msk (0x3ul << RTC_GPIOCTL0_OPMODE0_Pos) /*!< RTC_T::GPIOCTL0: OPMODE0 Mask */ 1057 1058 #define RTC_GPIOCTL0_DOUT0_Pos (2) /*!< RTC_T::GPIOCTL0: DOUT0 Position */ 1059 #define RTC_GPIOCTL0_DOUT0_Msk (0x1ul << RTC_GPIOCTL0_DOUT0_Pos) /*!< RTC_T::GPIOCTL0: DOUT0 Mask */ 1060 1061 #define RTC_GPIOCTL0_DINOFF0_Pos (3) /*!< RTC_T::GPIOCTL0: DINOFF0 Position */ 1062 #define RTC_GPIOCTL0_DINOFF0_Msk (0x1ul << RTC_GPIOCTL0_DINOFF0_Pos) /*!< RTC_T::GPIOCTL0: DINOFF0 Mask */ 1063 1064 #define RTC_GPIOCTL0_PUSEL0_Pos (4) /*!< RTC_T::GPIOCTL0: PUSEL0 Position */ 1065 #define RTC_GPIOCTL0_PUSEL0_Msk (0x3ul << RTC_GPIOCTL0_PUSEL0_Pos) /*!< RTC_T::GPIOCTL0: PUSEL0 Mask */ 1066 1067 #define RTC_GPIOCTL0_OPMODE1_Pos (8) /*!< RTC_T::GPIOCTL0: OPMODE1 Position */ 1068 #define RTC_GPIOCTL0_OPMODE1_Msk (0x3ul << RTC_GPIOCTL0_OPMODE1_Pos) /*!< RTC_T::GPIOCTL0: OPMODE1 Mask */ 1069 1070 #define RTC_GPIOCTL0_DOUT1_Pos (10) /*!< RTC_T::GPIOCTL0: DOUT1 Position */ 1071 #define RTC_GPIOCTL0_DOUT1_Msk (0x1ul << RTC_GPIOCTL0_DOUT1_Pos) /*!< RTC_T::GPIOCTL0: DOUT1 Mask */ 1072 1073 #define RTC_GPIOCTL0_DINOFF1_Pos (11) /*!< RTC_T::GPIOCTL0: DINOFF1 Position */ 1074 #define RTC_GPIOCTL0_DINOFF1_Msk (0x1ul << RTC_GPIOCTL0_DINOFF1_Pos) /*!< RTC_T::GPIOCTL0: DINOFF1 Mask */ 1075 1076 #define RTC_GPIOCTL0_PUSEL1_Pos (12) /*!< RTC_T::GPIOCTL0: PUSEL1 Position */ 1077 #define RTC_GPIOCTL0_PUSEL1_Msk (0x3ul << RTC_GPIOCTL0_PUSEL1_Pos) /*!< RTC_T::GPIOCTL0: PUSEL1 Mask */ 1078 1079 #define RTC_GPIOCTL0_OPMODE2_Pos (16) /*!< RTC_T::GPIOCTL0: OPMODE2 Position */ 1080 #define RTC_GPIOCTL0_OPMODE2_Msk (0x3ul << RTC_GPIOCTL0_OPMODE2_Pos) /*!< RTC_T::GPIOCTL0: OPMODE2 Mask */ 1081 1082 #define RTC_GPIOCTL0_DOUT2_Pos (18) /*!< RTC_T::GPIOCTL0: DOUT2 Position */ 1083 #define RTC_GPIOCTL0_DOUT2_Msk (0x1ul << RTC_GPIOCTL0_DOUT2_Pos) /*!< RTC_T::GPIOCTL0: DOUT2 Mask */ 1084 1085 #define RTC_GPIOCTL0_DINOFF2_Pos (19) /*!< RTC_T::GPIOCTL0: DINOFF2 Position */ 1086 #define RTC_GPIOCTL0_DINOFF2_Msk (0x1ul << RTC_GPIOCTL0_DINOFF2_Pos) /*!< RTC_T::GPIOCTL0: DINOFF2 Mask */ 1087 1088 #define RTC_GPIOCTL0_PUSEL2_Pos (20) /*!< RTC_T::GPIOCTL0: PUSEL2 Position */ 1089 #define RTC_GPIOCTL0_PUSEL2_Msk (0x3ul << RTC_GPIOCTL0_PUSEL2_Pos) /*!< RTC_T::GPIOCTL0: PUSEL2 Mask */ 1090 1091 #define RTC_GPIOCTL0_OPMODE3_Pos (24) /*!< RTC_T::GPIOCTL0: OPMODE3 Position */ 1092 #define RTC_GPIOCTL0_OPMODE3_Msk (0x3ul << RTC_GPIOCTL0_OPMODE3_Pos) /*!< RTC_T::GPIOCTL0: OPMODE3 Mask */ 1093 1094 #define RTC_GPIOCTL0_DOUT3_Pos (26) /*!< RTC_T::GPIOCTL0: DOUT3 Position */ 1095 #define RTC_GPIOCTL0_DOUT3_Msk (0x1ul << RTC_GPIOCTL0_DOUT3_Pos) /*!< RTC_T::GPIOCTL0: DOUT3 Mask */ 1096 1097 #define RTC_GPIOCTL0_DINOFF3_Pos (27) /*!< RTC_T::GPIOCTL0: DINOFF3 Position */ 1098 #define RTC_GPIOCTL0_DINOFF3_Msk (0x1ul << RTC_GPIOCTL0_DINOFF3_Pos) /*!< RTC_T::GPIOCTL0: DINOFF3 Mask */ 1099 1100 #define RTC_GPIOCTL0_PUSEL3_Pos (28) /*!< RTC_T::GPIOCTL0: PUSEL3 Position */ 1101 #define RTC_GPIOCTL0_PUSEL3_Msk (0x3ul << RTC_GPIOCTL0_PUSEL3_Pos) /*!< RTC_T::GPIOCTL0: PUSEL3 Mask */ 1102 1103 #define RTC_GPIOCTL1_OPMODE4_Pos (0) /*!< RTC_T::GPIOCTL1: OPMODE4 Position */ 1104 #define RTC_GPIOCTL1_OPMODE4_Msk (0x3ul << RTC_GPIOCTL1_OPMODE4_Pos) /*!< RTC_T::GPIOCTL1: OPMODE4 Mask */ 1105 1106 #define RTC_GPIOCTL1_DOUT4_Pos (2) /*!< RTC_T::GPIOCTL1: DOUT4 Position */ 1107 #define RTC_GPIOCTL1_DOUT4_Msk (0x1ul << RTC_GPIOCTL1_DOUT4_Pos) /*!< RTC_T::GPIOCTL1: DOUT4 Mask */ 1108 1109 #define RTC_GPIOCTL0_DINOFF4_Pos (3) /*!< RTC_T::GPIOCTL1: DINOFF4 Position */ 1110 #define RTC_GPIOCTL0_DINOFF4_Msk (0x1ul << RTC_GPIOCTL0_DINOFF4_Pos) /*!< RTC_T::GPIOCTL1: DINOFF4 Mask */ 1111 1112 #define RTC_GPIOCTL1_PUSEL4_Pos (4) /*!< RTC_T::GPIOCTL1: PUSEL4 Position */ 1113 #define RTC_GPIOCTL1_PUSEL4_Msk (0x3ul << RTC_GPIOCTL1_PUSEL4_Pos) /*!< RTC_T::GPIOCTL1: PUSEL4 Mask */ 1114 1115 #define RTC_GPIOCTL1_OPMODE5_Pos (8) /*!< RTC_T::GPIOCTL1: OPMODE5 Position */ 1116 #define RTC_GPIOCTL1_OPMODE5_Msk (0x3ul << RTC_GPIOCTL1_OPMODE5_Pos) /*!< RTC_T::GPIOCTL1: OPMODE5 Mask */ 1117 1118 #define RTC_GPIOCTL1_DOUT5_Pos (10) /*!< RTC_T::GPIOCTL1: DOUT5 Position */ 1119 #define RTC_GPIOCTL1_DOUT5_Msk (0x1ul << RTC_GPIOCTL1_DOUT5_Pos) /*!< RTC_T::GPIOCTL1: DOUT5 Mask */ 1120 1121 #define RTC_GPIOCTL0_DINOFF5_Pos (11) /*!< RTC_T::GPIOCTL1: DINOFF5 Position */ 1122 #define RTC_GPIOCTL0_DINOFF5_Msk (0x1ul << RTC_GPIOCTL0_DINOFF5_Pos) /*!< RTC_T::GPIOCTL1: DINOFF5 Mask */ 1123 1124 #define RTC_GPIOCTL1_PUSEL5_Pos (12) /*!< RTC_T::GPIOCTL1: PUSEL5 Position */ 1125 #define RTC_GPIOCTL1_PUSEL5_Msk (0x3ul << RTC_GPIOCTL1_PUSEL5_Pos) /*!< RTC_T::GPIOCTL1: PUSEL5 Mask */ 1126 1127 #define RTC_GPIOCTL1_OPMODE6_Pos (16) /*!< RTC_T::GPIOCTL1: OPMODE6 Position */ 1128 #define RTC_GPIOCTL1_OPMODE6_Msk (0x3ul << RTC_GPIOCTL1_OPMODE6_Pos) /*!< RTC_T::GPIOCTL1: OPMODE6 Mask */ 1129 1130 #define RTC_GPIOCTL1_DOUT6_Pos (18) /*!< RTC_T::GPIOCTL1: DOUT6 Position */ 1131 #define RTC_GPIOCTL1_DOUT6_Msk (0x1ul << RTC_GPIOCTL1_DOUT6_Pos) /*!< RTC_T::GPIOCTL1: DOUT6 Mask */ 1132 1133 #define RTC_GPIOCTL0_DINOFF6_Pos (19) /*!< RTC_T::GPIOCTL1: DINOFF6 Position */ 1134 #define RTC_GPIOCTL0_DINOFF6_Msk (0x1ul << RTC_GPIOCTL0_DINOFF6_Pos) /*!< RTC_T::GPIOCTL1: DINOFF6 Mask */ 1135 1136 #define RTC_GPIOCTL1_PUSEL6_Pos (20) /*!< RTC_T::GPIOCTL1: PUSEL6 Position */ 1137 #define RTC_GPIOCTL1_PUSEL6_Msk (0x3ul << RTC_GPIOCTL1_PUSEL6_Pos) /*!< RTC_T::GPIOCTL1: PUSEL6 Mask */ 1138 1139 #define RTC_GPIOCTL1_OPMODE7_Pos (24) /*!< RTC_T::GPIOCTL1: OPMODE7 Position */ 1140 #define RTC_GPIOCTL1_OPMODE7_Msk (0x3ul << RTC_GPIOCTL1_OPMODE7_Pos) /*!< RTC_T::GPIOCTL1: OPMODE7 Mask */ 1141 1142 #define RTC_GPIOCTL1_DOUT7_Pos (26) /*!< RTC_T::GPIOCTL1: DOUT7 Position */ 1143 #define RTC_GPIOCTL1_DOUT7_Msk (0x1ul << RTC_GPIOCTL1_DOUT7_Pos) /*!< RTC_T::GPIOCTL1: DOUT7 Mask */ 1144 1145 #define RTC_GPIOCTL0_DINOFF7_Pos (27) /*!< RTC_T::GPIOCTL1: DINOFF7 Position */ 1146 #define RTC_GPIOCTL0_DINOFF7_Msk (0x1ul << RTC_GPIOCTL0_DINOFF7_Pos) /*!< RTC_T::GPIOCTL1: DINOFF7 Mask */ 1147 1148 #define RTC_GPIOCTL1_PUSEL7_Pos (28) /*!< RTC_T::GPIOCTL1: PUSEL7 Position */ 1149 #define RTC_GPIOCTL1_PUSEL7_Msk (0x3ul << RTC_GPIOCTL1_PUSEL7_Pos) /*!< RTC_T::GPIOCTL1: PUSEL7 Mask */ 1150 1151 #define RTC_DSTCTL_ADDHR_Pos (0) /*!< RTC_T::DSTCTL: ADDHR Position */ 1152 #define RTC_DSTCTL_ADDHR_Msk (0x1ul << RTC_DSTCTL_ADDHR_Pos) /*!< RTC_T::DSTCTL: ADDHR Mask */ 1153 1154 #define RTC_DSTCTL_SUBHR_Pos (1) /*!< RTC_T::DSTCTL: SUBHR Position */ 1155 #define RTC_DSTCTL_SUBHR_Msk (0x1ul << RTC_DSTCTL_SUBHR_Pos) /*!< RTC_T::DSTCTL: SUBHR Mask */ 1156 1157 #define RTC_DSTCTL_DSBAK_Pos (2) /*!< RTC_T::DSTCTL: DSBAK Position */ 1158 #define RTC_DSTCTL_DSBAK_Msk (0x1ul << RTC_DSTCTL_DSBAK_Pos) /*!< RTC_T::DSTCTL: DSBAK Mask */ 1159 1160 #define RTC_TAMPCTL_DYN1ISS_Pos (0) /*!< RTC_T::TAMPCTL: DYN1ISS Position */ 1161 #define RTC_TAMPCTL_DYN1ISS_Msk (0x1ul << RTC_TAMPCTL_DYN1ISS_Pos) /*!< RTC_T::TAMPCTL: DYN1ISS Mask */ 1162 1163 #define RTC_TAMPCTL_DYN2ISS_Pos (1) /*!< RTC_T::TAMPCTL: DYN2ISS Position */ 1164 #define RTC_TAMPCTL_DYN2ISS_Msk (0x1ul << RTC_TAMPCTL_DYN2ISS_Pos) /*!< RTC_T::TAMPCTL: DYN2ISS Mask */ 1165 1166 #define RTC_TAMPCTL_DYNSRC_Pos (3) /*!< RTC_T::TAMPCTL: DYNSRC Position */ 1167 #define RTC_TAMPCTL_DYNSRC_Msk (0x1ul << RTC_TAMPCTL_DYNSRC_Pos) /*!< RTC_T::TAMPCTL: DYNSRC Mask */ 1168 1169 #define RTC_TAMPCTL_SEEDRLD_Pos (4) /*!< RTC_T::TAMPCTL: SEEDRLD Position */ 1170 #define RTC_TAMPCTL_SEEDRLD_Msk (0x1ul << RTC_TAMPCTL_SEEDRLD_Pos) /*!< RTC_T::TAMPCTL: SEEDRLD Mask */ 1171 1172 #define RTC_TAMPCTL_DYNRATE_Pos (5) /*!< RTC_T::TAMPCTL: DYNRATE Position */ 1173 #define RTC_TAMPCTL_DYNRATE_Msk (0x7ul << RTC_TAMPCTL_DYNRATE_Pos) /*!< RTC_T::TAMPCTL: DYNRATE Mask */ 1174 1175 #define RTC_TAMPCTL_TAMP0EN_Pos (8) /*!< RTC_T::TAMPCTL: TAMP0EN Position */ 1176 #define RTC_TAMPCTL_TAMP0EN_Msk (0x1ul << RTC_TAMPCTL_TAMP0EN_Pos) /*!< RTC_T::TAMPCTL: TAMP0EN Mask */ 1177 1178 #define RTC_TAMPCTL_TAMP0LV_Pos (9) /*!< RTC_T::TAMPCTL: TAMP0LV Position */ 1179 #define RTC_TAMPCTL_TAMP0LV_Msk (0x1ul << RTC_TAMPCTL_TAMP0LV_Pos) /*!< RTC_T::TAMPCTL: TAMP0LV Mask */ 1180 1181 #define RTC_TAMPCTL_TAMP0DBEN_Pos (10) /*!< RTC_T::TAMPCTL: TAMP0DBEN Position */ 1182 #define RTC_TAMPCTL_TAMP0DBEN_Msk (0x1ul << RTC_TAMPCTL_TAMP0DBEN_Pos) /*!< RTC_T::TAMPCTL: TAMP0DBEN Mask */ 1183 1184 #define RTC_TAMPCTL_TAMP1EN_Pos (12) /*!< RTC_T::TAMPCTL: TAMP1EN Position */ 1185 #define RTC_TAMPCTL_TAMP1EN_Msk (0x1ul << RTC_TAMPCTL_TAMP1EN_Pos) /*!< RTC_T::TAMPCTL: TAMP1EN Mask */ 1186 1187 #define RTC_TAMPCTL_TAMP1LV_Pos (13) /*!< RTC_T::TAMPCTL: TAMP1LV Position */ 1188 #define RTC_TAMPCTL_TAMP1LV_Msk (0x1ul << RTC_TAMPCTL_TAMP1LV_Pos) /*!< RTC_T::TAMPCTL: TAMP1LV Mask */ 1189 1190 #define RTC_TAMPCTL_TAMP1DBEN_Pos (14) /*!< RTC_T::TAMPCTL: TAMP1DBEN Position */ 1191 #define RTC_TAMPCTL_TAMP1DBEN_Msk (0x1ul << RTC_TAMPCTL_TAMP1DBEN_Pos) /*!< RTC_T::TAMPCTL: TAMP1DBEN Mask */ 1192 1193 #define RTC_TAMPCTL_DYNPR0EN_Pos (15) /*!< RTC_T::TAMPCTL: DYNPR0EN Position */ 1194 #define RTC_TAMPCTL_DYNPR0EN_Msk (0x1ul << RTC_TAMPCTL_DYNPR0EN_Pos) /*!< RTC_T::TAMPCTL: DYNPR0EN Mask */ 1195 1196 #define RTC_TAMPCTL_TAMP2EN_Pos (16) /*!< RTC_T::TAMPCTL: TAMP2EN Position */ 1197 #define RTC_TAMPCTL_TAMP2EN_Msk (0x1ul << RTC_TAMPCTL_TAMP2EN_Pos) /*!< RTC_T::TAMPCTL: TAMP2EN Mask */ 1198 1199 #define RTC_TAMPCTL_TAMP2LV_Pos (17) /*!< RTC_T::TAMPCTL: TAMP2LV Position */ 1200 #define RTC_TAMPCTL_TAMP2LV_Msk (0x1ul << RTC_TAMPCTL_TAMP2LV_Pos) /*!< RTC_T::TAMPCTL: TAMP2LV Mask */ 1201 1202 #define RTC_TAMPCTL_TAMP2DBEN_Pos (18) /*!< RTC_T::TAMPCTL: TAMP2DBEN Position */ 1203 #define RTC_TAMPCTL_TAMP2DBEN_Msk (0x1ul << RTC_TAMPCTL_TAMP2DBEN_Pos) /*!< RTC_T::TAMPCTL: TAMP2DBEN Mask */ 1204 1205 #define RTC_TAMPCTL_TAMP3EN_Pos (20) /*!< RTC_T::TAMPCTL: TAMP3EN Position */ 1206 #define RTC_TAMPCTL_TAMP3EN_Msk (0x1ul << RTC_TAMPCTL_TAMP3EN_Pos) /*!< RTC_T::TAMPCTL: TAMP3EN Mask */ 1207 1208 #define RTC_TAMPCTL_TAMP3LV_Pos (21) /*!< RTC_T::TAMPCTL: TAMP3LV Position */ 1209 #define RTC_TAMPCTL_TAMP3LV_Msk (0x1ul << RTC_TAMPCTL_TAMP3LV_Pos) /*!< RTC_T::TAMPCTL: TAMP3LV Mask */ 1210 1211 #define RTC_TAMPCTL_TAMP3DBEN_Pos (22) /*!< RTC_T::TAMPCTL: TAMP3DBEN Position */ 1212 #define RTC_TAMPCTL_TAMP3DBEN_Msk (0x1ul << RTC_TAMPCTL_TAMP3DBEN_Pos) /*!< RTC_T::TAMPCTL: TAMP3DBEN Mask */ 1213 1214 #define RTC_TAMPCTL_DYNPR1EN_Pos (23) /*!< RTC_T::TAMPCTL: DYNPR1EN Position */ 1215 #define RTC_TAMPCTL_DYNPR1EN_Msk (0x1ul << RTC_TAMPCTL_DYNPR1EN_Pos) /*!< RTC_T::TAMPCTL: DYNPR1EN Mask */ 1216 1217 #define RTC_TAMPCTL_TAMP4EN_Pos (24) /*!< RTC_T::TAMPCTL: TAMP4EN Position */ 1218 #define RTC_TAMPCTL_TAMP4EN_Msk (0x1ul << RTC_TAMPCTL_TAMP4EN_Pos) /*!< RTC_T::TAMPCTL: TAMP4EN Mask */ 1219 1220 #define RTC_TAMPCTL_TAMP4LV_Pos (25) /*!< RTC_T::TAMPCTL: TAMP4LV Position */ 1221 #define RTC_TAMPCTL_TAMP4LV_Msk (0x1ul << RTC_TAMPCTL_TAMP4LV_Pos) /*!< RTC_T::TAMPCTL: TAMP4LV Mask */ 1222 1223 #define RTC_TAMPCTL_TAMP4DBEN_Pos (26) /*!< RTC_T::TAMPCTL: TAMP4DBEN Position */ 1224 #define RTC_TAMPCTL_TAMP4DBEN_Msk (0x1ul << RTC_TAMPCTL_TAMP4DBEN_Pos) /*!< RTC_T::TAMPCTL: TAMP4DBEN Mask */ 1225 1226 #define RTC_TAMPCTL_TAMP5EN_Pos (28) /*!< RTC_T::TAMPCTL: TAMP5EN Position */ 1227 #define RTC_TAMPCTL_TAMP5EN_Msk (0x1ul << RTC_TAMPCTL_TAMP5EN_Pos) /*!< RTC_T::TAMPCTL: TAMP5EN Mask */ 1228 1229 #define RTC_TAMPCTL_TAMP5LV_Pos (29) /*!< RTC_T::TAMPCTL: TAMP5LV Position */ 1230 #define RTC_TAMPCTL_TAMP5LV_Msk (0x1ul << RTC_TAMPCTL_TAMP5LV_Pos) /*!< RTC_T::TAMPCTL: TAMP5LV Mask */ 1231 1232 #define RTC_TAMPCTL_TAMP5DBEN_Pos (30) /*!< RTC_T::TAMPCTL: TAMP5DBEN Position */ 1233 #define RTC_TAMPCTL_TAMP5DBEN_Msk (0x1ul << RTC_TAMPCTL_TAMP5DBEN_Pos) /*!< RTC_T::TAMPCTL: TAMP5DBEN Mask */ 1234 1235 #define RTC_TAMPCTL_DYNPR2EN_Pos (31) /*!< RTC_T::TAMPCTL: DYNPR2EN Position */ 1236 #define RTC_TAMPCTL_DYNPR2EN_Msk (0x1ul << RTC_TAMPCTL_DYNPR2EN_Pos) /*!< RTC_T::TAMPCTL: DYNPR2EN Mask */ 1237 1238 #define RTC_TAMPSEED_SEED_Pos (0) /*!< RTC_T::TAMPSEED: SEED Position */ 1239 #define RTC_TAMPSEED_SEED_Msk (0xfffffffful << RTC_TAMPSEED_SEED_Pos) /*!< RTC_T::TAMPSEED: SEED Mask */ 1240 1241 #define RTC_TAMPTIME_SEC_Pos (0) /*!< RTC_T::TAMPTIME: SEC Position */ 1242 #define RTC_TAMPTIME_SEC_Msk (0xful << RTC_TAMPTIME_SEC_Pos) /*!< RTC_T::TAMPTIME: SEC Mask */ 1243 1244 #define RTC_TAMPTIME_TENSEC_Pos (4) /*!< RTC_T::TAMPTIME: TENSEC Position */ 1245 #define RTC_TAMPTIME_TENSEC_Msk (0x7ul << RTC_TAMPTIME_TENSEC_Pos) /*!< RTC_T::TAMPTIME: TENSEC Mask */ 1246 1247 #define RTC_TAMPTIME_MIN_Pos (8) /*!< RTC_T::TAMPTIME: MIN Position */ 1248 #define RTC_TAMPTIME_MIN_Msk (0xful << RTC_TAMPTIME_MIN_Pos) /*!< RTC_T::TAMPTIME: MIN Mask */ 1249 1250 #define RTC_TAMPTIME_TENMIN_Pos (12) /*!< RTC_T::TAMPTIME: TENMIN Position */ 1251 #define RTC_TAMPTIME_TENMIN_Msk (0x7ul << RTC_TAMPTIME_TENMIN_Pos) /*!< RTC_T::TAMPTIME: TENMIN Mask */ 1252 1253 #define RTC_TAMPTIME_HR_Pos (16) /*!< RTC_T::TAMPTIME: HR Position */ 1254 #define RTC_TAMPTIME_HR_Msk (0xful << RTC_TAMPTIME_HR_Pos) /*!< RTC_T::TAMPTIME: HR Mask */ 1255 1256 #define RTC_TAMPTIME_TENHR_Pos (20) /*!< RTC_T::TAMPTIME: TENHR Position */ 1257 #define RTC_TAMPTIME_TENHR_Msk (0x3ul << RTC_TAMPTIME_TENHR_Pos) /*!< RTC_T::TAMPTIME: TENHR Mask */ 1258 1259 #define RTC_TAMPCAL_DAY_Pos (0) /*!< RTC_T::TAMPCAL: DAY Position */ 1260 #define RTC_TAMPCAL_DAY_Msk (0xful << RTC_TAMPCAL_DAY_Pos) /*!< RTC_T::TAMPCAL: DAY Mask */ 1261 1262 #define RTC_TAMPCAL_TENDAY_Pos (4) /*!< RTC_T::TAMPCAL: TENDAY Position */ 1263 #define RTC_TAMPCAL_TENDAY_Msk (0x3ul << RTC_TAMPCAL_TENDAY_Pos) /*!< RTC_T::TAMPCAL: TENDAY Mask */ 1264 1265 #define RTC_TAMPCAL_MON_Pos (8) /*!< RTC_T::TAMPCAL: MON Position */ 1266 #define RTC_TAMPCAL_MON_Msk (0xful << RTC_TAMPCAL_MON_Pos) /*!< RTC_T::TAMPCAL: MON Mask */ 1267 1268 #define RTC_TAMPCAL_TENMON_Pos (12) /*!< RTC_T::TAMPCAL: TENMON Position */ 1269 #define RTC_TAMPCAL_TENMON_Msk (0x1ul << RTC_TAMPCAL_TENMON_Pos) /*!< RTC_T::TAMPCAL: TENMON Mask */ 1270 1271 #define RTC_TAMPCAL_YEAR_Pos (16) /*!< RTC_T::TAMPCAL: YEAR Position */ 1272 #define RTC_TAMPCAL_YEAR_Msk (0xful << RTC_TAMPCAL_YEAR_Pos) /*!< RTC_T::TAMPCAL: YEAR Mask */ 1273 1274 #define RTC_TAMPCAL_TENYEAR_Pos (20) /*!< RTC_T::TAMPCAL: TENYEAR Position */ 1275 #define RTC_TAMPCAL_TENYEAR_Msk (0xful << RTC_TAMPCAL_TENYEAR_Pos) /*!< RTC_T::TAMPCAL: TENYEAR Mask */ 1276 1277 #define RTC_CLKDCTL_LXTFDEN_Pos (0) /*!< RTC_T::CLKDCTL: LXTFDEN Position */ 1278 #define RTC_CLKDCTL_LXTFDEN_Msk (0x1ul << RTC_CLKDCTL_LXTFDEN_Pos) /*!< RTC_T::CLKDCTL: LXTFDEN Mask */ 1279 1280 #define RTC_CLKDCTL_LXTFSW_Pos (1) /*!< RTC_T::CLKDCTL: LXTFSW Position */ 1281 #define RTC_CLKDCTL_LXTFSW_Msk (0x1ul << RTC_CLKDCTL_LXTFSW_Pos) /*!< RTC_T::CLKDCTL: LXTFSW Mask */ 1282 1283 #define RTC_CLKDCTL_LXTSTSW_Pos (2) /*!< RTC_T::CLKDCTL: LXTSTSW Position */ 1284 #define RTC_CLKDCTL_LXTSTSW_Msk (0x1ul << RTC_CLKDCTL_LXTSTSW_Pos) /*!< RTC_T::CLKDCTL: LXTSTSW Mask */ 1285 1286 #define RTC_CLKDCTL_SWLIRCF_Pos (16) /*!< RTC_T::CLKDCTL: SWLIRCF Position */ 1287 #define RTC_CLKDCTL_SWLIRCF_Msk (0x1ul << RTC_CLKDCTL_SWLIRCF_Pos) /*!< RTC_T::CLKDCTL: SWLIRCF Mask */ 1288 1289 #define RTC_CLKDCTL_LXTSLOWF_Pos (17) /*!< RTC_T::CLKDCTL: LXTSLOWF Position */ 1290 #define RTC_CLKDCTL_LXTSLOWF_Msk (0x1ul << RTC_CLKDCTL_LXTSLOWF_Pos) /*!< RTC_T::CLKDCTL: LXTSLOWF Mask */ 1291 1292 #define RTC_CDBR_STOPBD_Pos (0) /*!< RTC_T::CDBR: STOPBD Position */ 1293 #define RTC_CDBR_STOPBD_Msk (0xfful << RTC_CDBR_STOPBD_Pos) /*!< RTC_T::CDBR: STOPBD Mask */ 1294 1295 #define RTC_CDBR_FAILBD_Pos (16) /*!< RTC_T::CDBR: FAILBD Position */ 1296 #define RTC_CDBR_FAILBD_Msk (0xfful << RTC_CDBR_FAILBD_Pos) /*!< RTC_T::CDBR: FAILBD Mask */ 1297 1298 /**@}*/ /* RTC_CONST */ 1299 /**@}*/ /* end of RTC register group */ 1300 /**@}*/ /* end of REGISTER group */ 1301 1302 #endif /* __RTC_REG_H__ */ 1303
