1 /*! 2 \file gd32l23x_rtc.h 3 \brief definitions for the RTC 4 5 \version 2021-08-04, V1.0.0, firmware for GD32L23x 6 */ 7 8 /* 9 Copyright (c) 2021, GigaDevice Semiconductor Inc. 10 11 Redistribution and use in source and binary forms, with or without modification, 12 are permitted provided that the following conditions are met: 13 14 1. Redistributions of source code must retain the above copyright notice, this 15 list of conditions and the following disclaimer. 16 2. Redistributions in binary form must reproduce the above copyright notice, 17 this list of conditions and the following disclaimer in the documentation 18 and/or other materials provided with the distribution. 19 3. Neither the name of the copyright holder nor the names of its contributors 20 may be used to endorse or promote products derived from this software without 21 specific prior written permission. 22 23 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 24 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 25 WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 26 IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 27 INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 28 NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 29 PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 30 WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 32 OF SUCH DAMAGE. 33 */ 34 35 #ifndef GD32L23X_RTC_H 36 #define GD32L23X_RTC_H 37 38 #include "gd32l23x.h" 39 40 /* RTC definitions */ 41 #define RTC RTC_BASE 42 43 /* registers definitions */ 44 #define RTC_TIME REG32((RTC) + 0x00000000U) /*!< RTC time of day register */ 45 #define RTC_DATE REG32((RTC) + 0x00000004U) /*!< RTC date register */ 46 #define RTC_CTL REG32((RTC) + 0x00000008U) /*!< RTC control register */ 47 #define RTC_STAT REG32((RTC) + 0x0000000CU) /*!< RTC status register */ 48 #define RTC_PSC REG32((RTC) + 0x00000010U) /*!< RTC time prescaler register */ 49 #define RTC_WUT REG32((RTC) + 0x00000014U) /*!< RTC wakeup timer regiser */ 50 #define RTC_ALRM0TD REG32((RTC) + 0x0000001CU) /*!< RTC alarm 0 time and date register */ 51 #define RTC_ALRM1TD REG32((RTC) + 0x00000020U) /*!< RTC alarm 1 time and date register */ 52 #define RTC_WPK REG32((RTC) + 0x00000024U) /*!< RTC write protection key register */ 53 #define RTC_SS REG32((RTC) + 0x00000028U) /*!< RTC sub second register */ 54 #define RTC_SHIFTCTL REG32((RTC) + 0x0000002CU) /*!< RTC shift function control register */ 55 #define RTC_TTS REG32((RTC) + 0x00000030U) /*!< RTC time of timestamp register */ 56 #define RTC_DTS REG32((RTC) + 0x00000034U) /*!< RTC date of timestamp register */ 57 #define RTC_SSTS REG32((RTC) + 0x00000038U) /*!< RTC sub second of timestamp register */ 58 #define RTC_HRFC REG32((RTC) + 0x0000003CU) /*!< RTC high resolution frequency compensation register */ 59 #define RTC_TAMP REG32((RTC) + 0x00000040U) /*!< RTC tamper register */ 60 #define RTC_ALRM0SS REG32((RTC) + 0x00000044U) /*!< RTC alarm 0 sub second register */ 61 #define RTC_ALRM1SS REG32((RTC) + 0x00000048U) /*!< RTC alarm 1 sub second register */ 62 #define RTC_BKP0 REG32((RTC) + 0x00000050U) /*!< RTC backup 0 register */ 63 #define RTC_BKP1 REG32((RTC) + 0x00000054U) /*!< RTC backup 1 register */ 64 #define RTC_BKP2 REG32((RTC) + 0x00000058U) /*!< RTC backup 2 register */ 65 #define RTC_BKP3 REG32((RTC) + 0x0000005CU) /*!< RTC backup 3 register */ 66 #define RTC_BKP4 REG32((RTC) + 0x00000060U) /*!< RTC backup 4 register */ 67 68 /* bits definitions */ 69 /* RTC_TIME */ 70 #define RTC_TIME_SCU BITS(0,3) /*!< second units in BCD code */ 71 #define RTC_TIME_SCT BITS(4,6) /*!< second tens in BCD code */ 72 #define RTC_TIME_MNU BITS(8,11) /*!< minute units in BCD code */ 73 #define RTC_TIME_MNT BITS(12,14) /*!< minute tens in BCD code */ 74 #define RTC_TIME_HRU BITS(16,19) /*!< hour units in BCD code */ 75 #define RTC_TIME_HRT BITS(20,21) /*!< hour tens in BCD code */ 76 #define RTC_TIME_PM BIT(22) /*!< AM/PM notation */ 77 78 /* RTC_DATE */ 79 #define RTC_DATE_DAYU BITS(0,3) /*!< date units in BCD code */ 80 #define RTC_DATE_DAYT BITS(4,5) /*!< date tens in BCD code */ 81 #define RTC_DATE_MONU BITS(8,11) /*!< month units in BCD code */ 82 #define RTC_DATE_MONT BIT(12) /*!< month tens in BCD code */ 83 #define RTC_DATE_DOW BITS(13,15) /*!< day of week units */ 84 #define RTC_DATE_YRU BITS(16,19) /*!< year units in BCD code */ 85 #define RTC_DATE_YRT BITS(20,23) /*!< year tens in BCD code */ 86 87 /* RTC_CTL */ 88 #define RTC_CTL_WTCS BITS(0,2) /*!< auto wakeup timer clock selection */ 89 #define RTC_CTL_TSEG BIT(3) /*!< valid event edge of time-stamp */ 90 #define RTC_CTL_REFEN BIT(4) /*!< reference clock detection function enable */ 91 #define RTC_CTL_BPSHAD BIT(5) /*!< shadow registers bypass control */ 92 #define RTC_CTL_CS BIT(6) /*!< display format of clock system */ 93 #define RTC_CTL_ALRM0EN BIT(8) /*!< alarm0 function enable */ 94 #define RTC_CTL_ALRM1EN BIT(9) /*!< alarm1 function enable */ 95 #define RTC_CTL_WTEN BIT(10) /*!< auto wakeup timer function enable */ 96 #define RTC_CTL_TSEN BIT(11) /*!< time-stamp function enable */ 97 #define RTC_CTL_ALRM0IE BIT(12) /*!< RTC alarm0 interrupt enable */ 98 #define RTC_CTL_ALRM1IE BIT(13) /*!< RTC alarm1 interrupt enable */ 99 #define RTC_CTL_WTIE BIT(14) /*!< auto wakeup timer interrupt enable */ 100 #define RTC_CTL_TSIE BIT(15) /*!< time-stamp interrupt enable */ 101 #define RTC_CTL_A1H BIT(16) /*!< add 1 hour(summer time change) */ 102 #define RTC_CTL_S1H BIT(17) /*!< subtract 1 hour(winter time change) */ 103 #define RTC_CTL_DSM BIT(18) /*!< daylight saving mark */ 104 #define RTC_CTL_COS BIT(19) /*!< calibration output selection */ 105 #define RTC_CTL_OPOL BIT(20) /*!< output polarity */ 106 #define RTC_CTL_OS BITS(21,22) /*!< output selection */ 107 #define RTC_CTL_COEN BIT(23) /*!< calibration output enable */ 108 #define RTC_CTL_ITSEN BIT(24) /*!< internal timestamp event enable */ 109 #define RTC_CTL_OUT2EN BIT(31) /*!< RTC_OUT pin select */ 110 111 /* RTC_STAT */ 112 #define RTC_STAT_ALRM0WF BIT(0) /*!< alarm configuration can be write flag */ 113 #define RTC_STAT_ALRM1WF BIT(1) /*!< alarm1 configuration can be write flag */ 114 #define RTC_STAT_WTWF BIT(2) /*!< wakeup timer can be write flag */ 115 #define RTC_STAT_SOPF BIT(3) /*!< shift function operation pending flag */ 116 #define RTC_STAT_YCM BIT(4) /*!< year configuration mark status flag */ 117 #define RTC_STAT_RSYNF BIT(5) /*!< register synchronization flag */ 118 #define RTC_STAT_INITF BIT(6) /*!< initialization state flag */ 119 #define RTC_STAT_INITM BIT(7) /*!< enter initialization mode */ 120 #define RTC_STAT_ALRM0F BIT(8) /*!< alarm0 occurs flag */ 121 #define RTC_STAT_ALRM1F BIT(9) /*!< alarm1 occurs flag */ 122 #define RTC_STAT_WTF BIT(10) /*!< alarm1 occurs flag */ 123 #define RTC_STAT_TSF BIT(11) /*!< time-stamp flag */ 124 #define RTC_STAT_TSOVRF BIT(12) /*!< time-stamp overflow flag */ 125 #define RTC_STAT_TP0F BIT(13) /*!< RTC tamp 0 detected flag */ 126 #define RTC_STAT_TP1F BIT(14) /*!< RTC tamp 1 detected flag */ 127 #define RTC_STAT_TP2F BIT(15) /*!< RTC tamp 2 detected flag */ 128 #define RTC_STAT_SCPF BIT(16) /*!< Smooth calibration pending flag */ 129 #define RTC_STAT_ITSF BIT(17) /*!< Internal timestamp flag */ 130 131 /* RTC_PSC */ 132 #define RTC_PSC_FACTOR_S BITS(0,14) /*!< synchronous prescaler factor */ 133 #define RTC_PSC_FACTOR_A BITS(16,22) /*!< asynchronous prescaler factor */ 134 135 /* RTC_WUT */ 136 #define RTC_WUT_WTRV BITS(0,15) /*!< auto wakeup timer reloads value */ 137 138 /* RTC_ALRMxTD */ 139 #define RTC_ALRMXTD_SCU BITS(0,3) /*!< second units in BCD code */ 140 #define RTC_ALRMXTD_SCT BITS(4,6) /*!< second tens in BCD code */ 141 #define RTC_ALRMXTD_MSKS BIT(7) /*!< alarm second mask bit */ 142 #define RTC_ALRMXTD_MNU BITS(8,11) /*!< minutes units in BCD code */ 143 #define RTC_ALRMXTD_MNT BITS(12,14) /*!< minutes tens in BCD code */ 144 #define RTC_ALRMXTD_MSKM BIT(15) /*!< alarm minutes mask bit */ 145 #define RTC_ALRMXTD_HRU BITS(16,19) /*!< hour units in BCD code */ 146 #define RTC_ALRMXTD_HRT BITS(20,21) /*!< hour tens in BCD code */ 147 #define RTC_ALRMXTD_PM BIT(22) /*!< AM/PM flag */ 148 #define RTC_ALRMXTD_MSKH BIT(23) /*!< alarm hour mask bit */ 149 #define RTC_ALRMXTD_DAYU BITS(24,27) /*!< date units or week day in BCD code */ 150 #define RTC_ALRMXTD_DAYT BITS(28,29) /*!< date tens in BCD code */ 151 #define RTC_ALRMXTD_DOWS BIT(30) /*!< day of week selection */ 152 #define RTC_ALRMXTD_MSKD BIT(31) /*!< alarm date mask bit */ 153 /* RTC_WPK */ 154 #define RTC_WPK_WPK BITS(0,7) /*!< key for write protection */ 155 156 /* RTC_SS */ 157 #define RTC_SS_SSC BITS(0,15) /*!< sub second value */ 158 159 /* RTC_SHIFTCTL */ 160 #define RTC_SHIFTCTL_SFS BITS(0,14) /*!< subtract a fraction of a second */ 161 #define RTC_SHIFTCTL_A1S BIT(31) /*!< one second add */ 162 163 /* RTC_TTS */ 164 #define RTC_TTS_SCU BITS(0,3) /*!< second units in BCD code */ 165 #define RTC_TTS_SCT BITS(4,6) /*!< second units in BCD code */ 166 #define RTC_TTS_MNU BITS(8,11) /*!< minute units in BCD code */ 167 #define RTC_TTS_MNT BITS(12,14) /*!< minute tens in BCD code */ 168 #define RTC_TTS_HRU BITS(16,19) /*!< hour units in BCD code */ 169 #define RTC_TTS_HRT BITS(20,21) /*!< hour tens in BCD code */ 170 #define RTC_TTS_PM BIT(22) /*!< AM/PM notation */ 171 172 /* RTC_DTS */ 173 #define RTC_DTS_DAYU BITS(0,3) /*!< date units in BCD code */ 174 #define RTC_DTS_DAYT BITS(4,5) /*!< date tens in BCD code */ 175 #define RTC_DTS_MONU BITS(8,11) /*!< month units in BCD code */ 176 #define RTC_DTS_MONT BIT(12) /*!< month tens in BCD code */ 177 #define RTC_DTS_DOW BITS(13,15) /*!< day of week units */ 178 179 /* RTC_SSTS */ 180 #define RTC_SSTS_SSC BITS(0,15) /*!< timestamp sub second units */ 181 182 /* RTC_HRFC */ 183 #define RTC_HRFC_CMSK BITS(0,8) /*!< calibration mask number */ 184 #define RTC_HRFC_CWND16 BIT(13) /*!< calibration window select 16 seconds */ 185 #define RTC_HRFC_CWND8 BIT(14) /*!< calibration window select 16 seconds */ 186 #define RTC_HRFC_FREQI BIT(15) /*!< increase RTC frequency by 488.5ppm */ 187 188 /* RTC_TAMP */ 189 #define RTC_TAMP_TP0EN BIT(0) /*!< tamper 0 detection enable */ 190 #define RTC_TAMP_TP0EG BIT(1) /*!< tamper 0 event trigger edge for RTC tamp 0 input */ 191 #define RTC_TAMP_TPIE BIT(2) /*!< tamper detection interrupt enable */ 192 #define RTC_TAMP_TP1EN BIT(3) /*!< tamper 1 detection enable */ 193 #define RTC_TAMP_TP1EG BIT(4) /*!< tamper 1 event trigger edge for RTC tamp 1 input */ 194 #define RTC_TAMP_TP2EN BIT(5) /*!< tamper 2 detection enable */ 195 #define RTC_TAMP_TP2EG BIT(6) /*!< tamper 2 event trigger edge for RTC tamp 2 input */ 196 #define RTC_TAMP_TPTS BIT(7) /*!< make tamper function used for timestamp function */ 197 #define RTC_TAMP_FREQ BITS(8,10) /*!< sample frequency of tamper event detection */ 198 #define RTC_TAMP_FLT BITS(11,12) /*!< RTC tamp x filter count setting */ 199 #define RTC_TAMP_PRCH BITS(13,14) /*!< precharge duration time of RTC tamp x */ 200 #define RTC_TAMP_DISPU BIT(15) /*!< RTC tamp x pull up disable bit */ 201 #define RTC_TAMP_ALRMOUTTYPE BIT(18) /*!< RTC_ALARM output Type */ 202 #define RTC_TAMP_TP0NOERASE BIT(19) /*!< Tamper 0 event does not erase the backup registers */ 203 #define RTC_TAMP_TP1NOERASE BIT(20) /*!< Tamper 1 event does not erase the backup registers */ 204 #define RTC_TAMP_TP2NOERASE BIT(21) /*!< Tamper 2 event does not erase the backup registers */ 205 #define RTC_TAMP_TP0MASK BIT(23) /*!< Tamper 0 mask flag */ 206 #define RTC_TAMP_TP1MASK BIT(24) /*!< Tamper 1 mask flag */ 207 #define RTC_TAMP_TP2MASK BIT(25) /*!< Tamper 2 mask flag */ 208 #define RTC_TAMP_TP0IE BIT(27) /*!< Tamper 0 interrupt enable */ 209 #define RTC_TAMP_TP1IE BIT(28) /*!< Tamper 1 interrupt enable */ 210 #define RTC_TAMP_TP2IE BIT(29) /*!< Tamper 2 interrupt enable */ 211 #define RTC_TAMP_TPxIE BITS(27,29) /*!< All Tamper interrupt enable */ 212 213 /* RTC_ALRM0SS */ 214 #define RTC_ALRM0SS_SSC BITS(0,14) /*!< alarm0 sub second value */ 215 #define RTC_ALRM0SS_MASKSSC BITS(24,27) /*!< mask control bit of SS */ 216 217 /* RTC_ALRM1SS */ 218 #define RTC_ALRM1SS_SSC BITS(0,14) /*!< alarm1 sub second value */ 219 #define RTC_ALRM1SS_MASKSSC BITS(24,27) /*!< mask control bit of SS */ 220 221 /* RTC_BKP0 */ 222 #define RTC_BKP0_DATA BITS(0,31) /*!< backup domain registers */ 223 224 /* RTC_BKP1 */ 225 #define RTC_BKP1_DATA BITS(0,31) /*!< backup domain registers */ 226 227 /* RTC_BKP2 */ 228 #define RTC_BKP2_DATA BITS(0,31) /*!< backup domain registers */ 229 230 /* RTC_BKP3 */ 231 #define RTC_BKP3_DATA BITS(0,31) /*!< backup domain registers */ 232 233 /* RTC_BKP4 */ 234 #define RTC_BKP4_DATA BITS(0,31) /*!< backup domain registers */ 235 236 /* constants definitions */ 237 /* structure for initialization of the RTC */ 238 typedef struct { 239 uint8_t year; /*!< RTC year value: 0x0 - 0x99(BCD format) */ 240 uint8_t month; /*!< RTC month value */ 241 uint8_t date; /*!< RTC date value: 0x1 - 0x31(BCD format) */ 242 uint8_t day_of_week; /*!< RTC weekday value */ 243 uint8_t hour; /*!< RTC hour value */ 244 uint8_t minute; /*!< RTC minute value: 0x0 - 0x59(BCD format) */ 245 uint8_t second; /*!< RTC second value: 0x0 - 0x59(BCD format) */ 246 uint16_t factor_asyn; /*!< RTC asynchronous prescaler value: 0x0 - 0x7F */ 247 uint16_t factor_syn; /*!< RTC synchronous prescaler value: 0x0 - 0x7FFF */ 248 uint32_t am_pm; /*!< RTC AM/PM value */ 249 uint32_t display_format; /*!< RTC time notation */ 250 } rtc_parameter_struct; 251 252 /* structure for RTC alarm configuration */ 253 typedef struct { 254 uint32_t alarm_mask; /*!< RTC alarm mask */ 255 uint32_t weekday_or_date; /*!< specify RTC alarm is on date or weekday */ 256 uint8_t alarm_day; /*!< RTC alarm date or weekday value*/ 257 uint8_t alarm_hour; /*!< RTC alarm hour value */ 258 uint8_t alarm_minute; /*!< RTC alarm minute value: 0x0 - 0x59(BCD format) */ 259 uint8_t alarm_second; /*!< RTC alarm second value: 0x0 - 0x59(BCD format) */ 260 uint32_t am_pm; /*!< RTC alarm AM/PM value */ 261 } rtc_alarm_struct; 262 263 /* structure for RTC time-stamp configuration */ 264 typedef struct { 265 uint8_t timestamp_month; /*!< RTC time-stamp month value */ 266 uint8_t timestamp_date; /*!< RTC time-stamp date value: 0x1 - 0x31(BCD format) */ 267 uint8_t timestamp_day; /*!< RTC time-stamp weekday value */ 268 uint8_t timestamp_hour; /*!< RTC time-stamp hour value */ 269 uint8_t timestamp_minute; /*!< RTC time-stamp minute value: 0x0 - 0x59(BCD format) */ 270 uint8_t timestamp_second; /*!< RTC time-stamp second value: 0x0 - 0x59(BCD format) */ 271 uint32_t am_pm; /*!< RTC time-stamp AM/PM value */ 272 } rtc_timestamp_struct; 273 274 /* structure for RTC tamper configuration */ 275 typedef struct { 276 uint32_t tamper_source; /*!< RTC tamper source */ 277 uint32_t tamper_trigger; /*!< RTC tamper trigger */ 278 uint32_t tamper_filter; /*!< RTC tamper consecutive samples needed during a voltage level detection */ 279 uint32_t tamper_sample_frequency; /*!< RTC tamper sampling frequency during a voltage level detection */ 280 ControlStatus tamper_precharge_enable; /*!< RTC tamper precharge feature during a voltage level detection */ 281 uint32_t tamper_precharge_time; /*!< RTC tamper precharge duration if precharge feature is enabled */ 282 ControlStatus tamper_with_timestamp; /*!< RTC tamper time-stamp feature */ 283 } rtc_tamper_struct; 284 285 /* time register value */ 286 #define TIME_SC(regval) (BITS(0,6) & ((uint32_t)(regval) << 0)) /*!< write value to RTC_TIME_SC bit field */ 287 #define GET_TIME_SC(regval) GET_BITS((regval),0,6) /*!< get value of RTC_TIME_SC bit field */ 288 289 #define TIME_MN(regval) (BITS(8,14) & ((uint32_t)(regval) << 8)) /*!< write value to RTC_TIME_MN bit field */ 290 #define GET_TIME_MN(regval) GET_BITS((regval),8,14) /*!< get value of RTC_TIME_MN bit field */ 291 292 #define TIME_HR(regval) (BITS(16,21) & ((uint32_t)(regval) << 16)) /*!< write value to RTC_TIME_HR bit field */ 293 #define GET_TIME_HR(regval) GET_BITS((regval),16,21) /*!< get value of RTC_TIME_HR bit field */ 294 295 #define RTC_AM ((uint32_t)0x00000000U) /*!< AM format */ 296 #define RTC_PM RTC_TIME_PM /*!< PM format */ 297 298 /* date register value */ 299 #define DATE_DAY(regval) (BITS(0,5) & ((uint32_t)(regval) << 0)) /*!< write value to RTC_DATE_DAY bit field */ 300 #define GET_DATE_DAY(regval) GET_BITS((regval),0,5) /*!< get value of RTC_DATE_DAY bit field */ 301 302 #define DATE_MON(regval) (BITS(8,12) & ((uint32_t)(regval) << 8)) /*!< write value to RTC_DATE_MON bit field */ 303 #define GET_DATE_MON(regval) GET_BITS((regval),8,12) /*!< get value of RTC_DATE_MON bit field */ 304 #define RTC_JAN ((uint8_t)0x01U) /*!< Janurary */ 305 #define RTC_FEB ((uint8_t)0x02U) /*!< February */ 306 #define RTC_MAR ((uint8_t)0x03U) /*!< March */ 307 #define RTC_APR ((uint8_t)0x04U) /*!< April */ 308 #define RTC_MAY ((uint8_t)0x05U) /*!< May */ 309 #define RTC_JUN ((uint8_t)0x06U) /*!< June */ 310 #define RTC_JUL ((uint8_t)0x07U) /*!< July */ 311 #define RTC_AUG ((uint8_t)0x08U) /*!< August */ 312 #define RTC_SEP ((uint8_t)0x09U) /*!< September */ 313 #define RTC_OCT ((uint8_t)0x10U) /*!< October */ 314 #define RTC_NOV ((uint8_t)0x11U) /*!< November */ 315 #define RTC_DEC ((uint8_t)0x12U) /*!< December */ 316 317 #define DATE_DOW(regval) (BITS(13,15) & ((uint32_t)(regval) << 13)) /*!< write value to RTC_DATE_DOW bit field */ 318 #define GET_DATE_DOW(regval) GET_BITS((uint32_t)(regval),13,15) /*!< get value of RTC_DATE_DOW bit field */ 319 #define RTC_MONDAY ((uint8_t)0x01) /*!< monday */ 320 #define RTC_TUESDAY ((uint8_t)0x02) /*!< tuesday */ 321 #define RTC_WEDNESDAY ((uint8_t)0x03) /*!< wednesday */ 322 #define RTC_THURSDAY ((uint8_t)0x04) /*!< thursday */ 323 #define RTC_FRIDAY ((uint8_t)0x05) /*!< friday */ 324 #define RTC_SATURDAY ((uint8_t)0x06) /*!< saturday */ 325 #define RTC_SUNDAY ((uint8_t)0x07) /*!< sunday */ 326 327 #define DATE_YR(regval) (BITS(16,23) & ((uint32_t)(regval) << 16)) /*!< write value to RTC_DATE_YR bit field */ 328 #define GET_DATE_YR(regval) GET_BITS((regval),16,23) /*!< get value of RTC_DATE_YR bit field */ 329 330 #define RTC_OUT_PC13 ((uint32_t)0x00000000U) /*!< RTC_OUT is connected to PC13 */ 331 #define RTC_OUT_PB2 RTC_CTL_OUT2EN /*!< RTC_OUT is connected to PB2 */ 332 333 #define CTL_OS(regval) (BITS(21,22) & ((uint32_t)(regval) << 21)) /*!< write value to RTC_CTL_OS bit field */ 334 #define RTC_OS_DISABLE CTL_OS(0) /*!< disable output RTC_ALARM */ 335 #define RTC_OS_ALARM0 CTL_OS(1) /*!< enable alarm0 flag output */ 336 #define RTC_OS_ALARM1 CTL_OS(2) /*!< enable alarm1 flag output */ 337 #define RTC_OS_WAKEUP CTL_OS(3) /*!< enable wakeup flag output */ 338 339 #define RTC_ITSEN_DISABLE ((uint32_t)0x00000000U) /*!< disable output RTC_ALARM */ 340 #define RTC_ITSEN_ENABLE RTC_CTL_ITSEN /*!< enable alarm0 flag output */ 341 342 #define RTC_CALIBRATION_512HZ RTC_CTL_COEN /*!< calibration output of 512Hz is enable */ 343 #define RTC_CALIBRATION_1HZ (RTC_CTL_COEN | RTC_CTL_COS) /*!< calibration output of 1Hz is enable */ 344 #define RTC_ALARM0_HIGH RTC_OS_ALARM0 /*!< enable alarm0 flag output with high level */ 345 #define RTC_ALARM0_LOW (RTC_OS_ALARM0 | RTC_CTL_OPOL) /*!< enable alarm0 flag output with low level*/ 346 #define RTC_ALARM1_HIGH RTC_OS_ALARM1 /*!< enable alarm1 flag output with high level */ 347 #define RTC_ALARM1_LOW (RTC_OS_ALARM1 | RTC_CTL_OPOL) /*!< enable alarm1 flag output with low level*/ 348 #define RTC_WAKEUP_HIGH RTC_OS_WAKEUP /*!< enable wakeup flag output with high level */ 349 #define RTC_WAKEUP_LOW (RTC_OS_WAKEUP | RTC_CTL_OPOL) /*!< enable wakeup flag output with low level*/ 350 351 #define RTC_24HOUR ((uint32_t)0x00000000U) /*!< 24-hour format */ 352 #define RTC_12HOUR RTC_CTL_CS /*!< 12-hour format */ 353 354 #define RTC_TIMESTAMP_RISING_EDGE ((uint32_t)0x00000000U) /*!< rising edge is valid event edge for time-stamp event */ 355 #define RTC_TIMESTAMP_FALLING_EDGE RTC_CTL_TSEG /*!< falling edge is valid event edge for time-stamp event */ 356 357 #define CTL_WTCS(regval) (BITS(0,2) & ((regval)<< 0)) 358 #define WAKEUP_RTCCK_DIV16 CTL_WTCS(0) /*!< wakeup timer clock is RTC clock divided by 16 */ 359 #define WAKEUP_RTCCK_DIV8 CTL_WTCS(1) /*!< wakeup timer clock is RTC clock divided by 8 */ 360 #define WAKEUP_RTCCK_DIV4 CTL_WTCS(2) /*!< wakeup timer clock is RTC clock divided by 4 */ 361 #define WAKEUP_RTCCK_DIV2 CTL_WTCS(3) /*!< wakeup timer clock is RTC clock divided by 2 */ 362 #define WAKEUP_CKSPRE CTL_WTCS(4) /*!< wakeup timer clock is ckapre */ 363 #define WAKEUP_CKSPRE_2EXP16 CTL_WTCS(6) /*!< wakeup timer clock is ckapre and wakeup timer add 2exp16 */ 364 365 /* psc register value */ 366 #define PSC_FACTOR_S(regval) (BITS(0,14) & ((uint32_t)(regval) << 0)) /*!< write value to RTC_PSC_FACTOR_S bit field */ 367 #define GET_PSC_FACTOR_S(regval) GET_BITS((regval),0,14) /*!< get value of RTC_PSC_FACTOR_S bit field */ 368 369 #define PSC_FACTOR_A(regval) (BITS(16,22) & ((uint32_t)(regval) << 16)) /*!< write value to RTC_PSC_FACTOR_A bit field */ 370 #define GET_PSC_FACTOR_A(regval) GET_BITS((regval),16,22) /*!< get value of RTC_PSC_FACTOR_A bit field */ 371 372 /* alrmtd register value */ 373 #define ALRMTD_SC(regval) (BITS(0,6) & ((uint32_t)(regval)<< 0)) /*!< write value to RTC_ALRMTD_SC bit field */ 374 #define GET_ALRMTD_SC(regval) GET_BITS((regval),0,6) /*!< get value of RTC_ALRMTD_SC bit field */ 375 376 #define ALRMTD_MN(regval) (BITS(8,14) & ((uint32_t)(regval) << 8)) /*!< write value to RTC_ALRMTD_MN bit field */ 377 #define GET_ALRMTD_MN(regval) GET_BITS((regval),8,14) /*!< get value of RTC_ALRMTD_MN bit field */ 378 379 #define ALRMTD_HR(regval) (BITS(16,21) & ((uint32_t)(regval) << 16)) /*!< write value to RTC_ALRMTD_HR bit field */ 380 #define GET_ALRMTD_HR(regval) GET_BITS((regval),16,21) /*!< get value of RTC_ALRMTD_HR bit field */ 381 382 #define ALRMTD_DAY(regval) (BITS(24,29) & ((uint32_t)(regval) << 24)) /*!< write value to RTC_ALRMTD_DAY bit field */ 383 #define GET_ALRMTD_DAY(regval) GET_BITS((regval),24,29) /*!< get value of RTC_ALRMTD_DAY bit field */ 384 385 #define RTC_ALARM_NONE_MASK ((uint32_t)0x00000000U) /*!< alarm none mask */ 386 #define RTC_ALARM_DATE_MASK RTC_ALRMXTD_MSKD /*!< alarm date mask */ 387 #define RTC_ALARM_HOUR_MASK RTC_ALRMXTD_MSKH /*!< alarm hour mask */ 388 #define RTC_ALARM_MINUTE_MASK RTC_ALRMXTD_MSKM /*!< alarm minute mask */ 389 #define RTC_ALARM_SECOND_MASK RTC_ALRMXTD_MSKS /*!< alarm second mask */ 390 #define RTC_ALARM_ALL_MASK (RTC_ALRMXTD_MSKD|RTC_ALRMXTD_MSKH|RTC_ALRMXTD_MSKM|RTC_ALRMXTD_MSKS) /*!< alarm all mask */ 391 392 #define RTC_ALARM_DATE_SELECTED ((uint32_t)0x00000000U) /*!< alarm date format selected */ 393 #define RTC_ALARM_WEEKDAY_SELECTED RTC_ALRMXTD_DOWS /*!< alarm weekday format selected */ 394 395 /* wpk register value */ 396 #define WPK_WPK(regval) (BITS(0,7) & ((uint32_t)(regval) << 0)) /*!< write value to RTC_WPK_WPK bit field */ 397 398 /* ss register value */ 399 #define SS_SSC(regval) (BITS(0,15) & ((uint32_t)(regval) << 0)) /*!< write value to RTC_SS_SSC bit field */ 400 401 /* shiftctl register value */ 402 #define SHIFTCTL_SFS(regval) (BITS(0,14) & ((uint32_t)(regval) << 0)) /*!< write value to RTC_SHIFTCTL_SFS bit field */ 403 404 #define RTC_SHIFT_ADD1S_RESET ((uint32_t)0x00000000U) /*!< not add 1 second */ 405 #define RTC_SHIFT_ADD1S_SET RTC_SHIFTCTL_A1S /*!< add one second to the clock */ 406 407 /* tts register value */ 408 #define TTS_SC(regval) (BITS(0,6) & ((uint32_t)(regval) << 0)) /*!< write value to RTC_TTS_SC bit field */ 409 #define GET_TTS_SC(regval) GET_BITS((regval),0,6) /*!< get value of RTC_TTS_SC bit field */ 410 411 #define TTS_MN(regval) (BITS(8,14) & ((uint32_t)(regval) << 8)) /*!< write value to RTC_TTS_MN bit field */ 412 #define GET_TTS_MN(regval) GET_BITS((regval),8,14) /*!< get value of RTC_TTS_MN bit field */ 413 414 #define TTS_HR(regval) (BITS(16,21) & ((uint32_t)(regval) << 16)) /*!< write value to RTC_TTS_HR bit field */ 415 #define GET_TTS_HR(regval) GET_BITS((regval),16,21) /*!< get value of RTC_TTS_HR bit field */ 416 417 /* dts register value */ 418 #define DTS_DAY(regval) (BITS(0,5) & ((uint32_t)(regval) << 0)) /*!< write value to RTC_DTS_DAY bit field */ 419 #define GET_DTS_DAY(regval) GET_BITS((regval),0,5) /*!< get value of RTC_DTS_DAY bit field */ 420 421 #define DTS_MON(regval) (BITS(8,12) & ((uint32_t)(regval) << 8)) /*!< write value to RTC_DTS_MON bit field */ 422 #define GET_DTS_MON(regval) GET_BITS((regval),8,12) /*!< get value of RTC_DTS_MON bit field */ 423 424 #define DTS_DOW(regval) (BITS(13,15) & ((uint32_t)(regval) << 13)) /*!< write value to RTC_DTS_DOW bit field */ 425 #define GET_DTS_DOW(regval) GET_BITS((regval),13,15) /*!< get value of RTC_DTS_DOW bit field */ 426 427 /* ssts register value */ 428 #define SSTS_SSC(regval) (BITS(0,15) & ((uint32_t)(regval) << 0)) /*!< write value to RTC_SSTS_SSC bit field */ 429 430 /* hrfc register value */ 431 #define HRFC_CMSK(regval) (BITS(0,8) & ((uint32_t)(regval) << 0)) /*!< write value to RTC_HRFC_CMSK bit field */ 432 433 #define RTC_CALIBRATION_WINDOW_32S ((uint32_t)0x00000000U) /*!< 2exp20 RTCCLK cycles, 32s if RTCCLK = 32768 Hz */ 434 #define RTC_CALIBRATION_WINDOW_16S RTC_HRFC_CWND16 /*!< 2exp19 RTCCLK cycles, 16s if RTCCLK = 32768 Hz */ 435 #define RTC_CALIBRATION_WINDOW_8S RTC_HRFC_CWND8 /*!< 2exp18 RTCCLK cycles, 8s if RTCCLK = 32768 Hz */ 436 437 #define RTC_CALIBRATION_PLUS_SET RTC_HRFC_FREQI /*!< increase RTC frequency by 488.5ppm */ 438 #define RTC_CALIBRATION_PLUS_RESET ((uint32_t)0x00000000U) /*!< no effect */ 439 440 /* tamp register value */ 441 #define TAMP_TAMPXNOERASE(regval) (BITS(19,21) & ((uint32_t)(regval) << 19)) /*!< write value to RTC_TAMP_TAMPXNOERASE bits field */ 442 #define RTC_TAMPXNOERASE_NONE TAMP_TAMPXNOER(0) /*!< both tamper 0~3 event will trigger RTC_BKP registers reset */ 443 #define RTC_TAMPXNOERASE_TP0 TAMP_TAMPXNOER(1) /*!< tamper0 event will not trigger RTC_BKP registers reset */ 444 #define RTC_TAMPXNOERASE_TP1 TAMP_TAMPXNOER(2) /*!< tamper1 event will not trigger RTC_BKP registers reset */ 445 #define RTC_TAMPXNOERASE_TP2 TAMP_TAMPXNOER(4) /*!< tamper2 event will not trigger RTC_BKP registers reset */ 446 #define RTC_TAMPXNOERASE_TP0_TP1 TAMP_TAMPXNOER(3) /*!< Neither tamper0 nor tamper1 event will trigger RTC_BKP registers reset */ 447 #define RTC_TAMPXNOERASE_TP_ALL TAMP_TAMPXNOER(7) /*!< tamper 0~3 event all will not trigger RTC_BKP registers reset */ 448 449 450 /* tamp register value */ 451 #define TAMP_TAMPMASK(regval) (BITS(23,25) & ((uint32_t)(regval) << 23)) /*!< write value to RTC_TAMP_TAMPXMASK bits field */ 452 #define RTC_TAMPMASK_NONE TAMP_TAMPMASK(0) /*!< both tamper 0~3 would not be masked */ 453 #define RTC_TAMPMASK_TP0 TAMP_TAMPMASK(1) /*!< tamper0 will be masked */ 454 #define RTC_TAMPMASK_TP1 TAMP_TAMPMASK(2) /*!< tamper1 will be masked */ 455 #define RTC_TAMPMASK_TP2 TAMP_TAMPMASK(4) /*!< tamper2 will be masked */ 456 457 #define TAMP_PRCH(regval) (BITS(13,14) & ((uint32_t)(regval) << 13)) /*!< write value to RTC_TAMP_PRCH bit field */ 458 #define RTC_PRCH_1C TAMP_PRCH(0) /*!< 1 RTC clock prechagre time before each sampling */ 459 #define RTC_PRCH_2C TAMP_PRCH(1) /*!< 2 RTC clock prechagre time before each sampling */ 460 #define RTC_PRCH_4C TAMP_PRCH(2) /*!< 4 RTC clock prechagre time before each sampling */ 461 #define RTC_PRCH_8C TAMP_PRCH(3) /*!< 8 RTC clock prechagre time before each sampling */ 462 463 #define TAMP_FLT(regval) (BITS(11,12) & ((uint32_t)(regval) << 11)) /*!< write value to RTC_TAMP_FLT bit field */ 464 #define RTC_FLT_EDGE TAMP_FLT(0) /*!< detecting tamper event using edge mode. precharge duration is disabled automatically */ 465 #define RTC_FLT_2S TAMP_FLT(1) /*!< detecting tamper event using level mode.2 consecutive valid level samples will make a effective tamper event */ 466 #define RTC_FLT_4S TAMP_FLT(2) /*!< detecting tamper event using level mode.4 consecutive valid level samples will make an effective tamper event */ 467 #define RTC_FLT_8S TAMP_FLT(3) /*!< detecting tamper event using level mode.8 consecutive valid level samples will make a effective tamper event */ 468 469 #define TAMP_FREQ(regval) (BITS(8,10) & ((uint32_t)(regval) << 8)) /*!< write value to RTC_TAMP_FREQ bit field */ 470 #define RTC_FREQ_DIV32768 TAMP_FREQ(0) /*!< sample once every 32768 RTCCLK(1Hz if RTCCLK=32.768KHz) */ 471 #define RTC_FREQ_DIV16384 TAMP_FREQ(1) /*!< sample once every 16384 RTCCLK(2Hz if RTCCLK=32.768KHz) */ 472 #define RTC_FREQ_DIV8192 TAMP_FREQ(2) /*!< sample once every 8192 RTCCLK(4Hz if RTCCLK=32.768KHz) */ 473 #define RTC_FREQ_DIV4096 TAMP_FREQ(3) /*!< sample once every 4096 RTCCLK(8Hz if RTCCLK=32.768KHz) */ 474 #define RTC_FREQ_DIV2048 TAMP_FREQ(4) /*!< sample once every 2048 RTCCLK(16Hz if RTCCLK=32.768KHz) */ 475 #define RTC_FREQ_DIV1024 TAMP_FREQ(5) /*!< sample once every 1024 RTCCLK(32Hz if RTCCLK=32.768KHz) */ 476 #define RTC_FREQ_DIV512 TAMP_FREQ(6) /*!< sample once every 512 RTCCLK(64Hz if RTCCLK=32.768KHz) */ 477 #define RTC_FREQ_DIV256 TAMP_FREQ(7) /*!< sample once every 256 RTCCLK(128Hz if RTCCLK=32.768KHz) */ 478 479 #define RTC_TAMPER0 RTC_TAMP_TP0EN /*!< tamper 0 detection enable */ 480 #define RTC_TAMPER1 RTC_TAMP_TP1EN /*!< tamper 1 detection enable */ 481 #define RTC_TAMPER2 RTC_TAMP_TP2EN /*!< tamper 2 detection enable */ 482 483 #define RTC_TAMPER_TRIGGER_EDGE_RISING ((uint32_t)0x00000000U) /*!< tamper detection is in rising edge mode */ 484 #define RTC_TAMPER_TRIGGER_EDGE_FALLING RTC_TAMP_TP0EG /*!< tamper detection is in falling edge mode */ 485 #define RTC_TAMPER_TRIGGER_LEVEL_LOW ((uint32_t)0x00000000U) /*!< tamper detection is in low level mode */ 486 #define RTC_TAMPER_TRIGGER_LEVEL_HIGH RTC_TAMP_TP0EG /*!< tamper detection is in high level mode */ 487 488 #define RTC_TAMPER_TRIGGER_POS ((uint32_t)0x00000001U) /* shift position of trigger relative to source */ 489 490 #define RTC_ALARM_OUTPUT_OD ((uint32_t)0x00000000U) /*!< RTC alarm output open-drain mode */ 491 #define RTC_ALARM_OUTPUT_PP RTC_TAMP_ALRMOUTTYPE /*!< RTC alarm output push-pull mode */ 492 493 /* alrm0ss register value */ 494 #define ALRMXSS_SSC(regval) (BITS(0,14) & ((uint32_t)(regval)<< 0)) /*!< write value to RTC_ALRMXSS_SSC bit field */ 495 496 #define ALRMXSS_MSKSSC(regval) (BITS(24,27) & ((uint32_t)(regval) << 24)) /*!< write value to RTC_ALRMXSS_MSKSSC bit field */ 497 #define RTC_MSKSSC_0_14 ALRMXSS_MSKSSC(0) /*!< mask alarm subsecond configuration */ 498 #define RTC_MSKSSC_1_14 ALRMXSS_MSKSSC(1) /*!< mask RTC_ALRMXSS_SSC[14:1], and RTC_ALRMXSS_SSC[0] is to be compared */ 499 #define RTC_MSKSSC_2_14 ALRMXSS_MSKSSC(2) /*!< mask RTC_ALRMXSS_SSC[14:2], and RTC_ALRMXSS_SSC[1:0] is to be compared */ 500 #define RTC_MSKSSC_3_14 ALRMXSS_MSKSSC(3) /*!< mask RTC_ALRMXSS_SSC[14:3], and RTC_ALRMXSS_SSC[2:0] is to be compared */ 501 #define RTC_MSKSSC_4_14 ALRMXSS_MSKSSC(4) /*!< mask RTC_ALRMXSS_SSC[14:4]], and RTC_ALRMXSS_SSC[3:0] is to be compared */ 502 #define RTC_MSKSSC_5_14 ALRMXSS_MSKSSC(5) /*!< mask RTC_ALRMXSS_SSC[14:5], and RTC_ALRMXSS_SSC[4:0] is to be compared */ 503 #define RTC_MSKSSC_6_14 ALRMXSS_MSKSSC(6) /*!< mask RTC_ALRMXSS_SSC[14:6], and RTC_ALRMXSS_SSC[5:0] is to be compared */ 504 #define RTC_MSKSSC_7_14 ALRMXSS_MSKSSC(7) /*!< mask RTC_ALRMXSS_SSC[14:7], and RTC_ALRMXSS_SSC[6:0] is to be compared */ 505 #define RTC_MSKSSC_8_14 ALRMXSS_MSKSSC(8) /*!< mask RTC_ALRMXSS_SSC[14:8], and RTC_ALRMXSS_SSC[7:0] is to be compared */ 506 #define RTC_MSKSSC_9_14 ALRMXSS_MSKSSC(9) /*!< mask RTC_ALRMXSS_SSC[14:9], and RTC_ALRMXSS_SSC[8:0] is to be compared */ 507 #define RTC_MSKSSC_10_14 ALRMXSS_MSKSSC(10) /*!< mask RTC_ALRMXSS_SSC[14:10], and RTC_ALRMXSS_SSC[9:0] is to be compared */ 508 #define RTC_MSKSSC_11_14 ALRMXSS_MSKSSC(11) /*!< mask RTC_ALRMXSS_SSC[14:11], and RTC_ALRMXSS_SSC[10:0] is to be compared */ 509 #define RTC_MSKSSC_12_14 ALRMXSS_MSKSSC(12) /*!< mask RTC_ALRMXSS_SSC[14:12], and RTC_ALRMXSS_SSC[11:0] is to be compared */ 510 #define RTC_MSKSSC_13_14 ALRMXSS_MSKSSC(13) /*!< mask RTC_ALRMXSS_SSC[14:13], and RTC_ALRMXSS_SSC[12:0] is to be compared */ 511 #define RTC_MSKSSC_14 ALRMXSS_MSKSSC(14) /*!< mask RTC_ALRMXSS_SSC[14], and RTC_ALRMXSS_SSC[13:0] is to be compared */ 512 #define RTC_MSKSSC_NONE ALRMXSS_MSKSSC(15) /*!< mask none, and RTC_ALRMXSS_SSC[14:0] is to be compared */ 513 514 /* RTC interrupt source */ 515 #define RTC_INT_TIMESTAMP RTC_CTL_TSIE /*!< time-stamp interrupt enable */ 516 #define RTC_INT_ALARM0 RTC_CTL_ALRM0IE /*!< RTC alarm0 interrupt enable */ 517 #define RTC_INT_ALARM1 RTC_CTL_ALRM1IE /*!< RTC alarm1 interrupt enable */ 518 #define RTC_INT_TAMP0 RTC_TAMP_TP0IE /*!< tamper detection interrupt enable */ 519 #define RTC_INT_TAMP1 RTC_TAMP_TP1IE /*!< tamper detection interrupt enable */ 520 #define RTC_INT_TAMP2 RTC_TAMP_TP2IE /*!< tamper detection interrupt enable */ 521 #define RTC_INT_TAMP_ALL RTC_TAMP_TPxIE /*!< tamper detection interrupt enable */ 522 #define RTC_INT_WAKEUP RTC_CTL_WTIE /*!< RTC wakeup timer interrupt enable */ 523 524 /* write protect key */ 525 #define RTC_UNLOCK_KEY1 ((uint8_t)0xCAU) /*!< RTC unlock key1 */ 526 #define RTC_UNLOCK_KEY2 ((uint8_t)0x53U) /*!< RTC unlock key2 */ 527 #define RTC_LOCK_KEY ((uint8_t)0xFFU) /*!< RTC lock key */ 528 529 /* registers reset value */ 530 #define RTC_REGISTER_RESET ((uint32_t)0x00000000U) /*!< RTC common register reset value */ 531 #define RTC_DATE_RESET ((uint32_t)0x00002101U) /*!< RTC_DATE register reset value */ 532 #define RTC_STAT_RESET ((uint32_t)0x00000007U) /*!< RTC_STAT register reset value */ 533 #define RTC_PSC_RESET ((uint32_t)0x007F00FFU) /*!< RTC_PSC register reset value */ 534 #define RTC_WUT_RESET ((uint32_t)0x0000FFFFU) /*!< RTC_WUT register reset value */ 535 536 /* RTC alarm */ 537 #define RTC_ALARM0 ((uint8_t)0x01U) /*!< RTC alarm 0 */ 538 #define RTC_ALARM1 ((uint8_t)0x02U) /*!< RTC alarm 1 */ 539 540 /* RTC flag */ 541 #define RTC_FLAG_ALARM0W RTC_STAT_ALRM0WF /*!< alarm0 configuration can be write flag */ 542 #define RTC_FLAG_ALARM1W RTC_STAT_ALRM1WF /*!< alarm1 configuration can be write flag */ 543 #define RTC_FLAG_WTW RTC_STAT_WTWF /*!< wakeup timer can be write flag */ 544 #define RTC_FLAG_SOP RTC_STAT_SOPF /*!< shift function operation pending flag */ 545 #define RTC_FLAG_YCM RTC_STAT_YCM /*!< year parameter configured event flag */ 546 #define RTC_FLAG_RSYN RTC_STAT_RSYNF /*!< registers synchronized flag */ 547 #define RTC_FLAG_INIT RTC_STAT_INITF /*!< init mode event flag */ 548 #define RTC_FLAG_SCP RTC_STAT_SOPF /*!< smooth calibration pending flag */ 549 #define RTC_FLAG_ALARM0 RTC_STAT_ALRM0F /*!< alarm event flag */ 550 #define RTC_FLAG_ALARM1 RTC_STAT_ALRM1F /*!< alarm1 occurs flag */ 551 #define RTC_FLAG_WT RTC_STAT_WTF /*!< wakeup timer occurs flag */ 552 #define RTC_FLAG_TS RTC_STAT_TSF /*!< time-stamp flag */ 553 #define RTC_FLAG_TSOVR RTC_STAT_TSOVRF /*!< time-stamp overflow flag */ 554 #define RTC_FLAG_TP0 RTC_STAT_TP0F /*!< RTC tamper 0 detected flag */ 555 #define RTC_FLAG_TP1 RTC_STAT_TP1F /*!< RTC tamper 1 detected flag */ 556 #define RTC_FLAG_TP2 RTC_STAT_TP2F /*!< RTC tamper 2 detected flag */ 557 558 /* function declarations */ 559 /* initialization and configuration functions */ 560 /* reset most of the RTC registers */ 561 ErrStatus rtc_deinit(void); 562 /* initialize RTC registers */ 563 ErrStatus rtc_init(rtc_parameter_struct *rtc_initpara_struct); 564 /* enter RTC init mode */ 565 ErrStatus rtc_init_mode_enter(void); 566 /* exit RTC init mode */ 567 void rtc_init_mode_exit(void); 568 /* wait until RTC_TIME and RTC_DATE registers are synchronized with APB clock, and the shadow registers are updated */ 569 ErrStatus rtc_register_sync_wait(void); 570 571 /* get current time and date */ 572 void rtc_current_time_get(rtc_parameter_struct *rtc_initpara_struct); 573 /* get current subsecond value */ 574 uint32_t rtc_subsecond_get(void); 575 576 /* alarm configuration functions */ 577 /* configure RTC alarm */ 578 void rtc_alarm_config(uint8_t rtc_alarm, rtc_alarm_struct *rtc_alarm_time); 579 /* configure subsecond of RTC alarm */ 580 void rtc_alarm_subsecond_config(uint8_t rtc_alarm, uint32_t mask_subsecond, uint32_t subsecond); 581 /* get RTC alarm */ 582 void rtc_alarm_get(uint8_t rtc_alarm, rtc_alarm_struct *rtc_alarm_time); 583 /* get RTC alarm subsecond */ 584 uint32_t rtc_alarm_subsecond_get(uint8_t rtc_alarm); 585 /* enable RTC alarm */ 586 void rtc_alarm_enable(uint8_t rtc_alarm); 587 /* disable RTC alarm */ 588 ErrStatus rtc_alarm_disable(uint8_t rtc_alarm); 589 590 /* timestamp and tamper configuration functions */ 591 /* enable RTC time-stamp */ 592 void rtc_timestamp_enable(uint32_t edge); 593 /* disable RTC time-stamp */ 594 void rtc_timestamp_disable(void); 595 /* get RTC timestamp time and date */ 596 void rtc_timestamp_get(rtc_timestamp_struct *rtc_timestamp); 597 /* configure RTC time-stamp internal event */ 598 void rtc_timestamp_internalevent_config(uint32_t mode); 599 /* get RTC time-stamp subsecond */ 600 uint32_t rtc_timestamp_subsecond_get(void); 601 602 /* enable RTC tamper */ 603 void rtc_tamper_enable(rtc_tamper_struct *rtc_tamper); 604 /* disable RTC tamper */ 605 void rtc_tamper_disable(uint32_t source); 606 /* set specified RTC tamper mask function */ 607 void rtc_tamper_mask(uint32_t source); 608 /* tamperx event does not erase the RTC_BKP registers */ 609 void rtc_tamper_without_bkp_reset(uint32_t ne_source); 610 611 612 /* select the RTC output pin */ 613 void rtc_output_pin_select(uint32_t outputpin); 614 /* configure RTC alarm output source */ 615 void rtc_alarm_output_config(uint32_t source, uint32_t mode); 616 /* configure RTC calibration output source */ 617 void rtc_calibration_output_config(uint32_t source); 618 619 /* adjust the daylight saving time by adding or substracting one hour from the current time */ 620 void rtc_hour_adjust(uint32_t operation); 621 /* adjust RTC second or subsecond value of current time */ 622 ErrStatus rtc_second_adjust(uint32_t add, uint32_t minus); 623 624 /* enable RTC bypass shadow registers function */ 625 void rtc_bypass_shadow_enable(void); 626 /* disable RTC bypass shadow registers function */ 627 void rtc_bypass_shadow_disable(void); 628 629 /* enable RTC reference clock detection function */ 630 ErrStatus rtc_refclock_detection_enable(void); 631 /* disable RTC reference clock detection function */ 632 ErrStatus rtc_refclock_detection_disable(void); 633 634 /* enable RTC wakeup timer */ 635 void rtc_wakeup_enable(void); 636 /* disable RTC wakeup timer */ 637 ErrStatus rtc_wakeup_disable(void); 638 /* set auto wakeup timer clock */ 639 ErrStatus rtc_wakeup_clock_set(uint8_t wakeup_clock); 640 /* set auto wakeup timer value */ 641 ErrStatus rtc_wakeup_timer_set(uint16_t wakeup_timer); 642 /* get auto wakeup timer value */ 643 uint16_t rtc_wakeup_timer_get(void); 644 645 /* configure RTC smooth calibration */ 646 ErrStatus rtc_smooth_calibration_config(uint32_t window, uint32_t plus, uint32_t minus); 647 648 /* enable specified RTC interrupt */ 649 void rtc_interrupt_enable(uint32_t interrupt); 650 /* disable specified RTC interrupt */ 651 void rtc_interrupt_disable(uint32_t interrupt); 652 /* check specified flag */ 653 FlagStatus rtc_flag_get(uint32_t flag); 654 /* clear specified flag */ 655 void rtc_flag_clear(uint32_t flag); 656 657 658 #endif /* GD32L23X_RTC_H */ 659
