1 /* 2 * SPDX-FileCopyrightText: 2020-2024 Espressif Systems (Shanghai) CO LTD 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 #pragma once 7 8 #include <stdbool.h> 9 #include <stddef.h> 10 #include <stdint.h> 11 #include "soc/soc.h" 12 #include "soc/clk_tree_defs.h" 13 14 #ifdef __cplusplus 15 extern "C" { 16 #endif 17 18 /** 19 * @file rtc.h 20 * @brief Low-level RTC power, clock functions. 21 * 22 * Functions in this file facilitate configuration of ESP32's RTC_CNTL peripheral. 23 * RTC_CNTL peripheral handles many functions: 24 * - enables/disables clocks and power to various parts of the chip; this is 25 * done using direct register access (forcing power up or power down) or by 26 * allowing state machines to control power and clocks automatically 27 * - handles sleep and wakeup functions 28 * - maintains a 48-bit counter which can be used for timekeeping 29 * 30 * These functions are not thread safe, and should not be viewed as high level 31 * APIs. For example, while this file provides a function which can switch 32 * CPU frequency, this function is on its own is not sufficient to implement 33 * frequency switching in ESP-IDF context: some coordination with RTOS, 34 * peripheral drivers, and WiFi/BT stacks is also required. 35 * 36 * These functions will normally not be used in applications directly. 37 * ESP-IDF provides, or will provide, drivers and other facilities to use 38 * RTC subsystem functionality. 39 * 40 * The functions are loosely split into the following groups: 41 * - rtc_clk: clock switching, calibration 42 * - rtc_time: reading RTC counter, conversion between counter values and time 43 * - rtc_sleep: entry into sleep modes 44 */ 45 46 #define MHZ (1000000) 47 48 #define RTC_SLOW_CLK_150K_CAL_TIMEOUT_THRES(cycles) (cycles << 10) 49 #define RTC_SLOW_CLK_32K_CAL_TIMEOUT_THRES(cycles) (cycles << 12) 50 #define RTC_FAST_CLK_8M_CAL_TIMEOUT_THRES(cycles) (TIMG_RTC_CALI_TIMEOUT_THRES_V) // Just use the max timeout thres value 51 52 #define OTHER_BLOCKS_POWERUP 1 53 #define OTHER_BLOCKS_WAIT 1 54 55 // TODO: IDF-6254 56 /* Approximate mapping of voltages to RTC_CNTL_DBIAS_WAK, RTC_CNTL_DBIAS_SLP, 57 * RTC_CNTL_DIG_DBIAS_WAK, RTC_CNTL_DIG_DBIAS_SLP values. 58 */ 59 #define RTC_CNTL_DBIAS_SLP 5 //sleep dig_dbias & rtc_dbias 60 #define RTC_CNTL_DBIAS_0V90 13 //digital voltage 61 #define RTC_CNTL_DBIAS_0V95 16 62 #define RTC_CNTL_DBIAS_1V00 18 63 #define RTC_CNTL_DBIAS_1V05 20 64 #define RTC_CNTL_DBIAS_1V10 23 65 #define RTC_CNTL_DBIAS_1V15 25 66 #define RTC_CNTL_DBIAS_1V20 28 67 #define RTC_CNTL_DBIAS_1V25 30 68 #define RTC_CNTL_DBIAS_1V30 31 //voltage is about 1.34v in fact 69 70 /* Delays for various clock sources to be enabled/switched. 71 * All values are in microseconds. 72 */ 73 #define SOC_DELAY_RTC_FAST_CLK_SWITCH 3 74 #define SOC_DELAY_RTC_SLOW_CLK_SWITCH 300 75 #define SOC_DELAY_RC_FAST_ENABLE 50 76 #define SOC_DELAY_RC_FAST_DIGI_SWITCH 5 77 #define SOC_DELAY_RC32K_ENABLE 300 78 #define SOC_DELAY_LP_PLL_SWITCH 3 79 #define SOC_DELAY_LP_PLL_ENABLE 50 80 81 /* Core voltage: //TODO: IDF-6254 82 * Currently, ESP32H2 never adjust its wake voltage in runtime 83 * Only sets dig/rtc voltage dbias at startup time 84 */ 85 #define DIG_DBIAS_80M RTC_CNTL_DBIAS_1V20 86 #define DIG_DBIAS_160M RTC_CNTL_DBIAS_1V20 87 #define DIG_DBIAS_XTAL RTC_CNTL_DBIAS_1V10 88 #define DIG_DBIAS_2M RTC_CNTL_DBIAS_1V00 89 90 #define RTC_CNTL_PLL_BUF_WAIT_DEFAULT 20 91 #define RTC_CNTL_XTL_BUF_WAIT_DEFAULT 100 92 #define RTC_CNTL_CK8M_WAIT_DEFAULT 20 93 #define RTC_CK8M_ENABLE_WAIT_DEFAULT 5 94 95 #define RTC_CNTL_CK8M_DFREQ_DEFAULT 860 96 #define RTC_CNTL_SCK_DCAP_DEFAULT 85 97 #define RTC_CNTL_RC32K_DFREQ_DEFAULT 700 98 99 /* Various delays to be programmed into power control state machines */ 100 #define RTC_CNTL_XTL_BUF_WAIT_SLP_US (250) 101 #define RTC_CNTL_PLL_BUF_WAIT_SLP_CYCLES (1) 102 #define RTC_CNTL_CK8M_WAIT_SLP_CYCLES (4) 103 #define RTC_CNTL_WAKEUP_DELAY_CYCLES (5) 104 #define RTC_CNTL_OTHER_BLOCKS_POWERUP_CYCLES (1) 105 #define RTC_CNTL_OTHER_BLOCKS_WAIT_CYCLES (1) 106 #define RTC_CNTL_MIN_SLP_VAL_MIN (2) 107 108 /* 109 set sleep_init default param 110 */ 111 #define RTC_CNTL_DBG_ATTEN_LIGHTSLEEP_DEFAULT 5 112 #define RTC_CNTL_DBG_ATTEN_LIGHTSLEEP_NODROP 0 113 #define RTC_CNTL_DBG_ATTEN_DEEPSLEEP_DEFAULT 15 114 #define RTC_CNTL_DBG_ATTEN_MONITOR_DEFAULT 0 115 #define RTC_CNTL_BIASSLP_MONITOR_DEFAULT 0 116 #define RTC_CNTL_BIASSLP_SLEEP_ON 0 117 #define RTC_CNTL_BIASSLP_SLEEP_DEFAULT 1 118 #define RTC_CNTL_PD_CUR_MONITOR_DEFAULT 0 119 #define RTC_CNTL_PD_CUR_SLEEP_ON 0 120 #define RTC_CNTL_PD_CUR_SLEEP_DEFAULT 1 121 #define RTC_CNTL_DG_VDD_DRV_B_SLP_DEFAULT 254 122 123 /* 124 The follow value is used to get a reasonable rtc voltage dbias value according to digital dbias & some other value 125 storing in efuse (based on ATE 5k ECO3 chips) 126 */ 127 #define K_RTC_MID_MUL10000 215 128 #define K_DIG_MID_MUL10000 213 129 #define V_RTC_MID_MUL10000 10800 130 #define V_DIG_MID_MUL10000 10860 131 132 /** 133 * @brief Possible main XTAL frequency values. 134 * 135 * Enum values should be equal to frequency in MHz. 136 */ 137 typedef enum { 138 RTC_XTAL_FREQ_32M = 32, 139 } rtc_xtal_freq_t; 140 141 /** 142 * @brief CPU clock configuration structure 143 */ 144 typedef struct rtc_cpu_freq_config_s { 145 soc_cpu_clk_src_t source; //!< The clock from which CPU clock is derived 146 uint32_t source_freq_mhz; //!< Source clock frequency 147 uint32_t div; //!< Divider, freq_mhz = source_freq_mhz / div 148 uint32_t freq_mhz; //!< CPU clock frequency 149 } rtc_cpu_freq_config_t; 150 151 #define RTC_CLK_CAL_FRACT 19 //!< Number of fractional bits in values returned by rtc_clk_cal 152 153 #define RTC_VDDSDIO_TIEH_1_8V 0 //!< TIEH field value for 1.8V VDDSDIO 154 #define RTC_VDDSDIO_TIEH_3_3V 1 //!< TIEH field value for 3.3V VDDSDIO 155 156 /** 157 * @brief Clock source to be calibrated using rtc_clk_cal function 158 * 159 * @note On previous targets, the enum values somehow reflects the register field values of TIMG_RTC_CALI_CLK_SEL 160 * However, this is not true on ESP32H2. The conversion to register field values is explicitly done in 161 * rtc_clk_cal_internal 162 */ 163 typedef enum { 164 RTC_CAL_RTC_MUX = -1, //!< Currently selected RTC_SLOW_CLK 165 RTC_CAL_RC_SLOW = SOC_RTC_SLOW_CLK_SRC_RC_SLOW, //!< Internal 150kHz RC oscillator 166 RTC_CAL_RC32K = SOC_RTC_SLOW_CLK_SRC_RC32K, //!< Internal 32kHz RC oscillator, as one type of 32k clock 167 RTC_CAL_32K_XTAL = SOC_RTC_SLOW_CLK_SRC_XTAL32K, //!< External 32kHz XTAL, as one type of 32k clock 168 RTC_CAL_32K_OSC_SLOW = SOC_RTC_SLOW_CLK_SRC_OSC_SLOW, //!< External slow clock signal input by lp_pad_gpiox, as one type of 32k clock 169 RTC_CAL_RC_FAST //!< Internal 8MHz RC oscillator 170 } rtc_cal_sel_t; 171 172 /** 173 * Initialization parameters for rtc_clk_init 174 */ 175 typedef struct { 176 rtc_xtal_freq_t xtal_freq : 8; //!< Main XTAL frequency 177 uint32_t cpu_freq_mhz : 10; //!< CPU frequency to set, in MHz 178 soc_rtc_fast_clk_src_t fast_clk_src : 2; //!< RTC_FAST_CLK clock source to choose 179 soc_rtc_slow_clk_src_t slow_clk_src : 3; //!< RTC_SLOW_CLK clock source to choose 180 uint32_t clk_rtc_clk_div : 8; 181 uint32_t clk_8m_clk_div : 3; //!< RC_FAST clock divider (division is by clk_8m_div+1, i.e. 0 means ~8MHz frequency) 182 uint32_t slow_clk_dcap : 8; //!< RC_SLOW clock adjustment parameter (higher value leads to lower frequency) 183 uint32_t clk_8m_dfreq : 10; //!< RC_FAST clock adjustment parameter (higher value leads to higher frequency) 184 uint32_t rc32k_dfreq : 10; //!< Internal RC32K clock adjustment parameter (higher value leads to higher frequency) 185 } rtc_clk_config_t; 186 187 /** 188 * Default initializer for rtc_clk_config_t 189 */ 190 #define RTC_CLK_CONFIG_DEFAULT() { \ 191 .xtal_freq = RTC_XTAL_FREQ_32M, \ 192 .cpu_freq_mhz = 96, \ 193 .fast_clk_src = SOC_RTC_FAST_CLK_SRC_RC_FAST, \ 194 .slow_clk_src = SOC_RTC_SLOW_CLK_SRC_RC_SLOW, \ 195 .clk_rtc_clk_div = 0, \ 196 .clk_8m_clk_div = 0, \ 197 .slow_clk_dcap = RTC_CNTL_SCK_DCAP_DEFAULT, \ 198 .clk_8m_dfreq = RTC_CNTL_CK8M_DFREQ_DEFAULT, \ 199 .rc32k_dfreq = RTC_CNTL_RC32K_DFREQ_DEFAULT, \ 200 } 201 202 /** 203 * Initialize clocks and set CPU frequency 204 * 205 * @param cfg clock configuration as rtc_clk_config_t 206 */ 207 void rtc_clk_init(rtc_clk_config_t cfg); 208 209 /** 210 * @brief Get main XTAL frequency 211 * 212 * This is the value stored in RTC register RTC_XTAL_FREQ_REG by the bootloader. As passed to 213 * rtc_clk_init function 214 * 215 * @return XTAL frequency, one of rtc_xtal_freq_t 216 */ 217 rtc_xtal_freq_t rtc_clk_xtal_freq_get(void); 218 219 /** 220 * @brief Update XTAL frequency 221 * 222 * Updates the XTAL value stored in RTC_XTAL_FREQ_REG. Usually this value is ignored 223 * after startup. 224 * 225 * @param xtal_freq New frequency value 226 */ 227 void rtc_clk_xtal_freq_update(rtc_xtal_freq_t xtal_freq); 228 229 /** 230 * @brief Enable or disable 32 kHz XTAL oscillator 231 * @param en true to enable, false to disable 232 */ 233 void rtc_clk_32k_enable(bool en); 234 235 /** 236 * @brief Configure 32 kHz XTAL oscillator to accept external clock signal 237 */ 238 void rtc_clk_32k_enable_external(void); 239 240 /** 241 * @brief Get the state of 32k XTAL oscillator 242 * @return true if 32k XTAL oscillator has been enabled 243 */ 244 bool rtc_clk_32k_enabled(void); 245 246 /** 247 * @brief Enable 32k oscillator, configuring it for fast startup time. 248 * Note: to achieve higher frequency stability, rtc_clk_32k_enable function 249 * must be called one the 32k XTAL oscillator has started up. This function 250 * will initially disable the 32k XTAL oscillator, so it should not be called 251 * when the system is using 32k XTAL as RTC_SLOW_CLK. 252 * 253 * @param cycle Number of 32kHz cycles to bootstrap external crystal. 254 * If 0, no square wave will be used to bootstrap crystal oscillation. 255 */ 256 void rtc_clk_32k_bootstrap(uint32_t cycle); 257 258 /** 259 * @brief Enable or disable 32 kHz internal rc oscillator 260 * @param en true to enable, false to disable 261 */ 262 void rtc_clk_rc32k_enable(bool enable); 263 264 /** 265 * @brief Enable or disable 8 MHz internal oscillator 266 * 267 * @param clk_8m_en true to enable 8MHz generator 268 */ 269 void rtc_clk_8m_enable(bool clk_8m_en); 270 271 /** 272 * @brief Get the state of 8 MHz internal oscillator 273 * @return true if the oscillator is enabled 274 */ 275 bool rtc_clk_8m_enabled(void); 276 277 /** 278 * @brief Enable or disable LP_PLL_CLK 279 * @param enable true to enable, false to disable 280 */ 281 void rtc_clk_lp_pll_enable(bool enable); 282 283 /** 284 * @brief Select clock source for LP_PLL_CLK 285 * @param clk_src clock source (one of soc_lp_pll_clk_src_t values) 286 */ 287 void rtc_clk_lp_pll_src_set(soc_lp_pll_clk_src_t clk_src); 288 289 /** 290 * @brief Select source for RTC_SLOW_CLK 291 * @param clk_src clock source (one of soc_rtc_slow_clk_src_t values) 292 */ 293 void rtc_clk_slow_src_set(soc_rtc_slow_clk_src_t clk_src); 294 295 /** 296 * @brief Get the RTC_SLOW_CLK source 297 * @return currently selected clock source (one of soc_rtc_slow_clk_src_t values) 298 */ 299 soc_rtc_slow_clk_src_t rtc_clk_slow_src_get(void); 300 301 /** 302 * @brief Get the approximate frequency of RTC_SLOW_CLK, in Hz 303 * 304 * - if SOC_RTC_SLOW_CLK_SRC_RC_SLOW is selected, returns 136000 305 * - if SOC_RTC_SLOW_CLK_SRC_XTAL32K is selected, returns 32768 306 * - if SOC_RTC_SLOW_CLK_SRC_RC32K is selected, returns 32768 307 * - if SOC_RTC_SLOW_CLK_SRC_OSC_SLOW is selected, returns 32768 308 * 309 * rtc_clk_cal function can be used to get more precise value by comparing 310 * RTC_SLOW_CLK frequency to the frequency of main XTAL. 311 * 312 * @return RTC_SLOW_CLK frequency, in Hz 313 */ 314 uint32_t rtc_clk_slow_freq_get_hz(void); 315 316 /** 317 * @brief Select source for RTC_FAST_CLK 318 * @param clk_src clock source (one of soc_rtc_fast_clk_src_t values) 319 */ 320 void rtc_clk_fast_src_set(soc_rtc_fast_clk_src_t clk_src); 321 322 /** 323 * @brief Get the RTC_FAST_CLK source 324 * @return currently selected clock source (one of soc_rtc_fast_clk_src_t values) 325 */ 326 soc_rtc_fast_clk_src_t rtc_clk_fast_src_get(void); 327 328 /** 329 * @brief Get CPU frequency config for a given frequency 330 * @param freq_mhz Frequency in MHz 331 * @param[out] out_config Output, CPU frequency configuration structure 332 * @return true if frequency can be obtained, false otherwise 333 */ 334 bool rtc_clk_cpu_freq_mhz_to_config(uint32_t freq_mhz, rtc_cpu_freq_config_t *out_config); 335 336 /** 337 * @brief Switch CPU frequency 338 * 339 * This function sets CPU frequency according to the given configuration 340 * structure. It enables PLLs, if necessary. 341 * 342 * @note This function in not intended to be called by applications in FreeRTOS 343 * environment. This is because it does not adjust various timers based on the 344 * new CPU frequency. 345 * 346 * @param config CPU frequency configuration structure 347 */ 348 void rtc_clk_cpu_freq_set_config(const rtc_cpu_freq_config_t *config); 349 350 /** 351 * @brief Switch CPU frequency (optimized for speed) 352 * 353 * This function is a faster equivalent of rtc_clk_cpu_freq_set_config. 354 * It works faster because it does not disable PLLs when switching from PLL to 355 * XTAL and does not enabled them when switching back. If PLL is not already 356 * enabled when this function is called to switch from XTAL to PLL frequency, 357 * or the PLL which is enabled is the wrong one, this function will fall back 358 * to calling rtc_clk_cpu_freq_set_config. 359 * 360 * Unlike rtc_clk_cpu_freq_set_config, this function relies on static data, 361 * so it is less safe to use it e.g. from a panic handler (when memory might 362 * be corrupted). 363 * 364 * @note This function in not intended to be called by applications in FreeRTOS 365 * environment. This is because it does not adjust various timers based on the 366 * new CPU frequency. 367 * 368 * @param config CPU frequency configuration structure 369 */ 370 void rtc_clk_cpu_freq_set_config_fast(const rtc_cpu_freq_config_t *config); 371 372 /** 373 * @brief Get the currently used CPU frequency configuration 374 * @param[out] out_config Output, CPU frequency configuration structure 375 */ 376 void rtc_clk_cpu_freq_get_config(rtc_cpu_freq_config_t *out_config); 377 378 /** 379 * @brief Switch CPU clock source to XTAL 380 * 381 * Short form for filling in rtc_cpu_freq_config_t structure and calling 382 * rtc_clk_cpu_freq_set_config when a switch to XTAL is needed. 383 * Assumes that XTAL frequency has been determined — don't call in startup code. 384 * 385 * @note This function always disables BBPLL after switching the CPU clock source to XTAL for power saving purpose. 386 * If this is unwanted, please use rtc_clk_cpu_freq_set_config. It helps to check whether USB Serial JTAG is in use, 387 * if so, then BBPLL will not be turned off. 388 */ 389 void rtc_clk_cpu_freq_set_xtal(void); 390 391 /** 392 * @brief Get the current stored APB frequency. 393 * @return The APB frequency value as last set via rtc_clk_apb_freq_update(), in Hz. 394 */ 395 uint32_t rtc_clk_apb_freq_get(void); 396 397 /** 398 * @brief Measure RTC slow clock's period, based on main XTAL frequency 399 * 400 * This function will time out and return 0 if the time for the given number 401 * of cycles to be counted exceeds the expected time twice. This may happen if 402 * 32k XTAL is being calibrated, but the oscillator has not started up (due to 403 * incorrect loading capacitance, board design issue, or lack of 32 XTAL on board). 404 * 405 * @param cal_clk clock to be measured 406 * @param slow_clk_cycles number of slow clock cycles to average 407 * @return average slow clock period in microseconds, Q13.19 fixed point format, 408 * or 0 if calibration has timed out 409 */ 410 uint32_t rtc_clk_cal(rtc_cal_sel_t cal_clk, uint32_t slow_clk_cycles); 411 412 /** 413 * @brief Convert time interval from microseconds to RTC_SLOW_CLK cycles 414 * @param time_in_us Time interval in microseconds 415 * @param slow_clk_period Period of slow clock in microseconds, Q13.19 416 * fixed point format (as returned by rtc_slowck_cali). 417 * @return number of slow clock cycles 418 */ 419 uint64_t rtc_time_us_to_slowclk(uint64_t time_in_us, uint32_t period); 420 421 /** 422 * @brief Convert time interval from RTC_SLOW_CLK to microseconds 423 * @param time_in_us Time interval in RTC_SLOW_CLK cycles 424 * @param slow_clk_period Period of slow clock in microseconds, Q13.19 425 * fixed point format (as returned by rtc_slowck_cali). 426 * @return time interval in microseconds 427 */ 428 uint64_t rtc_time_slowclk_to_us(uint64_t rtc_cycles, uint32_t period); 429 430 /** 431 * @brief Get current value of RTC counter 432 * 433 * RTC has a 48-bit counter which is incremented by 2 every 2 RTC_SLOW_CLK 434 * cycles. Counter value is not writable by software. The value is not adjusted 435 * when switching to a different RTC_SLOW_CLK source. 436 * 437 * Note: this function may take up to 1 RTC_SLOW_CLK cycle to execute 438 * 439 * @return current value of RTC counter 440 */ 441 uint64_t rtc_time_get(void); 442 443 /** 444 * @brief Busy loop until next RTC_SLOW_CLK cycle 445 * 446 * This function returns not earlier than the next RTC_SLOW_CLK clock cycle. 447 * In some cases (e.g. when RTC_SLOW_CLK cycle is very close), it may return 448 * one RTC_SLOW_CLK cycle later. 449 */ 450 void rtc_clk_wait_for_slow_cycle(void); 451 452 /** 453 * @brief Enable the rtc digital 8M clock 454 * 455 * This function is used to enable the digital rtc 8M clock to support peripherals. 456 * For enabling the analog 8M clock, using `rtc_clk_8M_enable` function above. 457 */ 458 void rtc_dig_clk8m_enable(void); 459 460 /** 461 * @brief Disable the rtc digital 8M clock 462 * 463 * This function is used to disable the digital rtc 8M clock, which is only used to support peripherals. 464 */ 465 void rtc_dig_clk8m_disable(void); 466 467 /** 468 * @brief Get whether the rtc digital 8M clock is enabled 469 */ 470 bool rtc_dig_8m_enabled(void); 471 472 /** 473 * @brief Calculate the real clock value after the clock calibration 474 * 475 * @param cal_val Average slow clock period in microseconds, fixed point value as returned from `rtc_clk_cal` 476 * @return Frequency of the clock in Hz 477 */ 478 uint32_t rtc_clk_freq_cal(uint32_t cal_val); 479 480 // -------------------------- CLOCK TREE DEFS ALIAS ---------------------------- 481 // **WARNING**: The following are only for backwards compatibility. 482 // Please use the declarations in soc/clk_tree_defs.h instead. 483 /** 484 * @brief CPU clock source 485 */ 486 typedef soc_cpu_clk_src_t rtc_cpu_freq_src_t; 487 #define RTC_CPU_FREQ_SRC_XTAL SOC_CPU_CLK_SRC_XTAL //!< XTAL 488 #define RTC_CPU_FREQ_SRC_PLL SOC_CPU_CLK_SRC_PLL //!< PLL (96M) 489 #define RTC_CPU_FREQ_SRC_8M SOC_CPU_CLK_SRC_RC_FAST //!< Internal 8M RTC oscillator 490 491 /** 492 * @brief RTC SLOW_CLK frequency values 493 */ 494 typedef soc_rtc_slow_clk_src_t rtc_slow_freq_t; 495 #define RTC_SLOW_FREQ_RTC SOC_RTC_SLOW_CLK_SRC_RC_SLOW //!< Internal 150 kHz RC oscillator 496 #define RTC_SLOW_FREQ_32K_XTAL SOC_RTC_SLOW_CLK_SRC_XTAL32K //!< External 32 kHz XTAL 497 498 /** 499 * @brief RTC FAST_CLK frequency values 500 */ 501 typedef soc_rtc_fast_clk_src_t rtc_fast_freq_t; 502 #define RTC_FAST_FREQ_XTALD4 SOC_RTC_FAST_CLK_SRC_XTAL_DIV //!< Main XTAL, divided by 2 503 #define RTC_FAST_FREQ_8M SOC_RTC_FAST_CLK_SRC_RC_FAST //!< Internal 8 MHz RC oscillator 504 505 /* Alias of frequency related macros */ 506 #define RTC_FAST_CLK_FREQ_APPROX SOC_CLK_RC_FAST_FREQ_APPROX 507 #define RTC_FAST_CLK_FREQ_8M SOC_CLK_RC_FAST_FREQ_APPROX 508 #define RTC_SLOW_CLK_FREQ_150K SOC_CLK_RC_SLOW_FREQ_APPROX 509 #define RTC_SLOW_CLK_FREQ_32K SOC_CLK_XTAL32K_FREQ_APPROX 510 511 /* Alias of deprecated function names */ 512 #define rtc_clk_slow_freq_set(slow_freq) rtc_clk_slow_src_set(slow_freq) 513 #define rtc_clk_slow_freq_get() rtc_clk_slow_src_get() 514 #define rtc_clk_fast_freq_set(fast_freq) rtc_clk_fast_src_set(fast_freq) 515 #define rtc_clk_fast_freq_get() rtc_clk_fast_src_get() 516 517 #ifdef __cplusplus 518 } 519 #endif 520
