1 /* 2 * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 #pragma once 7 8 #include <stdbool.h> 9 #include <stddef.h> 10 #include <stdint.h> 11 #include "stubs.h" 12 #include "soc/soc.h" 13 #include "soc/clk_tree_defs.h" 14 15 #ifdef __cplusplus 16 extern "C" { 17 #endif 18 19 /** 20 * @file rtc.h 21 * @brief Low-level RTC power, clock functions. 22 * 23 * Functions in this file facilitate configuration of ESP32's RTC_CNTL peripheral. 24 * RTC_CNTL peripheral handles many functions: 25 * - enables/disables clocks and power to various parts of the chip; this is 26 * done using direct register access (forcing power up or power down) or by 27 * allowing state machines to control power and clocks automatically 28 * - handles sleep and wakeup functions 29 * - maintains a 48-bit counter which can be used for timekeeping 30 * 31 * These functions are not thread safe, and should not be viewed as high level 32 * APIs. For example, while this file provides a function which can switch 33 * CPU frequency, this function is on its own is not sufficient to implement 34 * frequency switching in ESP-IDF context: some coordination with RTOS, 35 * peripheral drivers, and WiFi/BT stacks is also required. 36 * 37 * These functions will normally not be used in applications directly. 38 * ESP-IDF provides, or will provide, drivers and other facilities to use 39 * RTC subsystem functionality. 40 * 41 * The functions are loosely split into the following groups: 42 * - rtc_clk: clock switching, calibration 43 * - rtc_time: reading RTC counter, conversion between counter values and time 44 */ 45 46 #define RTC_SLOW_CLK_150K_CAL_TIMEOUT_THRES(cycles) (cycles << 10) 47 #define RTC_SLOW_CLK_32K_CAL_TIMEOUT_THRES(cycles) (cycles << 12) 48 #define RTC_FAST_CLK_20M_CAL_TIMEOUT_THRES(cycles) (TIMG_RTC_CALI_TIMEOUT_THRES_V) // Just use the max timeout thres value 49 50 #define OTHER_BLOCKS_POWERUP 1 51 #define OTHER_BLOCKS_WAIT 1 52 53 // TODO: IDF-5781 54 /* Approximate mapping of voltages to RTC_CNTL_DBIAS_WAK, RTC_CNTL_DBIAS_SLP, 55 * RTC_CNTL_DIG_DBIAS_WAK, RTC_CNTL_DIG_DBIAS_SLP values. 56 */ 57 #define RTC_CNTL_DBIAS_SLP 5 //sleep dig_dbias & rtc_dbias 58 #define RTC_CNTL_DBIAS_0V90 13 //digital voltage 59 #define RTC_CNTL_DBIAS_0V95 16 60 #define RTC_CNTL_DBIAS_1V00 18 61 #define RTC_CNTL_DBIAS_1V05 20 62 #define RTC_CNTL_DBIAS_1V10 23 63 #define RTC_CNTL_DBIAS_1V15 25 64 #define RTC_CNTL_DBIAS_1V20 28 65 #define RTC_CNTL_DBIAS_1V25 30 66 #define RTC_CNTL_DBIAS_1V30 31 //voltage is about 1.34v in fact 67 68 /* Delays for various clock sources to be enabled/switched. 69 * All values are in microseconds. 70 */ 71 #define SOC_DELAY_RTC_FAST_CLK_SWITCH 3 72 #define SOC_DELAY_RTC_SLOW_CLK_SWITCH 300 73 #define SOC_DELAY_RC_FAST_ENABLE 50 74 #define SOC_DELAY_RC_FAST_DIGI_SWITCH 5 75 #define SOC_DELAY_RC32K_ENABLE 300 76 77 /* Core voltage: // TODO: IDF-5781 78 * Currently, ESP32C6 never adjust its wake voltage in runtime 79 * Only sets dig/rtc voltage dbias at startup time 80 */ 81 #define DIG_DBIAS_80M RTC_CNTL_DBIAS_1V20 82 #define DIG_DBIAS_160M RTC_CNTL_DBIAS_1V20 83 #define DIG_DBIAS_XTAL RTC_CNTL_DBIAS_1V10 84 #define DIG_DBIAS_2M RTC_CNTL_DBIAS_1V00 85 86 #define RTC_CNTL_PLL_BUF_WAIT_DEFAULT 20 87 #define RTC_CNTL_XTL_BUF_WAIT_DEFAULT 100 88 #define RTC_CNTL_CK8M_WAIT_DEFAULT 20 89 #define RTC_CK8M_ENABLE_WAIT_DEFAULT 5 90 91 #define RTC_CNTL_CK8M_DFREQ_DEFAULT 100 92 #define RTC_CNTL_SCK_DCAP_DEFAULT 128 93 #define RTC_CNTL_RC32K_DFREQ_DEFAULT 700 94 95 /* Various delays to be programmed into power control state machines */ 96 #define RTC_CNTL_XTL_BUF_WAIT_SLP_US (250) 97 #define RTC_CNTL_PLL_BUF_WAIT_SLP_CYCLES (1) 98 #define RTC_CNTL_CK8M_WAIT_SLP_CYCLES (4) 99 #define RTC_CNTL_WAKEUP_DELAY_CYCLES (5) 100 #define RTC_CNTL_OTHER_BLOCKS_POWERUP_CYCLES (1) 101 #define RTC_CNTL_OTHER_BLOCKS_WAIT_CYCLES (1) 102 #define RTC_CNTL_MIN_SLP_VAL_MIN (2) 103 104 /* 105 set sleep_init default param 106 */ 107 #define RTC_CNTL_DBG_ATTEN_LIGHTSLEEP_DEFAULT 5 108 #define RTC_CNTL_DBG_ATTEN_LIGHTSLEEP_NODROP 0 109 #define RTC_CNTL_DBG_ATTEN_DEEPSLEEP_DEFAULT 15 110 #define RTC_CNTL_DBG_ATTEN_MONITOR_DEFAULT 0 111 #define RTC_CNTL_BIASSLP_MONITOR_DEFAULT 0 112 #define RTC_CNTL_BIASSLP_SLEEP_ON 0 113 #define RTC_CNTL_BIASSLP_SLEEP_DEFAULT 1 114 #define RTC_CNTL_PD_CUR_MONITOR_DEFAULT 0 115 #define RTC_CNTL_PD_CUR_SLEEP_ON 0 116 #define RTC_CNTL_PD_CUR_SLEEP_DEFAULT 1 117 #define RTC_CNTL_DG_VDD_DRV_B_SLP_DEFAULT 254 118 119 /* 120 The follow value is used to get a reasonable rtc voltage dbias value according to digital dbias & some other value 121 storing in efuse (based on ATE 5k ECO3 chips) 122 */ 123 #define K_RTC_MID_MUL10000 215 124 #define K_DIG_MID_MUL10000 213 125 #define V_RTC_MID_MUL10000 10800 126 #define V_DIG_MID_MUL10000 10860 127 128 /** 129 * @brief Possible main XTAL frequency values. 130 * 131 * Enum values should be equal to frequency in MHz. 132 */ 133 typedef enum { 134 RTC_XTAL_FREQ_40M = 40, //!< 40 MHz XTAL 135 } rtc_xtal_freq_t; 136 137 /** 138 * @brief CPU clock configuration structure 139 */ 140 typedef struct rtc_cpu_freq_config_s { 141 soc_cpu_clk_src_t source; //!< The clock from which CPU clock is derived 142 uint32_t source_freq_mhz; //!< Source clock frequency 143 uint32_t div; //!< Divider, freq_mhz = SOC_ROOT_CLK freq_mhz / div 144 uint32_t freq_mhz; //!< CPU clock frequency 145 } rtc_cpu_freq_config_t; 146 147 #define RTC_CLK_CAL_FRACT 19 //!< Number of fractional bits in values returned by rtc_clk_cal 148 149 #define RTC_VDDSDIO_TIEH_1_8V 0 //!< TIEH field value for 1.8V VDDSDIO 150 #define RTC_VDDSDIO_TIEH_3_3V 1 //!< TIEH field value for 3.3V VDDSDIO 151 152 /** 153 * @brief Clock source to be calibrated using rtc_clk_cal function 154 * 155 * @note On previous targets, the enum values somehow reflects the register field values of TIMG_RTC_CALI_CLK_SEL 156 * However, this is not true on ESP32C6. The conversion to register field values is explicitly done in 157 * rtc_clk_cal_internal 158 */ 159 typedef enum { 160 RTC_CAL_RTC_MUX = -1, //!< Currently selected RTC_SLOW_CLK 161 RTC_CAL_RC_SLOW = SOC_RTC_SLOW_CLK_SRC_RC_SLOW, //!< Internal 150kHz RC oscillator 162 RTC_CAL_RC32K = SOC_RTC_SLOW_CLK_SRC_RC32K, //!< Internal 32kHz RC oscillator, as one type of 32k clock 163 RTC_CAL_32K_XTAL = SOC_RTC_SLOW_CLK_SRC_XTAL32K, //!< External 32kHz XTAL, as one type of 32k clock 164 RTC_CAL_32K_OSC_SLOW = SOC_RTC_SLOW_CLK_SRC_OSC_SLOW, //!< External slow clock signal input by lp_pad_gpio0, as one type of 32k clock 165 RTC_CAL_RC_FAST //!< Internal 20MHz RC oscillator 166 } rtc_cal_sel_t; 167 168 /** 169 * Initialization parameters for rtc_clk_init 170 */ 171 typedef struct { 172 rtc_xtal_freq_t xtal_freq : 8; //!< Main XTAL frequency 173 uint32_t cpu_freq_mhz : 10; //!< CPU frequency to set, in MHz 174 soc_rtc_fast_clk_src_t fast_clk_src : 2; //!< RTC_FAST_CLK clock source to choose 175 soc_rtc_slow_clk_src_t slow_clk_src : 3; //!< RTC_SLOW_CLK clock source to choose 176 uint32_t clk_rtc_clk_div : 8; 177 uint32_t clk_8m_clk_div : 3; //!< RC_FAST clock divider (division is by clk_8m_div+1, i.e. 0 means ~20MHz frequency) 178 uint32_t slow_clk_dcap : 8; //!< RC_SLOW clock adjustment parameter (higher value leads to lower frequency) 179 uint32_t clk_8m_dfreq : 10; //!< RC_FAST clock adjustment parameter (higher value leads to higher frequency) 180 uint32_t rc32k_dfreq : 10; //!< Internal RC32K clock adjustment parameter (higher value leads to higher frequency) 181 } rtc_clk_config_t; 182 183 /** 184 * Default initializer for rtc_clk_config_t 185 */ 186 #define RTC_CLK_CONFIG_DEFAULT() { \ 187 .xtal_freq = CONFIG_XTAL_FREQ, \ 188 .cpu_freq_mhz = 80, \ 189 .fast_clk_src = SOC_RTC_FAST_CLK_SRC_RC_FAST, \ 190 .slow_clk_src = SOC_RTC_SLOW_CLK_SRC_RC_SLOW, \ 191 .clk_rtc_clk_div = 0, \ 192 .clk_8m_clk_div = 0, \ 193 .slow_clk_dcap = RTC_CNTL_SCK_DCAP_DEFAULT, \ 194 .clk_8m_dfreq = RTC_CNTL_CK8M_DFREQ_DEFAULT, \ 195 .rc32k_dfreq = RTC_CNTL_RC32K_DFREQ_DEFAULT, \ 196 } 197 198 /** 199 * Initialize clocks and set CPU frequency 200 * 201 * @param cfg clock configuration as rtc_clk_config_t 202 */ 203 void rtc_clk_init(rtc_clk_config_t cfg); 204 205 /** 206 * @brief Get main XTAL frequency 207 * 208 * This is the value stored in RTC register RTC_XTAL_FREQ_REG by the bootloader. As passed to 209 * rtc_clk_init function 210 * 211 * @return XTAL frequency, one of rtc_xtal_freq_t 212 */ 213 rtc_xtal_freq_t rtc_clk_xtal_freq_get(void); 214 215 /** 216 * @brief Update XTAL frequency 217 * 218 * Updates the XTAL value stored in RTC_XTAL_FREQ_REG. Usually this value is ignored 219 * after startup. 220 * 221 * @param xtal_freq New frequency value 222 */ 223 void rtc_clk_xtal_freq_update(rtc_xtal_freq_t xtal_freq); 224 225 /** 226 * @brief Enable or disable 32 kHz XTAL oscillator 227 * @param en true to enable, false to disable 228 */ 229 void rtc_clk_32k_enable(bool en); 230 231 /** 232 * @brief Configure 32 kHz XTAL oscillator to accept external clock signal 233 */ 234 void rtc_clk_32k_enable_external(void); 235 236 /** 237 * @brief Get the state of 32k XTAL oscillator 238 * @return true if 32k XTAL oscillator has been enabled 239 */ 240 bool rtc_clk_32k_enabled(void); 241 242 /** 243 * @brief Enable 32k oscillator, configuring it for fast startup time. 244 * Note: to achieve higher frequency stability, rtc_clk_32k_enable function 245 * must be called one the 32k XTAL oscillator has started up. This function 246 * will initially disable the 32k XTAL oscillator, so it should not be called 247 * when the system is using 32k XTAL as RTC_SLOW_CLK. 248 * 249 * @param cycle Number of 32kHz cycles to bootstrap external crystal. 250 * If 0, no square wave will be used to bootstrap crystal oscillation. 251 */ 252 void rtc_clk_32k_bootstrap(uint32_t cycle); 253 254 /** 255 * @brief Enable or disable 32 kHz internal rc oscillator 256 * @param en true to enable, false to disable 257 */ 258 void rtc_clk_rc32k_enable(bool enable); 259 260 /** 261 * @brief Enable or disable 8 MHz internal oscillator 262 * 263 * @param clk_8m_en true to enable 8MHz generator 264 */ 265 void rtc_clk_8m_enable(bool clk_8m_en); 266 267 /** 268 * @brief Get the state of 8 MHz internal oscillator 269 * @return true if the oscillator is enabled 270 */ 271 bool rtc_clk_8m_enabled(void); 272 273 /** 274 * @brief Select source for RTC_SLOW_CLK 275 * @param clk_src clock source (one of soc_rtc_slow_clk_src_t values) 276 */ 277 void rtc_clk_slow_src_set(soc_rtc_slow_clk_src_t clk_src); 278 279 /** 280 * @brief Get the RTC_SLOW_CLK source 281 * @return currently selected clock source (one of soc_rtc_slow_clk_src_t values) 282 */ 283 soc_rtc_slow_clk_src_t rtc_clk_slow_src_get(void); 284 285 /** 286 * @brief Get the approximate frequency of RTC_SLOW_CLK, in Hz 287 * 288 * - if SOC_RTC_SLOW_CLK_SRC_RC_SLOW is selected, returns 136000 289 * - if SOC_RTC_SLOW_CLK_SRC_XTAL32K is selected, returns 32768 290 * - if SOC_RTC_SLOW_CLK_SRC_RC32K is selected, returns 32768 291 * - if SOC_RTC_SLOW_CLK_SRC_OSC_SLOW is selected, returns 32768 292 * 293 * rtc_clk_cal function can be used to get more precise value by comparing 294 * RTC_SLOW_CLK frequency to the frequency of main XTAL. 295 * 296 * @return RTC_SLOW_CLK frequency, in Hz 297 */ 298 uint32_t rtc_clk_slow_freq_get_hz(void); 299 300 /** 301 * @brief Select source for RTC_FAST_CLK 302 * @param clk_src clock source (one of soc_rtc_fast_clk_src_t values) 303 */ 304 void rtc_clk_fast_src_set(soc_rtc_fast_clk_src_t clk_src); 305 306 /** 307 * @brief Get the RTC_FAST_CLK source 308 * @return currently selected clock source (one of soc_rtc_fast_clk_src_t values) 309 */ 310 soc_rtc_fast_clk_src_t rtc_clk_fast_src_get(void); 311 312 /** 313 * @brief Get CPU frequency config for a given frequency 314 * @param freq_mhz Frequency in MHz 315 * @param[out] out_config Output, CPU frequency configuration structure 316 * @return true if frequency can be obtained, false otherwise 317 */ 318 bool rtc_clk_cpu_freq_mhz_to_config(uint32_t freq_mhz, rtc_cpu_freq_config_t *out_config); 319 320 /** 321 * @brief Switch CPU frequency 322 * 323 * This function sets CPU frequency according to the given configuration 324 * structure. It enables PLLs, if necessary. 325 * 326 * @note This function in not intended to be called by applications in FreeRTOS 327 * environment. This is because it does not adjust various timers based on the 328 * new CPU frequency. 329 * 330 * @param config CPU frequency configuration structure 331 */ 332 void rtc_clk_cpu_freq_set_config(const rtc_cpu_freq_config_t *config); 333 334 /** 335 * @brief Switch CPU frequency (optimized for speed) 336 * 337 * This function is a faster equivalent of rtc_clk_cpu_freq_set_config. 338 * It works faster because it does not disable PLLs when switching from PLL to 339 * XTAL and does not enabled them when switching back. If PLL is not already 340 * enabled when this function is called to switch from XTAL to PLL frequency, 341 * or the PLL which is enabled is the wrong one, this function will fall back 342 * to calling rtc_clk_cpu_freq_set_config. 343 * 344 * Unlike rtc_clk_cpu_freq_set_config, this function relies on static data, 345 * so it is less safe to use it e.g. from a panic handler (when memory might 346 * be corrupted). 347 * 348 * @note This function in not intended to be called by applications in FreeRTOS 349 * environment. This is because it does not adjust various timers based on the 350 * new CPU frequency. 351 * 352 * @param config CPU frequency configuration structure 353 */ 354 void rtc_clk_cpu_freq_set_config_fast(const rtc_cpu_freq_config_t *config); 355 356 /** 357 * @brief Get the currently used CPU frequency configuration 358 * @param[out] out_config Output, CPU frequency configuration structure 359 */ 360 void rtc_clk_cpu_freq_get_config(rtc_cpu_freq_config_t *out_config); 361 362 /** 363 * @brief Switch CPU clock source to XTAL 364 * 365 * Short form for filling in rtc_cpu_freq_config_t structure and calling 366 * rtc_clk_cpu_freq_set_config when a switch to XTAL is needed. 367 * Assumes that XTAL frequency has been determined — don't call in startup code. 368 * 369 * @note This function always disables BBPLL after switching the CPU clock source to XTAL for power saving purpose. 370 * If this is unwanted, please use rtc_clk_cpu_freq_set_config. It helps to check whether USB Serial JTAG is in use, 371 * if so, then BBPLL will not be turned off. 372 */ 373 void rtc_clk_cpu_freq_set_xtal(void); 374 375 /** 376 * @brief Switch root clock source to PLL (only used by sleep) release root clock source locked by PMU 377 * 378 * wifi receiving beacon frame in PMU modem state strongly depends on the BBPLL 379 * clock, PMU will forcibly lock the root clock source as PLL, when the root 380 * clock source of the software system is selected as PLL, we need to release 381 * the root clock source locking and switch the root clock source to PLL in the 382 * sleep process (a critical section). 383 * 384 * @param[in] Maximum CPU frequency, in MHz 385 */ 386 void rtc_clk_cpu_freq_to_pll_and_pll_lock_release(int cpu_freq_mhz); 387 388 /** 389 * @brief Get the current APB frequency. 390 * @return The calculated APB frequency value, in Hz. 391 */ 392 uint32_t rtc_clk_apb_freq_get(void); 393 394 /** 395 * @brief Measure RTC slow clock's period, based on main XTAL frequency 396 * 397 * This function will time out and return 0 if the time for the given number 398 * of cycles to be counted exceeds the expected time twice. This may happen if 399 * 32k XTAL is being calibrated, but the oscillator has not started up (due to 400 * incorrect loading capacitance, board design issue, or lack of 32 XTAL on board). 401 * 402 * @note When 32k CLK is being calibrated, this function will check the accuracy 403 * of the clock. Since the xtal 32k or ext osc 32k is generally very stable, if 404 * the check fails, then consider this an invalid 32k clock and return 0. This 405 * check can filter some jamming signal. 406 * 407 * @param cal_clk clock to be measured 408 * @param slow_clk_cycles number of slow clock cycles to average 409 * @return average slow clock period in microseconds, Q13.19 fixed point format, 410 * or 0 if calibration has timed out 411 */ 412 uint32_t rtc_clk_cal(rtc_cal_sel_t cal_clk, uint32_t slow_clk_cycles); 413 414 /** 415 * @brief Convert time interval from microseconds to RTC_SLOW_CLK cycles 416 * @param time_in_us Time interval in microseconds 417 * @param slow_clk_period Period of slow clock in microseconds, Q13.19 418 * fixed point format (as returned by rtc_slowck_cali). 419 * @return number of slow clock cycles 420 */ 421 uint64_t rtc_time_us_to_slowclk(uint64_t time_in_us, uint32_t period); 422 423 /** 424 * @brief Convert time interval from RTC_SLOW_CLK to microseconds 425 * @param time_in_us Time interval in RTC_SLOW_CLK cycles 426 * @param slow_clk_period Period of slow clock in microseconds, Q13.19 427 * fixed point format (as returned by rtc_slowck_cali). 428 * @return time interval in microseconds 429 */ 430 uint64_t rtc_time_slowclk_to_us(uint64_t rtc_cycles, uint32_t period); 431 432 /** 433 * @brief Get current value of RTC counter 434 * 435 * RTC has a 48-bit counter which is incremented by 2 every 2 RTC_SLOW_CLK 436 * cycles. Counter value is not writable by software. The value is not adjusted 437 * when switching to a different RTC_SLOW_CLK source. 438 * 439 * Note: this function may take up to 1 RTC_SLOW_CLK cycle to execute 440 * 441 * @return current value of RTC counter 442 */ 443 uint64_t rtc_time_get(void); 444 445 /** 446 * @brief Busy loop until next RTC_SLOW_CLK cycle 447 * 448 * This function returns not earlier than the next RTC_SLOW_CLK clock cycle. 449 * In some cases (e.g. when RTC_SLOW_CLK cycle is very close), it may return 450 * one RTC_SLOW_CLK cycle later. 451 */ 452 void rtc_clk_wait_for_slow_cycle(void); 453 454 /** 455 * @brief Enable the rtc digital 8M clock 456 * 457 * This function is used to enable the digital rtc 8M clock to support peripherals. 458 * For enabling the analog 8M clock, using `rtc_clk_8M_enable` function above. 459 */ 460 void rtc_dig_clk8m_enable(void); 461 462 /** 463 * @brief Disable the rtc digital 8M clock 464 * 465 * This function is used to disable the digital rtc 8M clock, which is only used to support peripherals. 466 */ 467 void rtc_dig_clk8m_disable(void); 468 469 /** 470 * @brief Get whether the rtc digital 8M clock is enabled 471 */ 472 bool rtc_dig_8m_enabled(void); 473 474 /** 475 * @brief Calculate the real clock value after the clock calibration 476 * 477 * @param cal_val Average slow clock period in microseconds, fixed point value as returned from `rtc_clk_cal` 478 * @return Frequency of the clock in Hz 479 */ 480 uint32_t rtc_clk_freq_cal(uint32_t cal_val); 481 482 /** 483 * @brief: Initialize the ICG map of some modem clock domains in the PMU_ACTIVE state 484 */ 485 void rtc_clk_modem_clock_domain_active_state_icg_map_preinit(void); 486 487 // -------------------------- CLOCK TREE DEFS ALIAS ---------------------------- 488 // **WARNING**: The following are only for backwards compatibility. 489 // Please use the declarations in soc/clk_tree_defs.h instead. 490 /** 491 * @brief CPU clock source 492 */ 493 typedef soc_cpu_clk_src_t rtc_cpu_freq_src_t; 494 #define RTC_CPU_FREQ_SRC_XTAL SOC_CPU_CLK_SRC_XTAL //!< XTAL 495 #define RTC_CPU_FREQ_SRC_PLL SOC_CPU_CLK_SRC_PLL //!< PLL (480M) 496 #define RTC_CPU_FREQ_SRC_8M SOC_CPU_CLK_SRC_RC_FAST //!< Internal 17.5M RTC oscillator 497 498 /** 499 * @brief RTC SLOW_CLK frequency values 500 */ 501 typedef soc_rtc_slow_clk_src_t rtc_slow_freq_t; 502 #define RTC_SLOW_FREQ_RTC SOC_RTC_SLOW_CLK_SRC_RC_SLOW //!< Internal 150 kHz RC oscillator 503 #define RTC_SLOW_FREQ_32K_XTAL SOC_RTC_SLOW_CLK_SRC_XTAL32K //!< External 32 kHz XTAL 504 505 /** 506 * @brief RTC FAST_CLK frequency values 507 */ 508 typedef soc_rtc_fast_clk_src_t rtc_fast_freq_t; 509 #define RTC_FAST_FREQ_XTALD4 SOC_RTC_FAST_CLK_SRC_XTAL_DIV //!< Main XTAL, divided by 2 510 #define RTC_FAST_FREQ_8M SOC_RTC_FAST_CLK_SRC_RC_FAST //!< Internal 17.5 MHz RC oscillator 511 512 /* Alias of frequency related macros */ 513 #define RTC_FAST_CLK_FREQ_APPROX SOC_CLK_RC_FAST_FREQ_APPROX 514 #define RTC_FAST_CLK_FREQ_8M SOC_CLK_RC_FAST_FREQ_APPROX 515 #define RTC_SLOW_CLK_FREQ_150K SOC_CLK_RC_SLOW_FREQ_APPROX 516 #define RTC_SLOW_CLK_FREQ_32K SOC_CLK_XTAL32K_FREQ_APPROX 517 518 /* Alias of deprecated function names */ 519 #define rtc_clk_slow_freq_set(slow_freq) rtc_clk_slow_src_set(slow_freq) 520 #define rtc_clk_slow_freq_get() rtc_clk_slow_src_get() 521 #define rtc_clk_fast_freq_set(fast_freq) rtc_clk_fast_src_set(fast_freq) 522 #define rtc_clk_fast_freq_get() rtc_clk_fast_src_get() 523 524 #ifdef __cplusplus 525 } 526 #endif 527
