1 // Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD 2 // 3 // Licensed under the Apache License, Version 2.0 (the "License"); 4 // you may not use this file except in compliance with the License. 5 // You may obtain a copy of the License at 6 // 7 // http://www.apache.org/licenses/LICENSE-2.0 8 // 9 // Unless required by applicable law or agreed to in writing, software 10 // distributed under the License is distributed on an "AS IS" BASIS, 11 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 // See the License for the specific language governing permissions and 13 // limitations under the License. 14 #ifndef _SOC_RTC_CNTL_REG_H_ 15 #define _SOC_RTC_CNTL_REG_H_ 16 17 /* The value that needs to be written to RTC_CNTL_WDT_WKEY to write-enable the wdt registers */ 18 #define RTC_CNTL_WDT_WKEY_VALUE 0x50D83AA1 19 20 /* Possible values for RTC_CNTL_WDT_CPU_RESET_LENGTH and RTC_CNTL_WDT_SYS_RESET_LENGTH */ 21 #define RTC_WDT_RESET_LENGTH_100_NS 0 22 #define RTC_WDT_RESET_LENGTH_200_NS 1 23 #define RTC_WDT_RESET_LENGTH_300_NS 2 24 #define RTC_WDT_RESET_LENGTH_400_NS 3 25 #define RTC_WDT_RESET_LENGTH_500_NS 4 26 #define RTC_WDT_RESET_LENGTH_800_NS 5 27 #define RTC_WDT_RESET_LENGTH_1600_NS 6 28 #define RTC_WDT_RESET_LENGTH_3200_NS 7 29 30 #ifdef __cplusplus 31 extern "C" { 32 #endif 33 #include "soc.h" 34 #define RTC_CNTL_TIME0_REG RTC_CNTL_TIME_LOW0_REG 35 #define RTC_CNTL_TIME1_REG RTC_CNTL_TIME_HIGH0_REG 36 37 #define RTC_CNTL_OPTIONS0_REG (DR_REG_RTCCNTL_BASE + 0x0000) 38 /* RTC_CNTL_SW_SYS_RST : WO ;bitpos:[31] ;default: 1'd0 ; */ 39 /*description: SW system reset*/ 40 #define RTC_CNTL_SW_SYS_RST (BIT(31)) 41 #define RTC_CNTL_SW_SYS_RST_M (BIT(31)) 42 #define RTC_CNTL_SW_SYS_RST_V 0x1 43 #define RTC_CNTL_SW_SYS_RST_S 31 44 /* RTC_CNTL_DG_WRAP_FORCE_NORST : R/W ;bitpos:[30] ;default: 1'd0 ; */ 45 /*description: digital core force no reset in deep sleep*/ 46 #define RTC_CNTL_DG_WRAP_FORCE_NORST (BIT(30)) 47 #define RTC_CNTL_DG_WRAP_FORCE_NORST_M (BIT(30)) 48 #define RTC_CNTL_DG_WRAP_FORCE_NORST_V 0x1 49 #define RTC_CNTL_DG_WRAP_FORCE_NORST_S 30 50 /* RTC_CNTL_DG_WRAP_FORCE_RST : R/W ;bitpos:[29] ;default: 1'd0 ; */ 51 /*description: digital wrap force reset in deep sleep*/ 52 #define RTC_CNTL_DG_WRAP_FORCE_RST (BIT(29)) 53 #define RTC_CNTL_DG_WRAP_FORCE_RST_M (BIT(29)) 54 #define RTC_CNTL_DG_WRAP_FORCE_RST_V 0x1 55 #define RTC_CNTL_DG_WRAP_FORCE_RST_S 29 56 /* RTC_CNTL_ANALOG_FORCE_NOISO : R/W ;bitpos:[28] ;default: 1'd1 ; */ 57 /*description: */ 58 #define RTC_CNTL_ANALOG_FORCE_NOISO (BIT(28)) 59 #define RTC_CNTL_ANALOG_FORCE_NOISO_M (BIT(28)) 60 #define RTC_CNTL_ANALOG_FORCE_NOISO_V 0x1 61 #define RTC_CNTL_ANALOG_FORCE_NOISO_S 28 62 /* RTC_CNTL_PLL_FORCE_NOISO : R/W ;bitpos:[27] ;default: 1'd1 ; */ 63 /*description: */ 64 #define RTC_CNTL_PLL_FORCE_NOISO (BIT(27)) 65 #define RTC_CNTL_PLL_FORCE_NOISO_M (BIT(27)) 66 #define RTC_CNTL_PLL_FORCE_NOISO_V 0x1 67 #define RTC_CNTL_PLL_FORCE_NOISO_S 27 68 /* RTC_CNTL_XTL_FORCE_NOISO : R/W ;bitpos:[26] ;default: 1'd1 ; */ 69 /*description: */ 70 #define RTC_CNTL_XTL_FORCE_NOISO (BIT(26)) 71 #define RTC_CNTL_XTL_FORCE_NOISO_M (BIT(26)) 72 #define RTC_CNTL_XTL_FORCE_NOISO_V 0x1 73 #define RTC_CNTL_XTL_FORCE_NOISO_S 26 74 /* RTC_CNTL_ANALOG_FORCE_ISO : R/W ;bitpos:[25] ;default: 1'd0 ; */ 75 /*description: */ 76 #define RTC_CNTL_ANALOG_FORCE_ISO (BIT(25)) 77 #define RTC_CNTL_ANALOG_FORCE_ISO_M (BIT(25)) 78 #define RTC_CNTL_ANALOG_FORCE_ISO_V 0x1 79 #define RTC_CNTL_ANALOG_FORCE_ISO_S 25 80 /* RTC_CNTL_PLL_FORCE_ISO : R/W ;bitpos:[24] ;default: 1'd0 ; */ 81 /*description: */ 82 #define RTC_CNTL_PLL_FORCE_ISO (BIT(24)) 83 #define RTC_CNTL_PLL_FORCE_ISO_M (BIT(24)) 84 #define RTC_CNTL_PLL_FORCE_ISO_V 0x1 85 #define RTC_CNTL_PLL_FORCE_ISO_S 24 86 /* RTC_CNTL_XTL_FORCE_ISO : R/W ;bitpos:[23] ;default: 1'd0 ; */ 87 /*description: */ 88 #define RTC_CNTL_XTL_FORCE_ISO (BIT(23)) 89 #define RTC_CNTL_XTL_FORCE_ISO_M (BIT(23)) 90 #define RTC_CNTL_XTL_FORCE_ISO_V 0x1 91 #define RTC_CNTL_XTL_FORCE_ISO_S 23 92 /* RTC_CNTL_XTL_EN_WAIT : R/W ;bitpos:[17:14] ;default: 4'd2 ; */ 93 /*description: wait bias_sleep and current source wakeup*/ 94 #define RTC_CNTL_XTL_EN_WAIT 0x0000000F 95 #define RTC_CNTL_XTL_EN_WAIT_M ((RTC_CNTL_XTL_EN_WAIT_V)<<(RTC_CNTL_XTL_EN_WAIT_S)) 96 #define RTC_CNTL_XTL_EN_WAIT_V 0xF 97 #define RTC_CNTL_XTL_EN_WAIT_S 14 98 /* RTC_CNTL_XTL_FORCE_PU : R/W ;bitpos:[13] ;default: 1'd1 ; */ 99 /*description: crystall force power up*/ 100 #define RTC_CNTL_XTL_FORCE_PU (BIT(13)) 101 #define RTC_CNTL_XTL_FORCE_PU_M (BIT(13)) 102 #define RTC_CNTL_XTL_FORCE_PU_V 0x1 103 #define RTC_CNTL_XTL_FORCE_PU_S 13 104 /* RTC_CNTL_XTL_FORCE_PD : R/W ;bitpos:[12] ;default: 1'b0 ; */ 105 /*description: crystall force power down*/ 106 #define RTC_CNTL_XTL_FORCE_PD (BIT(12)) 107 #define RTC_CNTL_XTL_FORCE_PD_M (BIT(12)) 108 #define RTC_CNTL_XTL_FORCE_PD_V 0x1 109 #define RTC_CNTL_XTL_FORCE_PD_S 12 110 /* RTC_CNTL_BBPLL_FORCE_PU : R/W ;bitpos:[11] ;default: 1'd0 ; */ 111 /*description: BB_PLL force power up*/ 112 #define RTC_CNTL_BBPLL_FORCE_PU (BIT(11)) 113 #define RTC_CNTL_BBPLL_FORCE_PU_M (BIT(11)) 114 #define RTC_CNTL_BBPLL_FORCE_PU_V 0x1 115 #define RTC_CNTL_BBPLL_FORCE_PU_S 11 116 /* RTC_CNTL_BBPLL_FORCE_PD : R/W ;bitpos:[10] ;default: 1'b0 ; */ 117 /*description: BB_PLL force power down*/ 118 #define RTC_CNTL_BBPLL_FORCE_PD (BIT(10)) 119 #define RTC_CNTL_BBPLL_FORCE_PD_M (BIT(10)) 120 #define RTC_CNTL_BBPLL_FORCE_PD_V 0x1 121 #define RTC_CNTL_BBPLL_FORCE_PD_S 10 122 /* RTC_CNTL_BBPLL_I2C_FORCE_PU : R/W ;bitpos:[9] ;default: 1'd0 ; */ 123 /*description: BB_PLL_I2C force power up*/ 124 #define RTC_CNTL_BBPLL_I2C_FORCE_PU (BIT(9)) 125 #define RTC_CNTL_BBPLL_I2C_FORCE_PU_M (BIT(9)) 126 #define RTC_CNTL_BBPLL_I2C_FORCE_PU_V 0x1 127 #define RTC_CNTL_BBPLL_I2C_FORCE_PU_S 9 128 /* RTC_CNTL_BBPLL_I2C_FORCE_PD : R/W ;bitpos:[8] ;default: 1'b0 ; */ 129 /*description: BB_PLL _I2C force power down*/ 130 #define RTC_CNTL_BBPLL_I2C_FORCE_PD (BIT(8)) 131 #define RTC_CNTL_BBPLL_I2C_FORCE_PD_M (BIT(8)) 132 #define RTC_CNTL_BBPLL_I2C_FORCE_PD_V 0x1 133 #define RTC_CNTL_BBPLL_I2C_FORCE_PD_S 8 134 /* RTC_CNTL_BB_I2C_FORCE_PU : R/W ;bitpos:[7] ;default: 1'd0 ; */ 135 /*description: BB_I2C force power up*/ 136 #define RTC_CNTL_BB_I2C_FORCE_PU (BIT(7)) 137 #define RTC_CNTL_BB_I2C_FORCE_PU_M (BIT(7)) 138 #define RTC_CNTL_BB_I2C_FORCE_PU_V 0x1 139 #define RTC_CNTL_BB_I2C_FORCE_PU_S 7 140 /* RTC_CNTL_BB_I2C_FORCE_PD : R/W ;bitpos:[6] ;default: 1'b0 ; */ 141 /*description: BB_I2C force power down*/ 142 #define RTC_CNTL_BB_I2C_FORCE_PD (BIT(6)) 143 #define RTC_CNTL_BB_I2C_FORCE_PD_M (BIT(6)) 144 #define RTC_CNTL_BB_I2C_FORCE_PD_V 0x1 145 #define RTC_CNTL_BB_I2C_FORCE_PD_S 6 146 /* RTC_CNTL_SW_PROCPU_RST : WO ;bitpos:[5] ;default: 1'b0 ; */ 147 /*description: PRO CPU SW reset*/ 148 #define RTC_CNTL_SW_PROCPU_RST (BIT(5)) 149 #define RTC_CNTL_SW_PROCPU_RST_M (BIT(5)) 150 #define RTC_CNTL_SW_PROCPU_RST_V 0x1 151 #define RTC_CNTL_SW_PROCPU_RST_S 5 152 /* RTC_CNTL_SW_APPCPU_RST : WO ;bitpos:[4] ;default: 1'b0 ; */ 153 /*description: APP CPU SW reset*/ 154 #define RTC_CNTL_SW_APPCPU_RST (BIT(4)) 155 #define RTC_CNTL_SW_APPCPU_RST_M (BIT(4)) 156 #define RTC_CNTL_SW_APPCPU_RST_V 0x1 157 #define RTC_CNTL_SW_APPCPU_RST_S 4 158 /* RTC_CNTL_SW_STALL_PROCPU_C0 : R/W ;bitpos:[3:2] ;default: 2'b0 ; */ 159 /*description: {reg_sw_stall_procpu_c1[5:0] reg_sw_stall_procpu_c0[1:0]} == 160 0x86 will stall PRO CPU*/ 161 #define RTC_CNTL_SW_STALL_PROCPU_C0 0x00000003 162 #define RTC_CNTL_SW_STALL_PROCPU_C0_M ((RTC_CNTL_SW_STALL_PROCPU_C0_V)<<(RTC_CNTL_SW_STALL_PROCPU_C0_S)) 163 #define RTC_CNTL_SW_STALL_PROCPU_C0_V 0x3 164 #define RTC_CNTL_SW_STALL_PROCPU_C0_S 2 165 /* RTC_CNTL_SW_STALL_APPCPU_C0 : R/W ;bitpos:[1:0] ;default: 2'b0 ; */ 166 /*description: {reg_sw_stall_appcpu_c1[5:0] reg_sw_stall_appcpu_c0[1:0]} == 167 0x86 will stall APP CPU*/ 168 #define RTC_CNTL_SW_STALL_APPCPU_C0 0x00000003 169 #define RTC_CNTL_SW_STALL_APPCPU_C0_M ((RTC_CNTL_SW_STALL_APPCPU_C0_V)<<(RTC_CNTL_SW_STALL_APPCPU_C0_S)) 170 #define RTC_CNTL_SW_STALL_APPCPU_C0_V 0x3 171 #define RTC_CNTL_SW_STALL_APPCPU_C0_S 0 172 173 #define RTC_CNTL_SLP_TIMER0_REG (DR_REG_RTCCNTL_BASE + 0x0004) 174 /* RTC_CNTL_SLP_VAL_LO : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ 175 /*description: RTC sleep timer low 32 bits*/ 176 #define RTC_CNTL_SLP_VAL_LO 0xFFFFFFFF 177 #define RTC_CNTL_SLP_VAL_LO_M ((RTC_CNTL_SLP_VAL_LO_V)<<(RTC_CNTL_SLP_VAL_LO_S)) 178 #define RTC_CNTL_SLP_VAL_LO_V 0xFFFFFFFF 179 #define RTC_CNTL_SLP_VAL_LO_S 0 180 181 #define RTC_CNTL_SLP_TIMER1_REG (DR_REG_RTCCNTL_BASE + 0x0008) 182 /* RTC_CNTL_MAIN_TIMER_ALARM_EN : WO ;bitpos:[16] ;default: 1'h0 ; */ 183 /*description: timer alarm enable bit*/ 184 #define RTC_CNTL_MAIN_TIMER_ALARM_EN (BIT(16)) 185 #define RTC_CNTL_MAIN_TIMER_ALARM_EN_M (BIT(16)) 186 #define RTC_CNTL_MAIN_TIMER_ALARM_EN_V 0x1 187 #define RTC_CNTL_MAIN_TIMER_ALARM_EN_S 16 188 /* RTC_CNTL_SLP_VAL_HI : R/W ;bitpos:[15:0] ;default: 16'h0 ; */ 189 /*description: RTC sleep timer high 16 bits*/ 190 #define RTC_CNTL_SLP_VAL_HI 0x0000FFFF 191 #define RTC_CNTL_SLP_VAL_HI_M ((RTC_CNTL_SLP_VAL_HI_V)<<(RTC_CNTL_SLP_VAL_HI_S)) 192 #define RTC_CNTL_SLP_VAL_HI_V 0xFFFF 193 #define RTC_CNTL_SLP_VAL_HI_S 0 194 195 #define RTC_CNTL_TIME_UPDATE_REG (DR_REG_RTCCNTL_BASE + 0x000C) 196 /* RTC_CNTL_TIME_UPDATE : WO ;bitpos:[31] ;default: 1'h0 ; */ 197 /*description: Set 1: to update register with RTC timer*/ 198 #define RTC_CNTL_TIME_UPDATE (BIT(31)) 199 #define RTC_CNTL_TIME_UPDATE_M (BIT(31)) 200 #define RTC_CNTL_TIME_UPDATE_V 0x1 201 #define RTC_CNTL_TIME_UPDATE_S 31 202 /* RTC_CNTL_TIMER_SYS_RST : R/W ;bitpos:[29] ;default: 1'b0 ; */ 203 /*description: enable to record system reset time*/ 204 #define RTC_CNTL_TIMER_SYS_RST (BIT(29)) 205 #define RTC_CNTL_TIMER_SYS_RST_M (BIT(29)) 206 #define RTC_CNTL_TIMER_SYS_RST_V 0x1 207 #define RTC_CNTL_TIMER_SYS_RST_S 29 208 /* RTC_CNTL_TIMER_XTL_OFF : R/W ;bitpos:[28] ;default: 1'b0 ; */ 209 /*description: Enable to record 40M XTAL OFF time*/ 210 #define RTC_CNTL_TIMER_XTL_OFF (BIT(28)) 211 #define RTC_CNTL_TIMER_XTL_OFF_M (BIT(28)) 212 #define RTC_CNTL_TIMER_XTL_OFF_V 0x1 213 #define RTC_CNTL_TIMER_XTL_OFF_S 28 214 /* RTC_CNTL_TIMER_SYS_STALL : R/W ;bitpos:[27] ;default: 1'b0 ; */ 215 /*description: Enable to record system stall time*/ 216 #define RTC_CNTL_TIMER_SYS_STALL (BIT(27)) 217 #define RTC_CNTL_TIMER_SYS_STALL_M (BIT(27)) 218 #define RTC_CNTL_TIMER_SYS_STALL_V 0x1 219 #define RTC_CNTL_TIMER_SYS_STALL_S 27 220 221 #define RTC_CNTL_TIME_LOW0_REG (DR_REG_RTCCNTL_BASE + 0x0010) 222 /* RTC_CNTL_TIMER_VALUE0_LOW : RO ;bitpos:[31:0] ;default: 32'h0 ; */ 223 /*description: RTC timer low 32 bits*/ 224 #define RTC_CNTL_TIMER_VALUE0_LOW 0xFFFFFFFF 225 #define RTC_CNTL_TIMER_VALUE0_LOW_M ((RTC_CNTL_TIMER_VALUE0_LOW_V)<<(RTC_CNTL_TIMER_VALUE0_LOW_S)) 226 #define RTC_CNTL_TIMER_VALUE0_LOW_V 0xFFFFFFFF 227 #define RTC_CNTL_TIMER_VALUE0_LOW_S 0 228 229 #define RTC_CNTL_TIME_HIGH0_REG (DR_REG_RTCCNTL_BASE + 0x0014) 230 /* RTC_CNTL_TIMER_VALUE0_HIGH : RO ;bitpos:[15:0] ;default: 16'h0 ; */ 231 /*description: RTC timer high 16 bits*/ 232 #define RTC_CNTL_TIMER_VALUE0_HIGH 0x0000FFFF 233 #define RTC_CNTL_TIMER_VALUE0_HIGH_M ((RTC_CNTL_TIMER_VALUE0_HIGH_V)<<(RTC_CNTL_TIMER_VALUE0_HIGH_S)) 234 #define RTC_CNTL_TIMER_VALUE0_HIGH_V 0xFFFF 235 #define RTC_CNTL_TIMER_VALUE0_HIGH_S 0 236 237 #define RTC_CNTL_STATE0_REG (DR_REG_RTCCNTL_BASE + 0x0018) 238 /* RTC_CNTL_SLEEP_EN : R/W ;bitpos:[31] ;default: 1'd0 ; */ 239 /*description: sleep enable bit*/ 240 #define RTC_CNTL_SLEEP_EN (BIT(31)) 241 #define RTC_CNTL_SLEEP_EN_M (BIT(31)) 242 #define RTC_CNTL_SLEEP_EN_V 0x1 243 #define RTC_CNTL_SLEEP_EN_S 31 244 /* RTC_CNTL_SLP_REJECT : R/W ;bitpos:[30] ;default: 1'd0 ; */ 245 /*description: leep reject bit*/ 246 #define RTC_CNTL_SLP_REJECT (BIT(30)) 247 #define RTC_CNTL_SLP_REJECT_M (BIT(30)) 248 #define RTC_CNTL_SLP_REJECT_V 0x1 249 #define RTC_CNTL_SLP_REJECT_S 30 250 /* RTC_CNTL_SLP_WAKEUP : R/W ;bitpos:[29] ;default: 1'd0 ; */ 251 /*description: leep wakeup bit*/ 252 #define RTC_CNTL_SLP_WAKEUP (BIT(29)) 253 #define RTC_CNTL_SLP_WAKEUP_M (BIT(29)) 254 #define RTC_CNTL_SLP_WAKEUP_V 0x1 255 #define RTC_CNTL_SLP_WAKEUP_S 29 256 /* RTC_CNTL_SDIO_ACTIVE_IND : RO ;bitpos:[28] ;default: 1'd0 ; */ 257 /*description: SDIO active indication*/ 258 #define RTC_CNTL_SDIO_ACTIVE_IND (BIT(28)) 259 #define RTC_CNTL_SDIO_ACTIVE_IND_M (BIT(28)) 260 #define RTC_CNTL_SDIO_ACTIVE_IND_V 0x1 261 #define RTC_CNTL_SDIO_ACTIVE_IND_S 28 262 /* RTC_CNTL_APB2RTC_BRIDGE_SEL : R/W ;bitpos:[22] ;default: 1'd0 ; */ 263 /*description: 1: APB to RTC using bridge 0: APB to RTC using sync*/ 264 #define RTC_CNTL_APB2RTC_BRIDGE_SEL (BIT(22)) 265 #define RTC_CNTL_APB2RTC_BRIDGE_SEL_M (BIT(22)) 266 #define RTC_CNTL_APB2RTC_BRIDGE_SEL_V 0x1 267 #define RTC_CNTL_APB2RTC_BRIDGE_SEL_S 22 268 /* RTC_CNTL_SLP_REJECT_CAUSE_CLR : WO ;bitpos:[1] ;default: 1'b0 ; */ 269 /*description: clear rtc sleep reject cause*/ 270 #define RTC_CNTL_SLP_REJECT_CAUSE_CLR (BIT(1)) 271 #define RTC_CNTL_SLP_REJECT_CAUSE_CLR_M (BIT(1)) 272 #define RTC_CNTL_SLP_REJECT_CAUSE_CLR_V 0x1 273 #define RTC_CNTL_SLP_REJECT_CAUSE_CLR_S 1 274 /* RTC_CNTL_SW_CPU_INT : WO ;bitpos:[0] ;default: 1'b0 ; */ 275 /*description: rtc software interrupt to main cpu*/ 276 #define RTC_CNTL_SW_CPU_INT (BIT(0)) 277 #define RTC_CNTL_SW_CPU_INT_M (BIT(0)) 278 #define RTC_CNTL_SW_CPU_INT_V 0x1 279 #define RTC_CNTL_SW_CPU_INT_S 0 280 281 #define RTC_CNTL_TIMER1_REG (DR_REG_RTCCNTL_BASE + 0x001C) 282 /* RTC_CNTL_PLL_BUF_WAIT : R/W ;bitpos:[31:24] ;default: 8'd40 ; */ 283 /*description: PLL wait cycles in slow_clk_rtc*/ 284 #define RTC_CNTL_PLL_BUF_WAIT 0x000000FF 285 #define RTC_CNTL_PLL_BUF_WAIT_M ((RTC_CNTL_PLL_BUF_WAIT_V)<<(RTC_CNTL_PLL_BUF_WAIT_S)) 286 #define RTC_CNTL_PLL_BUF_WAIT_V 0xFF 287 #define RTC_CNTL_PLL_BUF_WAIT_S 24 288 /* RTC_CNTL_XTL_BUF_WAIT : R/W ;bitpos:[23:14] ;default: 10'd80 ; */ 289 /*description: XTAL wait cycles in slow_clk_rtc*/ 290 #define RTC_CNTL_XTL_BUF_WAIT 0x000003FF 291 #define RTC_CNTL_XTL_BUF_WAIT_M ((RTC_CNTL_XTL_BUF_WAIT_V)<<(RTC_CNTL_XTL_BUF_WAIT_S)) 292 #define RTC_CNTL_XTL_BUF_WAIT_V 0x3FF 293 #define RTC_CNTL_XTL_BUF_WAIT_S 14 294 /* RTC_CNTL_CK8M_WAIT : R/W ;bitpos:[13:6] ;default: 8'h10 ; */ 295 /*description: CK8M wait cycles in slow_clk_rtc*/ 296 #define RTC_CNTL_CK8M_WAIT 0x000000FF 297 #define RTC_CNTL_CK8M_WAIT_M ((RTC_CNTL_CK8M_WAIT_V)<<(RTC_CNTL_CK8M_WAIT_S)) 298 #define RTC_CNTL_CK8M_WAIT_V 0xFF 299 #define RTC_CNTL_CK8M_WAIT_S 6 300 /* RTC_CNTL_CPU_STALL_WAIT : R/W ;bitpos:[5:1] ;default: 5'd1 ; */ 301 /*description: CPU stall wait cycles in fast_clk_rtc*/ 302 #define RTC_CNTL_CPU_STALL_WAIT 0x0000001F 303 #define RTC_CNTL_CPU_STALL_WAIT_M ((RTC_CNTL_CPU_STALL_WAIT_V)<<(RTC_CNTL_CPU_STALL_WAIT_S)) 304 #define RTC_CNTL_CPU_STALL_WAIT_V 0x1F 305 #define RTC_CNTL_CPU_STALL_WAIT_S 1 306 /* RTC_CNTL_CPU_STALL_EN : R/W ;bitpos:[0] ;default: 1'd1 ; */ 307 /*description: CPU stall enable bit*/ 308 #define RTC_CNTL_CPU_STALL_EN (BIT(0)) 309 #define RTC_CNTL_CPU_STALL_EN_M (BIT(0)) 310 #define RTC_CNTL_CPU_STALL_EN_V 0x1 311 #define RTC_CNTL_CPU_STALL_EN_S 0 312 313 #define RTC_CNTL_TIMER2_REG (DR_REG_RTCCNTL_BASE + 0x0020) 314 /* RTC_CNTL_MIN_TIME_CK8M_OFF : R/W ;bitpos:[31:24] ;default: 8'h1 ; */ 315 /*description: minimal cycles in slow_clk_rtc for CK8M in power down state*/ 316 #define RTC_CNTL_MIN_TIME_CK8M_OFF 0x000000FF 317 #define RTC_CNTL_MIN_TIME_CK8M_OFF_M ((RTC_CNTL_MIN_TIME_CK8M_OFF_V)<<(RTC_CNTL_MIN_TIME_CK8M_OFF_S)) 318 #define RTC_CNTL_MIN_TIME_CK8M_OFF_V 0xFF 319 #define RTC_CNTL_MIN_TIME_CK8M_OFF_S 24 320 /* RTC_CNTL_ULPCP_TOUCH_START_WAIT : R/W ;bitpos:[23:15] ;default: 9'h10 ; */ 321 /*description: wait cycles in slow_clk_rtc before ULP-coprocessor / touch controller 322 start to work*/ 323 #define RTC_CNTL_ULPCP_TOUCH_START_WAIT 0x000001FF 324 #define RTC_CNTL_ULPCP_TOUCH_START_WAIT_M ((RTC_CNTL_ULPCP_TOUCH_START_WAIT_V)<<(RTC_CNTL_ULPCP_TOUCH_START_WAIT_S)) 325 #define RTC_CNTL_ULPCP_TOUCH_START_WAIT_V 0x1FF 326 #define RTC_CNTL_ULPCP_TOUCH_START_WAIT_S 15 327 328 #define RTC_CNTL_TIMER3_REG (DR_REG_RTCCNTL_BASE + 0x0024) 329 /* RTC_CNTL_ROM_RAM_POWERUP_TIMER : R/W ;bitpos:[31:25] ;default: 7'd10 ; */ 330 /*description: */ 331 #define RTC_CNTL_ROM_RAM_POWERUP_TIMER 0x0000007F 332 #define RTC_CNTL_ROM_RAM_POWERUP_TIMER_M ((RTC_CNTL_ROM_RAM_POWERUP_TIMER_V)<<(RTC_CNTL_ROM_RAM_POWERUP_TIMER_S)) 333 #define RTC_CNTL_ROM_RAM_POWERUP_TIMER_V 0x7F 334 #define RTC_CNTL_ROM_RAM_POWERUP_TIMER_S 25 335 /* RTC_CNTL_ROM_RAM_WAIT_TIMER : R/W ;bitpos:[24:16] ;default: 9'h16 ; */ 336 /*description: */ 337 #define RTC_CNTL_ROM_RAM_WAIT_TIMER 0x000001FF 338 #define RTC_CNTL_ROM_RAM_WAIT_TIMER_M ((RTC_CNTL_ROM_RAM_WAIT_TIMER_V)<<(RTC_CNTL_ROM_RAM_WAIT_TIMER_S)) 339 #define RTC_CNTL_ROM_RAM_WAIT_TIMER_V 0x1FF 340 #define RTC_CNTL_ROM_RAM_WAIT_TIMER_S 16 341 /* RTC_CNTL_WIFI_POWERUP_TIMER : R/W ;bitpos:[15:9] ;default: 7'h5 ; */ 342 /*description: */ 343 #define RTC_CNTL_WIFI_POWERUP_TIMER 0x0000007F 344 #define RTC_CNTL_WIFI_POWERUP_TIMER_M ((RTC_CNTL_WIFI_POWERUP_TIMER_V)<<(RTC_CNTL_WIFI_POWERUP_TIMER_S)) 345 #define RTC_CNTL_WIFI_POWERUP_TIMER_V 0x7F 346 #define RTC_CNTL_WIFI_POWERUP_TIMER_S 9 347 /* RTC_CNTL_WIFI_WAIT_TIMER : R/W ;bitpos:[8:0] ;default: 9'h8 ; */ 348 /*description: */ 349 #define RTC_CNTL_WIFI_WAIT_TIMER 0x000001FF 350 #define RTC_CNTL_WIFI_WAIT_TIMER_M ((RTC_CNTL_WIFI_WAIT_TIMER_V)<<(RTC_CNTL_WIFI_WAIT_TIMER_S)) 351 #define RTC_CNTL_WIFI_WAIT_TIMER_V 0x1FF 352 #define RTC_CNTL_WIFI_WAIT_TIMER_S 0 353 354 #define RTC_CNTL_TIMER4_REG (DR_REG_RTCCNTL_BASE + 0x0028) 355 /* RTC_CNTL_DG_WRAP_POWERUP_TIMER : R/W ;bitpos:[31:25] ;default: 7'h8 ; */ 356 /*description: */ 357 #define RTC_CNTL_DG_WRAP_POWERUP_TIMER 0x0000007F 358 #define RTC_CNTL_DG_WRAP_POWERUP_TIMER_M ((RTC_CNTL_DG_WRAP_POWERUP_TIMER_V)<<(RTC_CNTL_DG_WRAP_POWERUP_TIMER_S)) 359 #define RTC_CNTL_DG_WRAP_POWERUP_TIMER_V 0x7F 360 #define RTC_CNTL_DG_WRAP_POWERUP_TIMER_S 25 361 /* RTC_CNTL_DG_WRAP_WAIT_TIMER : R/W ;bitpos:[24:16] ;default: 9'h20 ; */ 362 /*description: */ 363 #define RTC_CNTL_DG_WRAP_WAIT_TIMER 0x000001FF 364 #define RTC_CNTL_DG_WRAP_WAIT_TIMER_M ((RTC_CNTL_DG_WRAP_WAIT_TIMER_V)<<(RTC_CNTL_DG_WRAP_WAIT_TIMER_S)) 365 #define RTC_CNTL_DG_WRAP_WAIT_TIMER_V 0x1FF 366 #define RTC_CNTL_DG_WRAP_WAIT_TIMER_S 16 367 /* RTC_CNTL_POWERUP_TIMER : R/W ;bitpos:[15:9] ;default: 7'h5 ; */ 368 /*description: */ 369 #define RTC_CNTL_POWERUP_TIMER 0x0000007F 370 #define RTC_CNTL_POWERUP_TIMER_M ((RTC_CNTL_POWERUP_TIMER_V)<<(RTC_CNTL_POWERUP_TIMER_S)) 371 #define RTC_CNTL_POWERUP_TIMER_V 0x7F 372 #define RTC_CNTL_POWERUP_TIMER_S 9 373 /* RTC_CNTL_WAIT_TIMER : R/W ;bitpos:[8:0] ;default: 9'h8 ; */ 374 /*description: */ 375 #define RTC_CNTL_WAIT_TIMER 0x000001FF 376 #define RTC_CNTL_WAIT_TIMER_M ((RTC_CNTL_WAIT_TIMER_V)<<(RTC_CNTL_WAIT_TIMER_S)) 377 #define RTC_CNTL_WAIT_TIMER_V 0x1FF 378 #define RTC_CNTL_WAIT_TIMER_S 0 379 380 #define RTC_CNTL_TIMER5_REG (DR_REG_RTCCNTL_BASE + 0x002C) 381 /* RTC_CNTL_RTCMEM_POWERUP_TIMER : R/W ;bitpos:[31:25] ;default: 7'h9 ; */ 382 /*description: */ 383 #define RTC_CNTL_RTCMEM_POWERUP_TIMER 0x0000007F 384 #define RTC_CNTL_RTCMEM_POWERUP_TIMER_M ((RTC_CNTL_RTCMEM_POWERUP_TIMER_V)<<(RTC_CNTL_RTCMEM_POWERUP_TIMER_S)) 385 #define RTC_CNTL_RTCMEM_POWERUP_TIMER_V 0x7F 386 #define RTC_CNTL_RTCMEM_POWERUP_TIMER_S 25 387 /* RTC_CNTL_RTCMEM_WAIT_TIMER : R/W ;bitpos:[24:16] ;default: 9'h14 ; */ 388 /*description: */ 389 #define RTC_CNTL_RTCMEM_WAIT_TIMER 0x000001FF 390 #define RTC_CNTL_RTCMEM_WAIT_TIMER_M ((RTC_CNTL_RTCMEM_WAIT_TIMER_V)<<(RTC_CNTL_RTCMEM_WAIT_TIMER_S)) 391 #define RTC_CNTL_RTCMEM_WAIT_TIMER_V 0x1FF 392 #define RTC_CNTL_RTCMEM_WAIT_TIMER_S 16 393 /* RTC_CNTL_MIN_SLP_VAL : R/W ;bitpos:[15:8] ;default: 8'h80 ; */ 394 /*description: minimal sleep cycles in slow_clk_rtc*/ 395 #define RTC_CNTL_MIN_SLP_VAL 0x000000FF 396 #define RTC_CNTL_MIN_SLP_VAL_M ((RTC_CNTL_MIN_SLP_VAL_V)<<(RTC_CNTL_MIN_SLP_VAL_S)) 397 #define RTC_CNTL_MIN_SLP_VAL_V 0xFF 398 #define RTC_CNTL_MIN_SLP_VAL_S 8 399 #define RTC_CNTL_MIN_SLP_VAL_MIN 2 400 401 #define RTC_CNTL_TIMER6_REG (DR_REG_RTCCNTL_BASE + 0x0030) 402 /* RTC_CNTL_DG_DCDC_POWERUP_TIMER : R/W ;bitpos:[31:25] ;default: 7'h8 ; */ 403 /*description: */ 404 #define RTC_CNTL_DG_DCDC_POWERUP_TIMER 0x0000007F 405 #define RTC_CNTL_DG_DCDC_POWERUP_TIMER_M ((RTC_CNTL_DG_DCDC_POWERUP_TIMER_V)<<(RTC_CNTL_DG_DCDC_POWERUP_TIMER_S)) 406 #define RTC_CNTL_DG_DCDC_POWERUP_TIMER_V 0x7F 407 #define RTC_CNTL_DG_DCDC_POWERUP_TIMER_S 25 408 /* RTC_CNTL_DG_DCDC_WAIT_TIMER : R/W ;bitpos:[24:16] ;default: 9'h20 ; */ 409 /*description: */ 410 #define RTC_CNTL_DG_DCDC_WAIT_TIMER 0x000001FF 411 #define RTC_CNTL_DG_DCDC_WAIT_TIMER_M ((RTC_CNTL_DG_DCDC_WAIT_TIMER_V)<<(RTC_CNTL_DG_DCDC_WAIT_TIMER_S)) 412 #define RTC_CNTL_DG_DCDC_WAIT_TIMER_V 0x1FF 413 #define RTC_CNTL_DG_DCDC_WAIT_TIMER_S 16 414 415 #define RTC_CNTL_ANA_CONF_REG (DR_REG_RTCCNTL_BASE + 0x0034) 416 /* RTC_CNTL_PLL_I2C_PU : R/W ;bitpos:[31] ;default: 1'd0 ; */ 417 /*description: */ 418 #define RTC_CNTL_PLL_I2C_PU (BIT(31)) 419 #define RTC_CNTL_PLL_I2C_PU_M (BIT(31)) 420 #define RTC_CNTL_PLL_I2C_PU_V 0x1 421 #define RTC_CNTL_PLL_I2C_PU_S 31 422 /* RTC_CNTL_CKGEN_I2C_PU : R/W ;bitpos:[30] ;default: 1'd0 ; */ 423 /*description: 1: CKGEN_I2C power up otherwise power down*/ 424 #define RTC_CNTL_CKGEN_I2C_PU (BIT(30)) 425 #define RTC_CNTL_CKGEN_I2C_PU_M (BIT(30)) 426 #define RTC_CNTL_CKGEN_I2C_PU_V 0x1 427 #define RTC_CNTL_CKGEN_I2C_PU_S 30 428 /* RTC_CNTL_RFRX_PBUS_PU : R/W ;bitpos:[28] ;default: 1'd0 ; */ 429 /*description: 1: RFRX_PBUS power up otherwise power down*/ 430 #define RTC_CNTL_RFRX_PBUS_PU (BIT(28)) 431 #define RTC_CNTL_RFRX_PBUS_PU_M (BIT(28)) 432 #define RTC_CNTL_RFRX_PBUS_PU_V 0x1 433 #define RTC_CNTL_RFRX_PBUS_PU_S 28 434 /* RTC_CNTL_TXRF_I2C_PU : R/W ;bitpos:[27] ;default: 1'd0 ; */ 435 /*description: 1: TXRF_I2C power up otherwise power down*/ 436 #define RTC_CNTL_TXRF_I2C_PU (BIT(27)) 437 #define RTC_CNTL_TXRF_I2C_PU_M (BIT(27)) 438 #define RTC_CNTL_TXRF_I2C_PU_V 0x1 439 #define RTC_CNTL_TXRF_I2C_PU_S 27 440 /* RTC_CNTL_PVTMON_PU : R/W ;bitpos:[26] ;default: 1'b0 ; */ 441 /*description: 1: PVTMON power up otherwise power down*/ 442 #define RTC_CNTL_PVTMON_PU (BIT(26)) 443 #define RTC_CNTL_PVTMON_PU_M (BIT(26)) 444 #define RTC_CNTL_PVTMON_PU_V 0x1 445 #define RTC_CNTL_PVTMON_PU_S 26 446 /* RTC_CNTL_BBPLL_CAL_SLP_START : R/W ;bitpos:[25] ;default: 1'b0 ; */ 447 /*description: start BBPLL calibration during sleep*/ 448 #define RTC_CNTL_BBPLL_CAL_SLP_START (BIT(25)) 449 #define RTC_CNTL_BBPLL_CAL_SLP_START_M (BIT(25)) 450 #define RTC_CNTL_BBPLL_CAL_SLP_START_V 0x1 451 #define RTC_CNTL_BBPLL_CAL_SLP_START_S 25 452 /* RTC_CNTL_PLLA_FORCE_PU : R/W ;bitpos:[24] ;default: 1'b0 ; */ 453 /*description: PLLA force power up*/ 454 #define RTC_CNTL_PLLA_FORCE_PU (BIT(24)) 455 #define RTC_CNTL_PLLA_FORCE_PU_M (BIT(24)) 456 #define RTC_CNTL_PLLA_FORCE_PU_V 0x1 457 #define RTC_CNTL_PLLA_FORCE_PU_S 24 458 /* RTC_CNTL_PLLA_FORCE_PD : R/W ;bitpos:[23] ;default: 1'b1 ; */ 459 /*description: PLLA force power down*/ 460 #define RTC_CNTL_PLLA_FORCE_PD (BIT(23)) 461 #define RTC_CNTL_PLLA_FORCE_PD_M (BIT(23)) 462 #define RTC_CNTL_PLLA_FORCE_PD_V 0x1 463 #define RTC_CNTL_PLLA_FORCE_PD_S 23 464 /* RTC_CNTL_SAR_I2C_FORCE_PU : R/W ;bitpos:[22] ;default: 1'b0 ; */ 465 /*description: PLLA force power up*/ 466 #define RTC_CNTL_SAR_I2C_FORCE_PU (BIT(22)) 467 #define RTC_CNTL_SAR_I2C_FORCE_PU_M (BIT(22)) 468 #define RTC_CNTL_SAR_I2C_FORCE_PU_V 0x1 469 #define RTC_CNTL_SAR_I2C_FORCE_PU_S 22 470 /* RTC_CNTL_SAR_I2C_FORCE_PD : R/W ;bitpos:[21] ;default: 1'b1 ; */ 471 /*description: PLLA force power down*/ 472 #define RTC_CNTL_SAR_I2C_FORCE_PD (BIT(21)) 473 #define RTC_CNTL_SAR_I2C_FORCE_PD_M (BIT(21)) 474 #define RTC_CNTL_SAR_I2C_FORCE_PD_V 0x1 475 #define RTC_CNTL_SAR_I2C_FORCE_PD_S 21 476 /* RTC_CNTL_GLITCH_RST_EN : R/W ;bitpos:[20] ;default: 1'b0 ; */ 477 /*description: */ 478 #define RTC_CNTL_GLITCH_RST_EN (BIT(20)) 479 #define RTC_CNTL_GLITCH_RST_EN_M (BIT(20)) 480 #define RTC_CNTL_GLITCH_RST_EN_V 0x1 481 #define RTC_CNTL_GLITCH_RST_EN_S 20 482 /* RTC_CNTL_I2C_RESET_POR_FORCE_PU : R/W ;bitpos:[19] ;default: 1'b0 ; */ 483 /*description: */ 484 #define RTC_CNTL_I2C_RESET_POR_FORCE_PU (BIT(19)) 485 #define RTC_CNTL_I2C_RESET_POR_FORCE_PU_M (BIT(19)) 486 #define RTC_CNTL_I2C_RESET_POR_FORCE_PU_V 0x1 487 #define RTC_CNTL_I2C_RESET_POR_FORCE_PU_S 19 488 /* RTC_CNTL_I2C_RESET_POR_FORCE_PD : R/W ;bitpos:[18] ;default: 1'b1 ; */ 489 /*description: */ 490 #define RTC_CNTL_I2C_RESET_POR_FORCE_PD (BIT(18)) 491 #define RTC_CNTL_I2C_RESET_POR_FORCE_PD_M (BIT(18)) 492 #define RTC_CNTL_I2C_RESET_POR_FORCE_PD_V 0x1 493 #define RTC_CNTL_I2C_RESET_POR_FORCE_PD_S 18 494 495 #define RTC_CNTL_RESET_STATE_REG (DR_REG_RTCCNTL_BASE + 0x0038) 496 /* RTC_CNTL_PROCPU_STAT_VECTOR_SEL : R/W ;bitpos:[13] ;default: 1'b1 ; */ 497 /*description: PRO CPU state vector sel*/ 498 #define RTC_CNTL_PROCPU_STAT_VECTOR_SEL (BIT(13)) 499 #define RTC_CNTL_PROCPU_STAT_VECTOR_SEL_M (BIT(13)) 500 #define RTC_CNTL_PROCPU_STAT_VECTOR_SEL_V 0x1 501 #define RTC_CNTL_PROCPU_STAT_VECTOR_SEL_S 13 502 /* RTC_CNTL_APPCPU_STAT_VECTOR_SEL : R/W ;bitpos:[12] ;default: 1'b1 ; */ 503 /*description: APP CPU state vector sel*/ 504 #define RTC_CNTL_APPCPU_STAT_VECTOR_SEL (BIT(12)) 505 #define RTC_CNTL_APPCPU_STAT_VECTOR_SEL_M (BIT(12)) 506 #define RTC_CNTL_APPCPU_STAT_VECTOR_SEL_V 0x1 507 #define RTC_CNTL_APPCPU_STAT_VECTOR_SEL_S 12 508 /* RTC_CNTL_RESET_CAUSE_APPCPU : RO ;bitpos:[11:6] ;default: 0 ; */ 509 /*description: reset cause of APP CPU*/ 510 #define RTC_CNTL_RESET_CAUSE_APPCPU 0x0000003F 511 #define RTC_CNTL_RESET_CAUSE_APPCPU_M ((RTC_CNTL_RESET_CAUSE_APPCPU_V)<<(RTC_CNTL_RESET_CAUSE_APPCPU_S)) 512 #define RTC_CNTL_RESET_CAUSE_APPCPU_V 0x3F 513 #define RTC_CNTL_RESET_CAUSE_APPCPU_S 6 514 /* RTC_CNTL_RESET_CAUSE_PROCPU : RO ;bitpos:[5:0] ;default: 0 ; */ 515 /*description: reset cause of PRO CPU*/ 516 #define RTC_CNTL_RESET_CAUSE_PROCPU 0x0000003F 517 #define RTC_CNTL_RESET_CAUSE_PROCPU_M ((RTC_CNTL_RESET_CAUSE_PROCPU_V)<<(RTC_CNTL_RESET_CAUSE_PROCPU_S)) 518 #define RTC_CNTL_RESET_CAUSE_PROCPU_V 0x3F 519 #define RTC_CNTL_RESET_CAUSE_PROCPU_S 0 520 521 #define RTC_CNTL_WAKEUP_STATE_REG (DR_REG_RTCCNTL_BASE + 0x003C) 522 /* RTC_CNTL_WAKEUP_ENA : R/W ;bitpos:[31:15] ;default: 17'b1100 ; */ 523 /*description: wakeup enable bitmap*/ 524 #define RTC_CNTL_WAKEUP_ENA 0x0001FFFF 525 #define RTC_CNTL_WAKEUP_ENA_M ((RTC_CNTL_WAKEUP_ENA_V)<<(RTC_CNTL_WAKEUP_ENA_S)) 526 #define RTC_CNTL_WAKEUP_ENA_V 0x1FFFF 527 #define RTC_CNTL_WAKEUP_ENA_S 15 528 529 #define RTC_CNTL_INT_ENA_REG (DR_REG_RTCCNTL_BASE + 0x0040) 530 /* RTC_CNTL_GLITCH_DET_INT_ENA : R/W ;bitpos:[19] ;default: 1'b0 ; */ 531 /*description: enbale gitch det interrupt*/ 532 #define RTC_CNTL_GLITCH_DET_INT_ENA (BIT(19)) 533 #define RTC_CNTL_GLITCH_DET_INT_ENA_M (BIT(19)) 534 #define RTC_CNTL_GLITCH_DET_INT_ENA_V 0x1 535 #define RTC_CNTL_GLITCH_DET_INT_ENA_S 19 536 /* RTC_CNTL_TOUCH_TIMEOUT_INT_ENA : R/W ;bitpos:[18] ;default: 1'b0 ; */ 537 /*description: enable touch timeout interrupt*/ 538 #define RTC_CNTL_TOUCH_TIMEOUT_INT_ENA (BIT(18)) 539 #define RTC_CNTL_TOUCH_TIMEOUT_INT_ENA_M (BIT(18)) 540 #define RTC_CNTL_TOUCH_TIMEOUT_INT_ENA_V 0x1 541 #define RTC_CNTL_TOUCH_TIMEOUT_INT_ENA_S 18 542 /* RTC_CNTL_COCPU_TRAP_INT_ENA : R/W ;bitpos:[17] ;default: 1'b0 ; */ 543 /*description: enable cocpu trap interrupt*/ 544 #define RTC_CNTL_COCPU_TRAP_INT_ENA (BIT(17)) 545 #define RTC_CNTL_COCPU_TRAP_INT_ENA_M (BIT(17)) 546 #define RTC_CNTL_COCPU_TRAP_INT_ENA_V 0x1 547 #define RTC_CNTL_COCPU_TRAP_INT_ENA_S 17 548 /* RTC_CNTL_XTAL32K_DEAD_INT_ENA : R/W ;bitpos:[16] ;default: 1'b0 ; */ 549 /*description: enable xtal32k_dead interrupt*/ 550 #define RTC_CNTL_XTAL32K_DEAD_INT_ENA (BIT(16)) 551 #define RTC_CNTL_XTAL32K_DEAD_INT_ENA_M (BIT(16)) 552 #define RTC_CNTL_XTAL32K_DEAD_INT_ENA_V 0x1 553 #define RTC_CNTL_XTAL32K_DEAD_INT_ENA_S 16 554 /* RTC_CNTL_SWD_INT_ENA : R/W ;bitpos:[15] ;default: 1'b0 ; */ 555 /*description: enable super watch dog interrupt*/ 556 #define RTC_CNTL_SWD_INT_ENA (BIT(15)) 557 #define RTC_CNTL_SWD_INT_ENA_M (BIT(15)) 558 #define RTC_CNTL_SWD_INT_ENA_V 0x1 559 #define RTC_CNTL_SWD_INT_ENA_S 15 560 /* RTC_CNTL_SARADC2_INT_ENA : R/W ;bitpos:[14] ;default: 1'b0 ; */ 561 /*description: enable saradc2 interrupt*/ 562 #define RTC_CNTL_SARADC2_INT_ENA (BIT(14)) 563 #define RTC_CNTL_SARADC2_INT_ENA_M (BIT(14)) 564 #define RTC_CNTL_SARADC2_INT_ENA_V 0x1 565 #define RTC_CNTL_SARADC2_INT_ENA_S 14 566 /* RTC_CNTL_COCPU_INT_ENA : R/W ;bitpos:[13] ;default: 1'b0 ; */ 567 /*description: enable riscV cocpu interrupt*/ 568 #define RTC_CNTL_COCPU_INT_ENA (BIT(13)) 569 #define RTC_CNTL_COCPU_INT_ENA_M (BIT(13)) 570 #define RTC_CNTL_COCPU_INT_ENA_V 0x1 571 #define RTC_CNTL_COCPU_INT_ENA_S 13 572 /* RTC_CNTL_TSENS_INT_ENA : R/W ;bitpos:[12] ;default: 1'b0 ; */ 573 /*description: enable tsens interrupt*/ 574 #define RTC_CNTL_TSENS_INT_ENA (BIT(12)) 575 #define RTC_CNTL_TSENS_INT_ENA_M (BIT(12)) 576 #define RTC_CNTL_TSENS_INT_ENA_V 0x1 577 #define RTC_CNTL_TSENS_INT_ENA_S 12 578 /* RTC_CNTL_SARADC1_INT_ENA : R/W ;bitpos:[11] ;default: 1'b0 ; */ 579 /*description: enable saradc1 interrupt*/ 580 #define RTC_CNTL_SARADC1_INT_ENA (BIT(11)) 581 #define RTC_CNTL_SARADC1_INT_ENA_M (BIT(11)) 582 #define RTC_CNTL_SARADC1_INT_ENA_V 0x1 583 #define RTC_CNTL_SARADC1_INT_ENA_S 11 584 /* RTC_CNTL_MAIN_TIMER_INT_ENA : R/W ;bitpos:[10] ;default: 1'b0 ; */ 585 /*description: enable RTC main timer interrupt*/ 586 #define RTC_CNTL_MAIN_TIMER_INT_ENA (BIT(10)) 587 #define RTC_CNTL_MAIN_TIMER_INT_ENA_M (BIT(10)) 588 #define RTC_CNTL_MAIN_TIMER_INT_ENA_V 0x1 589 #define RTC_CNTL_MAIN_TIMER_INT_ENA_S 10 590 /* RTC_CNTL_BROWN_OUT_INT_ENA : R/W ;bitpos:[9] ;default: 1'b0 ; */ 591 /*description: enable brown out interrupt*/ 592 #define RTC_CNTL_BROWN_OUT_INT_ENA (BIT(9)) 593 #define RTC_CNTL_BROWN_OUT_INT_ENA_M (BIT(9)) 594 #define RTC_CNTL_BROWN_OUT_INT_ENA_V 0x1 595 #define RTC_CNTL_BROWN_OUT_INT_ENA_S 9 596 /* RTC_CNTL_TOUCH_INACTIVE_INT_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */ 597 /*description: enable touch inactive interrupt*/ 598 #define RTC_CNTL_TOUCH_INACTIVE_INT_ENA (BIT(8)) 599 #define RTC_CNTL_TOUCH_INACTIVE_INT_ENA_M (BIT(8)) 600 #define RTC_CNTL_TOUCH_INACTIVE_INT_ENA_V 0x1 601 #define RTC_CNTL_TOUCH_INACTIVE_INT_ENA_S 8 602 /* RTC_CNTL_TOUCH_ACTIVE_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */ 603 /*description: enable touch active interrupt*/ 604 #define RTC_CNTL_TOUCH_ACTIVE_INT_ENA (BIT(7)) 605 #define RTC_CNTL_TOUCH_ACTIVE_INT_ENA_M (BIT(7)) 606 #define RTC_CNTL_TOUCH_ACTIVE_INT_ENA_V 0x1 607 #define RTC_CNTL_TOUCH_ACTIVE_INT_ENA_S 7 608 /* RTC_CNTL_TOUCH_DONE_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */ 609 /*description: enable touch done interrupt*/ 610 #define RTC_CNTL_TOUCH_DONE_INT_ENA (BIT(6)) 611 #define RTC_CNTL_TOUCH_DONE_INT_ENA_M (BIT(6)) 612 #define RTC_CNTL_TOUCH_DONE_INT_ENA_V 0x1 613 #define RTC_CNTL_TOUCH_DONE_INT_ENA_S 6 614 /* RTC_CNTL_ULP_CP_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */ 615 /*description: enable ULP-coprocessor interrupt*/ 616 #define RTC_CNTL_ULP_CP_INT_ENA (BIT(5)) 617 #define RTC_CNTL_ULP_CP_INT_ENA_M (BIT(5)) 618 #define RTC_CNTL_ULP_CP_INT_ENA_V 0x1 619 #define RTC_CNTL_ULP_CP_INT_ENA_S 5 620 /* RTC_CNTL_TOUCH_SCAN_DONE_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */ 621 /*description: enable touch scan done interrupt*/ 622 #define RTC_CNTL_TOUCH_SCAN_DONE_INT_ENA (BIT(4)) 623 #define RTC_CNTL_TOUCH_SCAN_DONE_INT_ENA_M (BIT(4)) 624 #define RTC_CNTL_TOUCH_SCAN_DONE_INT_ENA_V 0x1 625 #define RTC_CNTL_TOUCH_SCAN_DONE_INT_ENA_S 4 626 /* RTC_CNTL_WDT_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */ 627 /*description: enable RTC WDT interrupt*/ 628 #define RTC_CNTL_WDT_INT_ENA (BIT(3)) 629 #define RTC_CNTL_WDT_INT_ENA_M (BIT(3)) 630 #define RTC_CNTL_WDT_INT_ENA_V 0x1 631 #define RTC_CNTL_WDT_INT_ENA_S 3 632 /* RTC_CNTL_SDIO_IDLE_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */ 633 /*description: enable SDIO idle interrupt*/ 634 #define RTC_CNTL_SDIO_IDLE_INT_ENA (BIT(2)) 635 #define RTC_CNTL_SDIO_IDLE_INT_ENA_M (BIT(2)) 636 #define RTC_CNTL_SDIO_IDLE_INT_ENA_V 0x1 637 #define RTC_CNTL_SDIO_IDLE_INT_ENA_S 2 638 /* RTC_CNTL_SLP_REJECT_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */ 639 /*description: enable sleep reject interrupt*/ 640 #define RTC_CNTL_SLP_REJECT_INT_ENA (BIT(1)) 641 #define RTC_CNTL_SLP_REJECT_INT_ENA_M (BIT(1)) 642 #define RTC_CNTL_SLP_REJECT_INT_ENA_V 0x1 643 #define RTC_CNTL_SLP_REJECT_INT_ENA_S 1 644 /* RTC_CNTL_SLP_WAKEUP_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ 645 /*description: enable sleep wakeup interrupt*/ 646 #define RTC_CNTL_SLP_WAKEUP_INT_ENA (BIT(0)) 647 #define RTC_CNTL_SLP_WAKEUP_INT_ENA_M (BIT(0)) 648 #define RTC_CNTL_SLP_WAKEUP_INT_ENA_V 0x1 649 #define RTC_CNTL_SLP_WAKEUP_INT_ENA_S 0 650 651 #define RTC_CNTL_INT_RAW_REG (DR_REG_RTCCNTL_BASE + 0x0044) 652 /* RTC_CNTL_GLITCH_DET_INT_RAW : RO ;bitpos:[19] ;default: 1'b0 ; */ 653 /*description: glitch_det_interrupt_raw*/ 654 #define RTC_CNTL_GLITCH_DET_INT_RAW (BIT(19)) 655 #define RTC_CNTL_GLITCH_DET_INT_RAW_M (BIT(19)) 656 #define RTC_CNTL_GLITCH_DET_INT_RAW_V 0x1 657 #define RTC_CNTL_GLITCH_DET_INT_RAW_S 19 658 /* RTC_CNTL_TOUCH_TIMEOUT_INT_RAW : RO ;bitpos:[18] ;default: 1'b0 ; */ 659 /*description: touch timeout interrupt raw*/ 660 #define RTC_CNTL_TOUCH_TIMEOUT_INT_RAW (BIT(18)) 661 #define RTC_CNTL_TOUCH_TIMEOUT_INT_RAW_M (BIT(18)) 662 #define RTC_CNTL_TOUCH_TIMEOUT_INT_RAW_V 0x1 663 #define RTC_CNTL_TOUCH_TIMEOUT_INT_RAW_S 18 664 /* RTC_CNTL_COCPU_TRAP_INT_RAW : RO ;bitpos:[17] ;default: 1'b0 ; */ 665 /*description: cocpu trap interrupt raw*/ 666 #define RTC_CNTL_COCPU_TRAP_INT_RAW (BIT(17)) 667 #define RTC_CNTL_COCPU_TRAP_INT_RAW_M (BIT(17)) 668 #define RTC_CNTL_COCPU_TRAP_INT_RAW_V 0x1 669 #define RTC_CNTL_COCPU_TRAP_INT_RAW_S 17 670 /* RTC_CNTL_XTAL32K_DEAD_INT_RAW : RO ;bitpos:[16] ;default: 1'b0 ; */ 671 /*description: xtal32k dead detection interrupt raw*/ 672 #define RTC_CNTL_XTAL32K_DEAD_INT_RAW (BIT(16)) 673 #define RTC_CNTL_XTAL32K_DEAD_INT_RAW_M (BIT(16)) 674 #define RTC_CNTL_XTAL32K_DEAD_INT_RAW_V 0x1 675 #define RTC_CNTL_XTAL32K_DEAD_INT_RAW_S 16 676 /* RTC_CNTL_SWD_INT_RAW : RO ;bitpos:[15] ;default: 1'b0 ; */ 677 /*description: super watch dog interrupt raw*/ 678 #define RTC_CNTL_SWD_INT_RAW (BIT(15)) 679 #define RTC_CNTL_SWD_INT_RAW_M (BIT(15)) 680 #define RTC_CNTL_SWD_INT_RAW_V 0x1 681 #define RTC_CNTL_SWD_INT_RAW_S 15 682 /* RTC_CNTL_SARADC2_INT_RAW : RO ;bitpos:[14] ;default: 1'b0 ; */ 683 /*description: saradc2 interrupt raw*/ 684 #define RTC_CNTL_SARADC2_INT_RAW (BIT(14)) 685 #define RTC_CNTL_SARADC2_INT_RAW_M (BIT(14)) 686 #define RTC_CNTL_SARADC2_INT_RAW_V 0x1 687 #define RTC_CNTL_SARADC2_INT_RAW_S 14 688 /* RTC_CNTL_COCPU_INT_RAW : RO ;bitpos:[13] ;default: 1'b0 ; */ 689 /*description: riscV cocpu interrupt raw*/ 690 #define RTC_CNTL_COCPU_INT_RAW (BIT(13)) 691 #define RTC_CNTL_COCPU_INT_RAW_M (BIT(13)) 692 #define RTC_CNTL_COCPU_INT_RAW_V 0x1 693 #define RTC_CNTL_COCPU_INT_RAW_S 13 694 /* RTC_CNTL_TSENS_INT_RAW : RO ;bitpos:[12] ;default: 1'b0 ; */ 695 /*description: tsens interrupt raw*/ 696 #define RTC_CNTL_TSENS_INT_RAW (BIT(12)) 697 #define RTC_CNTL_TSENS_INT_RAW_M (BIT(12)) 698 #define RTC_CNTL_TSENS_INT_RAW_V 0x1 699 #define RTC_CNTL_TSENS_INT_RAW_S 12 700 /* RTC_CNTL_SARADC1_INT_RAW : RO ;bitpos:[11] ;default: 1'b0 ; */ 701 /*description: saradc1 interrupt raw*/ 702 #define RTC_CNTL_SARADC1_INT_RAW (BIT(11)) 703 #define RTC_CNTL_SARADC1_INT_RAW_M (BIT(11)) 704 #define RTC_CNTL_SARADC1_INT_RAW_V 0x1 705 #define RTC_CNTL_SARADC1_INT_RAW_S 11 706 /* RTC_CNTL_MAIN_TIMER_INT_RAW : RO ;bitpos:[10] ;default: 1'b0 ; */ 707 /*description: RTC main timer interrupt raw*/ 708 #define RTC_CNTL_MAIN_TIMER_INT_RAW (BIT(10)) 709 #define RTC_CNTL_MAIN_TIMER_INT_RAW_M (BIT(10)) 710 #define RTC_CNTL_MAIN_TIMER_INT_RAW_V 0x1 711 #define RTC_CNTL_MAIN_TIMER_INT_RAW_S 10 712 /* RTC_CNTL_BROWN_OUT_INT_RAW : RO ;bitpos:[9] ;default: 1'b0 ; */ 713 /*description: brown out interrupt raw*/ 714 #define RTC_CNTL_BROWN_OUT_INT_RAW (BIT(9)) 715 #define RTC_CNTL_BROWN_OUT_INT_RAW_M (BIT(9)) 716 #define RTC_CNTL_BROWN_OUT_INT_RAW_V 0x1 717 #define RTC_CNTL_BROWN_OUT_INT_RAW_S 9 718 /* RTC_CNTL_TOUCH_INACTIVE_INT_RAW : RO ;bitpos:[8] ;default: 1'b0 ; */ 719 /*description: touch inactive interrupt raw*/ 720 #define RTC_CNTL_TOUCH_INACTIVE_INT_RAW (BIT(8)) 721 #define RTC_CNTL_TOUCH_INACTIVE_INT_RAW_M (BIT(8)) 722 #define RTC_CNTL_TOUCH_INACTIVE_INT_RAW_V 0x1 723 #define RTC_CNTL_TOUCH_INACTIVE_INT_RAW_S 8 724 /* RTC_CNTL_TOUCH_ACTIVE_INT_RAW : RO ;bitpos:[7] ;default: 1'b0 ; */ 725 /*description: touch active interrupt raw*/ 726 #define RTC_CNTL_TOUCH_ACTIVE_INT_RAW (BIT(7)) 727 #define RTC_CNTL_TOUCH_ACTIVE_INT_RAW_M (BIT(7)) 728 #define RTC_CNTL_TOUCH_ACTIVE_INT_RAW_V 0x1 729 #define RTC_CNTL_TOUCH_ACTIVE_INT_RAW_S 7 730 /* RTC_CNTL_TOUCH_DONE_INT_RAW : RO ;bitpos:[6] ;default: 1'b0 ; */ 731 /*description: touch interrupt raw*/ 732 #define RTC_CNTL_TOUCH_DONE_INT_RAW (BIT(6)) 733 #define RTC_CNTL_TOUCH_DONE_INT_RAW_M (BIT(6)) 734 #define RTC_CNTL_TOUCH_DONE_INT_RAW_V 0x1 735 #define RTC_CNTL_TOUCH_DONE_INT_RAW_S 6 736 /* RTC_CNTL_ULP_CP_INT_RAW : RO ;bitpos:[5] ;default: 1'b0 ; */ 737 /*description: ULP-coprocessor interrupt raw*/ 738 #define RTC_CNTL_ULP_CP_INT_RAW (BIT(5)) 739 #define RTC_CNTL_ULP_CP_INT_RAW_M (BIT(5)) 740 #define RTC_CNTL_ULP_CP_INT_RAW_V 0x1 741 #define RTC_CNTL_ULP_CP_INT_RAW_S 5 742 /* RTC_CNTL_TOUCH_SCAN_DONE_INT_RAW : RO ;bitpos:[4] ;default: 1'b0 ; */ 743 /*description: */ 744 #define RTC_CNTL_TOUCH_SCAN_DONE_INT_RAW (BIT(4)) 745 #define RTC_CNTL_TOUCH_SCAN_DONE_INT_RAW_M (BIT(4)) 746 #define RTC_CNTL_TOUCH_SCAN_DONE_INT_RAW_V 0x1 747 #define RTC_CNTL_TOUCH_SCAN_DONE_INT_RAW_S 4 748 /* RTC_CNTL_WDT_INT_RAW : RO ;bitpos:[3] ;default: 1'b0 ; */ 749 /*description: RTC WDT interrupt raw*/ 750 #define RTC_CNTL_WDT_INT_RAW (BIT(3)) 751 #define RTC_CNTL_WDT_INT_RAW_M (BIT(3)) 752 #define RTC_CNTL_WDT_INT_RAW_V 0x1 753 #define RTC_CNTL_WDT_INT_RAW_S 3 754 /* RTC_CNTL_SDIO_IDLE_INT_RAW : RO ;bitpos:[2] ;default: 1'b0 ; */ 755 /*description: SDIO idle interrupt raw*/ 756 #define RTC_CNTL_SDIO_IDLE_INT_RAW (BIT(2)) 757 #define RTC_CNTL_SDIO_IDLE_INT_RAW_M (BIT(2)) 758 #define RTC_CNTL_SDIO_IDLE_INT_RAW_V 0x1 759 #define RTC_CNTL_SDIO_IDLE_INT_RAW_S 2 760 /* RTC_CNTL_SLP_REJECT_INT_RAW : RO ;bitpos:[1] ;default: 1'b0 ; */ 761 /*description: sleep reject interrupt raw*/ 762 #define RTC_CNTL_SLP_REJECT_INT_RAW (BIT(1)) 763 #define RTC_CNTL_SLP_REJECT_INT_RAW_M (BIT(1)) 764 #define RTC_CNTL_SLP_REJECT_INT_RAW_V 0x1 765 #define RTC_CNTL_SLP_REJECT_INT_RAW_S 1 766 /* RTC_CNTL_SLP_WAKEUP_INT_RAW : RO ;bitpos:[0] ;default: 1'b0 ; */ 767 /*description: sleep wakeup interrupt raw*/ 768 #define RTC_CNTL_SLP_WAKEUP_INT_RAW (BIT(0)) 769 #define RTC_CNTL_SLP_WAKEUP_INT_RAW_M (BIT(0)) 770 #define RTC_CNTL_SLP_WAKEUP_INT_RAW_V 0x1 771 #define RTC_CNTL_SLP_WAKEUP_INT_RAW_S 0 772 773 #define RTC_CNTL_INT_ST_REG (DR_REG_RTCCNTL_BASE + 0x0048) 774 /* RTC_CNTL_GLITCH_DET_INT_ST : RO ;bitpos:[19] ;default: 1'b0 ; */ 775 /*description: glitch_det_interrupt state*/ 776 #define RTC_CNTL_GLITCH_DET_INT_ST (BIT(19)) 777 #define RTC_CNTL_GLITCH_DET_INT_ST_M (BIT(19)) 778 #define RTC_CNTL_GLITCH_DET_INT_ST_V 0x1 779 #define RTC_CNTL_GLITCH_DET_INT_ST_S 19 780 /* RTC_CNTL_TOUCH_TIMEOUT_INT_ST : RO ;bitpos:[18] ;default: 1'b0 ; */ 781 /*description: Touch timeout interrupt state*/ 782 #define RTC_CNTL_TOUCH_TIMEOUT_INT_ST (BIT(18)) 783 #define RTC_CNTL_TOUCH_TIMEOUT_INT_ST_M (BIT(18)) 784 #define RTC_CNTL_TOUCH_TIMEOUT_INT_ST_V 0x1 785 #define RTC_CNTL_TOUCH_TIMEOUT_INT_ST_S 18 786 /* RTC_CNTL_COCPU_TRAP_INT_ST : RO ;bitpos:[17] ;default: 1'b0 ; */ 787 /*description: cocpu trap interrupt state*/ 788 #define RTC_CNTL_COCPU_TRAP_INT_ST (BIT(17)) 789 #define RTC_CNTL_COCPU_TRAP_INT_ST_M (BIT(17)) 790 #define RTC_CNTL_COCPU_TRAP_INT_ST_V 0x1 791 #define RTC_CNTL_COCPU_TRAP_INT_ST_S 17 792 /* RTC_CNTL_XTAL32K_DEAD_INT_ST : RO ;bitpos:[16] ;default: 1'b0 ; */ 793 /*description: xtal32k dead detection interrupt state*/ 794 #define RTC_CNTL_XTAL32K_DEAD_INT_ST (BIT(16)) 795 #define RTC_CNTL_XTAL32K_DEAD_INT_ST_M (BIT(16)) 796 #define RTC_CNTL_XTAL32K_DEAD_INT_ST_V 0x1 797 #define RTC_CNTL_XTAL32K_DEAD_INT_ST_S 16 798 /* RTC_CNTL_SWD_INT_ST : RO ;bitpos:[15] ;default: 1'b0 ; */ 799 /*description: super watch dog interrupt state*/ 800 #define RTC_CNTL_SWD_INT_ST (BIT(15)) 801 #define RTC_CNTL_SWD_INT_ST_M (BIT(15)) 802 #define RTC_CNTL_SWD_INT_ST_V 0x1 803 #define RTC_CNTL_SWD_INT_ST_S 15 804 /* RTC_CNTL_SARADC2_INT_ST : RO ;bitpos:[14] ;default: 1'b0 ; */ 805 /*description: saradc2 interrupt state*/ 806 #define RTC_CNTL_SARADC2_INT_ST (BIT(14)) 807 #define RTC_CNTL_SARADC2_INT_ST_M (BIT(14)) 808 #define RTC_CNTL_SARADC2_INT_ST_V 0x1 809 #define RTC_CNTL_SARADC2_INT_ST_S 14 810 /* RTC_CNTL_COCPU_INT_ST : RO ;bitpos:[13] ;default: 1'b0 ; */ 811 /*description: riscV cocpu interrupt state*/ 812 #define RTC_CNTL_COCPU_INT_ST (BIT(13)) 813 #define RTC_CNTL_COCPU_INT_ST_M (BIT(13)) 814 #define RTC_CNTL_COCPU_INT_ST_V 0x1 815 #define RTC_CNTL_COCPU_INT_ST_S 13 816 /* RTC_CNTL_TSENS_INT_ST : RO ;bitpos:[12] ;default: 1'b0 ; */ 817 /*description: tsens interrupt state*/ 818 #define RTC_CNTL_TSENS_INT_ST (BIT(12)) 819 #define RTC_CNTL_TSENS_INT_ST_M (BIT(12)) 820 #define RTC_CNTL_TSENS_INT_ST_V 0x1 821 #define RTC_CNTL_TSENS_INT_ST_S 12 822 /* RTC_CNTL_SARADC1_INT_ST : RO ;bitpos:[11] ;default: 1'b0 ; */ 823 /*description: saradc1 interrupt state*/ 824 #define RTC_CNTL_SARADC1_INT_ST (BIT(11)) 825 #define RTC_CNTL_SARADC1_INT_ST_M (BIT(11)) 826 #define RTC_CNTL_SARADC1_INT_ST_V 0x1 827 #define RTC_CNTL_SARADC1_INT_ST_S 11 828 /* RTC_CNTL_MAIN_TIMER_INT_ST : RO ;bitpos:[10] ;default: 1'b0 ; */ 829 /*description: RTC main timer interrupt state*/ 830 #define RTC_CNTL_MAIN_TIMER_INT_ST (BIT(10)) 831 #define RTC_CNTL_MAIN_TIMER_INT_ST_M (BIT(10)) 832 #define RTC_CNTL_MAIN_TIMER_INT_ST_V 0x1 833 #define RTC_CNTL_MAIN_TIMER_INT_ST_S 10 834 /* RTC_CNTL_BROWN_OUT_INT_ST : RO ;bitpos:[9] ;default: 1'b0 ; */ 835 /*description: brown out interrupt state*/ 836 #define RTC_CNTL_BROWN_OUT_INT_ST (BIT(9)) 837 #define RTC_CNTL_BROWN_OUT_INT_ST_M (BIT(9)) 838 #define RTC_CNTL_BROWN_OUT_INT_ST_V 0x1 839 #define RTC_CNTL_BROWN_OUT_INT_ST_S 9 840 /* RTC_CNTL_TOUCH_INACTIVE_INT_ST : RO ;bitpos:[8] ;default: 1'b0 ; */ 841 /*description: touch inactive interrupt state*/ 842 #define RTC_CNTL_TOUCH_INACTIVE_INT_ST (BIT(8)) 843 #define RTC_CNTL_TOUCH_INACTIVE_INT_ST_M (BIT(8)) 844 #define RTC_CNTL_TOUCH_INACTIVE_INT_ST_V 0x1 845 #define RTC_CNTL_TOUCH_INACTIVE_INT_ST_S 8 846 /* RTC_CNTL_TOUCH_ACTIVE_INT_ST : RO ;bitpos:[7] ;default: 1'b0 ; */ 847 /*description: touch active interrupt state*/ 848 #define RTC_CNTL_TOUCH_ACTIVE_INT_ST (BIT(7)) 849 #define RTC_CNTL_TOUCH_ACTIVE_INT_ST_M (BIT(7)) 850 #define RTC_CNTL_TOUCH_ACTIVE_INT_ST_V 0x1 851 #define RTC_CNTL_TOUCH_ACTIVE_INT_ST_S 7 852 /* RTC_CNTL_TOUCH_DONE_INT_ST : RO ;bitpos:[6] ;default: 1'b0 ; */ 853 /*description: touch done interrupt state*/ 854 #define RTC_CNTL_TOUCH_DONE_INT_ST (BIT(6)) 855 #define RTC_CNTL_TOUCH_DONE_INT_ST_M (BIT(6)) 856 #define RTC_CNTL_TOUCH_DONE_INT_ST_V 0x1 857 #define RTC_CNTL_TOUCH_DONE_INT_ST_S 6 858 /* RTC_CNTL_ULP_CP_INT_ST : RO ;bitpos:[5] ;default: 1'b0 ; */ 859 /*description: ULP-coprocessor interrupt state*/ 860 #define RTC_CNTL_ULP_CP_INT_ST (BIT(5)) 861 #define RTC_CNTL_ULP_CP_INT_ST_M (BIT(5)) 862 #define RTC_CNTL_ULP_CP_INT_ST_V 0x1 863 #define RTC_CNTL_ULP_CP_INT_ST_S 5 864 /* RTC_CNTL_TOUCH_SCAN_DONE_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */ 865 /*description: */ 866 #define RTC_CNTL_TOUCH_SCAN_DONE_INT_ST (BIT(4)) 867 #define RTC_CNTL_TOUCH_SCAN_DONE_INT_ST_M (BIT(4)) 868 #define RTC_CNTL_TOUCH_SCAN_DONE_INT_ST_V 0x1 869 #define RTC_CNTL_TOUCH_SCAN_DONE_INT_ST_S 4 870 /* RTC_CNTL_WDT_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */ 871 /*description: RTC WDT interrupt state*/ 872 #define RTC_CNTL_WDT_INT_ST (BIT(3)) 873 #define RTC_CNTL_WDT_INT_ST_M (BIT(3)) 874 #define RTC_CNTL_WDT_INT_ST_V 0x1 875 #define RTC_CNTL_WDT_INT_ST_S 3 876 /* RTC_CNTL_SDIO_IDLE_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */ 877 /*description: SDIO idle interrupt state*/ 878 #define RTC_CNTL_SDIO_IDLE_INT_ST (BIT(2)) 879 #define RTC_CNTL_SDIO_IDLE_INT_ST_M (BIT(2)) 880 #define RTC_CNTL_SDIO_IDLE_INT_ST_V 0x1 881 #define RTC_CNTL_SDIO_IDLE_INT_ST_S 2 882 /* RTC_CNTL_SLP_REJECT_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */ 883 /*description: sleep reject interrupt state*/ 884 #define RTC_CNTL_SLP_REJECT_INT_ST (BIT(1)) 885 #define RTC_CNTL_SLP_REJECT_INT_ST_M (BIT(1)) 886 #define RTC_CNTL_SLP_REJECT_INT_ST_V 0x1 887 #define RTC_CNTL_SLP_REJECT_INT_ST_S 1 888 /* RTC_CNTL_SLP_WAKEUP_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */ 889 /*description: sleep wakeup interrupt state*/ 890 #define RTC_CNTL_SLP_WAKEUP_INT_ST (BIT(0)) 891 #define RTC_CNTL_SLP_WAKEUP_INT_ST_M (BIT(0)) 892 #define RTC_CNTL_SLP_WAKEUP_INT_ST_V 0x1 893 #define RTC_CNTL_SLP_WAKEUP_INT_ST_S 0 894 895 #define RTC_CNTL_INT_CLR_REG (DR_REG_RTCCNTL_BASE + 0x004C) 896 /* RTC_CNTL_GLITCH_DET_INT_CLR : WO ;bitpos:[19] ;default: 1'b0 ; */ 897 /*description: Clear glitch det interrupt state*/ 898 #define RTC_CNTL_GLITCH_DET_INT_CLR (BIT(19)) 899 #define RTC_CNTL_GLITCH_DET_INT_CLR_M (BIT(19)) 900 #define RTC_CNTL_GLITCH_DET_INT_CLR_V 0x1 901 #define RTC_CNTL_GLITCH_DET_INT_CLR_S 19 902 /* RTC_CNTL_TOUCH_TIMEOUT_INT_CLR : WO ;bitpos:[18] ;default: 1'b0 ; */ 903 /*description: Clear touch timeout interrupt state*/ 904 #define RTC_CNTL_TOUCH_TIMEOUT_INT_CLR (BIT(18)) 905 #define RTC_CNTL_TOUCH_TIMEOUT_INT_CLR_M (BIT(18)) 906 #define RTC_CNTL_TOUCH_TIMEOUT_INT_CLR_V 0x1 907 #define RTC_CNTL_TOUCH_TIMEOUT_INT_CLR_S 18 908 /* RTC_CNTL_COCPU_TRAP_INT_CLR : WO ;bitpos:[17] ;default: 1'b0 ; */ 909 /*description: Clear cocpu trap interrupt state*/ 910 #define RTC_CNTL_COCPU_TRAP_INT_CLR (BIT(17)) 911 #define RTC_CNTL_COCPU_TRAP_INT_CLR_M (BIT(17)) 912 #define RTC_CNTL_COCPU_TRAP_INT_CLR_V 0x1 913 #define RTC_CNTL_COCPU_TRAP_INT_CLR_S 17 914 /* RTC_CNTL_XTAL32K_DEAD_INT_CLR : WO ;bitpos:[16] ;default: 1'b0 ; */ 915 /*description: Clear RTC WDT interrupt state*/ 916 #define RTC_CNTL_XTAL32K_DEAD_INT_CLR (BIT(16)) 917 #define RTC_CNTL_XTAL32K_DEAD_INT_CLR_M (BIT(16)) 918 #define RTC_CNTL_XTAL32K_DEAD_INT_CLR_V 0x1 919 #define RTC_CNTL_XTAL32K_DEAD_INT_CLR_S 16 920 /* RTC_CNTL_SWD_INT_CLR : WO ;bitpos:[15] ;default: 1'b0 ; */ 921 /*description: Clear super watch dog interrupt state*/ 922 #define RTC_CNTL_SWD_INT_CLR (BIT(15)) 923 #define RTC_CNTL_SWD_INT_CLR_M (BIT(15)) 924 #define RTC_CNTL_SWD_INT_CLR_V 0x1 925 #define RTC_CNTL_SWD_INT_CLR_S 15 926 /* RTC_CNTL_SARADC2_INT_CLR : WO ;bitpos:[14] ;default: 1'b0 ; */ 927 /*description: Clear saradc2 interrupt state*/ 928 #define RTC_CNTL_SARADC2_INT_CLR (BIT(14)) 929 #define RTC_CNTL_SARADC2_INT_CLR_M (BIT(14)) 930 #define RTC_CNTL_SARADC2_INT_CLR_V 0x1 931 #define RTC_CNTL_SARADC2_INT_CLR_S 14 932 /* RTC_CNTL_COCPU_INT_CLR : WO ;bitpos:[13] ;default: 1'b0 ; */ 933 /*description: Clear riscV cocpu interrupt state*/ 934 #define RTC_CNTL_COCPU_INT_CLR (BIT(13)) 935 #define RTC_CNTL_COCPU_INT_CLR_M (BIT(13)) 936 #define RTC_CNTL_COCPU_INT_CLR_V 0x1 937 #define RTC_CNTL_COCPU_INT_CLR_S 13 938 /* RTC_CNTL_TSENS_INT_CLR : WO ;bitpos:[12] ;default: 1'b0 ; */ 939 /*description: Clear tsens interrupt state*/ 940 #define RTC_CNTL_TSENS_INT_CLR (BIT(12)) 941 #define RTC_CNTL_TSENS_INT_CLR_M (BIT(12)) 942 #define RTC_CNTL_TSENS_INT_CLR_V 0x1 943 #define RTC_CNTL_TSENS_INT_CLR_S 12 944 /* RTC_CNTL_SARADC1_INT_CLR : WO ;bitpos:[11] ;default: 1'b0 ; */ 945 /*description: Clear saradc1 interrupt state*/ 946 #define RTC_CNTL_SARADC1_INT_CLR (BIT(11)) 947 #define RTC_CNTL_SARADC1_INT_CLR_M (BIT(11)) 948 #define RTC_CNTL_SARADC1_INT_CLR_V 0x1 949 #define RTC_CNTL_SARADC1_INT_CLR_S 11 950 /* RTC_CNTL_MAIN_TIMER_INT_CLR : WO ;bitpos:[10] ;default: 1'b0 ; */ 951 /*description: Clear RTC main timer interrupt state*/ 952 #define RTC_CNTL_MAIN_TIMER_INT_CLR (BIT(10)) 953 #define RTC_CNTL_MAIN_TIMER_INT_CLR_M (BIT(10)) 954 #define RTC_CNTL_MAIN_TIMER_INT_CLR_V 0x1 955 #define RTC_CNTL_MAIN_TIMER_INT_CLR_S 10 956 /* RTC_CNTL_BROWN_OUT_INT_CLR : WO ;bitpos:[9] ;default: 1'b0 ; */ 957 /*description: Clear brown out interrupt state*/ 958 #define RTC_CNTL_BROWN_OUT_INT_CLR (BIT(9)) 959 #define RTC_CNTL_BROWN_OUT_INT_CLR_M (BIT(9)) 960 #define RTC_CNTL_BROWN_OUT_INT_CLR_V 0x1 961 #define RTC_CNTL_BROWN_OUT_INT_CLR_S 9 962 /* RTC_CNTL_TOUCH_INACTIVE_INT_CLR : WO ;bitpos:[8] ;default: 1'b0 ; */ 963 /*description: Clear touch inactive interrupt state*/ 964 #define RTC_CNTL_TOUCH_INACTIVE_INT_CLR (BIT(8)) 965 #define RTC_CNTL_TOUCH_INACTIVE_INT_CLR_M (BIT(8)) 966 #define RTC_CNTL_TOUCH_INACTIVE_INT_CLR_V 0x1 967 #define RTC_CNTL_TOUCH_INACTIVE_INT_CLR_S 8 968 /* RTC_CNTL_TOUCH_ACTIVE_INT_CLR : WO ;bitpos:[7] ;default: 1'b0 ; */ 969 /*description: Clear touch active interrupt state*/ 970 #define RTC_CNTL_TOUCH_ACTIVE_INT_CLR (BIT(7)) 971 #define RTC_CNTL_TOUCH_ACTIVE_INT_CLR_M (BIT(7)) 972 #define RTC_CNTL_TOUCH_ACTIVE_INT_CLR_V 0x1 973 #define RTC_CNTL_TOUCH_ACTIVE_INT_CLR_S 7 974 /* RTC_CNTL_TOUCH_DONE_INT_CLR : WO ;bitpos:[6] ;default: 1'b0 ; */ 975 /*description: Clear touch done interrupt state*/ 976 #define RTC_CNTL_TOUCH_DONE_INT_CLR (BIT(6)) 977 #define RTC_CNTL_TOUCH_DONE_INT_CLR_M (BIT(6)) 978 #define RTC_CNTL_TOUCH_DONE_INT_CLR_V 0x1 979 #define RTC_CNTL_TOUCH_DONE_INT_CLR_S 6 980 /* RTC_CNTL_ULP_CP_INT_CLR : WO ;bitpos:[5] ;default: 1'b0 ; */ 981 /*description: Clear ULP-coprocessor interrupt state*/ 982 #define RTC_CNTL_ULP_CP_INT_CLR (BIT(5)) 983 #define RTC_CNTL_ULP_CP_INT_CLR_M (BIT(5)) 984 #define RTC_CNTL_ULP_CP_INT_CLR_V 0x1 985 #define RTC_CNTL_ULP_CP_INT_CLR_S 5 986 /* RTC_CNTL_TOUCH_SCAN_DONE_INT_CLR : WO ;bitpos:[4] ;default: 1'b0 ; */ 987 /*description: */ 988 #define RTC_CNTL_TOUCH_SCAN_DONE_INT_CLR (BIT(4)) 989 #define RTC_CNTL_TOUCH_SCAN_DONE_INT_CLR_M (BIT(4)) 990 #define RTC_CNTL_TOUCH_SCAN_DONE_INT_CLR_V 0x1 991 #define RTC_CNTL_TOUCH_SCAN_DONE_INT_CLR_S 4 992 /* RTC_CNTL_WDT_INT_CLR : WO ;bitpos:[3] ;default: 1'b0 ; */ 993 /*description: Clear RTC WDT interrupt state*/ 994 #define RTC_CNTL_WDT_INT_CLR (BIT(3)) 995 #define RTC_CNTL_WDT_INT_CLR_M (BIT(3)) 996 #define RTC_CNTL_WDT_INT_CLR_V 0x1 997 #define RTC_CNTL_WDT_INT_CLR_S 3 998 /* RTC_CNTL_SDIO_IDLE_INT_CLR : WO ;bitpos:[2] ;default: 1'b0 ; */ 999 /*description: Clear SDIO idle interrupt state*/ 1000 #define RTC_CNTL_SDIO_IDLE_INT_CLR (BIT(2)) 1001 #define RTC_CNTL_SDIO_IDLE_INT_CLR_M (BIT(2)) 1002 #define RTC_CNTL_SDIO_IDLE_INT_CLR_V 0x1 1003 #define RTC_CNTL_SDIO_IDLE_INT_CLR_S 2 1004 /* RTC_CNTL_SLP_REJECT_INT_CLR : WO ;bitpos:[1] ;default: 1'b0 ; */ 1005 /*description: Clear sleep reject interrupt state*/ 1006 #define RTC_CNTL_SLP_REJECT_INT_CLR (BIT(1)) 1007 #define RTC_CNTL_SLP_REJECT_INT_CLR_M (BIT(1)) 1008 #define RTC_CNTL_SLP_REJECT_INT_CLR_V 0x1 1009 #define RTC_CNTL_SLP_REJECT_INT_CLR_S 1 1010 /* RTC_CNTL_SLP_WAKEUP_INT_CLR : WO ;bitpos:[0] ;default: 1'b0 ; */ 1011 /*description: Clear sleep wakeup interrupt state*/ 1012 #define RTC_CNTL_SLP_WAKEUP_INT_CLR (BIT(0)) 1013 #define RTC_CNTL_SLP_WAKEUP_INT_CLR_M (BIT(0)) 1014 #define RTC_CNTL_SLP_WAKEUP_INT_CLR_V 0x1 1015 #define RTC_CNTL_SLP_WAKEUP_INT_CLR_S 0 1016 1017 #define RTC_CNTL_STORE0_REG (DR_REG_RTCCNTL_BASE + 0x0050) 1018 /* RTC_CNTL_SCRATCH0 : R/W ;bitpos:[31:0] ;default: 0 ; */ 1019 /*description: */ 1020 #define RTC_CNTL_SCRATCH0 0xFFFFFFFF 1021 #define RTC_CNTL_SCRATCH0_M ((RTC_CNTL_SCRATCH0_V)<<(RTC_CNTL_SCRATCH0_S)) 1022 #define RTC_CNTL_SCRATCH0_V 0xFFFFFFFF 1023 #define RTC_CNTL_SCRATCH0_S 0 1024 1025 #define RTC_CNTL_STORE1_REG (DR_REG_RTCCNTL_BASE + 0x0054) 1026 /* RTC_CNTL_SCRATCH1 : R/W ;bitpos:[31:0] ;default: 0 ; */ 1027 /*description: */ 1028 #define RTC_CNTL_SCRATCH1 0xFFFFFFFF 1029 #define RTC_CNTL_SCRATCH1_M ((RTC_CNTL_SCRATCH1_V)<<(RTC_CNTL_SCRATCH1_S)) 1030 #define RTC_CNTL_SCRATCH1_V 0xFFFFFFFF 1031 #define RTC_CNTL_SCRATCH1_S 0 1032 1033 #define RTC_CNTL_STORE2_REG (DR_REG_RTCCNTL_BASE + 0x0058) 1034 /* RTC_CNTL_SCRATCH2 : R/W ;bitpos:[31:0] ;default: 0 ; */ 1035 /*description: */ 1036 #define RTC_CNTL_SCRATCH2 0xFFFFFFFF 1037 #define RTC_CNTL_SCRATCH2_M ((RTC_CNTL_SCRATCH2_V)<<(RTC_CNTL_SCRATCH2_S)) 1038 #define RTC_CNTL_SCRATCH2_V 0xFFFFFFFF 1039 #define RTC_CNTL_SCRATCH2_S 0 1040 1041 #define RTC_CNTL_STORE3_REG (DR_REG_RTCCNTL_BASE + 0x005C) 1042 /* RTC_CNTL_SCRATCH3 : R/W ;bitpos:[31:0] ;default: 0 ; */ 1043 /*description: */ 1044 #define RTC_CNTL_SCRATCH3 0xFFFFFFFF 1045 #define RTC_CNTL_SCRATCH3_M ((RTC_CNTL_SCRATCH3_V)<<(RTC_CNTL_SCRATCH3_S)) 1046 #define RTC_CNTL_SCRATCH3_V 0xFFFFFFFF 1047 #define RTC_CNTL_SCRATCH3_S 0 1048 1049 #define RTC_CNTL_EXT_XTL_CONF_REG (DR_REG_RTCCNTL_BASE + 0x0060) 1050 /* RTC_CNTL_XTL_EXT_CTR_EN : R/W ;bitpos:[31] ;default: 1'b0 ; */ 1051 /*description: */ 1052 #define RTC_CNTL_XTL_EXT_CTR_EN (BIT(31)) 1053 #define RTC_CNTL_XTL_EXT_CTR_EN_M (BIT(31)) 1054 #define RTC_CNTL_XTL_EXT_CTR_EN_V 0x1 1055 #define RTC_CNTL_XTL_EXT_CTR_EN_S 31 1056 /* RTC_CNTL_XTL_EXT_CTR_LV : R/W ;bitpos:[30] ;default: 1'b0 ; */ 1057 /*description: 0: power down XTAL at high level 1: power down XTAL at low level*/ 1058 #define RTC_CNTL_XTL_EXT_CTR_LV (BIT(30)) 1059 #define RTC_CNTL_XTL_EXT_CTR_LV_M (BIT(30)) 1060 #define RTC_CNTL_XTL_EXT_CTR_LV_V 0x1 1061 #define RTC_CNTL_XTL_EXT_CTR_LV_S 30 1062 /* RTC_CNTL_XTAL32K_GPIO_SEL : R/W ;bitpos:[23] ;default: 1'b0 ; */ 1063 /*description: XTAL_32K sel. 0: external XTAL_32K 1: CLK from RTC pad X32P_C*/ 1064 #define RTC_CNTL_XTAL32K_GPIO_SEL (BIT(23)) 1065 #define RTC_CNTL_XTAL32K_GPIO_SEL_M (BIT(23)) 1066 #define RTC_CNTL_XTAL32K_GPIO_SEL_V 0x1 1067 #define RTC_CNTL_XTAL32K_GPIO_SEL_S 23 1068 /* RTC_CNTL_WDT_STATE : RO ;bitpos:[22:20] ;default: 3'h0 ; */ 1069 /*description: state of 32k_wdt*/ 1070 #define RTC_CNTL_WDT_STATE 0x00000007 1071 #define RTC_CNTL_WDT_STATE_M ((RTC_CNTL_WDT_STATE_V)<<(RTC_CNTL_WDT_STATE_S)) 1072 #define RTC_CNTL_WDT_STATE_V 0x7 1073 #define RTC_CNTL_WDT_STATE_S 20 1074 /* RTC_CNTL_DAC_XTAL_32K : R/W ;bitpos:[19:17] ;default: 3'd3 ; */ 1075 /*description: DAC_XTAL_32K*/ 1076 #define RTC_CNTL_DAC_XTAL_32K 0x00000007 1077 #define RTC_CNTL_DAC_XTAL_32K_M ((RTC_CNTL_DAC_XTAL_32K_V)<<(RTC_CNTL_DAC_XTAL_32K_S)) 1078 #define RTC_CNTL_DAC_XTAL_32K_V 0x7 1079 #define RTC_CNTL_DAC_XTAL_32K_S 17 1080 /* RTC_CNTL_XPD_XTAL_32K : R/W ;bitpos:[16] ;default: 1'd0 ; */ 1081 /*description: XPD_XTAL_32K*/ 1082 #define RTC_CNTL_XPD_XTAL_32K (BIT(16)) 1083 #define RTC_CNTL_XPD_XTAL_32K_M (BIT(16)) 1084 #define RTC_CNTL_XPD_XTAL_32K_V 0x1 1085 #define RTC_CNTL_XPD_XTAL_32K_S 16 1086 /* RTC_CNTL_DRES_XTAL_32K : R/W ;bitpos:[15:13] ;default: 3'd3 ; */ 1087 /*description: DRES_XTAL_32K*/ 1088 #define RTC_CNTL_DRES_XTAL_32K 0x00000007 1089 #define RTC_CNTL_DRES_XTAL_32K_M ((RTC_CNTL_DRES_XTAL_32K_V)<<(RTC_CNTL_DRES_XTAL_32K_S)) 1090 #define RTC_CNTL_DRES_XTAL_32K_V 0x7 1091 #define RTC_CNTL_DRES_XTAL_32K_S 13 1092 /* RTC_CNTL_DGM_XTAL_32K : R/W ;bitpos:[12:10] ;default: 3'd3 ; */ 1093 /*description: xtal_32k gm control*/ 1094 #define RTC_CNTL_DGM_XTAL_32K 0x00000007 1095 #define RTC_CNTL_DGM_XTAL_32K_M ((RTC_CNTL_DGM_XTAL_32K_V)<<(RTC_CNTL_DGM_XTAL_32K_S)) 1096 #define RTC_CNTL_DGM_XTAL_32K_V 0x7 1097 #define RTC_CNTL_DGM_XTAL_32K_S 10 1098 /* RTC_CNTL_DBUF_XTAL_32K : R/W ;bitpos:[9] ;default: 1'b0 ; */ 1099 /*description: 0: single-end buffer 1: differential buffer*/ 1100 #define RTC_CNTL_DBUF_XTAL_32K (BIT(9)) 1101 #define RTC_CNTL_DBUF_XTAL_32K_M (BIT(9)) 1102 #define RTC_CNTL_DBUF_XTAL_32K_V 0x1 1103 #define RTC_CNTL_DBUF_XTAL_32K_S 9 1104 /* RTC_CNTL_ENCKINIT_XTAL_32K : R/W ;bitpos:[8] ;default: 1'b0 ; */ 1105 /*description: apply an internal clock to help xtal 32k to start*/ 1106 #define RTC_CNTL_ENCKINIT_XTAL_32K (BIT(8)) 1107 #define RTC_CNTL_ENCKINIT_XTAL_32K_M (BIT(8)) 1108 #define RTC_CNTL_ENCKINIT_XTAL_32K_V 0x1 1109 #define RTC_CNTL_ENCKINIT_XTAL_32K_S 8 1110 /* RTC_CNTL_XTAL32K_XPD_FORCE : R/W ;bitpos:[7] ;default: 1'b1 ; */ 1111 /*description: Xtal 32k xpd control by sw or fsm*/ 1112 #define RTC_CNTL_XTAL32K_XPD_FORCE (BIT(7)) 1113 #define RTC_CNTL_XTAL32K_XPD_FORCE_M (BIT(7)) 1114 #define RTC_CNTL_XTAL32K_XPD_FORCE_V 0x1 1115 #define RTC_CNTL_XTAL32K_XPD_FORCE_S 7 1116 /* RTC_CNTL_XTAL32K_AUTO_RETURN : R/W ;bitpos:[6] ;default: 1'b0 ; */ 1117 /*description: xtal 32k switch back xtal when xtal is restarted*/ 1118 #define RTC_CNTL_XTAL32K_AUTO_RETURN (BIT(6)) 1119 #define RTC_CNTL_XTAL32K_AUTO_RETURN_M (BIT(6)) 1120 #define RTC_CNTL_XTAL32K_AUTO_RETURN_V 0x1 1121 #define RTC_CNTL_XTAL32K_AUTO_RETURN_S 6 1122 /* RTC_CNTL_XTAL32K_AUTO_RESTART : R/W ;bitpos:[5] ;default: 1'b0 ; */ 1123 /*description: xtal 32k restart xtal when xtal is dead*/ 1124 #define RTC_CNTL_XTAL32K_AUTO_RESTART (BIT(5)) 1125 #define RTC_CNTL_XTAL32K_AUTO_RESTART_M (BIT(5)) 1126 #define RTC_CNTL_XTAL32K_AUTO_RESTART_V 0x1 1127 #define RTC_CNTL_XTAL32K_AUTO_RESTART_S 5 1128 /* RTC_CNTL_XTAL32K_AUTO_BACKUP : R/W ;bitpos:[4] ;default: 1'b0 ; */ 1129 /*description: xtal 32k switch to back up clock when xtal is dead*/ 1130 #define RTC_CNTL_XTAL32K_AUTO_BACKUP (BIT(4)) 1131 #define RTC_CNTL_XTAL32K_AUTO_BACKUP_M (BIT(4)) 1132 #define RTC_CNTL_XTAL32K_AUTO_BACKUP_V 0x1 1133 #define RTC_CNTL_XTAL32K_AUTO_BACKUP_S 4 1134 /* RTC_CNTL_XTAL32K_EXT_CLK_FO : R/W ;bitpos:[3] ;default: 1'b0 ; */ 1135 /*description: xtal 32k external xtal clock force on*/ 1136 #define RTC_CNTL_XTAL32K_EXT_CLK_FO (BIT(3)) 1137 #define RTC_CNTL_XTAL32K_EXT_CLK_FO_M (BIT(3)) 1138 #define RTC_CNTL_XTAL32K_EXT_CLK_FO_V 0x1 1139 #define RTC_CNTL_XTAL32K_EXT_CLK_FO_S 3 1140 /* RTC_CNTL_XTAL32K_WDT_RESET : R/W ;bitpos:[2] ;default: 1'b0 ; */ 1141 /*description: xtal 32k watch dog sw reset*/ 1142 #define RTC_CNTL_XTAL32K_WDT_RESET (BIT(2)) 1143 #define RTC_CNTL_XTAL32K_WDT_RESET_M (BIT(2)) 1144 #define RTC_CNTL_XTAL32K_WDT_RESET_V 0x1 1145 #define RTC_CNTL_XTAL32K_WDT_RESET_S 2 1146 /* RTC_CNTL_XTAL32K_WDT_CLK_FO : R/W ;bitpos:[1] ;default: 1'b0 ; */ 1147 /*description: xtal 32k watch dog clock force on*/ 1148 #define RTC_CNTL_XTAL32K_WDT_CLK_FO (BIT(1)) 1149 #define RTC_CNTL_XTAL32K_WDT_CLK_FO_M (BIT(1)) 1150 #define RTC_CNTL_XTAL32K_WDT_CLK_FO_V 0x1 1151 #define RTC_CNTL_XTAL32K_WDT_CLK_FO_S 1 1152 /* RTC_CNTL_XTAL32K_WDT_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */ 1153 /*description: xtal 32k watch dog enable*/ 1154 #define RTC_CNTL_XTAL32K_WDT_EN (BIT(0)) 1155 #define RTC_CNTL_XTAL32K_WDT_EN_M (BIT(0)) 1156 #define RTC_CNTL_XTAL32K_WDT_EN_V 0x1 1157 #define RTC_CNTL_XTAL32K_WDT_EN_S 0 1158 1159 #define RTC_CNTL_EXT_WAKEUP_CONF_REG (DR_REG_RTCCNTL_BASE + 0x0064) 1160 /* RTC_CNTL_EXT_WAKEUP1_LV : R/W ;bitpos:[31] ;default: 1'b0 ; */ 1161 /*description: */ 1162 #define RTC_CNTL_EXT_WAKEUP1_LV (BIT(31)) 1163 #define RTC_CNTL_EXT_WAKEUP1_LV_M (BIT(31)) 1164 #define RTC_CNTL_EXT_WAKEUP1_LV_V 0x1 1165 #define RTC_CNTL_EXT_WAKEUP1_LV_S 31 1166 /* RTC_CNTL_EXT_WAKEUP0_LV : R/W ;bitpos:[30] ;default: 1'b0 ; */ 1167 /*description: 0: external wakeup at low level 1: external wakeup at high level*/ 1168 #define RTC_CNTL_EXT_WAKEUP0_LV (BIT(30)) 1169 #define RTC_CNTL_EXT_WAKEUP0_LV_M (BIT(30)) 1170 #define RTC_CNTL_EXT_WAKEUP0_LV_V 0x1 1171 #define RTC_CNTL_EXT_WAKEUP0_LV_S 30 1172 /* RTC_CNTL_GPIO_WAKEUP_FILTER : R/W ;bitpos:[29] ;default: 1'd0 ; */ 1173 /*description: enable filter for gpio wakeup event*/ 1174 #define RTC_CNTL_GPIO_WAKEUP_FILTER (BIT(29)) 1175 #define RTC_CNTL_GPIO_WAKEUP_FILTER_M (BIT(29)) 1176 #define RTC_CNTL_GPIO_WAKEUP_FILTER_V 0x1 1177 #define RTC_CNTL_GPIO_WAKEUP_FILTER_S 29 1178 1179 #define RTC_CNTL_SLP_REJECT_CONF_REG (DR_REG_RTCCNTL_BASE + 0x0068) 1180 /* RTC_CNTL_DEEP_SLP_REJECT_EN : R/W ;bitpos:[31] ;default: 1'b0 ; */ 1181 /*description: enable reject for deep sleep*/ 1182 #define RTC_CNTL_DEEP_SLP_REJECT_EN (BIT(31)) 1183 #define RTC_CNTL_DEEP_SLP_REJECT_EN_M (BIT(31)) 1184 #define RTC_CNTL_DEEP_SLP_REJECT_EN_V 0x1 1185 #define RTC_CNTL_DEEP_SLP_REJECT_EN_S 31 1186 /* RTC_CNTL_LIGHT_SLP_REJECT_EN : R/W ;bitpos:[30] ;default: 1'b0 ; */ 1187 /*description: enable reject for light sleep*/ 1188 #define RTC_CNTL_LIGHT_SLP_REJECT_EN (BIT(30)) 1189 #define RTC_CNTL_LIGHT_SLP_REJECT_EN_M (BIT(30)) 1190 #define RTC_CNTL_LIGHT_SLP_REJECT_EN_V 0x1 1191 #define RTC_CNTL_LIGHT_SLP_REJECT_EN_S 30 1192 /* RTC_CNTL_SLEEP_REJECT_ENA : R/W ;bitpos:[29:13] ;default: 16'd0 ; */ 1193 /*description: sleep reject enable*/ 1194 #define RTC_CNTL_SLEEP_REJECT_ENA 0x0001FFFF 1195 #define RTC_CNTL_SLEEP_REJECT_ENA_M ((RTC_CNTL_SLEEP_REJECT_ENA_V)<<(RTC_CNTL_SLEEP_REJECT_ENA_S)) 1196 #define RTC_CNTL_SLEEP_REJECT_ENA_V 0x1FFFF 1197 #define RTC_CNTL_SLEEP_REJECT_ENA_S 13 1198 1199 #define RTC_CNTL_CPU_PERIOD_CONF_REG (DR_REG_RTCCNTL_BASE + 0x006C) 1200 /* RTC_CNTL_CPUPERIOD_SEL : R/W ;bitpos:[31:30] ;default: 2'b00 ; */ 1201 /*description: */ 1202 #define RTC_CNTL_CPUPERIOD_SEL 0x00000003 1203 #define RTC_CNTL_CPUPERIOD_SEL_M ((RTC_CNTL_CPUPERIOD_SEL_V)<<(RTC_CNTL_CPUPERIOD_SEL_S)) 1204 #define RTC_CNTL_CPUPERIOD_SEL_V 0x3 1205 #define RTC_CNTL_CPUPERIOD_SEL_S 30 1206 /* RTC_CNTL_CPUSEL_CONF : R/W ;bitpos:[29] ;default: 1'b0 ; */ 1207 /*description: CPU sel option*/ 1208 #define RTC_CNTL_CPUSEL_CONF (BIT(29)) 1209 #define RTC_CNTL_CPUSEL_CONF_M (BIT(29)) 1210 #define RTC_CNTL_CPUSEL_CONF_V 0x1 1211 #define RTC_CNTL_CPUSEL_CONF_S 29 1212 1213 #define RTC_CNTL_SDIO_ACT_CONF_REG (DR_REG_RTCCNTL_BASE + 0x0070) 1214 /* RTC_CNTL_SDIO_ACT_DNUM : R/W ;bitpos:[31:22] ;default: 10'b0 ; */ 1215 /*description: */ 1216 #define RTC_CNTL_SDIO_ACT_DNUM 0x000003FF 1217 #define RTC_CNTL_SDIO_ACT_DNUM_M ((RTC_CNTL_SDIO_ACT_DNUM_V)<<(RTC_CNTL_SDIO_ACT_DNUM_S)) 1218 #define RTC_CNTL_SDIO_ACT_DNUM_V 0x3FF 1219 #define RTC_CNTL_SDIO_ACT_DNUM_S 22 1220 1221 #define RTC_CNTL_CLK_CONF_REG (DR_REG_RTCCNTL_BASE + 0x0074) 1222 /* RTC_CNTL_ANA_CLK_RTC_SEL : R/W ;bitpos:[31:30] ;default: 2'd0 ; */ 1223 /*description: */ 1224 #define RTC_CNTL_ANA_CLK_RTC_SEL 0x00000003 1225 #define RTC_CNTL_ANA_CLK_RTC_SEL_M ((RTC_CNTL_ANA_CLK_RTC_SEL_V)<<(RTC_CNTL_ANA_CLK_RTC_SEL_S)) 1226 #define RTC_CNTL_ANA_CLK_RTC_SEL_V 0x3 1227 #define RTC_CNTL_ANA_CLK_RTC_SEL_S 30 1228 /* RTC_CNTL_FAST_CLK_RTC_SEL : R/W ;bitpos:[29] ;default: 1'b0 ; */ 1229 /*description: fast_clk_rtc sel. 0: XTAL div 4 1: CK8M*/ 1230 #define RTC_CNTL_FAST_CLK_RTC_SEL (BIT(29)) 1231 #define RTC_CNTL_FAST_CLK_RTC_SEL_M (BIT(29)) 1232 #define RTC_CNTL_FAST_CLK_RTC_SEL_V 0x1 1233 #define RTC_CNTL_FAST_CLK_RTC_SEL_S 29 1234 /* RTC_CNTL_CK8M_FORCE_PU : R/W ;bitpos:[26] ;default: 1'd0 ; */ 1235 /*description: CK8M force power up*/ 1236 #define RTC_CNTL_CK8M_FORCE_PU (BIT(26)) 1237 #define RTC_CNTL_CK8M_FORCE_PU_M (BIT(26)) 1238 #define RTC_CNTL_CK8M_FORCE_PU_V 0x1 1239 #define RTC_CNTL_CK8M_FORCE_PU_S 26 1240 /* RTC_CNTL_CK8M_FORCE_PD : R/W ;bitpos:[25] ;default: 1'd0 ; */ 1241 /*description: CK8M force power down*/ 1242 #define RTC_CNTL_CK8M_FORCE_PD (BIT(25)) 1243 #define RTC_CNTL_CK8M_FORCE_PD_M (BIT(25)) 1244 #define RTC_CNTL_CK8M_FORCE_PD_V 0x1 1245 #define RTC_CNTL_CK8M_FORCE_PD_S 25 1246 /* RTC_CNTL_CK8M_DFREQ : R/W ;bitpos:[24:17] ;default: 8'd172 ; */ 1247 /*description: CK8M_DFREQ*/ 1248 #define RTC_CNTL_CK8M_DFREQ 0x000000FF 1249 #define RTC_CNTL_CK8M_DFREQ_M ((RTC_CNTL_CK8M_DFREQ_V)<<(RTC_CNTL_CK8M_DFREQ_S)) 1250 #define RTC_CNTL_CK8M_DFREQ_V 0xFF 1251 #define RTC_CNTL_CK8M_DFREQ_S 17 1252 #define RTC_CNTL_CK8M_DFREQ_DEFAULT 172 //TODO, may change in chip7.2.3 1253 /* RTC_CNTL_CK8M_FORCE_NOGATING : R/W ;bitpos:[16] ;default: 1'd0 ; */ 1254 /*description: CK8M force no gating during sleep*/ 1255 #define RTC_CNTL_CK8M_FORCE_NOGATING (BIT(16)) 1256 #define RTC_CNTL_CK8M_FORCE_NOGATING_M (BIT(16)) 1257 #define RTC_CNTL_CK8M_FORCE_NOGATING_V 0x1 1258 #define RTC_CNTL_CK8M_FORCE_NOGATING_S 16 1259 /* RTC_CNTL_XTAL_FORCE_NOGATING : R/W ;bitpos:[15] ;default: 1'd0 ; */ 1260 /*description: XTAL force no gating during sleep*/ 1261 #define RTC_CNTL_XTAL_FORCE_NOGATING (BIT(15)) 1262 #define RTC_CNTL_XTAL_FORCE_NOGATING_M (BIT(15)) 1263 #define RTC_CNTL_XTAL_FORCE_NOGATING_V 0x1 1264 #define RTC_CNTL_XTAL_FORCE_NOGATING_S 15 1265 /* RTC_CNTL_CK8M_DIV_SEL : R/W ;bitpos:[14:12] ;default: 3'd3 ; */ 1266 /*description: divider = reg_ck8m_div_sel + 1*/ 1267 #define RTC_CNTL_CK8M_DIV_SEL 0x00000007 1268 #define RTC_CNTL_CK8M_DIV_SEL_M ((RTC_CNTL_CK8M_DIV_SEL_V)<<(RTC_CNTL_CK8M_DIV_SEL_S)) 1269 #define RTC_CNTL_CK8M_DIV_SEL_V 0x7 1270 #define RTC_CNTL_CK8M_DIV_SEL_S 12 1271 /* RTC_CNTL_DIG_CLK8M_EN : R/W ;bitpos:[10] ;default: 1'd0 ; */ 1272 /*description: enable CK8M for digital core (no relationship with RTC core)*/ 1273 #define RTC_CNTL_DIG_CLK8M_EN (BIT(10)) 1274 #define RTC_CNTL_DIG_CLK8M_EN_M (BIT(10)) 1275 #define RTC_CNTL_DIG_CLK8M_EN_V 0x1 1276 #define RTC_CNTL_DIG_CLK8M_EN_S 10 1277 /* RTC_CNTL_DIG_CLK8M_D256_EN : R/W ;bitpos:[9] ;default: 1'd1 ; */ 1278 /*description: enable CK8M_D256_OUT for digital core (no relationship with RTC core)*/ 1279 #define RTC_CNTL_DIG_CLK8M_D256_EN (BIT(9)) 1280 #define RTC_CNTL_DIG_CLK8M_D256_EN_M (BIT(9)) 1281 #define RTC_CNTL_DIG_CLK8M_D256_EN_V 0x1 1282 #define RTC_CNTL_DIG_CLK8M_D256_EN_S 9 1283 /* RTC_CNTL_DIG_XTAL32K_EN : R/W ;bitpos:[8] ;default: 1'd0 ; */ 1284 /*description: enable CK_XTAL_32K for digital core (no relationship with RTC core)*/ 1285 #define RTC_CNTL_DIG_XTAL32K_EN (BIT(8)) 1286 #define RTC_CNTL_DIG_XTAL32K_EN_M (BIT(8)) 1287 #define RTC_CNTL_DIG_XTAL32K_EN_V 0x1 1288 #define RTC_CNTL_DIG_XTAL32K_EN_S 8 1289 /* RTC_CNTL_ENB_CK8M_DIV : R/W ;bitpos:[7] ;default: 1'd0 ; */ 1290 /*description: 1: CK8M_D256_OUT is actually CK8M 0: CK8M_D256_OUT is CK8M divided by 256*/ 1291 #define RTC_CNTL_ENB_CK8M_DIV (BIT(7)) 1292 #define RTC_CNTL_ENB_CK8M_DIV_M (BIT(7)) 1293 #define RTC_CNTL_ENB_CK8M_DIV_V 0x1 1294 #define RTC_CNTL_ENB_CK8M_DIV_S 7 1295 /* RTC_CNTL_ENB_CK8M : R/W ;bitpos:[6] ;default: 1'd0 ; */ 1296 /*description: disable CK8M and CK8M_D256_OUT*/ 1297 #define RTC_CNTL_ENB_CK8M (BIT(6)) 1298 #define RTC_CNTL_ENB_CK8M_M (BIT(6)) 1299 #define RTC_CNTL_ENB_CK8M_V 0x1 1300 #define RTC_CNTL_ENB_CK8M_S 6 1301 /* RTC_CNTL_CK8M_DIV : R/W ;bitpos:[5:4] ;default: 2'b01 ; */ 1302 /*description: CK8M_D256_OUT divider. 00: div128 01: div256 10: div512 11: div1024.*/ 1303 #define RTC_CNTL_CK8M_DIV 0x00000003 1304 #define RTC_CNTL_CK8M_DIV_M ((RTC_CNTL_CK8M_DIV_V)<<(RTC_CNTL_CK8M_DIV_S)) 1305 #define RTC_CNTL_CK8M_DIV_V 0x3 1306 #define RTC_CNTL_CK8M_DIV_S 4 1307 /* RTC_CNTL_CK8M_DIV_SEL_VLD : R/W ;bitpos:[3] ;default: 1'b1 ; */ 1308 /*description: used to sync reg_ck8m_div_sel bus. Clear vld before set reg_ck8m_div_sel 1309 then set vld to actually switch the clk*/ 1310 #define RTC_CNTL_CK8M_DIV_SEL_VLD (BIT(3)) 1311 #define RTC_CNTL_CK8M_DIV_SEL_VLD_M (BIT(3)) 1312 #define RTC_CNTL_CK8M_DIV_SEL_VLD_V 0x1 1313 #define RTC_CNTL_CK8M_DIV_SEL_VLD_S 3 1314 1315 #define RTC_CNTL_SLOW_CLK_CONF_REG (DR_REG_RTCCNTL_BASE + 0x0078) 1316 /* RTC_CNTL_SLOW_CLK_NEXT_EDGE : R/W ;bitpos:[31] ;default: 1'b0 ; */ 1317 /*description: */ 1318 #define RTC_CNTL_SLOW_CLK_NEXT_EDGE (BIT(31)) 1319 #define RTC_CNTL_SLOW_CLK_NEXT_EDGE_M (BIT(31)) 1320 #define RTC_CNTL_SLOW_CLK_NEXT_EDGE_V 0x1 1321 #define RTC_CNTL_SLOW_CLK_NEXT_EDGE_S 31 1322 /* RTC_CNTL_ANA_CLK_DIV : R/W ;bitpos:[30:23] ;default: 8'd0 ; */ 1323 /*description: */ 1324 #define RTC_CNTL_ANA_CLK_DIV 0x000000FF 1325 #define RTC_CNTL_ANA_CLK_DIV_M ((RTC_CNTL_ANA_CLK_DIV_V)<<(RTC_CNTL_ANA_CLK_DIV_S)) 1326 #define RTC_CNTL_ANA_CLK_DIV_V 0xFF 1327 #define RTC_CNTL_ANA_CLK_DIV_S 23 1328 /* RTC_CNTL_ANA_CLK_DIV_VLD : R/W ;bitpos:[22] ;default: 1'b1 ; */ 1329 /*description: used to sync div bus. clear vld before set reg_rtc_ana_clk_div 1330 then set vld to actually switch the clk*/ 1331 #define RTC_CNTL_ANA_CLK_DIV_VLD (BIT(22)) 1332 #define RTC_CNTL_ANA_CLK_DIV_VLD_M (BIT(22)) 1333 #define RTC_CNTL_ANA_CLK_DIV_VLD_V 0x1 1334 #define RTC_CNTL_ANA_CLK_DIV_VLD_S 22 1335 1336 #define RTC_CNTL_SDIO_CONF_REG (DR_REG_RTCCNTL_BASE + 0x007C) 1337 /* RTC_CNTL_XPD_SDIO_REG : R/W ;bitpos:[31] ;default: 1'd0 ; */ 1338 /*description: */ 1339 #define RTC_CNTL_XPD_SDIO_REG (BIT(31)) 1340 #define RTC_CNTL_XPD_SDIO_REG_M (BIT(31)) 1341 #define RTC_CNTL_XPD_SDIO_REG_V 0x1 1342 #define RTC_CNTL_XPD_SDIO_REG_S 31 1343 /* RTC_CNTL_DREFH_SDIO : R/W ;bitpos:[30:29] ;default: 2'b00 ; */ 1344 /*description: SW option for DREFH_SDIO. Only active when reg_sdio_force = 1*/ 1345 #define RTC_CNTL_DREFH_SDIO 0x00000003 1346 #define RTC_CNTL_DREFH_SDIO_M ((RTC_CNTL_DREFH_SDIO_V)<<(RTC_CNTL_DREFH_SDIO_S)) 1347 #define RTC_CNTL_DREFH_SDIO_V 0x3 1348 #define RTC_CNTL_DREFH_SDIO_S 29 1349 /* RTC_CNTL_DREFM_SDIO : R/W ;bitpos:[28:27] ;default: 2'b00 ; */ 1350 /*description: SW option for DREFM_SDIO. Only active when reg_sdio_force = 1*/ 1351 #define RTC_CNTL_DREFM_SDIO 0x00000003 1352 #define RTC_CNTL_DREFM_SDIO_M ((RTC_CNTL_DREFM_SDIO_V)<<(RTC_CNTL_DREFM_SDIO_S)) 1353 #define RTC_CNTL_DREFM_SDIO_V 0x3 1354 #define RTC_CNTL_DREFM_SDIO_S 27 1355 /* RTC_CNTL_DREFL_SDIO : R/W ;bitpos:[26:25] ;default: 2'b01 ; */ 1356 /*description: SW option for DREFL_SDIO. Only active when reg_sdio_force = 1*/ 1357 #define RTC_CNTL_DREFL_SDIO 0x00000003 1358 #define RTC_CNTL_DREFL_SDIO_M ((RTC_CNTL_DREFL_SDIO_V)<<(RTC_CNTL_DREFL_SDIO_S)) 1359 #define RTC_CNTL_DREFL_SDIO_V 0x3 1360 #define RTC_CNTL_DREFL_SDIO_S 25 1361 /* RTC_CNTL_REG1P8_READY : RO ;bitpos:[24] ;default: 1'd0 ; */ 1362 /*description: read only register for REG1P8_READY*/ 1363 #define RTC_CNTL_REG1P8_READY (BIT(24)) 1364 #define RTC_CNTL_REG1P8_READY_M (BIT(24)) 1365 #define RTC_CNTL_REG1P8_READY_V 0x1 1366 #define RTC_CNTL_REG1P8_READY_S 24 1367 /* RTC_CNTL_SDIO_TIEH : R/W ;bitpos:[23] ;default: 1'd1 ; */ 1368 /*description: SW option for SDIO_TIEH. Only active when reg_sdio_force = 1*/ 1369 #define RTC_CNTL_SDIO_TIEH (BIT(23)) 1370 #define RTC_CNTL_SDIO_TIEH_M (BIT(23)) 1371 #define RTC_CNTL_SDIO_TIEH_V 0x1 1372 #define RTC_CNTL_SDIO_TIEH_S 23 1373 /* RTC_CNTL_SDIO_FORCE : R/W ;bitpos:[22] ;default: 1'd0 ; */ 1374 /*description: 1: use SW option to control SDIO_REG 0: use state machine*/ 1375 #define RTC_CNTL_SDIO_FORCE (BIT(22)) 1376 #define RTC_CNTL_SDIO_FORCE_M (BIT(22)) 1377 #define RTC_CNTL_SDIO_FORCE_V 0x1 1378 #define RTC_CNTL_SDIO_FORCE_S 22 1379 /* RTC_CNTL_SDIO_PD_EN : R/W ;bitpos:[21] ;default: 1'd1 ; */ 1380 /*description: power down SDIO_REG in sleep. Only active when reg_sdio_force = 0*/ 1381 #define RTC_CNTL_SDIO_PD_EN (BIT(21)) 1382 #define RTC_CNTL_SDIO_PD_EN_M (BIT(21)) 1383 #define RTC_CNTL_SDIO_PD_EN_V 0x1 1384 #define RTC_CNTL_SDIO_PD_EN_S 21 1385 /* RTC_CNTL_SDIO_ENCURLIM : R/W ;bitpos:[20] ;default: 1'd1 ; */ 1386 /*description: enable current limit*/ 1387 #define RTC_CNTL_SDIO_ENCURLIM (BIT(20)) 1388 #define RTC_CNTL_SDIO_ENCURLIM_M (BIT(20)) 1389 #define RTC_CNTL_SDIO_ENCURLIM_V 0x1 1390 #define RTC_CNTL_SDIO_ENCURLIM_S 20 1391 /* RTC_CNTL_SDIO_MODECURLIM : R/W ;bitpos:[19] ;default: 1'd0 ; */ 1392 /*description: select current limit mode*/ 1393 #define RTC_CNTL_SDIO_MODECURLIM (BIT(19)) 1394 #define RTC_CNTL_SDIO_MODECURLIM_M (BIT(19)) 1395 #define RTC_CNTL_SDIO_MODECURLIM_V 0x1 1396 #define RTC_CNTL_SDIO_MODECURLIM_S 19 1397 /* RTC_CNTL_SDIO_DCURLIM : R/W ;bitpos:[18:16] ;default: 3'd0 ; */ 1398 /*description: tune current limit threshold when tieh = 0. About 800mA/(8+d)*/ 1399 #define RTC_CNTL_SDIO_DCURLIM 0x00000007 1400 #define RTC_CNTL_SDIO_DCURLIM_M ((RTC_CNTL_SDIO_DCURLIM_V)<<(RTC_CNTL_SDIO_DCURLIM_S)) 1401 #define RTC_CNTL_SDIO_DCURLIM_V 0x7 1402 #define RTC_CNTL_SDIO_DCURLIM_S 16 1403 /* RTC_CNTL_SDIO_EN_INITI : R/W ;bitpos:[15] ;default: 1'd1 ; */ 1404 /*description: 0 to set init[1:0]=0*/ 1405 #define RTC_CNTL_SDIO_EN_INITI (BIT(15)) 1406 #define RTC_CNTL_SDIO_EN_INITI_M (BIT(15)) 1407 #define RTC_CNTL_SDIO_EN_INITI_V 0x1 1408 #define RTC_CNTL_SDIO_EN_INITI_S 15 1409 /* RTC_CNTL_SDIO_INITI : R/W ;bitpos:[14:13] ;default: 2'd1 ; */ 1410 /*description: add resistor from ldo output to ground. 0: no res 1: 6k 2: 4k 3: 2k*/ 1411 #define RTC_CNTL_SDIO_INITI 0x00000003 1412 #define RTC_CNTL_SDIO_INITI_M ((RTC_CNTL_SDIO_INITI_V)<<(RTC_CNTL_SDIO_INITI_S)) 1413 #define RTC_CNTL_SDIO_INITI_V 0x3 1414 #define RTC_CNTL_SDIO_INITI_S 13 1415 /* RTC_CNTL_SDIO_DCAP : R/W ;bitpos:[12:11] ;default: 2'b11 ; */ 1416 /*description: ability to prevent LDO from overshoot*/ 1417 #define RTC_CNTL_SDIO_DCAP 0x00000003 1418 #define RTC_CNTL_SDIO_DCAP_M ((RTC_CNTL_SDIO_DCAP_V)<<(RTC_CNTL_SDIO_DCAP_S)) 1419 #define RTC_CNTL_SDIO_DCAP_V 0x3 1420 #define RTC_CNTL_SDIO_DCAP_S 11 1421 /* RTC_CNTL_SDIO_DTHDRV : R/W ;bitpos:[10:9] ;default: 2'b11 ; */ 1422 /*description: Tieh = 1 mode drive ability. Initially set to 0 to limit charge 1423 current set to 3 after several us.*/ 1424 #define RTC_CNTL_SDIO_DTHDRV 0x00000003 1425 #define RTC_CNTL_SDIO_DTHDRV_M ((RTC_CNTL_SDIO_DTHDRV_V)<<(RTC_CNTL_SDIO_DTHDRV_S)) 1426 #define RTC_CNTL_SDIO_DTHDRV_V 0x3 1427 #define RTC_CNTL_SDIO_DTHDRV_S 9 1428 /* RTC_CNTL_SDIO_TIMER_TARGET : R/W ;bitpos:[7:0] ;default: 8'd10 ; */ 1429 /*description: timer count to apply reg_sdio_dcap after sdio power on*/ 1430 #define RTC_CNTL_SDIO_TIMER_TARGET 0x000000FF 1431 #define RTC_CNTL_SDIO_TIMER_TARGET_M ((RTC_CNTL_SDIO_TIMER_TARGET_V)<<(RTC_CNTL_SDIO_TIMER_TARGET_S)) 1432 #define RTC_CNTL_SDIO_TIMER_TARGET_V 0xFF 1433 #define RTC_CNTL_SDIO_TIMER_TARGET_S 0 1434 1435 #define RTC_CNTL_BIAS_CONF_REG (DR_REG_RTCCNTL_BASE + 0x0080) 1436 /* RTC_CNTL_RST_BIAS_I2C : R/W ;bitpos:[31] ;default: 1'd0 ; */ 1437 /*description: */ 1438 #define RTC_CNTL_RST_BIAS_I2C (BIT(31)) 1439 #define RTC_CNTL_RST_BIAS_I2C_M (BIT(31)) 1440 #define RTC_CNTL_RST_BIAS_I2C_V 0x1 1441 #define RTC_CNTL_RST_BIAS_I2C_S 31 1442 /* RTC_CNTL_DEC_HEARTBEAT_WIDTH : R/W ;bitpos:[30] ;default: 1'd0 ; */ 1443 /*description: DEC_HEARTBEAT_WIDTH*/ 1444 #define RTC_CNTL_DEC_HEARTBEAT_WIDTH (BIT(30)) 1445 #define RTC_CNTL_DEC_HEARTBEAT_WIDTH_M (BIT(30)) 1446 #define RTC_CNTL_DEC_HEARTBEAT_WIDTH_V 0x1 1447 #define RTC_CNTL_DEC_HEARTBEAT_WIDTH_S 30 1448 /* RTC_CNTL_INC_HEARTBEAT_PERIOD : R/W ;bitpos:[29] ;default: 1'd0 ; */ 1449 /*description: INC_HEARTBEAT_PERIOD*/ 1450 #define RTC_CNTL_INC_HEARTBEAT_PERIOD (BIT(29)) 1451 #define RTC_CNTL_INC_HEARTBEAT_PERIOD_M (BIT(29)) 1452 #define RTC_CNTL_INC_HEARTBEAT_PERIOD_V 0x1 1453 #define RTC_CNTL_INC_HEARTBEAT_PERIOD_S 29 1454 /* RTC_CNTL_DEC_HEARTBEAT_PERIOD : R/W ;bitpos:[28] ;default: 1'd0 ; */ 1455 /*description: DEC_HEARTBEAT_PERIOD*/ 1456 #define RTC_CNTL_DEC_HEARTBEAT_PERIOD (BIT(28)) 1457 #define RTC_CNTL_DEC_HEARTBEAT_PERIOD_M (BIT(28)) 1458 #define RTC_CNTL_DEC_HEARTBEAT_PERIOD_V 0x1 1459 #define RTC_CNTL_DEC_HEARTBEAT_PERIOD_S 28 1460 /* RTC_CNTL_INC_HEARTBEAT_REFRESH : R/W ;bitpos:[27] ;default: 1'd0 ; */ 1461 /*description: INC_HEARTBEAT_REFRESH*/ 1462 #define RTC_CNTL_INC_HEARTBEAT_REFRESH (BIT(27)) 1463 #define RTC_CNTL_INC_HEARTBEAT_REFRESH_M (BIT(27)) 1464 #define RTC_CNTL_INC_HEARTBEAT_REFRESH_V 0x1 1465 #define RTC_CNTL_INC_HEARTBEAT_REFRESH_S 27 1466 /* RTC_CNTL_ENB_SCK_XTAL : R/W ;bitpos:[26] ;default: 1'd0 ; */ 1467 /*description: ENB_SCK_XTAL*/ 1468 #define RTC_CNTL_ENB_SCK_XTAL (BIT(26)) 1469 #define RTC_CNTL_ENB_SCK_XTAL_M (BIT(26)) 1470 #define RTC_CNTL_ENB_SCK_XTAL_V 0x1 1471 #define RTC_CNTL_ENB_SCK_XTAL_S 26 1472 /* RTC_CNTL_DBG_ATTEN_MONITOR : R/W ;bitpos:[25:22] ;default: 4'd0 ; */ 1473 /*description: DBG_ATTEN when rtc in monitor state*/ 1474 #define RTC_CNTL_DBG_ATTEN_MONITOR 0x0000000F 1475 #define RTC_CNTL_DBG_ATTEN_MONITOR_M ((RTC_CNTL_DBG_ATTEN_MONITOR_V)<<(RTC_CNTL_DBG_ATTEN_MONITOR_S)) 1476 #define RTC_CNTL_DBG_ATTEN_MONITOR_V 0xF 1477 #define RTC_CNTL_DBG_ATTEN_MONITOR_S 22 1478 /* RTC_CNTL_DBG_ATTEN_DEEP_SLP : R/W ;bitpos:[21:18] ;default: 4'd0 ; */ 1479 /*description: DBG_ATTEN when rtc in sleep state*/ 1480 #define RTC_CNTL_DBG_ATTEN_DEEP_SLP 0x0000000F 1481 #define RTC_CNTL_DBG_ATTEN_DEEP_SLP_M ((RTC_CNTL_DBG_ATTEN_DEEP_SLP_V)<<(RTC_CNTL_DBG_ATTEN_DEEP_SLP_S)) 1482 #define RTC_CNTL_DBG_ATTEN_DEEP_SLP_V 0xF 1483 #define RTC_CNTL_DBG_ATTEN_DEEP_SLP_S 18 1484 /* RTC_CNTL_BIAS_SLEEP_MONITOR : R/W ;bitpos:[17] ;default: 1'b0 ; */ 1485 /*description: bias_sleep when rtc in monitor state*/ 1486 #define RTC_CNTL_BIAS_SLEEP_MONITOR (BIT(17)) 1487 #define RTC_CNTL_BIAS_SLEEP_MONITOR_M (BIT(17)) 1488 #define RTC_CNTL_BIAS_SLEEP_MONITOR_V 0x1 1489 #define RTC_CNTL_BIAS_SLEEP_MONITOR_S 17 1490 /* RTC_CNTL_BIAS_SLEEP_DEEP_SLP : R/W ;bitpos:[16] ;default: 1'b1 ; */ 1491 /*description: bias_sleep when rtc in sleep_state*/ 1492 #define RTC_CNTL_BIAS_SLEEP_DEEP_SLP (BIT(16)) 1493 #define RTC_CNTL_BIAS_SLEEP_DEEP_SLP_M (BIT(16)) 1494 #define RTC_CNTL_BIAS_SLEEP_DEEP_SLP_V 0x1 1495 #define RTC_CNTL_BIAS_SLEEP_DEEP_SLP_S 16 1496 /* RTC_CNTL_PD_CUR_MONITOR : R/W ;bitpos:[15] ;default: 1'b0 ; */ 1497 /*description: xpd cur when rtc in monitor state*/ 1498 #define RTC_CNTL_PD_CUR_MONITOR (BIT(15)) 1499 #define RTC_CNTL_PD_CUR_MONITOR_M (BIT(15)) 1500 #define RTC_CNTL_PD_CUR_MONITOR_V 0x1 1501 #define RTC_CNTL_PD_CUR_MONITOR_S 15 1502 /* RTC_CNTL_PD_CUR_DEEP_SLP : R/W ;bitpos:[14] ;default: 1'b0 ; */ 1503 /*description: xpd cur when rtc in sleep_state*/ 1504 #define RTC_CNTL_PD_CUR_DEEP_SLP (BIT(14)) 1505 #define RTC_CNTL_PD_CUR_DEEP_SLP_M (BIT(14)) 1506 #define RTC_CNTL_PD_CUR_DEEP_SLP_V 0x1 1507 #define RTC_CNTL_PD_CUR_DEEP_SLP_S 14 1508 /* RTC_CNTL_BIAS_BUF_MONITOR : R/W ;bitpos:[13] ;default: 1'b0 ; */ 1509 /*description: */ 1510 #define RTC_CNTL_BIAS_BUF_MONITOR (BIT(13)) 1511 #define RTC_CNTL_BIAS_BUF_MONITOR_M (BIT(13)) 1512 #define RTC_CNTL_BIAS_BUF_MONITOR_V 0x1 1513 #define RTC_CNTL_BIAS_BUF_MONITOR_S 13 1514 /* RTC_CNTL_BIAS_BUF_DEEP_SLP : R/W ;bitpos:[12] ;default: 1'b0 ; */ 1515 /*description: */ 1516 #define RTC_CNTL_BIAS_BUF_DEEP_SLP (BIT(12)) 1517 #define RTC_CNTL_BIAS_BUF_DEEP_SLP_M (BIT(12)) 1518 #define RTC_CNTL_BIAS_BUF_DEEP_SLP_V 0x1 1519 #define RTC_CNTL_BIAS_BUF_DEEP_SLP_S 12 1520 /* RTC_CNTL_BIAS_BUF_WAKE : R/W ;bitpos:[11] ;default: 1'b1 ; */ 1521 /*description: */ 1522 #define RTC_CNTL_BIAS_BUF_WAKE (BIT(11)) 1523 #define RTC_CNTL_BIAS_BUF_WAKE_M (BIT(11)) 1524 #define RTC_CNTL_BIAS_BUF_WAKE_V 0x1 1525 #define RTC_CNTL_BIAS_BUF_WAKE_S 11 1526 /* RTC_CNTL_BIAS_BUF_IDLE : R/W ;bitpos:[10] ;default: 1'b0 ; */ 1527 /*description: */ 1528 #define RTC_CNTL_BIAS_BUF_IDLE (BIT(10)) 1529 #define RTC_CNTL_BIAS_BUF_IDLE_M (BIT(10)) 1530 #define RTC_CNTL_BIAS_BUF_IDLE_V 0x1 1531 #define RTC_CNTL_BIAS_BUF_IDLE_S 10 1532 1533 #define RTC_CNTL_REG (DR_REG_RTCCNTL_BASE + 0x0084) 1534 /* RTC_CNTL_REGULATOR_FORCE_PU : R/W ;bitpos:[31] ;default: 1'd1 ; */ 1535 /*description: */ 1536 #define RTC_CNTL_REGULATOR_FORCE_PU (BIT(31)) 1537 #define RTC_CNTL_REGULATOR_FORCE_PU_M (BIT(31)) 1538 #define RTC_CNTL_REGULATOR_FORCE_PU_V 0x1 1539 #define RTC_CNTL_REGULATOR_FORCE_PU_S 31 1540 /* RTC_CNTL_REGULATOR_FORCE_PD : R/W ;bitpos:[30] ;default: 1'd0 ; */ 1541 /*description: RTC_REG force power down (for RTC_REG power down means decrease 1542 the voltage to 0.8v or lower )*/ 1543 #define RTC_CNTL_REGULATOR_FORCE_PD (BIT(30)) 1544 #define RTC_CNTL_REGULATOR_FORCE_PD_M (BIT(30)) 1545 #define RTC_CNTL_REGULATOR_FORCE_PD_V 0x1 1546 #define RTC_CNTL_REGULATOR_FORCE_PD_S 30 1547 /* RTC_CNTL_DBOOST_FORCE_PU : R/W ;bitpos:[29] ;default: 1'd1 ; */ 1548 /*description: RTC_DBOOST force power up*/ 1549 #define RTC_CNTL_DBOOST_FORCE_PU (BIT(29)) 1550 #define RTC_CNTL_DBOOST_FORCE_PU_M (BIT(29)) 1551 #define RTC_CNTL_DBOOST_FORCE_PU_V 0x1 1552 #define RTC_CNTL_DBOOST_FORCE_PU_S 29 1553 /* RTC_CNTL_DBOOST_FORCE_PD : R/W ;bitpos:[28] ;default: 1'd0 ; */ 1554 /*description: RTC_DBOOST force power down*/ 1555 #define RTC_CNTL_DBOOST_FORCE_PD (BIT(28)) 1556 #define RTC_CNTL_DBOOST_FORCE_PD_M (BIT(28)) 1557 #define RTC_CNTL_DBOOST_FORCE_PD_V 0x1 1558 #define RTC_CNTL_DBOOST_FORCE_PD_S 28 1559 /* RTC_CNTL_DBIAS_WAK : R/W ;bitpos:[27:25] ;default: 3'd4 ; */ 1560 /*description: RTC_DBIAS during wakeup*/ 1561 #define RTC_CNTL_DBIAS_WAK 0x00000007 1562 #define RTC_CNTL_DBIAS_WAK_M ((RTC_CNTL_DBIAS_WAK_V)<<(RTC_CNTL_DBIAS_WAK_S)) 1563 #define RTC_CNTL_DBIAS_WAK_V 0x7 1564 #define RTC_CNTL_DBIAS_WAK_S 25 1565 /* Approximate mapping of voltages to RTC_CNTL_DBIAS_WAK, RTC_CNTL_DBIAS_SLP, 1566 * RTC_CNTL_DIG_DBIAS_WAK, RTC_CNTL_DIG_DBIAS_SLP values. 1567 * Valid if RTC_CNTL_DBG_ATTEN is 0. 1568 */ 1569 #define RTC_CNTL_DIG_DBIAS_0V85 0 1570 #define RTC_CNTL_DIG_DBIAS_0V90 1 1571 #define RTC_CNTL_DIG_DBIAS_0V95 2 1572 #define RTC_CNTL_DIG_DBIAS_1V00 3 1573 #define RTC_CNTL_DIG_DBIAS_1V05 4 1574 #define RTC_CNTL_DIG_DBIAS_1V10 5 1575 #define RTC_CNTL_DIG_DBIAS_1V15 6 1576 #define RTC_CNTL_DIG_DBIAS_1V20 7 1577 1578 /* RTC_CNTL_DBIAS_SLP : R/W ;bitpos:[24:22] ;default: 3'd4 ; */ 1579 /*description: RTC_DBIAS during sleep*/ 1580 #define RTC_CNTL_DBIAS_SLP 0x00000007 1581 #define RTC_CNTL_DBIAS_SLP_M ((RTC_CNTL_DBIAS_SLP_V)<<(RTC_CNTL_DBIAS_SLP_S)) 1582 #define RTC_CNTL_DBIAS_SLP_V 0x7 1583 #define RTC_CNTL_DBIAS_SLP_S 22 1584 /* RTC_CNTL_SCK_DCAP : R/W ;bitpos:[21:14] ;default: 8'd0 ; */ 1585 /*description: SCK_DCAP*/ 1586 #define RTC_CNTL_SCK_DCAP 0x000000FF 1587 #define RTC_CNTL_SCK_DCAP_M ((RTC_CNTL_SCK_DCAP_V)<<(RTC_CNTL_SCK_DCAP_S)) 1588 #define RTC_CNTL_SCK_DCAP_V 0xFF 1589 #define RTC_CNTL_SCK_DCAP_S 14 1590 /* RTC_CNTL_DIG_DBIAS_WAK : R/W ;bitpos:[13:11] ;default: 3'd4 ; */ 1591 /*description: DIG_REG_DBIAS during wakeup*/ 1592 #define RTC_CNTL_DIG_DBIAS_WAK 0x00000007 1593 #define RTC_CNTL_DIG_DBIAS_WAK_M ((RTC_CNTL_DIG_DBIAS_WAK_V)<<(RTC_CNTL_DIG_DBIAS_WAK_S)) 1594 #define RTC_CNTL_DIG_DBIAS_WAK_V 0x7 1595 #define RTC_CNTL_DIG_DBIAS_WAK_S 11 1596 /* RTC_CNTL_DIG_DBIAS_SLP : R/W ;bitpos:[10:8] ;default: 3'd4 ; */ 1597 /*description: DIG_REG_DBIAS during sleep*/ 1598 #define RTC_CNTL_DIG_DBIAS_SLP 0x00000007 1599 #define RTC_CNTL_DIG_DBIAS_SLP_M ((RTC_CNTL_DIG_DBIAS_SLP_V)<<(RTC_CNTL_DIG_DBIAS_SLP_S)) 1600 #define RTC_CNTL_DIG_DBIAS_SLP_V 0x7 1601 #define RTC_CNTL_DIG_DBIAS_SLP_S 8 1602 1603 #define RTC_CNTL_PWC_REG (DR_REG_RTCCNTL_BASE + 0x0088) 1604 /* RTC_CNTL_PAD_FORCE_HOLD : R/W ;bitpos:[21] ;default: 1'd0 ; */ 1605 /*description: rtc pad force hold*/ 1606 #define RTC_CNTL_PAD_FORCE_HOLD (BIT(21)) 1607 #define RTC_CNTL_PAD_FORCE_HOLD_M (BIT(21)) 1608 #define RTC_CNTL_PAD_FORCE_HOLD_V 0x1 1609 #define RTC_CNTL_PAD_FORCE_HOLD_S 21 1610 /* RTC_CNTL_PD_EN : R/W ;bitpos:[20] ;default: 1'd0 ; */ 1611 /*description: enable power down rtc_peri in sleep*/ 1612 #define RTC_CNTL_PD_EN (BIT(20)) 1613 #define RTC_CNTL_PD_EN_M (BIT(20)) 1614 #define RTC_CNTL_PD_EN_V 0x1 1615 #define RTC_CNTL_PD_EN_S 20 1616 /* RTC_CNTL_FORCE_PU : R/W ;bitpos:[19] ;default: 1'd0 ; */ 1617 /*description: rtc_peri force power up*/ 1618 #define RTC_CNTL_FORCE_PU (BIT(19)) 1619 #define RTC_CNTL_FORCE_PU_M (BIT(19)) 1620 #define RTC_CNTL_FORCE_PU_V 0x1 1621 #define RTC_CNTL_FORCE_PU_S 19 1622 /* RTC_CNTL_FORCE_PD : R/W ;bitpos:[18] ;default: 1'b0 ; */ 1623 /*description: rtc_peri force power down*/ 1624 #define RTC_CNTL_FORCE_PD (BIT(18)) 1625 #define RTC_CNTL_FORCE_PD_M (BIT(18)) 1626 #define RTC_CNTL_FORCE_PD_V 0x1 1627 #define RTC_CNTL_FORCE_PD_S 18 1628 /* RTC_CNTL_SLOWMEM_PD_EN : R/W ;bitpos:[17] ;default: 1'b0 ; */ 1629 /*description: enable power down RTC memory in sleep*/ 1630 #define RTC_CNTL_SLOWMEM_PD_EN (BIT(17)) 1631 #define RTC_CNTL_SLOWMEM_PD_EN_M (BIT(17)) 1632 #define RTC_CNTL_SLOWMEM_PD_EN_V 0x1 1633 #define RTC_CNTL_SLOWMEM_PD_EN_S 17 1634 /* RTC_CNTL_SLOWMEM_FORCE_PU : R/W ;bitpos:[16] ;default: 1'b1 ; */ 1635 /*description: RTC memory force power up*/ 1636 #define RTC_CNTL_SLOWMEM_FORCE_PU (BIT(16)) 1637 #define RTC_CNTL_SLOWMEM_FORCE_PU_M (BIT(16)) 1638 #define RTC_CNTL_SLOWMEM_FORCE_PU_V 0x1 1639 #define RTC_CNTL_SLOWMEM_FORCE_PU_S 16 1640 /* RTC_CNTL_SLOWMEM_FORCE_PD : R/W ;bitpos:[15] ;default: 1'b0 ; */ 1641 /*description: RTC memory force power down*/ 1642 #define RTC_CNTL_SLOWMEM_FORCE_PD (BIT(15)) 1643 #define RTC_CNTL_SLOWMEM_FORCE_PD_M (BIT(15)) 1644 #define RTC_CNTL_SLOWMEM_FORCE_PD_V 0x1 1645 #define RTC_CNTL_SLOWMEM_FORCE_PD_S 15 1646 /* RTC_CNTL_FASTMEM_PD_EN : R/W ;bitpos:[14] ;default: 1'b0 ; */ 1647 /*description: enable power down fast RTC memory in sleep*/ 1648 #define RTC_CNTL_FASTMEM_PD_EN (BIT(14)) 1649 #define RTC_CNTL_FASTMEM_PD_EN_M (BIT(14)) 1650 #define RTC_CNTL_FASTMEM_PD_EN_V 0x1 1651 #define RTC_CNTL_FASTMEM_PD_EN_S 14 1652 /* RTC_CNTL_FASTMEM_FORCE_PU : R/W ;bitpos:[13] ;default: 1'b1 ; */ 1653 /*description: Fast RTC memory force power up*/ 1654 #define RTC_CNTL_FASTMEM_FORCE_PU (BIT(13)) 1655 #define RTC_CNTL_FASTMEM_FORCE_PU_M (BIT(13)) 1656 #define RTC_CNTL_FASTMEM_FORCE_PU_V 0x1 1657 #define RTC_CNTL_FASTMEM_FORCE_PU_S 13 1658 /* RTC_CNTL_FASTMEM_FORCE_PD : R/W ;bitpos:[12] ;default: 1'b0 ; */ 1659 /*description: Fast RTC memory force power down*/ 1660 #define RTC_CNTL_FASTMEM_FORCE_PD (BIT(12)) 1661 #define RTC_CNTL_FASTMEM_FORCE_PD_M (BIT(12)) 1662 #define RTC_CNTL_FASTMEM_FORCE_PD_V 0x1 1663 #define RTC_CNTL_FASTMEM_FORCE_PD_S 12 1664 /* RTC_CNTL_SLOWMEM_FORCE_LPU : R/W ;bitpos:[11] ;default: 1'b1 ; */ 1665 /*description: RTC memory force no PD*/ 1666 #define RTC_CNTL_SLOWMEM_FORCE_LPU (BIT(11)) 1667 #define RTC_CNTL_SLOWMEM_FORCE_LPU_M (BIT(11)) 1668 #define RTC_CNTL_SLOWMEM_FORCE_LPU_V 0x1 1669 #define RTC_CNTL_SLOWMEM_FORCE_LPU_S 11 1670 /* RTC_CNTL_SLOWMEM_FORCE_LPD : R/W ;bitpos:[10] ;default: 1'b0 ; */ 1671 /*description: RTC memory force PD*/ 1672 #define RTC_CNTL_SLOWMEM_FORCE_LPD (BIT(10)) 1673 #define RTC_CNTL_SLOWMEM_FORCE_LPD_M (BIT(10)) 1674 #define RTC_CNTL_SLOWMEM_FORCE_LPD_V 0x1 1675 #define RTC_CNTL_SLOWMEM_FORCE_LPD_S 10 1676 /* RTC_CNTL_SLOWMEM_FOLW_CPU : R/W ;bitpos:[9] ;default: 1'b0 ; */ 1677 /*description: 1: RTC memory PD following CPU 0: RTC memory PD following RTC state machine*/ 1678 #define RTC_CNTL_SLOWMEM_FOLW_CPU (BIT(9)) 1679 #define RTC_CNTL_SLOWMEM_FOLW_CPU_M (BIT(9)) 1680 #define RTC_CNTL_SLOWMEM_FOLW_CPU_V 0x1 1681 #define RTC_CNTL_SLOWMEM_FOLW_CPU_S 9 1682 /* RTC_CNTL_FASTMEM_FORCE_LPU : R/W ;bitpos:[8] ;default: 1'b1 ; */ 1683 /*description: Fast RTC memory force no PD*/ 1684 #define RTC_CNTL_FASTMEM_FORCE_LPU (BIT(8)) 1685 #define RTC_CNTL_FASTMEM_FORCE_LPU_M (BIT(8)) 1686 #define RTC_CNTL_FASTMEM_FORCE_LPU_V 0x1 1687 #define RTC_CNTL_FASTMEM_FORCE_LPU_S 8 1688 /* RTC_CNTL_FASTMEM_FORCE_LPD : R/W ;bitpos:[7] ;default: 1'b0 ; */ 1689 /*description: Fast RTC memory force PD*/ 1690 #define RTC_CNTL_FASTMEM_FORCE_LPD (BIT(7)) 1691 #define RTC_CNTL_FASTMEM_FORCE_LPD_M (BIT(7)) 1692 #define RTC_CNTL_FASTMEM_FORCE_LPD_V 0x1 1693 #define RTC_CNTL_FASTMEM_FORCE_LPD_S 7 1694 /* RTC_CNTL_FASTMEM_FOLW_CPU : R/W ;bitpos:[6] ;default: 1'b0 ; */ 1695 /*description: 1: Fast RTC memory PD following CPU 0: fast RTC memory PD following 1696 RTC state machine*/ 1697 #define RTC_CNTL_FASTMEM_FOLW_CPU (BIT(6)) 1698 #define RTC_CNTL_FASTMEM_FOLW_CPU_M (BIT(6)) 1699 #define RTC_CNTL_FASTMEM_FOLW_CPU_V 0x1 1700 #define RTC_CNTL_FASTMEM_FOLW_CPU_S 6 1701 /* RTC_CNTL_FORCE_NOISO : R/W ;bitpos:[5] ;default: 1'd1 ; */ 1702 /*description: rtc_peri force no ISO*/ 1703 #define RTC_CNTL_FORCE_NOISO (BIT(5)) 1704 #define RTC_CNTL_FORCE_NOISO_M (BIT(5)) 1705 #define RTC_CNTL_FORCE_NOISO_V 0x1 1706 #define RTC_CNTL_FORCE_NOISO_S 5 1707 /* RTC_CNTL_FORCE_ISO : R/W ;bitpos:[4] ;default: 1'd0 ; */ 1708 /*description: rtc_peri force ISO*/ 1709 #define RTC_CNTL_FORCE_ISO (BIT(4)) 1710 #define RTC_CNTL_FORCE_ISO_M (BIT(4)) 1711 #define RTC_CNTL_FORCE_ISO_V 0x1 1712 #define RTC_CNTL_FORCE_ISO_S 4 1713 /* RTC_CNTL_SLOWMEM_FORCE_ISO : R/W ;bitpos:[3] ;default: 1'b0 ; */ 1714 /*description: RTC memory force ISO*/ 1715 #define RTC_CNTL_SLOWMEM_FORCE_ISO (BIT(3)) 1716 #define RTC_CNTL_SLOWMEM_FORCE_ISO_M (BIT(3)) 1717 #define RTC_CNTL_SLOWMEM_FORCE_ISO_V 0x1 1718 #define RTC_CNTL_SLOWMEM_FORCE_ISO_S 3 1719 /* RTC_CNTL_SLOWMEM_FORCE_NOISO : R/W ;bitpos:[2] ;default: 1'b1 ; */ 1720 /*description: RTC memory force no ISO*/ 1721 #define RTC_CNTL_SLOWMEM_FORCE_NOISO (BIT(2)) 1722 #define RTC_CNTL_SLOWMEM_FORCE_NOISO_M (BIT(2)) 1723 #define RTC_CNTL_SLOWMEM_FORCE_NOISO_V 0x1 1724 #define RTC_CNTL_SLOWMEM_FORCE_NOISO_S 2 1725 /* RTC_CNTL_FASTMEM_FORCE_ISO : R/W ;bitpos:[1] ;default: 1'b0 ; */ 1726 /*description: Fast RTC memory force ISO*/ 1727 #define RTC_CNTL_FASTMEM_FORCE_ISO (BIT(1)) 1728 #define RTC_CNTL_FASTMEM_FORCE_ISO_M (BIT(1)) 1729 #define RTC_CNTL_FASTMEM_FORCE_ISO_V 0x1 1730 #define RTC_CNTL_FASTMEM_FORCE_ISO_S 1 1731 /* RTC_CNTL_FASTMEM_FORCE_NOISO : R/W ;bitpos:[0] ;default: 1'b1 ; */ 1732 /*description: Fast RTC memory force no ISO*/ 1733 #define RTC_CNTL_FASTMEM_FORCE_NOISO (BIT(0)) 1734 #define RTC_CNTL_FASTMEM_FORCE_NOISO_M (BIT(0)) 1735 #define RTC_CNTL_FASTMEM_FORCE_NOISO_V 0x1 1736 #define RTC_CNTL_FASTMEM_FORCE_NOISO_S 0 1737 /* Useful groups of RTC_CNTL_PWC_REG bits */ 1738 #define RTC_CNTL_MEM_FORCE_ISO \ 1739 (RTC_CNTL_SLOWMEM_FORCE_ISO | RTC_CNTL_FASTMEM_FORCE_ISO) 1740 #define RTC_CNTL_MEM_FORCE_NOISO \ 1741 (RTC_CNTL_SLOWMEM_FORCE_NOISO | RTC_CNTL_FASTMEM_FORCE_NOISO) 1742 #define RTC_CNTL_MEM_PD_EN \ 1743 (RTC_CNTL_SLOWMEM_PD_EN | RTC_CNTL_FASTMEM_PD_EN) 1744 #define RTC_CNTL_MEM_FORCE_PU \ 1745 (RTC_CNTL_SLOWMEM_FORCE_PU | RTC_CNTL_FASTMEM_FORCE_PU) 1746 #define RTC_CNTL_MEM_FORCE_PD \ 1747 (RTC_CNTL_SLOWMEM_FORCE_PD | RTC_CNTL_FASTMEM_FORCE_PD) 1748 #define RTC_CNTL_MEM_FOLW_CPU \ 1749 (RTC_CNTL_SLOWMEM_FOLW_CPU | RTC_CNTL_FASTMEM_FOLW_CPU) 1750 #define RTC_CNTL_MEM_FORCE_LPU \ 1751 (RTC_CNTL_SLOWMEM_FORCE_LPU | RTC_CNTL_FASTMEM_FORCE_LPU) 1752 #define RTC_CNTL_MEM_FORCE_LPD \ 1753 (RTC_CNTL_SLOWMEM_FORCE_LPD | RTC_CNTL_FASTMEM_FORCE_LPD) 1754 1755 #define RTC_CNTL_DIG_PWC_REG (DR_REG_RTCCNTL_BASE + 0x008C) 1756 /* RTC_CNTL_DG_WRAP_PD_EN : R/W ;bitpos:[31] ;default: 0 ; */ 1757 /*description: */ 1758 #define RTC_CNTL_DG_WRAP_PD_EN (BIT(31)) 1759 #define RTC_CNTL_DG_WRAP_PD_EN_M (BIT(31)) 1760 #define RTC_CNTL_DG_WRAP_PD_EN_V 0x1 1761 #define RTC_CNTL_DG_WRAP_PD_EN_S 31 1762 /* RTC_CNTL_WIFI_PD_EN : R/W ;bitpos:[30] ;default: 0 ; */ 1763 /*description: enable power down wifi in sleep*/ 1764 #define RTC_CNTL_WIFI_PD_EN (BIT(30)) 1765 #define RTC_CNTL_WIFI_PD_EN_M (BIT(30)) 1766 #define RTC_CNTL_WIFI_PD_EN_V 0x1 1767 #define RTC_CNTL_WIFI_PD_EN_S 30 1768 /* RTC_CNTL_INTER_RAM4_PD_EN : R/W ;bitpos:[29] ;default: 0 ; */ 1769 /*description: enable power down internal SRAM 4 in sleep*/ 1770 #define RTC_CNTL_INTER_RAM4_PD_EN (BIT(29)) 1771 #define RTC_CNTL_INTER_RAM4_PD_EN_M (BIT(29)) 1772 #define RTC_CNTL_INTER_RAM4_PD_EN_V 0x1 1773 #define RTC_CNTL_INTER_RAM4_PD_EN_S 29 1774 /* RTC_CNTL_INTER_RAM3_PD_EN : R/W ;bitpos:[28] ;default: 0 ; */ 1775 /*description: enable power down internal SRAM 3 in sleep*/ 1776 #define RTC_CNTL_INTER_RAM3_PD_EN (BIT(28)) 1777 #define RTC_CNTL_INTER_RAM3_PD_EN_M (BIT(28)) 1778 #define RTC_CNTL_INTER_RAM3_PD_EN_V 0x1 1779 #define RTC_CNTL_INTER_RAM3_PD_EN_S 28 1780 /* RTC_CNTL_INTER_RAM2_PD_EN : R/W ;bitpos:[27] ;default: 0 ; */ 1781 /*description: enable power down internal SRAM 2 in sleep*/ 1782 #define RTC_CNTL_INTER_RAM2_PD_EN (BIT(27)) 1783 #define RTC_CNTL_INTER_RAM2_PD_EN_M (BIT(27)) 1784 #define RTC_CNTL_INTER_RAM2_PD_EN_V 0x1 1785 #define RTC_CNTL_INTER_RAM2_PD_EN_S 27 1786 /* RTC_CNTL_INTER_RAM1_PD_EN : R/W ;bitpos:[26] ;default: 0 ; */ 1787 /*description: enable power down internal SRAM 1 in sleep*/ 1788 #define RTC_CNTL_INTER_RAM1_PD_EN (BIT(26)) 1789 #define RTC_CNTL_INTER_RAM1_PD_EN_M (BIT(26)) 1790 #define RTC_CNTL_INTER_RAM1_PD_EN_V 0x1 1791 #define RTC_CNTL_INTER_RAM1_PD_EN_S 26 1792 /* RTC_CNTL_INTER_RAM0_PD_EN : R/W ;bitpos:[25] ;default: 0 ; */ 1793 /*description: enable power down internal SRAM 0 in sleep*/ 1794 #define RTC_CNTL_INTER_RAM0_PD_EN (BIT(25)) 1795 #define RTC_CNTL_INTER_RAM0_PD_EN_M (BIT(25)) 1796 #define RTC_CNTL_INTER_RAM0_PD_EN_V 0x1 1797 #define RTC_CNTL_INTER_RAM0_PD_EN_S 25 1798 /* RTC_CNTL_ROM0_PD_EN : R/W ;bitpos:[24] ;default: 0 ; */ 1799 /*description: enable power down ROM in sleep*/ 1800 #define RTC_CNTL_ROM0_PD_EN (BIT(24)) 1801 #define RTC_CNTL_ROM0_PD_EN_M (BIT(24)) 1802 #define RTC_CNTL_ROM0_PD_EN_V 0x1 1803 #define RTC_CNTL_ROM0_PD_EN_S 24 1804 /* RTC_CNTL_DG_DCDC_PD_EN : R/W ;bitpos:[23] ;default: 0 ; */ 1805 /*description: enable power down digital dcdc in sleep*/ 1806 #define RTC_CNTL_DG_DCDC_PD_EN (BIT(23)) 1807 #define RTC_CNTL_DG_DCDC_PD_EN_M (BIT(23)) 1808 #define RTC_CNTL_DG_DCDC_PD_EN_V 0x1 1809 #define RTC_CNTL_DG_DCDC_PD_EN_S 23 1810 /* RTC_CNTL_DG_DCDC_FORCE_PU : R/W ;bitpos:[22] ;default: 1'd1 ; */ 1811 /*description: digital dcdc force power up*/ 1812 #define RTC_CNTL_DG_DCDC_FORCE_PU (BIT(22)) 1813 #define RTC_CNTL_DG_DCDC_FORCE_PU_M (BIT(22)) 1814 #define RTC_CNTL_DG_DCDC_FORCE_PU_V 0x1 1815 #define RTC_CNTL_DG_DCDC_FORCE_PU_S 22 1816 /* RTC_CNTL_DG_DCDC_FORCE_PD : R/W ;bitpos:[21] ;default: 1'b0 ; */ 1817 /*description: digital dcdc force power down*/ 1818 #define RTC_CNTL_DG_DCDC_FORCE_PD (BIT(21)) 1819 #define RTC_CNTL_DG_DCDC_FORCE_PD_M (BIT(21)) 1820 #define RTC_CNTL_DG_DCDC_FORCE_PD_V 0x1 1821 #define RTC_CNTL_DG_DCDC_FORCE_PD_S 21 1822 /* RTC_CNTL_DG_WRAP_FORCE_PU : R/W ;bitpos:[20] ;default: 1'd1 ; */ 1823 /*description: digital core force power up*/ 1824 #define RTC_CNTL_DG_WRAP_FORCE_PU (BIT(20)) 1825 #define RTC_CNTL_DG_WRAP_FORCE_PU_M (BIT(20)) 1826 #define RTC_CNTL_DG_WRAP_FORCE_PU_V 0x1 1827 #define RTC_CNTL_DG_WRAP_FORCE_PU_S 20 1828 /* RTC_CNTL_DG_WRAP_FORCE_PD : R/W ;bitpos:[19] ;default: 1'b0 ; */ 1829 /*description: digital core force power down*/ 1830 #define RTC_CNTL_DG_WRAP_FORCE_PD (BIT(19)) 1831 #define RTC_CNTL_DG_WRAP_FORCE_PD_M (BIT(19)) 1832 #define RTC_CNTL_DG_WRAP_FORCE_PD_V 0x1 1833 #define RTC_CNTL_DG_WRAP_FORCE_PD_S 19 1834 /* RTC_CNTL_WIFI_FORCE_PU : R/W ;bitpos:[18] ;default: 1'd1 ; */ 1835 /*description: wifi force power up*/ 1836 #define RTC_CNTL_WIFI_FORCE_PU (BIT(18)) 1837 #define RTC_CNTL_WIFI_FORCE_PU_M (BIT(18)) 1838 #define RTC_CNTL_WIFI_FORCE_PU_V 0x1 1839 #define RTC_CNTL_WIFI_FORCE_PU_S 18 1840 /* RTC_CNTL_WIFI_FORCE_PD : R/W ;bitpos:[17] ;default: 1'b0 ; */ 1841 /*description: wifi force power down*/ 1842 #define RTC_CNTL_WIFI_FORCE_PD (BIT(17)) 1843 #define RTC_CNTL_WIFI_FORCE_PD_M (BIT(17)) 1844 #define RTC_CNTL_WIFI_FORCE_PD_V 0x1 1845 #define RTC_CNTL_WIFI_FORCE_PD_S 17 1846 /* RTC_CNTL_INTER_RAM4_FORCE_PU : R/W ;bitpos:[16] ;default: 1'd1 ; */ 1847 /*description: internal SRAM 4 force power up*/ 1848 #define RTC_CNTL_INTER_RAM4_FORCE_PU (BIT(16)) 1849 #define RTC_CNTL_INTER_RAM4_FORCE_PU_M (BIT(16)) 1850 #define RTC_CNTL_INTER_RAM4_FORCE_PU_V 0x1 1851 #define RTC_CNTL_INTER_RAM4_FORCE_PU_S 16 1852 /* RTC_CNTL_INTER_RAM4_FORCE_PD : R/W ;bitpos:[15] ;default: 1'b0 ; */ 1853 /*description: internal SRAM 4 force power down*/ 1854 #define RTC_CNTL_INTER_RAM4_FORCE_PD (BIT(15)) 1855 #define RTC_CNTL_INTER_RAM4_FORCE_PD_M (BIT(15)) 1856 #define RTC_CNTL_INTER_RAM4_FORCE_PD_V 0x1 1857 #define RTC_CNTL_INTER_RAM4_FORCE_PD_S 15 1858 /* RTC_CNTL_INTER_RAM3_FORCE_PU : R/W ;bitpos:[14] ;default: 1'd1 ; */ 1859 /*description: internal SRAM 3 force power up*/ 1860 #define RTC_CNTL_INTER_RAM3_FORCE_PU (BIT(14)) 1861 #define RTC_CNTL_INTER_RAM3_FORCE_PU_M (BIT(14)) 1862 #define RTC_CNTL_INTER_RAM3_FORCE_PU_V 0x1 1863 #define RTC_CNTL_INTER_RAM3_FORCE_PU_S 14 1864 /* RTC_CNTL_INTER_RAM3_FORCE_PD : R/W ;bitpos:[13] ;default: 1'b0 ; */ 1865 /*description: internal SRAM 3 force power down*/ 1866 #define RTC_CNTL_INTER_RAM3_FORCE_PD (BIT(13)) 1867 #define RTC_CNTL_INTER_RAM3_FORCE_PD_M (BIT(13)) 1868 #define RTC_CNTL_INTER_RAM3_FORCE_PD_V 0x1 1869 #define RTC_CNTL_INTER_RAM3_FORCE_PD_S 13 1870 /* RTC_CNTL_INTER_RAM2_FORCE_PU : R/W ;bitpos:[12] ;default: 1'd1 ; */ 1871 /*description: internal SRAM 2 force power up*/ 1872 #define RTC_CNTL_INTER_RAM2_FORCE_PU (BIT(12)) 1873 #define RTC_CNTL_INTER_RAM2_FORCE_PU_M (BIT(12)) 1874 #define RTC_CNTL_INTER_RAM2_FORCE_PU_V 0x1 1875 #define RTC_CNTL_INTER_RAM2_FORCE_PU_S 12 1876 /* RTC_CNTL_INTER_RAM2_FORCE_PD : R/W ;bitpos:[11] ;default: 1'b0 ; */ 1877 /*description: internal SRAM 2 force power down*/ 1878 #define RTC_CNTL_INTER_RAM2_FORCE_PD (BIT(11)) 1879 #define RTC_CNTL_INTER_RAM2_FORCE_PD_M (BIT(11)) 1880 #define RTC_CNTL_INTER_RAM2_FORCE_PD_V 0x1 1881 #define RTC_CNTL_INTER_RAM2_FORCE_PD_S 11 1882 /* RTC_CNTL_INTER_RAM1_FORCE_PU : R/W ;bitpos:[10] ;default: 1'd1 ; */ 1883 /*description: internal SRAM 1 force power up*/ 1884 #define RTC_CNTL_INTER_RAM1_FORCE_PU (BIT(10)) 1885 #define RTC_CNTL_INTER_RAM1_FORCE_PU_M (BIT(10)) 1886 #define RTC_CNTL_INTER_RAM1_FORCE_PU_V 0x1 1887 #define RTC_CNTL_INTER_RAM1_FORCE_PU_S 10 1888 /* RTC_CNTL_INTER_RAM1_FORCE_PD : R/W ;bitpos:[9] ;default: 1'b0 ; */ 1889 /*description: internal SRAM 1 force power down*/ 1890 #define RTC_CNTL_INTER_RAM1_FORCE_PD (BIT(9)) 1891 #define RTC_CNTL_INTER_RAM1_FORCE_PD_M (BIT(9)) 1892 #define RTC_CNTL_INTER_RAM1_FORCE_PD_V 0x1 1893 #define RTC_CNTL_INTER_RAM1_FORCE_PD_S 9 1894 /* RTC_CNTL_INTER_RAM0_FORCE_PU : R/W ;bitpos:[8] ;default: 1'd1 ; */ 1895 /*description: internal SRAM 0 force power up*/ 1896 #define RTC_CNTL_INTER_RAM0_FORCE_PU (BIT(8)) 1897 #define RTC_CNTL_INTER_RAM0_FORCE_PU_M (BIT(8)) 1898 #define RTC_CNTL_INTER_RAM0_FORCE_PU_V 0x1 1899 #define RTC_CNTL_INTER_RAM0_FORCE_PU_S 8 1900 /* RTC_CNTL_INTER_RAM0_FORCE_PD : R/W ;bitpos:[7] ;default: 1'b0 ; */ 1901 /*description: internal SRAM 0 force power down*/ 1902 #define RTC_CNTL_INTER_RAM0_FORCE_PD (BIT(7)) 1903 #define RTC_CNTL_INTER_RAM0_FORCE_PD_M (BIT(7)) 1904 #define RTC_CNTL_INTER_RAM0_FORCE_PD_V 0x1 1905 #define RTC_CNTL_INTER_RAM0_FORCE_PD_S 7 1906 /* RTC_CNTL_ROM0_FORCE_PU : R/W ;bitpos:[6] ;default: 1'd1 ; */ 1907 /*description: ROM force power up*/ 1908 #define RTC_CNTL_ROM0_FORCE_PU (BIT(6)) 1909 #define RTC_CNTL_ROM0_FORCE_PU_M (BIT(6)) 1910 #define RTC_CNTL_ROM0_FORCE_PU_V 0x1 1911 #define RTC_CNTL_ROM0_FORCE_PU_S 6 1912 /* RTC_CNTL_ROM0_FORCE_PD : R/W ;bitpos:[5] ;default: 1'b0 ; */ 1913 /*description: ROM force power down*/ 1914 #define RTC_CNTL_ROM0_FORCE_PD (BIT(5)) 1915 #define RTC_CNTL_ROM0_FORCE_PD_M (BIT(5)) 1916 #define RTC_CNTL_ROM0_FORCE_PD_V 0x1 1917 #define RTC_CNTL_ROM0_FORCE_PD_S 5 1918 /* RTC_CNTL_LSLP_MEM_FORCE_PU : R/W ;bitpos:[4] ;default: 1'b1 ; */ 1919 /*description: memories in digital core force no PD in sleep*/ 1920 #define RTC_CNTL_LSLP_MEM_FORCE_PU (BIT(4)) 1921 #define RTC_CNTL_LSLP_MEM_FORCE_PU_M (BIT(4)) 1922 #define RTC_CNTL_LSLP_MEM_FORCE_PU_V 0x1 1923 #define RTC_CNTL_LSLP_MEM_FORCE_PU_S 4 1924 /* RTC_CNTL_LSLP_MEM_FORCE_PD : R/W ;bitpos:[3] ;default: 1'b0 ; */ 1925 /*description: memories in digital core force PD in sleep*/ 1926 #define RTC_CNTL_LSLP_MEM_FORCE_PD (BIT(3)) 1927 #define RTC_CNTL_LSLP_MEM_FORCE_PD_M (BIT(3)) 1928 #define RTC_CNTL_LSLP_MEM_FORCE_PD_V 0x1 1929 #define RTC_CNTL_LSLP_MEM_FORCE_PD_S 3 1930 1931 #define RTC_CNTL_DIG_ISO_REG (DR_REG_RTCCNTL_BASE + 0x0090) 1932 /* RTC_CNTL_DG_WRAP_FORCE_NOISO : R/W ;bitpos:[31] ;default: 1'd1 ; */ 1933 /*description: */ 1934 #define RTC_CNTL_DG_WRAP_FORCE_NOISO (BIT(31)) 1935 #define RTC_CNTL_DG_WRAP_FORCE_NOISO_M (BIT(31)) 1936 #define RTC_CNTL_DG_WRAP_FORCE_NOISO_V 0x1 1937 #define RTC_CNTL_DG_WRAP_FORCE_NOISO_S 31 1938 /* RTC_CNTL_DG_WRAP_FORCE_ISO : R/W ;bitpos:[30] ;default: 1'd0 ; */ 1939 /*description: digital core force ISO*/ 1940 #define RTC_CNTL_DG_WRAP_FORCE_ISO (BIT(30)) 1941 #define RTC_CNTL_DG_WRAP_FORCE_ISO_M (BIT(30)) 1942 #define RTC_CNTL_DG_WRAP_FORCE_ISO_V 0x1 1943 #define RTC_CNTL_DG_WRAP_FORCE_ISO_S 30 1944 /* RTC_CNTL_WIFI_FORCE_NOISO : R/W ;bitpos:[29] ;default: 1'd1 ; */ 1945 /*description: wifi force no ISO*/ 1946 #define RTC_CNTL_WIFI_FORCE_NOISO (BIT(29)) 1947 #define RTC_CNTL_WIFI_FORCE_NOISO_M (BIT(29)) 1948 #define RTC_CNTL_WIFI_FORCE_NOISO_V 0x1 1949 #define RTC_CNTL_WIFI_FORCE_NOISO_S 29 1950 /* RTC_CNTL_WIFI_FORCE_ISO : R/W ;bitpos:[28] ;default: 1'd0 ; */ 1951 /*description: wifi force ISO*/ 1952 #define RTC_CNTL_WIFI_FORCE_ISO (BIT(28)) 1953 #define RTC_CNTL_WIFI_FORCE_ISO_M (BIT(28)) 1954 #define RTC_CNTL_WIFI_FORCE_ISO_V 0x1 1955 #define RTC_CNTL_WIFI_FORCE_ISO_S 28 1956 /* RTC_CNTL_INTER_RAM4_FORCE_NOISO : R/W ;bitpos:[27] ;default: 1'd1 ; */ 1957 /*description: internal SRAM 4 force no ISO*/ 1958 #define RTC_CNTL_INTER_RAM4_FORCE_NOISO (BIT(27)) 1959 #define RTC_CNTL_INTER_RAM4_FORCE_NOISO_M (BIT(27)) 1960 #define RTC_CNTL_INTER_RAM4_FORCE_NOISO_V 0x1 1961 #define RTC_CNTL_INTER_RAM4_FORCE_NOISO_S 27 1962 /* RTC_CNTL_INTER_RAM4_FORCE_ISO : R/W ;bitpos:[26] ;default: 1'd0 ; */ 1963 /*description: internal SRAM 4 force ISO*/ 1964 #define RTC_CNTL_INTER_RAM4_FORCE_ISO (BIT(26)) 1965 #define RTC_CNTL_INTER_RAM4_FORCE_ISO_M (BIT(26)) 1966 #define RTC_CNTL_INTER_RAM4_FORCE_ISO_V 0x1 1967 #define RTC_CNTL_INTER_RAM4_FORCE_ISO_S 26 1968 /* RTC_CNTL_INTER_RAM3_FORCE_NOISO : R/W ;bitpos:[25] ;default: 1'd1 ; */ 1969 /*description: internal SRAM 3 force no ISO*/ 1970 #define RTC_CNTL_INTER_RAM3_FORCE_NOISO (BIT(25)) 1971 #define RTC_CNTL_INTER_RAM3_FORCE_NOISO_M (BIT(25)) 1972 #define RTC_CNTL_INTER_RAM3_FORCE_NOISO_V 0x1 1973 #define RTC_CNTL_INTER_RAM3_FORCE_NOISO_S 25 1974 /* RTC_CNTL_INTER_RAM3_FORCE_ISO : R/W ;bitpos:[24] ;default: 1'd0 ; */ 1975 /*description: internal SRAM 3 force ISO*/ 1976 #define RTC_CNTL_INTER_RAM3_FORCE_ISO (BIT(24)) 1977 #define RTC_CNTL_INTER_RAM3_FORCE_ISO_M (BIT(24)) 1978 #define RTC_CNTL_INTER_RAM3_FORCE_ISO_V 0x1 1979 #define RTC_CNTL_INTER_RAM3_FORCE_ISO_S 24 1980 /* RTC_CNTL_INTER_RAM2_FORCE_NOISO : R/W ;bitpos:[23] ;default: 1'd1 ; */ 1981 /*description: internal SRAM 2 force no ISO*/ 1982 #define RTC_CNTL_INTER_RAM2_FORCE_NOISO (BIT(23)) 1983 #define RTC_CNTL_INTER_RAM2_FORCE_NOISO_M (BIT(23)) 1984 #define RTC_CNTL_INTER_RAM2_FORCE_NOISO_V 0x1 1985 #define RTC_CNTL_INTER_RAM2_FORCE_NOISO_S 23 1986 /* RTC_CNTL_INTER_RAM2_FORCE_ISO : R/W ;bitpos:[22] ;default: 1'd0 ; */ 1987 /*description: internal SRAM 2 force ISO*/ 1988 #define RTC_CNTL_INTER_RAM2_FORCE_ISO (BIT(22)) 1989 #define RTC_CNTL_INTER_RAM2_FORCE_ISO_M (BIT(22)) 1990 #define RTC_CNTL_INTER_RAM2_FORCE_ISO_V 0x1 1991 #define RTC_CNTL_INTER_RAM2_FORCE_ISO_S 22 1992 /* RTC_CNTL_INTER_RAM1_FORCE_NOISO : R/W ;bitpos:[21] ;default: 1'd1 ; */ 1993 /*description: internal SRAM 1 force no ISO*/ 1994 #define RTC_CNTL_INTER_RAM1_FORCE_NOISO (BIT(21)) 1995 #define RTC_CNTL_INTER_RAM1_FORCE_NOISO_M (BIT(21)) 1996 #define RTC_CNTL_INTER_RAM1_FORCE_NOISO_V 0x1 1997 #define RTC_CNTL_INTER_RAM1_FORCE_NOISO_S 21 1998 /* RTC_CNTL_INTER_RAM1_FORCE_ISO : R/W ;bitpos:[20] ;default: 1'd0 ; */ 1999 /*description: internal SRAM 1 force ISO*/ 2000 #define RTC_CNTL_INTER_RAM1_FORCE_ISO (BIT(20)) 2001 #define RTC_CNTL_INTER_RAM1_FORCE_ISO_M (BIT(20)) 2002 #define RTC_CNTL_INTER_RAM1_FORCE_ISO_V 0x1 2003 #define RTC_CNTL_INTER_RAM1_FORCE_ISO_S 20 2004 /* RTC_CNTL_INTER_RAM0_FORCE_NOISO : R/W ;bitpos:[19] ;default: 1'd1 ; */ 2005 /*description: internal SRAM 0 force no ISO*/ 2006 #define RTC_CNTL_INTER_RAM0_FORCE_NOISO (BIT(19)) 2007 #define RTC_CNTL_INTER_RAM0_FORCE_NOISO_M (BIT(19)) 2008 #define RTC_CNTL_INTER_RAM0_FORCE_NOISO_V 0x1 2009 #define RTC_CNTL_INTER_RAM0_FORCE_NOISO_S 19 2010 /* RTC_CNTL_INTER_RAM0_FORCE_ISO : R/W ;bitpos:[18] ;default: 1'd0 ; */ 2011 /*description: internal SRAM 0 force ISO*/ 2012 #define RTC_CNTL_INTER_RAM0_FORCE_ISO (BIT(18)) 2013 #define RTC_CNTL_INTER_RAM0_FORCE_ISO_M (BIT(18)) 2014 #define RTC_CNTL_INTER_RAM0_FORCE_ISO_V 0x1 2015 #define RTC_CNTL_INTER_RAM0_FORCE_ISO_S 18 2016 /* RTC_CNTL_ROM0_FORCE_NOISO : R/W ;bitpos:[17] ;default: 1'd1 ; */ 2017 /*description: ROM force no ISO*/ 2018 #define RTC_CNTL_ROM0_FORCE_NOISO (BIT(17)) 2019 #define RTC_CNTL_ROM0_FORCE_NOISO_M (BIT(17)) 2020 #define RTC_CNTL_ROM0_FORCE_NOISO_V 0x1 2021 #define RTC_CNTL_ROM0_FORCE_NOISO_S 17 2022 /* RTC_CNTL_ROM0_FORCE_ISO : R/W ;bitpos:[16] ;default: 1'd0 ; */ 2023 /*description: ROM force ISO*/ 2024 #define RTC_CNTL_ROM0_FORCE_ISO (BIT(16)) 2025 #define RTC_CNTL_ROM0_FORCE_ISO_M (BIT(16)) 2026 #define RTC_CNTL_ROM0_FORCE_ISO_V 0x1 2027 #define RTC_CNTL_ROM0_FORCE_ISO_S 16 2028 /* RTC_CNTL_DG_PAD_FORCE_HOLD : R/W ;bitpos:[15] ;default: 1'd0 ; */ 2029 /*description: digital pad force hold*/ 2030 #define RTC_CNTL_DG_PAD_FORCE_HOLD (BIT(15)) 2031 #define RTC_CNTL_DG_PAD_FORCE_HOLD_M (BIT(15)) 2032 #define RTC_CNTL_DG_PAD_FORCE_HOLD_V 0x1 2033 #define RTC_CNTL_DG_PAD_FORCE_HOLD_S 15 2034 /* RTC_CNTL_DG_PAD_FORCE_UNHOLD : R/W ;bitpos:[14] ;default: 1'd1 ; */ 2035 /*description: digital pad force un-hold*/ 2036 #define RTC_CNTL_DG_PAD_FORCE_UNHOLD (BIT(14)) 2037 #define RTC_CNTL_DG_PAD_FORCE_UNHOLD_M (BIT(14)) 2038 #define RTC_CNTL_DG_PAD_FORCE_UNHOLD_V 0x1 2039 #define RTC_CNTL_DG_PAD_FORCE_UNHOLD_S 14 2040 /* RTC_CNTL_DG_PAD_FORCE_ISO : R/W ;bitpos:[13] ;default: 1'd0 ; */ 2041 /*description: digital pad force ISO*/ 2042 #define RTC_CNTL_DG_PAD_FORCE_ISO (BIT(13)) 2043 #define RTC_CNTL_DG_PAD_FORCE_ISO_M (BIT(13)) 2044 #define RTC_CNTL_DG_PAD_FORCE_ISO_V 0x1 2045 #define RTC_CNTL_DG_PAD_FORCE_ISO_S 13 2046 /* RTC_CNTL_DG_PAD_FORCE_NOISO : R/W ;bitpos:[12] ;default: 1'd1 ; */ 2047 /*description: digital pad force no ISO*/ 2048 #define RTC_CNTL_DG_PAD_FORCE_NOISO (BIT(12)) 2049 #define RTC_CNTL_DG_PAD_FORCE_NOISO_M (BIT(12)) 2050 #define RTC_CNTL_DG_PAD_FORCE_NOISO_V 0x1 2051 #define RTC_CNTL_DG_PAD_FORCE_NOISO_S 12 2052 /* RTC_CNTL_DG_PAD_AUTOHOLD_EN : R/W ;bitpos:[11] ;default: 1'd0 ; */ 2053 /*description: digital pad enable auto-hold*/ 2054 #define RTC_CNTL_DG_PAD_AUTOHOLD_EN (BIT(11)) 2055 #define RTC_CNTL_DG_PAD_AUTOHOLD_EN_M (BIT(11)) 2056 #define RTC_CNTL_DG_PAD_AUTOHOLD_EN_V 0x1 2057 #define RTC_CNTL_DG_PAD_AUTOHOLD_EN_S 11 2058 /* RTC_CNTL_CLR_DG_PAD_AUTOHOLD : WO ;bitpos:[10] ;default: 1'd0 ; */ 2059 /*description: wtite only register to clear digital pad auto-hold*/ 2060 #define RTC_CNTL_CLR_DG_PAD_AUTOHOLD (BIT(10)) 2061 #define RTC_CNTL_CLR_DG_PAD_AUTOHOLD_M (BIT(10)) 2062 #define RTC_CNTL_CLR_DG_PAD_AUTOHOLD_V 0x1 2063 #define RTC_CNTL_CLR_DG_PAD_AUTOHOLD_S 10 2064 /* RTC_CNTL_DG_PAD_AUTOHOLD : RO ;bitpos:[9] ;default: 1'd0 ; */ 2065 /*description: read only register to indicate digital pad auto-hold status*/ 2066 #define RTC_CNTL_DG_PAD_AUTOHOLD (BIT(9)) 2067 #define RTC_CNTL_DG_PAD_AUTOHOLD_M (BIT(9)) 2068 #define RTC_CNTL_DG_PAD_AUTOHOLD_V 0x1 2069 #define RTC_CNTL_DG_PAD_AUTOHOLD_S 9 2070 /* RTC_CNTL_DIG_ISO_FORCE_ON : R/W ;bitpos:[8] ;default: 1'd0 ; */ 2071 /*description: */ 2072 #define RTC_CNTL_DIG_ISO_FORCE_ON (BIT(8)) 2073 #define RTC_CNTL_DIG_ISO_FORCE_ON_M (BIT(8)) 2074 #define RTC_CNTL_DIG_ISO_FORCE_ON_V 0x1 2075 #define RTC_CNTL_DIG_ISO_FORCE_ON_S 8 2076 /* RTC_CNTL_DIG_ISO_FORCE_OFF : R/W ;bitpos:[7] ;default: 1'd0 ; */ 2077 /*description: */ 2078 #define RTC_CNTL_DIG_ISO_FORCE_OFF (BIT(7)) 2079 #define RTC_CNTL_DIG_ISO_FORCE_OFF_M (BIT(7)) 2080 #define RTC_CNTL_DIG_ISO_FORCE_OFF_V 0x1 2081 #define RTC_CNTL_DIG_ISO_FORCE_OFF_S 7 2082 2083 #define RTC_CNTL_WDTCONFIG0_REG (DR_REG_RTCCNTL_BASE + 0x0094) 2084 /* RTC_CNTL_WDT_EN : R/W ;bitpos:[31] ;default: 1'h0 ; */ 2085 /*description: */ 2086 #define RTC_CNTL_WDT_EN (BIT(31)) 2087 #define RTC_CNTL_WDT_EN_M (BIT(31)) 2088 #define RTC_CNTL_WDT_EN_V 0x1 2089 #define RTC_CNTL_WDT_EN_S 31 2090 /* RTC_CNTL_WDT_STG0 : R/W ;bitpos:[30:28] ;default: 3'h0 ; */ 2091 /*description: 1: interrupt stage en 2: CPU reset stage en 3: system reset 2092 stage en 4: RTC reset stage en*/ 2093 #define RTC_CNTL_WDT_STG0 0x00000007 2094 #define RTC_CNTL_WDT_STG0_M ((RTC_CNTL_WDT_STG0_V)<<(RTC_CNTL_WDT_STG0_S)) 2095 #define RTC_CNTL_WDT_STG0_V 0x7 2096 #define RTC_CNTL_WDT_STG0_S 28 2097 /* RTC_CNTL_WDT_STG1 : R/W ;bitpos:[27:25] ;default: 3'h0 ; */ 2098 /*description: 1: interrupt stage en 2: CPU reset stage en 3: system reset 2099 stage en 4: RTC reset stage en*/ 2100 #define RTC_CNTL_WDT_STG1 0x00000007 2101 #define RTC_CNTL_WDT_STG1_M ((RTC_CNTL_WDT_STG1_V)<<(RTC_CNTL_WDT_STG1_S)) 2102 #define RTC_CNTL_WDT_STG1_V 0x7 2103 #define RTC_CNTL_WDT_STG1_S 25 2104 /* RTC_CNTL_WDT_STG2 : R/W ;bitpos:[24:22] ;default: 3'h0 ; */ 2105 /*description: 1: interrupt stage en 2: CPU reset stage en 3: system reset 2106 stage en 4: RTC reset stage en*/ 2107 #define RTC_CNTL_WDT_STG2 0x00000007 2108 #define RTC_CNTL_WDT_STG2_M ((RTC_CNTL_WDT_STG2_V)<<(RTC_CNTL_WDT_STG2_S)) 2109 #define RTC_CNTL_WDT_STG2_V 0x7 2110 #define RTC_CNTL_WDT_STG2_S 22 2111 /* RTC_CNTL_WDT_STG3 : R/W ;bitpos:[21:19] ;default: 3'h0 ; */ 2112 /*description: 1: interrupt stage en 2: CPU reset stage en 3: system reset 2113 stage en 4: RTC reset stage en*/ 2114 #define RTC_CNTL_WDT_STG3 0x00000007 2115 #define RTC_CNTL_WDT_STG3_M ((RTC_CNTL_WDT_STG3_V)<<(RTC_CNTL_WDT_STG3_S)) 2116 #define RTC_CNTL_WDT_STG3_V 0x7 2117 #define RTC_CNTL_WDT_STG3_S 19 2118 /* RTC_CNTL_WDT_STGX : */ 2119 /*description: stage action selection values */ 2120 #define RTC_WDT_STG_SEL_OFF 0 2121 #define RTC_WDT_STG_SEL_INT 1 2122 #define RTC_WDT_STG_SEL_RESET_CPU 2 2123 #define RTC_WDT_STG_SEL_RESET_SYSTEM 3 2124 #define RTC_WDT_STG_SEL_RESET_RTC 4 2125 2126 /* RTC_CNTL_WDT_CPU_RESET_LENGTH : R/W ;bitpos:[18:16] ;default: 3'h1 ; */ 2127 /*description: CPU reset counter length*/ 2128 #define RTC_CNTL_WDT_CPU_RESET_LENGTH 0x00000007 2129 #define RTC_CNTL_WDT_CPU_RESET_LENGTH_M ((RTC_CNTL_WDT_CPU_RESET_LENGTH_V)<<(RTC_CNTL_WDT_CPU_RESET_LENGTH_S)) 2130 #define RTC_CNTL_WDT_CPU_RESET_LENGTH_V 0x7 2131 #define RTC_CNTL_WDT_CPU_RESET_LENGTH_S 16 2132 /* RTC_CNTL_WDT_SYS_RESET_LENGTH : R/W ;bitpos:[15:13] ;default: 3'h1 ; */ 2133 /*description: system reset counter length*/ 2134 #define RTC_CNTL_WDT_SYS_RESET_LENGTH 0x00000007 2135 #define RTC_CNTL_WDT_SYS_RESET_LENGTH_M ((RTC_CNTL_WDT_SYS_RESET_LENGTH_V)<<(RTC_CNTL_WDT_SYS_RESET_LENGTH_S)) 2136 #define RTC_CNTL_WDT_SYS_RESET_LENGTH_V 0x7 2137 #define RTC_CNTL_WDT_SYS_RESET_LENGTH_S 13 2138 /* RTC_CNTL_WDT_FLASHBOOT_MOD_EN : R/W ;bitpos:[12] ;default: 1'h1 ; */ 2139 /*description: enable WDT in flash boot*/ 2140 #define RTC_CNTL_WDT_FLASHBOOT_MOD_EN (BIT(12)) 2141 #define RTC_CNTL_WDT_FLASHBOOT_MOD_EN_M (BIT(12)) 2142 #define RTC_CNTL_WDT_FLASHBOOT_MOD_EN_V 0x1 2143 #define RTC_CNTL_WDT_FLASHBOOT_MOD_EN_S 12 2144 /* RTC_CNTL_WDT_PROCPU_RESET_EN : R/W ;bitpos:[11] ;default: 1'd0 ; */ 2145 /*description: enable WDT reset PRO CPU*/ 2146 #define RTC_CNTL_WDT_PROCPU_RESET_EN (BIT(11)) 2147 #define RTC_CNTL_WDT_PROCPU_RESET_EN_M (BIT(11)) 2148 #define RTC_CNTL_WDT_PROCPU_RESET_EN_V 0x1 2149 #define RTC_CNTL_WDT_PROCPU_RESET_EN_S 11 2150 /* RTC_CNTL_WDT_APPCPU_RESET_EN : R/W ;bitpos:[10] ;default: 1'd0 ; */ 2151 /*description: enable WDT reset APP CPU*/ 2152 #define RTC_CNTL_WDT_APPCPU_RESET_EN (BIT(10)) 2153 #define RTC_CNTL_WDT_APPCPU_RESET_EN_M (BIT(10)) 2154 #define RTC_CNTL_WDT_APPCPU_RESET_EN_V 0x1 2155 #define RTC_CNTL_WDT_APPCPU_RESET_EN_S 10 2156 /* RTC_CNTL_WDT_PAUSE_IN_SLP : R/W ;bitpos:[9] ;default: 1'd1 ; */ 2157 /*description: pause WDT in sleep*/ 2158 #define RTC_CNTL_WDT_PAUSE_IN_SLP (BIT(9)) 2159 #define RTC_CNTL_WDT_PAUSE_IN_SLP_M (BIT(9)) 2160 #define RTC_CNTL_WDT_PAUSE_IN_SLP_V 0x1 2161 #define RTC_CNTL_WDT_PAUSE_IN_SLP_S 9 2162 /* RTC_CNTL_WDT_CHIP_RESET_EN : R/W ;bitpos:[8] ;default: 1'b0 ; */ 2163 /*description: wdt reset whole chip enable*/ 2164 #define RTC_CNTL_WDT_CHIP_RESET_EN (BIT(8)) 2165 #define RTC_CNTL_WDT_CHIP_RESET_EN_M (BIT(8)) 2166 #define RTC_CNTL_WDT_CHIP_RESET_EN_V 0x1 2167 #define RTC_CNTL_WDT_CHIP_RESET_EN_S 8 2168 /* RTC_CNTL_WDT_CHIP_RESET_WIDTH : R/W ;bitpos:[7:0] ;default: 8'd20 ; */ 2169 /*description: chip reset siginal pulse width*/ 2170 #define RTC_CNTL_WDT_CHIP_RESET_WIDTH 0x000000FF 2171 #define RTC_CNTL_WDT_CHIP_RESET_WIDTH_M ((RTC_CNTL_WDT_CHIP_RESET_WIDTH_V)<<(RTC_CNTL_WDT_CHIP_RESET_WIDTH_S)) 2172 #define RTC_CNTL_WDT_CHIP_RESET_WIDTH_V 0xFF 2173 #define RTC_CNTL_WDT_CHIP_RESET_WIDTH_S 0 2174 2175 #define RTC_CNTL_WDTCONFIG1_REG (DR_REG_RTCCNTL_BASE + 0x0098) 2176 /* RTC_CNTL_WDT_STG0_HOLD : R/W ;bitpos:[31:0] ;default: 32'd200000 ; */ 2177 /*description: */ 2178 #define RTC_CNTL_WDT_STG0_HOLD 0xFFFFFFFF 2179 #define RTC_CNTL_WDT_STG0_HOLD_M ((RTC_CNTL_WDT_STG0_HOLD_V)<<(RTC_CNTL_WDT_STG0_HOLD_S)) 2180 #define RTC_CNTL_WDT_STG0_HOLD_V 0xFFFFFFFF 2181 #define RTC_CNTL_WDT_STG0_HOLD_S 0 2182 2183 #define RTC_CNTL_WDTCONFIG2_REG (DR_REG_RTCCNTL_BASE + 0x009C) 2184 /* RTC_CNTL_WDT_STG1_HOLD : R/W ;bitpos:[31:0] ;default: 32'd80000 ; */ 2185 /*description: */ 2186 #define RTC_CNTL_WDT_STG1_HOLD 0xFFFFFFFF 2187 #define RTC_CNTL_WDT_STG1_HOLD_M ((RTC_CNTL_WDT_STG1_HOLD_V)<<(RTC_CNTL_WDT_STG1_HOLD_S)) 2188 #define RTC_CNTL_WDT_STG1_HOLD_V 0xFFFFFFFF 2189 #define RTC_CNTL_WDT_STG1_HOLD_S 0 2190 2191 #define RTC_CNTL_WDTCONFIG3_REG (DR_REG_RTCCNTL_BASE + 0x00A0) 2192 /* RTC_CNTL_WDT_STG2_HOLD : R/W ;bitpos:[31:0] ;default: 32'hfff ; */ 2193 /*description: */ 2194 #define RTC_CNTL_WDT_STG2_HOLD 0xFFFFFFFF 2195 #define RTC_CNTL_WDT_STG2_HOLD_M ((RTC_CNTL_WDT_STG2_HOLD_V)<<(RTC_CNTL_WDT_STG2_HOLD_S)) 2196 #define RTC_CNTL_WDT_STG2_HOLD_V 0xFFFFFFFF 2197 #define RTC_CNTL_WDT_STG2_HOLD_S 0 2198 2199 #define RTC_CNTL_WDTCONFIG4_REG (DR_REG_RTCCNTL_BASE + 0x00A4) 2200 /* RTC_CNTL_WDT_STG3_HOLD : R/W ;bitpos:[31:0] ;default: 32'hfff ; */ 2201 /*description: */ 2202 #define RTC_CNTL_WDT_STG3_HOLD 0xFFFFFFFF 2203 #define RTC_CNTL_WDT_STG3_HOLD_M ((RTC_CNTL_WDT_STG3_HOLD_V)<<(RTC_CNTL_WDT_STG3_HOLD_S)) 2204 #define RTC_CNTL_WDT_STG3_HOLD_V 0xFFFFFFFF 2205 #define RTC_CNTL_WDT_STG3_HOLD_S 0 2206 2207 #define RTC_CNTL_WDTFEED_REG (DR_REG_RTCCNTL_BASE + 0x00A8) 2208 /* RTC_CNTL_WDT_FEED : WO ;bitpos:[31] ;default: 1'd0 ; */ 2209 /*description: */ 2210 #define RTC_CNTL_WDT_FEED (BIT(31)) 2211 #define RTC_CNTL_WDT_FEED_M (BIT(31)) 2212 #define RTC_CNTL_WDT_FEED_V 0x1 2213 #define RTC_CNTL_WDT_FEED_S 31 2214 2215 #define RTC_CNTL_WDTWPROTECT_REG (DR_REG_RTCCNTL_BASE + 0x00AC) 2216 /* RTC_CNTL_WDT_WKEY : R/W ;bitpos:[31:0] ;default: 32'h50d83aa1 ; */ 2217 /*description: */ 2218 #define RTC_CNTL_WDT_WKEY 0xFFFFFFFF 2219 #define RTC_CNTL_WDT_WKEY_M ((RTC_CNTL_WDT_WKEY_V)<<(RTC_CNTL_WDT_WKEY_S)) 2220 #define RTC_CNTL_WDT_WKEY_V 0xFFFFFFFF 2221 #define RTC_CNTL_WDT_WKEY_S 0 2222 2223 #define RTC_CNTL_SWD_CONF_REG (DR_REG_RTCCNTL_BASE + 0x00B0) 2224 /* RTC_CNTL_SWD_AUTO_FEED_EN : R/W ;bitpos:[31] ;default: 1'b0 ; */ 2225 /*description: automatically feed swd when int comes*/ 2226 #define RTC_CNTL_SWD_AUTO_FEED_EN (BIT(31)) 2227 #define RTC_CNTL_SWD_AUTO_FEED_EN_M (BIT(31)) 2228 #define RTC_CNTL_SWD_AUTO_FEED_EN_V 0x1 2229 #define RTC_CNTL_SWD_AUTO_FEED_EN_S 31 2230 /* RTC_CNTL_SWD_DISABLE : R/W ;bitpos:[30] ;default: 1'b0 ; */ 2231 /*description: disabel SWD*/ 2232 #define RTC_CNTL_SWD_DISABLE (BIT(30)) 2233 #define RTC_CNTL_SWD_DISABLE_M (BIT(30)) 2234 #define RTC_CNTL_SWD_DISABLE_V 0x1 2235 #define RTC_CNTL_SWD_DISABLE_S 30 2236 /* RTC_CNTL_SWD_FEED : WO ;bitpos:[29] ;default: 1'b0 ; */ 2237 /*description: Sw feed swd*/ 2238 #define RTC_CNTL_SWD_FEED (BIT(29)) 2239 #define RTC_CNTL_SWD_FEED_M (BIT(29)) 2240 #define RTC_CNTL_SWD_FEED_V 0x1 2241 #define RTC_CNTL_SWD_FEED_S 29 2242 /* RTC_CNTL_SWD_RST_FLAG_CLR : WO ;bitpos:[28] ;default: 1'b0 ; */ 2243 /*description: reset swd reset flag*/ 2244 #define RTC_CNTL_SWD_RST_FLAG_CLR (BIT(28)) 2245 #define RTC_CNTL_SWD_RST_FLAG_CLR_M (BIT(28)) 2246 #define RTC_CNTL_SWD_RST_FLAG_CLR_V 0x1 2247 #define RTC_CNTL_SWD_RST_FLAG_CLR_S 28 2248 /* RTC_CNTL_SWD_SIGNAL_WIDTH : R/W ;bitpos:[27:18] ;default: 10'd300 ; */ 2249 /*description: adjust signal width send to swd*/ 2250 #define RTC_CNTL_SWD_SIGNAL_WIDTH 0x000003FF 2251 #define RTC_CNTL_SWD_SIGNAL_WIDTH_M ((RTC_CNTL_SWD_SIGNAL_WIDTH_V)<<(RTC_CNTL_SWD_SIGNAL_WIDTH_S)) 2252 #define RTC_CNTL_SWD_SIGNAL_WIDTH_V 0x3FF 2253 #define RTC_CNTL_SWD_SIGNAL_WIDTH_S 18 2254 /* RTC_CNTL_SWD_FEED_INT : RO ;bitpos:[1] ;default: 1'b0 ; */ 2255 /*description: swd interrupt for feeding*/ 2256 #define RTC_CNTL_SWD_FEED_INT (BIT(1)) 2257 #define RTC_CNTL_SWD_FEED_INT_M (BIT(1)) 2258 #define RTC_CNTL_SWD_FEED_INT_V 0x1 2259 #define RTC_CNTL_SWD_FEED_INT_S 1 2260 /* RTC_CNTL_SWD_RESET_FLAG : RO ;bitpos:[0] ;default: 1'b0 ; */ 2261 /*description: swd reset flag*/ 2262 #define RTC_CNTL_SWD_RESET_FLAG (BIT(0)) 2263 #define RTC_CNTL_SWD_RESET_FLAG_M (BIT(0)) 2264 #define RTC_CNTL_SWD_RESET_FLAG_V 0x1 2265 #define RTC_CNTL_SWD_RESET_FLAG_S 0 2266 2267 #define RTC_CNTL_SWD_WPROTECT_REG (DR_REG_RTCCNTL_BASE + 0x00B4) 2268 /* RTC_CNTL_SWD_WKEY : R/W ;bitpos:[31:0] ;default: 32'h8f1d312a ; */ 2269 /*description: swd write protect*/ 2270 #define RTC_CNTL_SWD_WKEY 0xFFFFFFFF 2271 #define RTC_CNTL_SWD_WKEY_M ((RTC_CNTL_SWD_WKEY_V)<<(RTC_CNTL_SWD_WKEY_S)) 2272 #define RTC_CNTL_SWD_WKEY_V 0xFFFFFFFF 2273 #define RTC_CNTL_SWD_WKEY_S 0 2274 2275 #define RTC_CNTL_SW_CPU_STALL_REG (DR_REG_RTCCNTL_BASE + 0x00B8) 2276 /* RTC_CNTL_SW_STALL_PROCPU_C1 : R/W ;bitpos:[31:26] ;default: 6'b0 ; */ 2277 /*description: */ 2278 #define RTC_CNTL_SW_STALL_PROCPU_C1 0x0000003F 2279 #define RTC_CNTL_SW_STALL_PROCPU_C1_M ((RTC_CNTL_SW_STALL_PROCPU_C1_V)<<(RTC_CNTL_SW_STALL_PROCPU_C1_S)) 2280 #define RTC_CNTL_SW_STALL_PROCPU_C1_V 0x3F 2281 #define RTC_CNTL_SW_STALL_PROCPU_C1_S 26 2282 /* RTC_CNTL_SW_STALL_APPCPU_C1 : R/W ;bitpos:[25:20] ;default: 6'b0 ; */ 2283 /*description: {reg_sw_stall_appcpu_c1[5:0] reg_sw_stall_appcpu_c0[1:0]} == 2284 0x86 will stall APP CPU*/ 2285 #define RTC_CNTL_SW_STALL_APPCPU_C1 0x0000003F 2286 #define RTC_CNTL_SW_STALL_APPCPU_C1_M ((RTC_CNTL_SW_STALL_APPCPU_C1_V)<<(RTC_CNTL_SW_STALL_APPCPU_C1_S)) 2287 #define RTC_CNTL_SW_STALL_APPCPU_C1_V 0x3F 2288 #define RTC_CNTL_SW_STALL_APPCPU_C1_S 20 2289 2290 #define RTC_CNTL_STORE4_REG (DR_REG_RTCCNTL_BASE + 0x00BC) 2291 /* RTC_CNTL_SCRATCH4 : R/W ;bitpos:[31:0] ;default: 0 ; */ 2292 /*description: */ 2293 #define RTC_CNTL_SCRATCH4 0xFFFFFFFF 2294 #define RTC_CNTL_SCRATCH4_M ((RTC_CNTL_SCRATCH4_V)<<(RTC_CNTL_SCRATCH4_S)) 2295 #define RTC_CNTL_SCRATCH4_V 0xFFFFFFFF 2296 #define RTC_CNTL_SCRATCH4_S 0 2297 2298 #define RTC_CNTL_STORE5_REG (DR_REG_RTCCNTL_BASE + 0x00C0) 2299 /* RTC_CNTL_SCRATCH5 : R/W ;bitpos:[31:0] ;default: 0 ; */ 2300 /*description: */ 2301 #define RTC_CNTL_SCRATCH5 0xFFFFFFFF 2302 #define RTC_CNTL_SCRATCH5_M ((RTC_CNTL_SCRATCH5_V)<<(RTC_CNTL_SCRATCH5_S)) 2303 #define RTC_CNTL_SCRATCH5_V 0xFFFFFFFF 2304 #define RTC_CNTL_SCRATCH5_S 0 2305 2306 #define RTC_CNTL_STORE6_REG (DR_REG_RTCCNTL_BASE + 0x00C4) 2307 /* RTC_CNTL_SCRATCH6 : R/W ;bitpos:[31:0] ;default: 0 ; */ 2308 /*description: */ 2309 #define RTC_CNTL_SCRATCH6 0xFFFFFFFF 2310 #define RTC_CNTL_SCRATCH6_M ((RTC_CNTL_SCRATCH6_V)<<(RTC_CNTL_SCRATCH6_S)) 2311 #define RTC_CNTL_SCRATCH6_V 0xFFFFFFFF 2312 #define RTC_CNTL_SCRATCH6_S 0 2313 2314 #define RTC_CNTL_STORE7_REG (DR_REG_RTCCNTL_BASE + 0x00C8) 2315 /* RTC_CNTL_SCRATCH7 : R/W ;bitpos:[31:0] ;default: 0 ; */ 2316 /*description: */ 2317 #define RTC_CNTL_SCRATCH7 0xFFFFFFFF 2318 #define RTC_CNTL_SCRATCH7_M ((RTC_CNTL_SCRATCH7_V)<<(RTC_CNTL_SCRATCH7_S)) 2319 #define RTC_CNTL_SCRATCH7_V 0xFFFFFFFF 2320 #define RTC_CNTL_SCRATCH7_S 0 2321 2322 #define RTC_CNTL_LOW_POWER_ST_REG (DR_REG_RTCCNTL_BASE + 0x00CC) 2323 /* RTC_CNTL_MAIN_STATE : RO ;bitpos:[31:28] ;default: 4'd0 ; */ 2324 /*description: rtc main state machine status*/ 2325 #define RTC_CNTL_MAIN_STATE 0x0000000F 2326 #define RTC_CNTL_MAIN_STATE_M ((RTC_CNTL_MAIN_STATE_V)<<(RTC_CNTL_MAIN_STATE_S)) 2327 #define RTC_CNTL_MAIN_STATE_V 0xF 2328 #define RTC_CNTL_MAIN_STATE_S 28 2329 /* RTC_CNTL_MAIN_STATE_IN_IDLE : RO ;bitpos:[27] ;default: 1'b0 ; */ 2330 /*description: rtc main state machine is in idle state*/ 2331 #define RTC_CNTL_MAIN_STATE_IN_IDLE (BIT(27)) 2332 #define RTC_CNTL_MAIN_STATE_IN_IDLE_M (BIT(27)) 2333 #define RTC_CNTL_MAIN_STATE_IN_IDLE_V 0x1 2334 #define RTC_CNTL_MAIN_STATE_IN_IDLE_S 27 2335 /* RTC_CNTL_MAIN_STATE_IN_SLP : RO ;bitpos:[26] ;default: 1'b0 ; */ 2336 /*description: rtc main state machine is in sleep state*/ 2337 #define RTC_CNTL_MAIN_STATE_IN_SLP (BIT(26)) 2338 #define RTC_CNTL_MAIN_STATE_IN_SLP_M (BIT(26)) 2339 #define RTC_CNTL_MAIN_STATE_IN_SLP_V 0x1 2340 #define RTC_CNTL_MAIN_STATE_IN_SLP_S 26 2341 /* RTC_CNTL_MAIN_STATE_IN_WAIT_XTL : RO ;bitpos:[25] ;default: 1'b0 ; */ 2342 /*description: rtc main state machine is in wait xtal state*/ 2343 #define RTC_CNTL_MAIN_STATE_IN_WAIT_XTL (BIT(25)) 2344 #define RTC_CNTL_MAIN_STATE_IN_WAIT_XTL_M (BIT(25)) 2345 #define RTC_CNTL_MAIN_STATE_IN_WAIT_XTL_V 0x1 2346 #define RTC_CNTL_MAIN_STATE_IN_WAIT_XTL_S 25 2347 /* RTC_CNTL_MAIN_STATE_IN_WAIT_PLL : RO ;bitpos:[24] ;default: 1'b0 ; */ 2348 /*description: rtc main state machine is in wait pll state*/ 2349 #define RTC_CNTL_MAIN_STATE_IN_WAIT_PLL (BIT(24)) 2350 #define RTC_CNTL_MAIN_STATE_IN_WAIT_PLL_M (BIT(24)) 2351 #define RTC_CNTL_MAIN_STATE_IN_WAIT_PLL_V 0x1 2352 #define RTC_CNTL_MAIN_STATE_IN_WAIT_PLL_S 24 2353 /* RTC_CNTL_MAIN_STATE_IN_WAIT_8M : RO ;bitpos:[23] ;default: 1'b0 ; */ 2354 /*description: rtc main state machine is in wait 8m state*/ 2355 #define RTC_CNTL_MAIN_STATE_IN_WAIT_8M (BIT(23)) 2356 #define RTC_CNTL_MAIN_STATE_IN_WAIT_8M_M (BIT(23)) 2357 #define RTC_CNTL_MAIN_STATE_IN_WAIT_8M_V 0x1 2358 #define RTC_CNTL_MAIN_STATE_IN_WAIT_8M_S 23 2359 /* RTC_CNTL_IN_LOW_POWER_STATE : RO ;bitpos:[22] ;default: 1'b0 ; */ 2360 /*description: rtc main state machine is in the states of low power*/ 2361 #define RTC_CNTL_IN_LOW_POWER_STATE (BIT(22)) 2362 #define RTC_CNTL_IN_LOW_POWER_STATE_M (BIT(22)) 2363 #define RTC_CNTL_IN_LOW_POWER_STATE_V 0x1 2364 #define RTC_CNTL_IN_LOW_POWER_STATE_S 22 2365 /* RTC_CNTL_IN_WAKEUP_STATE : RO ;bitpos:[21] ;default: 1'b0 ; */ 2366 /*description: rtc main state machine is in the states of wakeup process*/ 2367 #define RTC_CNTL_IN_WAKEUP_STATE (BIT(21)) 2368 #define RTC_CNTL_IN_WAKEUP_STATE_M (BIT(21)) 2369 #define RTC_CNTL_IN_WAKEUP_STATE_V 0x1 2370 #define RTC_CNTL_IN_WAKEUP_STATE_S 21 2371 /* RTC_CNTL_MAIN_STATE_WAIT_END : RO ;bitpos:[20] ;default: 1'b0 ; */ 2372 /*description: rtc main state machine has been waited for some cycles*/ 2373 #define RTC_CNTL_MAIN_STATE_WAIT_END (BIT(20)) 2374 #define RTC_CNTL_MAIN_STATE_WAIT_END_M (BIT(20)) 2375 #define RTC_CNTL_MAIN_STATE_WAIT_END_V 0x1 2376 #define RTC_CNTL_MAIN_STATE_WAIT_END_S 20 2377 /* RTC_CNTL_RDY_FOR_WAKEUP : RO ;bitpos:[19] ;default: 1'b0 ; */ 2378 /*description: rtc is ready to receive wake up trigger from wake up source*/ 2379 #define RTC_CNTL_RDY_FOR_WAKEUP (BIT(19)) 2380 #define RTC_CNTL_RDY_FOR_WAKEUP_M (BIT(19)) 2381 #define RTC_CNTL_RDY_FOR_WAKEUP_V 0x1 2382 #define RTC_CNTL_RDY_FOR_WAKEUP_S 19 2383 /* RTC_CNTL_MAIN_STATE_PLL_ON : RO ;bitpos:[18] ;default: 1'b0 ; */ 2384 /*description: rtc main state machine is in states that pll should be running*/ 2385 #define RTC_CNTL_MAIN_STATE_PLL_ON (BIT(18)) 2386 #define RTC_CNTL_MAIN_STATE_PLL_ON_M (BIT(18)) 2387 #define RTC_CNTL_MAIN_STATE_PLL_ON_V 0x1 2388 #define RTC_CNTL_MAIN_STATE_PLL_ON_S 18 2389 /* RTC_CNTL_MAIN_STATE_XTAL_ISO : RO ;bitpos:[17] ;default: 1'b0 ; */ 2390 /*description: no use any more*/ 2391 #define RTC_CNTL_MAIN_STATE_XTAL_ISO (BIT(17)) 2392 #define RTC_CNTL_MAIN_STATE_XTAL_ISO_M (BIT(17)) 2393 #define RTC_CNTL_MAIN_STATE_XTAL_ISO_V 0x1 2394 #define RTC_CNTL_MAIN_STATE_XTAL_ISO_S 17 2395 /* RTC_CNTL_COCPU_STATE_DONE : RO ;bitpos:[16] ;default: 1'b0 ; */ 2396 /*description: ulp/cocpu is done*/ 2397 #define RTC_CNTL_COCPU_STATE_DONE (BIT(16)) 2398 #define RTC_CNTL_COCPU_STATE_DONE_M (BIT(16)) 2399 #define RTC_CNTL_COCPU_STATE_DONE_V 0x1 2400 #define RTC_CNTL_COCPU_STATE_DONE_S 16 2401 /* RTC_CNTL_COCPU_STATE_SLP : RO ;bitpos:[15] ;default: 1'b0 ; */ 2402 /*description: ulp/cocpu is in sleep state*/ 2403 #define RTC_CNTL_COCPU_STATE_SLP (BIT(15)) 2404 #define RTC_CNTL_COCPU_STATE_SLP_M (BIT(15)) 2405 #define RTC_CNTL_COCPU_STATE_SLP_V 0x1 2406 #define RTC_CNTL_COCPU_STATE_SLP_S 15 2407 /* RTC_CNTL_COCPU_STATE_SWITCH : RO ;bitpos:[14] ;default: 1'b0 ; */ 2408 /*description: ulp/cocpu is about to working. Switch rtc main state*/ 2409 #define RTC_CNTL_COCPU_STATE_SWITCH (BIT(14)) 2410 #define RTC_CNTL_COCPU_STATE_SWITCH_M (BIT(14)) 2411 #define RTC_CNTL_COCPU_STATE_SWITCH_V 0x1 2412 #define RTC_CNTL_COCPU_STATE_SWITCH_S 14 2413 /* RTC_CNTL_COCPU_STATE_START : RO ;bitpos:[13] ;default: 1'b0 ; */ 2414 /*description: ulp/cocpu should start to work*/ 2415 #define RTC_CNTL_COCPU_STATE_START (BIT(13)) 2416 #define RTC_CNTL_COCPU_STATE_START_M (BIT(13)) 2417 #define RTC_CNTL_COCPU_STATE_START_V 0x1 2418 #define RTC_CNTL_COCPU_STATE_START_S 13 2419 /* RTC_CNTL_TOUCH_STATE_DONE : RO ;bitpos:[12] ;default: 1'b0 ; */ 2420 /*description: touch is done*/ 2421 #define RTC_CNTL_TOUCH_STATE_DONE (BIT(12)) 2422 #define RTC_CNTL_TOUCH_STATE_DONE_M (BIT(12)) 2423 #define RTC_CNTL_TOUCH_STATE_DONE_V 0x1 2424 #define RTC_CNTL_TOUCH_STATE_DONE_S 12 2425 /* RTC_CNTL_TOUCH_STATE_SLP : RO ;bitpos:[11] ;default: 1'b0 ; */ 2426 /*description: touch is in sleep state*/ 2427 #define RTC_CNTL_TOUCH_STATE_SLP (BIT(11)) 2428 #define RTC_CNTL_TOUCH_STATE_SLP_M (BIT(11)) 2429 #define RTC_CNTL_TOUCH_STATE_SLP_V 0x1 2430 #define RTC_CNTL_TOUCH_STATE_SLP_S 11 2431 /* RTC_CNTL_TOUCH_STATE_SWITCH : RO ;bitpos:[10] ;default: 1'b0 ; */ 2432 /*description: touch is about to working. Switch rtc main state*/ 2433 #define RTC_CNTL_TOUCH_STATE_SWITCH (BIT(10)) 2434 #define RTC_CNTL_TOUCH_STATE_SWITCH_M (BIT(10)) 2435 #define RTC_CNTL_TOUCH_STATE_SWITCH_V 0x1 2436 #define RTC_CNTL_TOUCH_STATE_SWITCH_S 10 2437 /* RTC_CNTL_TOUCH_STATE_START : RO ;bitpos:[9] ;default: 1'b0 ; */ 2438 /*description: touch should start to work*/ 2439 #define RTC_CNTL_TOUCH_STATE_START (BIT(9)) 2440 #define RTC_CNTL_TOUCH_STATE_START_M (BIT(9)) 2441 #define RTC_CNTL_TOUCH_STATE_START_V 0x1 2442 #define RTC_CNTL_TOUCH_STATE_START_S 9 2443 /* RTC_CNTL_XPD_DIG : RO ;bitpos:[8] ;default: 1'b0 ; */ 2444 /*description: digital wrap power down*/ 2445 #define RTC_CNTL_XPD_DIG (BIT(8)) 2446 #define RTC_CNTL_XPD_DIG_M (BIT(8)) 2447 #define RTC_CNTL_XPD_DIG_V 0x1 2448 #define RTC_CNTL_XPD_DIG_S 8 2449 /* RTC_CNTL_DIG_ISO : RO ;bitpos:[7] ;default: 1'b0 ; */ 2450 /*description: digital wrap iso*/ 2451 #define RTC_CNTL_DIG_ISO (BIT(7)) 2452 #define RTC_CNTL_DIG_ISO_M (BIT(7)) 2453 #define RTC_CNTL_DIG_ISO_V 0x1 2454 #define RTC_CNTL_DIG_ISO_S 7 2455 /* RTC_CNTL_XPD_WIFI : RO ;bitpos:[6] ;default: 1'b0 ; */ 2456 /*description: wifi wrap power down*/ 2457 #define RTC_CNTL_XPD_WIFI (BIT(6)) 2458 #define RTC_CNTL_XPD_WIFI_M (BIT(6)) 2459 #define RTC_CNTL_XPD_WIFI_V 0x1 2460 #define RTC_CNTL_XPD_WIFI_S 6 2461 /* RTC_CNTL_WIFI_ISO : RO ;bitpos:[5] ;default: 1'b0 ; */ 2462 /*description: wifi iso*/ 2463 #define RTC_CNTL_WIFI_ISO (BIT(5)) 2464 #define RTC_CNTL_WIFI_ISO_M (BIT(5)) 2465 #define RTC_CNTL_WIFI_ISO_V 0x1 2466 #define RTC_CNTL_WIFI_ISO_S 5 2467 /* RTC_CNTL_XPD_RTC_PERI : RO ;bitpos:[4] ;default: 1'b0 ; */ 2468 /*description: rtc peripheral power down*/ 2469 #define RTC_CNTL_XPD_RTC_PERI (BIT(4)) 2470 #define RTC_CNTL_XPD_RTC_PERI_M (BIT(4)) 2471 #define RTC_CNTL_XPD_RTC_PERI_V 0x1 2472 #define RTC_CNTL_XPD_RTC_PERI_S 4 2473 /* RTC_CNTL_PERI_ISO : RO ;bitpos:[3] ;default: 1'b0 ; */ 2474 /*description: rtc peripheral iso*/ 2475 #define RTC_CNTL_PERI_ISO (BIT(3)) 2476 #define RTC_CNTL_PERI_ISO_M (BIT(3)) 2477 #define RTC_CNTL_PERI_ISO_V 0x1 2478 #define RTC_CNTL_PERI_ISO_S 3 2479 /* RTC_CNTL_XPD_DIG_DCDC : RO ;bitpos:[2] ;default: 1'b0 ; */ 2480 /*description: External DCDC power down*/ 2481 #define RTC_CNTL_XPD_DIG_DCDC (BIT(2)) 2482 #define RTC_CNTL_XPD_DIG_DCDC_M (BIT(2)) 2483 #define RTC_CNTL_XPD_DIG_DCDC_V 0x1 2484 #define RTC_CNTL_XPD_DIG_DCDC_S 2 2485 /* RTC_CNTL_XPD_ROM0 : RO ;bitpos:[0] ;default: 1'b0 ; */ 2486 /*description: rom0 power down*/ 2487 #define RTC_CNTL_XPD_ROM0 (BIT(0)) 2488 #define RTC_CNTL_XPD_ROM0_M (BIT(0)) 2489 #define RTC_CNTL_XPD_ROM0_V 0x1 2490 #define RTC_CNTL_XPD_ROM0_S 0 2491 2492 #define RTC_CNTL_DIAG0_REG (DR_REG_RTCCNTL_BASE + 0x00D0) 2493 /* RTC_CNTL_LOW_POWER_DIAG1 : RO ;bitpos:[31:0] ;default: 0 ; */ 2494 /*description: */ 2495 #define RTC_CNTL_LOW_POWER_DIAG1 0xFFFFFFFF 2496 #define RTC_CNTL_LOW_POWER_DIAG1_M ((RTC_CNTL_LOW_POWER_DIAG1_V)<<(RTC_CNTL_LOW_POWER_DIAG1_S)) 2497 #define RTC_CNTL_LOW_POWER_DIAG1_V 0xFFFFFFFF 2498 #define RTC_CNTL_LOW_POWER_DIAG1_S 0 2499 2500 #define RTC_CNTL_PAD_HOLD_REG (DR_REG_RTCCNTL_BASE + 0x00D4) 2501 /* RTC_CNTL_PAD21_HOLD : R/W ;bitpos:[21] ;default: 1'b0 ; */ 2502 /*description: */ 2503 #define RTC_CNTL_PAD21_HOLD (BIT(21)) 2504 #define RTC_CNTL_PAD21_HOLD_M (BIT(21)) 2505 #define RTC_CNTL_PAD21_HOLD_V 0x1 2506 #define RTC_CNTL_PAD21_HOLD_S 21 2507 /* RTC_CNTL_PAD20_HOLD : R/W ;bitpos:[20] ;default: 1'b0 ; */ 2508 /*description: */ 2509 #define RTC_CNTL_PAD20_HOLD (BIT(20)) 2510 #define RTC_CNTL_PAD20_HOLD_M (BIT(20)) 2511 #define RTC_CNTL_PAD20_HOLD_V 0x1 2512 #define RTC_CNTL_PAD20_HOLD_S 20 2513 /* RTC_CNTL_PAD19_HOLD : R/W ;bitpos:[19] ;default: 1'b0 ; */ 2514 /*description: */ 2515 #define RTC_CNTL_PAD19_HOLD (BIT(19)) 2516 #define RTC_CNTL_PAD19_HOLD_M (BIT(19)) 2517 #define RTC_CNTL_PAD19_HOLD_V 0x1 2518 #define RTC_CNTL_PAD19_HOLD_S 19 2519 /* RTC_CNTL_PDAC2_HOLD : R/W ;bitpos:[18] ;default: 1'b0 ; */ 2520 /*description: */ 2521 #define RTC_CNTL_PDAC2_HOLD (BIT(18)) 2522 #define RTC_CNTL_PDAC2_HOLD_M (BIT(18)) 2523 #define RTC_CNTL_PDAC2_HOLD_V 0x1 2524 #define RTC_CNTL_PDAC2_HOLD_S 18 2525 /* RTC_CNTL_PDAC1_HOLD : R/W ;bitpos:[17] ;default: 1'b0 ; */ 2526 /*description: */ 2527 #define RTC_CNTL_PDAC1_HOLD (BIT(17)) 2528 #define RTC_CNTL_PDAC1_HOLD_M (BIT(17)) 2529 #define RTC_CNTL_PDAC1_HOLD_V 0x1 2530 #define RTC_CNTL_PDAC1_HOLD_S 17 2531 /* RTC_CNTL_X32N_HOLD : R/W ;bitpos:[16] ;default: 1'b0 ; */ 2532 /*description: */ 2533 #define RTC_CNTL_X32N_HOLD (BIT(16)) 2534 #define RTC_CNTL_X32N_HOLD_M (BIT(16)) 2535 #define RTC_CNTL_X32N_HOLD_V 0x1 2536 #define RTC_CNTL_X32N_HOLD_S 16 2537 /* RTC_CNTL_X32P_HOLD : R/W ;bitpos:[15] ;default: 1'b0 ; */ 2538 /*description: */ 2539 #define RTC_CNTL_X32P_HOLD (BIT(15)) 2540 #define RTC_CNTL_X32P_HOLD_M (BIT(15)) 2541 #define RTC_CNTL_X32P_HOLD_V 0x1 2542 #define RTC_CNTL_X32P_HOLD_S 15 2543 /* RTC_CNTL_TOUCH_PAD14_HOLD : R/W ;bitpos:[14] ;default: 1'b0 ; */ 2544 /*description: */ 2545 #define RTC_CNTL_TOUCH_PAD14_HOLD (BIT(14)) 2546 #define RTC_CNTL_TOUCH_PAD14_HOLD_M (BIT(14)) 2547 #define RTC_CNTL_TOUCH_PAD14_HOLD_V 0x1 2548 #define RTC_CNTL_TOUCH_PAD14_HOLD_S 14 2549 /* RTC_CNTL_TOUCH_PAD13_HOLD : R/W ;bitpos:[13] ;default: 1'b0 ; */ 2550 /*description: */ 2551 #define RTC_CNTL_TOUCH_PAD13_HOLD (BIT(13)) 2552 #define RTC_CNTL_TOUCH_PAD13_HOLD_M (BIT(13)) 2553 #define RTC_CNTL_TOUCH_PAD13_HOLD_V 0x1 2554 #define RTC_CNTL_TOUCH_PAD13_HOLD_S 13 2555 /* RTC_CNTL_TOUCH_PAD12_HOLD : R/W ;bitpos:[12] ;default: 1'b0 ; */ 2556 /*description: */ 2557 #define RTC_CNTL_TOUCH_PAD12_HOLD (BIT(12)) 2558 #define RTC_CNTL_TOUCH_PAD12_HOLD_M (BIT(12)) 2559 #define RTC_CNTL_TOUCH_PAD12_HOLD_V 0x1 2560 #define RTC_CNTL_TOUCH_PAD12_HOLD_S 12 2561 /* RTC_CNTL_TOUCH_PAD11_HOLD : R/W ;bitpos:[11] ;default: 1'b0 ; */ 2562 /*description: */ 2563 #define RTC_CNTL_TOUCH_PAD11_HOLD (BIT(11)) 2564 #define RTC_CNTL_TOUCH_PAD11_HOLD_M (BIT(11)) 2565 #define RTC_CNTL_TOUCH_PAD11_HOLD_V 0x1 2566 #define RTC_CNTL_TOUCH_PAD11_HOLD_S 11 2567 /* RTC_CNTL_TOUCH_PAD10_HOLD : R/W ;bitpos:[10] ;default: 1'b0 ; */ 2568 /*description: */ 2569 #define RTC_CNTL_TOUCH_PAD10_HOLD (BIT(10)) 2570 #define RTC_CNTL_TOUCH_PAD10_HOLD_M (BIT(10)) 2571 #define RTC_CNTL_TOUCH_PAD10_HOLD_V 0x1 2572 #define RTC_CNTL_TOUCH_PAD10_HOLD_S 10 2573 /* RTC_CNTL_TOUCH_PAD9_HOLD : R/W ;bitpos:[9] ;default: 1'b0 ; */ 2574 /*description: */ 2575 #define RTC_CNTL_TOUCH_PAD9_HOLD (BIT(9)) 2576 #define RTC_CNTL_TOUCH_PAD9_HOLD_M (BIT(9)) 2577 #define RTC_CNTL_TOUCH_PAD9_HOLD_V 0x1 2578 #define RTC_CNTL_TOUCH_PAD9_HOLD_S 9 2579 /* RTC_CNTL_TOUCH_PAD8_HOLD : R/W ;bitpos:[8] ;default: 1'b0 ; */ 2580 /*description: */ 2581 #define RTC_CNTL_TOUCH_PAD8_HOLD (BIT(8)) 2582 #define RTC_CNTL_TOUCH_PAD8_HOLD_M (BIT(8)) 2583 #define RTC_CNTL_TOUCH_PAD8_HOLD_V 0x1 2584 #define RTC_CNTL_TOUCH_PAD8_HOLD_S 8 2585 /* RTC_CNTL_TOUCH_PAD7_HOLD : R/W ;bitpos:[7] ;default: 1'b0 ; */ 2586 /*description: */ 2587 #define RTC_CNTL_TOUCH_PAD7_HOLD (BIT(7)) 2588 #define RTC_CNTL_TOUCH_PAD7_HOLD_M (BIT(7)) 2589 #define RTC_CNTL_TOUCH_PAD7_HOLD_V 0x1 2590 #define RTC_CNTL_TOUCH_PAD7_HOLD_S 7 2591 /* RTC_CNTL_TOUCH_PAD6_HOLD : R/W ;bitpos:[6] ;default: 1'b0 ; */ 2592 /*description: */ 2593 #define RTC_CNTL_TOUCH_PAD6_HOLD (BIT(6)) 2594 #define RTC_CNTL_TOUCH_PAD6_HOLD_M (BIT(6)) 2595 #define RTC_CNTL_TOUCH_PAD6_HOLD_V 0x1 2596 #define RTC_CNTL_TOUCH_PAD6_HOLD_S 6 2597 /* RTC_CNTL_TOUCH_PAD5_HOLD : R/W ;bitpos:[5] ;default: 1'b0 ; */ 2598 /*description: */ 2599 #define RTC_CNTL_TOUCH_PAD5_HOLD (BIT(5)) 2600 #define RTC_CNTL_TOUCH_PAD5_HOLD_M (BIT(5)) 2601 #define RTC_CNTL_TOUCH_PAD5_HOLD_V 0x1 2602 #define RTC_CNTL_TOUCH_PAD5_HOLD_S 5 2603 /* RTC_CNTL_TOUCH_PAD4_HOLD : R/W ;bitpos:[4] ;default: 1'b0 ; */ 2604 /*description: */ 2605 #define RTC_CNTL_TOUCH_PAD4_HOLD (BIT(4)) 2606 #define RTC_CNTL_TOUCH_PAD4_HOLD_M (BIT(4)) 2607 #define RTC_CNTL_TOUCH_PAD4_HOLD_V 0x1 2608 #define RTC_CNTL_TOUCH_PAD4_HOLD_S 4 2609 /* RTC_CNTL_TOUCH_PAD3_HOLD : R/W ;bitpos:[3] ;default: 1'b0 ; */ 2610 /*description: */ 2611 #define RTC_CNTL_TOUCH_PAD3_HOLD (BIT(3)) 2612 #define RTC_CNTL_TOUCH_PAD3_HOLD_M (BIT(3)) 2613 #define RTC_CNTL_TOUCH_PAD3_HOLD_V 0x1 2614 #define RTC_CNTL_TOUCH_PAD3_HOLD_S 3 2615 /* RTC_CNTL_TOUCH_PAD2_HOLD : R/W ;bitpos:[2] ;default: 1'b0 ; */ 2616 /*description: */ 2617 #define RTC_CNTL_TOUCH_PAD2_HOLD (BIT(2)) 2618 #define RTC_CNTL_TOUCH_PAD2_HOLD_M (BIT(2)) 2619 #define RTC_CNTL_TOUCH_PAD2_HOLD_V 0x1 2620 #define RTC_CNTL_TOUCH_PAD2_HOLD_S 2 2621 /* RTC_CNTL_TOUCH_PAD1_HOLD : R/W ;bitpos:[1] ;default: 1'b0 ; */ 2622 /*description: */ 2623 #define RTC_CNTL_TOUCH_PAD1_HOLD (BIT(1)) 2624 #define RTC_CNTL_TOUCH_PAD1_HOLD_M (BIT(1)) 2625 #define RTC_CNTL_TOUCH_PAD1_HOLD_V 0x1 2626 #define RTC_CNTL_TOUCH_PAD1_HOLD_S 1 2627 /* RTC_CNTL_TOUCH_PAD0_HOLD : R/W ;bitpos:[0] ;default: 1'b0 ; */ 2628 /*description: */ 2629 #define RTC_CNTL_TOUCH_PAD0_HOLD (BIT(0)) 2630 #define RTC_CNTL_TOUCH_PAD0_HOLD_M (BIT(0)) 2631 #define RTC_CNTL_TOUCH_PAD0_HOLD_V 0x1 2632 #define RTC_CNTL_TOUCH_PAD0_HOLD_S 0 2633 2634 #define RTC_CNTL_DIG_PAD_HOLD_REG (DR_REG_RTCCNTL_BASE + 0x00D8) 2635 /* RTC_CNTL_DIG_PAD_HOLD : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ 2636 /*description: */ 2637 #define RTC_CNTL_DIG_PAD_HOLD 0xFFFFFFFF 2638 #define RTC_CNTL_DIG_PAD_HOLD_M ((RTC_CNTL_DIG_PAD_HOLD_V)<<(RTC_CNTL_DIG_PAD_HOLD_S)) 2639 #define RTC_CNTL_DIG_PAD_HOLD_V 0xFFFFFFFF 2640 #define RTC_CNTL_DIG_PAD_HOLD_S 0 2641 2642 #define RTC_CNTL_EXT_WAKEUP1_REG (DR_REG_RTCCNTL_BASE + 0x00DC) 2643 /* RTC_CNTL_EXT_WAKEUP1_STATUS_CLR : WO ;bitpos:[22] ;default: 1'd0 ; */ 2644 /*description: clear ext wakeup1 status*/ 2645 #define RTC_CNTL_EXT_WAKEUP1_STATUS_CLR (BIT(22)) 2646 #define RTC_CNTL_EXT_WAKEUP1_STATUS_CLR_M (BIT(22)) 2647 #define RTC_CNTL_EXT_WAKEUP1_STATUS_CLR_V 0x1 2648 #define RTC_CNTL_EXT_WAKEUP1_STATUS_CLR_S 22 2649 /* RTC_CNTL_EXT_WAKEUP1_SEL : R/W ;bitpos:[21:0] ;default: 22'd0 ; */ 2650 /*description: Bitmap to select RTC pads for ext wakeup1*/ 2651 #define RTC_CNTL_EXT_WAKEUP1_SEL 0x003FFFFF 2652 #define RTC_CNTL_EXT_WAKEUP1_SEL_M ((RTC_CNTL_EXT_WAKEUP1_SEL_V)<<(RTC_CNTL_EXT_WAKEUP1_SEL_S)) 2653 #define RTC_CNTL_EXT_WAKEUP1_SEL_V 0x3FFFFF 2654 #define RTC_CNTL_EXT_WAKEUP1_SEL_S 0 2655 2656 #define RTC_CNTL_EXT_WAKEUP1_STATUS_REG (DR_REG_RTCCNTL_BASE + 0x00E0) 2657 /* RTC_CNTL_EXT_WAKEUP1_STATUS : RO ;bitpos:[21:0] ;default: 22'd0 ; */ 2658 /*description: ext wakeup1 status*/ 2659 #define RTC_CNTL_EXT_WAKEUP1_STATUS 0x003FFFFF 2660 #define RTC_CNTL_EXT_WAKEUP1_STATUS_M ((RTC_CNTL_EXT_WAKEUP1_STATUS_V)<<(RTC_CNTL_EXT_WAKEUP1_STATUS_S)) 2661 #define RTC_CNTL_EXT_WAKEUP1_STATUS_V 0x3FFFFF 2662 #define RTC_CNTL_EXT_WAKEUP1_STATUS_S 0 2663 2664 #define RTC_CNTL_BROWN_OUT_REG (DR_REG_RTCCNTL_BASE + 0x00E4) 2665 /* RTC_CNTL_BROWN_OUT_DET : RO ;bitpos:[31] ;default: 1'b0 ; */ 2666 /*description: */ 2667 #define RTC_CNTL_BROWN_OUT_DET (BIT(31)) 2668 #define RTC_CNTL_BROWN_OUT_DET_M (BIT(31)) 2669 #define RTC_CNTL_BROWN_OUT_DET_V 0x1 2670 #define RTC_CNTL_BROWN_OUT_DET_S 31 2671 /* RTC_CNTL_BROWN_OUT_ENA : R/W ;bitpos:[30] ;default: 1'b0 ; */ 2672 /*description: enable brown out*/ 2673 #define RTC_CNTL_BROWN_OUT_ENA (BIT(30)) 2674 #define RTC_CNTL_BROWN_OUT_ENA_M (BIT(30)) 2675 #define RTC_CNTL_BROWN_OUT_ENA_V 0x1 2676 #define RTC_CNTL_BROWN_OUT_ENA_S 30 2677 /* RTC_CNTL_BROWN_OUT_CNT_CLR : WO ;bitpos:[29] ;default: 1'b0 ; */ 2678 /*description: clear brown out counter*/ 2679 #define RTC_CNTL_BROWN_OUT_CNT_CLR (BIT(29)) 2680 #define RTC_CNTL_BROWN_OUT_CNT_CLR_M (BIT(29)) 2681 #define RTC_CNTL_BROWN_OUT_CNT_CLR_V 0x1 2682 #define RTC_CNTL_BROWN_OUT_CNT_CLR_S 29 2683 /* RTC_CNTL_BROWN_OUT_RST_SEL : R/W ;bitpos:[27] ;default: 1'b0 ; */ 2684 /*description: 1: 4-pos reset*/ 2685 #define RTC_CNTL_BROWN_OUT_RST_SEL (BIT(27)) 2686 #define RTC_CNTL_BROWN_OUT_RST_SEL_M (BIT(27)) 2687 #define RTC_CNTL_BROWN_OUT_RST_SEL_V 0x1 2688 #define RTC_CNTL_BROWN_OUT_RST_SEL_S 27 2689 /* RTC_CNTL_BROWN_OUT_RST_ENA : R/W ;bitpos:[26] ;default: 1'b0 ; */ 2690 /*description: enable brown out reset*/ 2691 #define RTC_CNTL_BROWN_OUT_RST_ENA (BIT(26)) 2692 #define RTC_CNTL_BROWN_OUT_RST_ENA_M (BIT(26)) 2693 #define RTC_CNTL_BROWN_OUT_RST_ENA_V 0x1 2694 #define RTC_CNTL_BROWN_OUT_RST_ENA_S 26 2695 /* RTC_CNTL_BROWN_OUT_RST_WAIT : R/W ;bitpos:[25:16] ;default: 10'h3ff ; */ 2696 /*description: brown out reset wait cycles*/ 2697 #define RTC_CNTL_BROWN_OUT_RST_WAIT 0x000003FF 2698 #define RTC_CNTL_BROWN_OUT_RST_WAIT_M ((RTC_CNTL_BROWN_OUT_RST_WAIT_V)<<(RTC_CNTL_BROWN_OUT_RST_WAIT_S)) 2699 #define RTC_CNTL_BROWN_OUT_RST_WAIT_V 0x3FF 2700 #define RTC_CNTL_BROWN_OUT_RST_WAIT_S 16 2701 /* RTC_CNTL_BROWN_OUT_PD_RF_ENA : R/W ;bitpos:[15] ;default: 1'b0 ; */ 2702 /*description: enable power down RF when brown out happens*/ 2703 #define RTC_CNTL_BROWN_OUT_PD_RF_ENA (BIT(15)) 2704 #define RTC_CNTL_BROWN_OUT_PD_RF_ENA_M (BIT(15)) 2705 #define RTC_CNTL_BROWN_OUT_PD_RF_ENA_V 0x1 2706 #define RTC_CNTL_BROWN_OUT_PD_RF_ENA_S 15 2707 /* RTC_CNTL_BROWN_OUT_CLOSE_FLASH_ENA : R/W ;bitpos:[14] ;default: 1'b0 ; */ 2708 /*description: enable close flash when brown out happens*/ 2709 #define RTC_CNTL_BROWN_OUT_CLOSE_FLASH_ENA (BIT(14)) 2710 #define RTC_CNTL_BROWN_OUT_CLOSE_FLASH_ENA_M (BIT(14)) 2711 #define RTC_CNTL_BROWN_OUT_CLOSE_FLASH_ENA_V 0x1 2712 #define RTC_CNTL_BROWN_OUT_CLOSE_FLASH_ENA_S 14 2713 /* RTC_CNTL_BROWN_OUT_INT_WAIT : R/W ;bitpos:[13:4] ;default: 10'h2ff ; */ 2714 /*description: brown out interrupt wait cycles*/ 2715 #define RTC_CNTL_BROWN_OUT_INT_WAIT 0x000003FF 2716 #define RTC_CNTL_BROWN_OUT_INT_WAIT_M ((RTC_CNTL_BROWN_OUT_INT_WAIT_V)<<(RTC_CNTL_BROWN_OUT_INT_WAIT_S)) 2717 #define RTC_CNTL_BROWN_OUT_INT_WAIT_V 0x3FF 2718 #define RTC_CNTL_BROWN_OUT_INT_WAIT_S 4 2719 /* RTC_CNTL_BROWN_OUT2_ENA : R/W ;bitpos:[0] ;default: 1'b1 ; */ 2720 /*description: enable brown_out2 to start chip reset*/ 2721 #define RTC_CNTL_BROWN_OUT2_ENA (BIT(0)) 2722 #define RTC_CNTL_BROWN_OUT2_ENA_M (BIT(0)) 2723 #define RTC_CNTL_BROWN_OUT2_ENA_V 0x1 2724 #define RTC_CNTL_BROWN_OUT2_ENA_S 0 2725 2726 #define RTC_CNTL_TIME_LOW1_REG (DR_REG_RTCCNTL_BASE + 0x00E8) 2727 /* RTC_CNTL_TIMER_VALUE1_LOW : RO ;bitpos:[31:0] ;default: 32'h0 ; */ 2728 /*description: RTC timer low 32 bits*/ 2729 #define RTC_CNTL_TIMER_VALUE1_LOW 0xFFFFFFFF 2730 #define RTC_CNTL_TIMER_VALUE1_LOW_M ((RTC_CNTL_TIMER_VALUE1_LOW_V)<<(RTC_CNTL_TIMER_VALUE1_LOW_S)) 2731 #define RTC_CNTL_TIMER_VALUE1_LOW_V 0xFFFFFFFF 2732 #define RTC_CNTL_TIMER_VALUE1_LOW_S 0 2733 2734 #define RTC_CNTL_TIME_HIGH1_REG (DR_REG_RTCCNTL_BASE + 0x00EC) 2735 /* RTC_CNTL_TIMER_VALUE1_HIGH : RO ;bitpos:[15:0] ;default: 16'h0 ; */ 2736 /*description: RTC timer high 16 bits*/ 2737 #define RTC_CNTL_TIMER_VALUE1_HIGH 0x0000FFFF 2738 #define RTC_CNTL_TIMER_VALUE1_HIGH_M ((RTC_CNTL_TIMER_VALUE1_HIGH_V)<<(RTC_CNTL_TIMER_VALUE1_HIGH_S)) 2739 #define RTC_CNTL_TIMER_VALUE1_HIGH_V 0xFFFF 2740 #define RTC_CNTL_TIMER_VALUE1_HIGH_S 0 2741 2742 #define RTC_CNTL_XTAL32K_CLK_FACTOR_REG (DR_REG_RTCCNTL_BASE + 0x00F0) 2743 /* RTC_CNTL_XTAL32K_CLK_FACTOR : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ 2744 /*description: xtal 32k watch dog backup clock factor*/ 2745 #define RTC_CNTL_XTAL32K_CLK_FACTOR 0xFFFFFFFF 2746 #define RTC_CNTL_XTAL32K_CLK_FACTOR_M ((RTC_CNTL_XTAL32K_CLK_FACTOR_V)<<(RTC_CNTL_XTAL32K_CLK_FACTOR_S)) 2747 #define RTC_CNTL_XTAL32K_CLK_FACTOR_V 0xFFFFFFFF 2748 #define RTC_CNTL_XTAL32K_CLK_FACTOR_S 0 2749 2750 #define RTC_CNTL_XTAL32K_CONF_REG (DR_REG_RTCCNTL_BASE + 0x00F4) 2751 /* RTC_CNTL_XTAL32K_STABLE_THRES : R/W ;bitpos:[31:28] ;default: 4'h0 ; */ 2752 /*description: if restarted xtal32k period is smaller than this it is regarded as stable*/ 2753 #define RTC_CNTL_XTAL32K_STABLE_THRES 0x0000000F 2754 #define RTC_CNTL_XTAL32K_STABLE_THRES_M ((RTC_CNTL_XTAL32K_STABLE_THRES_V)<<(RTC_CNTL_XTAL32K_STABLE_THRES_S)) 2755 #define RTC_CNTL_XTAL32K_STABLE_THRES_V 0xF 2756 #define RTC_CNTL_XTAL32K_STABLE_THRES_S 28 2757 /* RTC_CNTL_XTAL32K_WDT_TIMEOUT : R/W ;bitpos:[27:20] ;default: 8'hff ; */ 2758 /*description: If no clock detected for this amount of time 32k is regarded as dead*/ 2759 #define RTC_CNTL_XTAL32K_WDT_TIMEOUT 0x000000FF 2760 #define RTC_CNTL_XTAL32K_WDT_TIMEOUT_M ((RTC_CNTL_XTAL32K_WDT_TIMEOUT_V)<<(RTC_CNTL_XTAL32K_WDT_TIMEOUT_S)) 2761 #define RTC_CNTL_XTAL32K_WDT_TIMEOUT_V 0xFF 2762 #define RTC_CNTL_XTAL32K_WDT_TIMEOUT_S 20 2763 /* RTC_CNTL_XTAL32K_RESTART_WAIT : R/W ;bitpos:[19:4] ;default: 16'h0 ; */ 2764 /*description: cycles to wait to repower on xtal 32k*/ 2765 #define RTC_CNTL_XTAL32K_RESTART_WAIT 0x0000FFFF 2766 #define RTC_CNTL_XTAL32K_RESTART_WAIT_M ((RTC_CNTL_XTAL32K_RESTART_WAIT_V)<<(RTC_CNTL_XTAL32K_RESTART_WAIT_S)) 2767 #define RTC_CNTL_XTAL32K_RESTART_WAIT_V 0xFFFF 2768 #define RTC_CNTL_XTAL32K_RESTART_WAIT_S 4 2769 /* RTC_CNTL_XTAL32K_RETURN_WAIT : R/W ;bitpos:[3:0] ;default: 4'h0 ; */ 2770 /*description: cycles to wait to return noral xtal 32k*/ 2771 #define RTC_CNTL_XTAL32K_RETURN_WAIT 0x0000000F 2772 #define RTC_CNTL_XTAL32K_RETURN_WAIT_M ((RTC_CNTL_XTAL32K_RETURN_WAIT_V)<<(RTC_CNTL_XTAL32K_RETURN_WAIT_S)) 2773 #define RTC_CNTL_XTAL32K_RETURN_WAIT_V 0xF 2774 #define RTC_CNTL_XTAL32K_RETURN_WAIT_S 0 2775 2776 #define RTC_CNTL_ULP_CP_TIMER_REG (DR_REG_RTCCNTL_BASE + 0x00F8) 2777 /* RTC_CNTL_ULP_CP_SLP_TIMER_EN : R/W ;bitpos:[31] ;default: 1'd0 ; */ 2778 /*description: ULP-coprocessor timer enable bit*/ 2779 #define RTC_CNTL_ULP_CP_SLP_TIMER_EN (BIT(31)) 2780 #define RTC_CNTL_ULP_CP_SLP_TIMER_EN_M (BIT(31)) 2781 #define RTC_CNTL_ULP_CP_SLP_TIMER_EN_V 0x1 2782 #define RTC_CNTL_ULP_CP_SLP_TIMER_EN_S 31 2783 /* RTC_CNTL_ULP_CP_GPIO_WAKEUP_CLR : WO ;bitpos:[30] ;default: 1'd0 ; */ 2784 /*description: ULP-coprocessor wakeup by GPIO state clear*/ 2785 #define RTC_CNTL_ULP_CP_GPIO_WAKEUP_CLR (BIT(30)) 2786 #define RTC_CNTL_ULP_CP_GPIO_WAKEUP_CLR_M (BIT(30)) 2787 #define RTC_CNTL_ULP_CP_GPIO_WAKEUP_CLR_V 0x1 2788 #define RTC_CNTL_ULP_CP_GPIO_WAKEUP_CLR_S 30 2789 /* RTC_CNTL_ULP_CP_GPIO_WAKEUP_ENA : R/W ;bitpos:[29] ;default: 1'd0 ; */ 2790 /*description: ULP-coprocessor wakeup by GPIO enable*/ 2791 #define RTC_CNTL_ULP_CP_GPIO_WAKEUP_ENA (BIT(29)) 2792 #define RTC_CNTL_ULP_CP_GPIO_WAKEUP_ENA_M (BIT(29)) 2793 #define RTC_CNTL_ULP_CP_GPIO_WAKEUP_ENA_V 0x1 2794 #define RTC_CNTL_ULP_CP_GPIO_WAKEUP_ENA_S 29 2795 /* RTC_CNTL_ULP_CP_PC_INIT : R/W ;bitpos:[10:0] ;default: 11'b0 ; */ 2796 /*description: ULP-coprocessor PC initial address*/ 2797 #define RTC_CNTL_ULP_CP_PC_INIT 0x000007FF 2798 #define RTC_CNTL_ULP_CP_PC_INIT_M ((RTC_CNTL_ULP_CP_PC_INIT_V)<<(RTC_CNTL_ULP_CP_PC_INIT_S)) 2799 #define RTC_CNTL_ULP_CP_PC_INIT_V 0x7FF 2800 #define RTC_CNTL_ULP_CP_PC_INIT_S 0 2801 2802 #define RTC_CNTL_ULP_CP_CTRL_REG (DR_REG_RTCCNTL_BASE + 0x00FC) 2803 /* RTC_CNTL_ULP_CP_START_TOP : R/W ;bitpos:[31] ;default: 1'd0 ; */ 2804 /*description: Write 1 to start ULP-coprocessor*/ 2805 #define RTC_CNTL_ULP_CP_START_TOP (BIT(31)) 2806 #define RTC_CNTL_ULP_CP_START_TOP_M (BIT(31)) 2807 #define RTC_CNTL_ULP_CP_START_TOP_V 0x1 2808 #define RTC_CNTL_ULP_CP_START_TOP_S 31 2809 /* RTC_CNTL_ULP_CP_FORCE_START_TOP : R/W ;bitpos:[30] ;default: 1'd0 ; */ 2810 /*description: 1: ULP-coprocessor is started by SW*/ 2811 #define RTC_CNTL_ULP_CP_FORCE_START_TOP (BIT(30)) 2812 #define RTC_CNTL_ULP_CP_FORCE_START_TOP_M (BIT(30)) 2813 #define RTC_CNTL_ULP_CP_FORCE_START_TOP_V 0x1 2814 #define RTC_CNTL_ULP_CP_FORCE_START_TOP_S 30 2815 /* RTC_CNTL_ULP_CP_RESET : R/W ;bitpos:[29] ;default: 1'd0 ; */ 2816 /*description: ulp coprocessor clk software reset*/ 2817 #define RTC_CNTL_ULP_CP_RESET (BIT(29)) 2818 #define RTC_CNTL_ULP_CP_RESET_M (BIT(29)) 2819 #define RTC_CNTL_ULP_CP_RESET_V 0x1 2820 #define RTC_CNTL_ULP_CP_RESET_S 29 2821 /* RTC_CNTL_ULP_CP_CLK_FO : R/W ;bitpos:[28] ;default: 1'd0 ; */ 2822 /*description: ulp coprocessor clk force on*/ 2823 #define RTC_CNTL_ULP_CP_CLK_FO (BIT(28)) 2824 #define RTC_CNTL_ULP_CP_CLK_FO_M (BIT(28)) 2825 #define RTC_CNTL_ULP_CP_CLK_FO_V 0x1 2826 #define RTC_CNTL_ULP_CP_CLK_FO_S 28 2827 /* RTC_CNTL_ULP_CP_MEM_OFFST_CLR : WO ;bitpos:[22] ;default: 1'd0 ; */ 2828 /*description: */ 2829 #define RTC_CNTL_ULP_CP_MEM_OFFST_CLR (BIT(22)) 2830 #define RTC_CNTL_ULP_CP_MEM_OFFST_CLR_M (BIT(22)) 2831 #define RTC_CNTL_ULP_CP_MEM_OFFST_CLR_V 0x1 2832 #define RTC_CNTL_ULP_CP_MEM_OFFST_CLR_S 22 2833 /* RTC_CNTL_ULP_CP_MEM_ADDR_SIZE : R/W ;bitpos:[21:11] ;default: 11'd512 ; */ 2834 /*description: */ 2835 #define RTC_CNTL_ULP_CP_MEM_ADDR_SIZE 0x000007FF 2836 #define RTC_CNTL_ULP_CP_MEM_ADDR_SIZE_M ((RTC_CNTL_ULP_CP_MEM_ADDR_SIZE_V)<<(RTC_CNTL_ULP_CP_MEM_ADDR_SIZE_S)) 2837 #define RTC_CNTL_ULP_CP_MEM_ADDR_SIZE_V 0x7FF 2838 #define RTC_CNTL_ULP_CP_MEM_ADDR_SIZE_S 11 2839 /* RTC_CNTL_ULP_CP_MEM_ADDR_INIT : R/W ;bitpos:[10:0] ;default: 11'd512 ; */ 2840 /*description: */ 2841 #define RTC_CNTL_ULP_CP_MEM_ADDR_INIT 0x000007FF 2842 #define RTC_CNTL_ULP_CP_MEM_ADDR_INIT_M ((RTC_CNTL_ULP_CP_MEM_ADDR_INIT_V)<<(RTC_CNTL_ULP_CP_MEM_ADDR_INIT_S)) 2843 #define RTC_CNTL_ULP_CP_MEM_ADDR_INIT_V 0x7FF 2844 #define RTC_CNTL_ULP_CP_MEM_ADDR_INIT_S 0 2845 2846 #define RTC_CNTL_COCPU_CTRL_REG (DR_REG_RTCCNTL_BASE + 0x0100) 2847 /* RTC_CNTL_COCPU_SW_INT_TRIGGER : WO ;bitpos:[26] ;default: 1'b0 ; */ 2848 /*description: trigger cocpu register interrupt*/ 2849 #define RTC_CNTL_COCPU_SW_INT_TRIGGER (BIT(26)) 2850 #define RTC_CNTL_COCPU_SW_INT_TRIGGER_M (BIT(26)) 2851 #define RTC_CNTL_COCPU_SW_INT_TRIGGER_V 0x1 2852 #define RTC_CNTL_COCPU_SW_INT_TRIGGER_S 26 2853 /* RTC_CNTL_COCPU_DONE : R/W ;bitpos:[25] ;default: 1'b0 ; */ 2854 /*description: done signal used by riscv to control timer.*/ 2855 #define RTC_CNTL_COCPU_DONE (BIT(25)) 2856 #define RTC_CNTL_COCPU_DONE_M (BIT(25)) 2857 #define RTC_CNTL_COCPU_DONE_V 0x1 2858 #define RTC_CNTL_COCPU_DONE_S 25 2859 /* RTC_CNTL_COCPU_DONE_FORCE : R/W ;bitpos:[24] ;default: 1'b0 ; */ 2860 /*description: 1: select riscv done 0: select ulp done*/ 2861 #define RTC_CNTL_COCPU_DONE_FORCE (BIT(24)) 2862 #define RTC_CNTL_COCPU_DONE_FORCE_M (BIT(24)) 2863 #define RTC_CNTL_COCPU_DONE_FORCE_V 0x1 2864 #define RTC_CNTL_COCPU_DONE_FORCE_S 24 2865 /* RTC_CNTL_COCPU_SEL : R/W ;bitpos:[23] ;default: 1'b1 ; */ 2866 /*description: 1: old ULP 0: new riscV*/ 2867 #define RTC_CNTL_COCPU_SEL (BIT(23)) 2868 #define RTC_CNTL_COCPU_SEL_M (BIT(23)) 2869 #define RTC_CNTL_COCPU_SEL_V 0x1 2870 #define RTC_CNTL_COCPU_SEL_S 23 2871 /* RTC_CNTL_COCPU_SHUT_RESET_EN : R/W ;bitpos:[22] ;default: 1'b0 ; */ 2872 /*description: to reset cocpu*/ 2873 #define RTC_CNTL_COCPU_SHUT_RESET_EN (BIT(22)) 2874 #define RTC_CNTL_COCPU_SHUT_RESET_EN_M (BIT(22)) 2875 #define RTC_CNTL_COCPU_SHUT_RESET_EN_V 0x1 2876 #define RTC_CNTL_COCPU_SHUT_RESET_EN_S 22 2877 /* RTC_CNTL_COCPU_SHUT_2_CLK_DIS : R/W ;bitpos:[21:14] ;default: 8'd40 ; */ 2878 /*description: time from shut cocpu to disable clk*/ 2879 #define RTC_CNTL_COCPU_SHUT_2_CLK_DIS 0x000000FF 2880 #define RTC_CNTL_COCPU_SHUT_2_CLK_DIS_M ((RTC_CNTL_COCPU_SHUT_2_CLK_DIS_V)<<(RTC_CNTL_COCPU_SHUT_2_CLK_DIS_S)) 2881 #define RTC_CNTL_COCPU_SHUT_2_CLK_DIS_V 0xFF 2882 #define RTC_CNTL_COCPU_SHUT_2_CLK_DIS_S 14 2883 /* RTC_CNTL_COCPU_SHUT : R/W ;bitpos:[13] ;default: 1'b0 ; */ 2884 /*description: to shut cocpu*/ 2885 #define RTC_CNTL_COCPU_SHUT (BIT(13)) 2886 #define RTC_CNTL_COCPU_SHUT_M (BIT(13)) 2887 #define RTC_CNTL_COCPU_SHUT_V 0x1 2888 #define RTC_CNTL_COCPU_SHUT_S 13 2889 /* RTC_CNTL_COCPU_START_2_INTR_EN : R/W ;bitpos:[12:7] ;default: 6'd16 ; */ 2890 /*description: time from start cocpu to give start interrupt*/ 2891 #define RTC_CNTL_COCPU_START_2_INTR_EN 0x0000003F 2892 #define RTC_CNTL_COCPU_START_2_INTR_EN_M ((RTC_CNTL_COCPU_START_2_INTR_EN_V)<<(RTC_CNTL_COCPU_START_2_INTR_EN_S)) 2893 #define RTC_CNTL_COCPU_START_2_INTR_EN_V 0x3F 2894 #define RTC_CNTL_COCPU_START_2_INTR_EN_S 7 2895 /* RTC_CNTL_COCPU_START_2_RESET_DIS : R/W ;bitpos:[6:1] ;default: 6'd8 ; */ 2896 /*description: time from start cocpu to pull down reset*/ 2897 #define RTC_CNTL_COCPU_START_2_RESET_DIS 0x0000003F 2898 #define RTC_CNTL_COCPU_START_2_RESET_DIS_M ((RTC_CNTL_COCPU_START_2_RESET_DIS_V)<<(RTC_CNTL_COCPU_START_2_RESET_DIS_S)) 2899 #define RTC_CNTL_COCPU_START_2_RESET_DIS_V 0x3F 2900 #define RTC_CNTL_COCPU_START_2_RESET_DIS_S 1 2901 /* RTC_CNTL_COCPU_CLK_FO : R/W ;bitpos:[0] ;default: 1'b0 ; */ 2902 /*description: cocpu clk force on*/ 2903 #define RTC_CNTL_COCPU_CLK_FO (BIT(0)) 2904 #define RTC_CNTL_COCPU_CLK_FO_M (BIT(0)) 2905 #define RTC_CNTL_COCPU_CLK_FO_V 0x1 2906 #define RTC_CNTL_COCPU_CLK_FO_S 0 2907 2908 #define RTC_CNTL_TOUCH_CTRL1_REG (DR_REG_RTCCNTL_BASE + 0x0104) 2909 /* RTC_CNTL_TOUCH_MEAS_NUM : R/W ;bitpos:[31:16] ;default: 16'h1000 ; */ 2910 /*description: the meas length (in 8MHz)*/ 2911 #define RTC_CNTL_TOUCH_MEAS_NUM 0x0000FFFF 2912 #define RTC_CNTL_TOUCH_MEAS_NUM_M ((RTC_CNTL_TOUCH_MEAS_NUM_V)<<(RTC_CNTL_TOUCH_MEAS_NUM_S)) 2913 #define RTC_CNTL_TOUCH_MEAS_NUM_V 0xFFFF 2914 #define RTC_CNTL_TOUCH_MEAS_NUM_S 16 2915 /* RTC_CNTL_TOUCH_SLEEP_CYCLES : R/W ;bitpos:[15:0] ;default: 16'h100 ; */ 2916 /*description: sleep cycles for timer*/ 2917 #define RTC_CNTL_TOUCH_SLEEP_CYCLES 0x0000FFFF 2918 #define RTC_CNTL_TOUCH_SLEEP_CYCLES_M ((RTC_CNTL_TOUCH_SLEEP_CYCLES_V)<<(RTC_CNTL_TOUCH_SLEEP_CYCLES_S)) 2919 #define RTC_CNTL_TOUCH_SLEEP_CYCLES_V 0xFFFF 2920 #define RTC_CNTL_TOUCH_SLEEP_CYCLES_S 0 2921 2922 #define RTC_CNTL_TOUCH_CTRL2_REG (DR_REG_RTCCNTL_BASE + 0x0108) 2923 /* RTC_CNTL_TOUCH_CLKGATE_EN : R/W ;bitpos:[31] ;default: 1'b0 ; */ 2924 /*description: touch clock enable*/ 2925 #define RTC_CNTL_TOUCH_CLKGATE_EN (BIT(31)) 2926 #define RTC_CNTL_TOUCH_CLKGATE_EN_M (BIT(31)) 2927 #define RTC_CNTL_TOUCH_CLKGATE_EN_V 0x1 2928 #define RTC_CNTL_TOUCH_CLKGATE_EN_S 31 2929 /* RTC_CNTL_TOUCH_CLK_FO : R/W ;bitpos:[30] ;default: 1'b0 ; */ 2930 /*description: touch clock force on*/ 2931 #define RTC_CNTL_TOUCH_CLK_FO (BIT(30)) 2932 #define RTC_CNTL_TOUCH_CLK_FO_M (BIT(30)) 2933 #define RTC_CNTL_TOUCH_CLK_FO_V 0x1 2934 #define RTC_CNTL_TOUCH_CLK_FO_S 30 2935 /* RTC_CNTL_TOUCH_RESET : R/W ;bitpos:[29] ;default: 1'b0 ; */ 2936 /*description: reset upgrade touch*/ 2937 #define RTC_CNTL_TOUCH_RESET (BIT(29)) 2938 #define RTC_CNTL_TOUCH_RESET_M (BIT(29)) 2939 #define RTC_CNTL_TOUCH_RESET_V 0x1 2940 #define RTC_CNTL_TOUCH_RESET_S 29 2941 /* RTC_CNTL_TOUCH_TIMER_FORCE_DONE : R/W ;bitpos:[28:27] ;default: 2'b0 ; */ 2942 /*description: force touch timer done*/ 2943 #define RTC_CNTL_TOUCH_TIMER_FORCE_DONE 0x00000003 2944 #define RTC_CNTL_TOUCH_TIMER_FORCE_DONE_M ((RTC_CNTL_TOUCH_TIMER_FORCE_DONE_V)<<(RTC_CNTL_TOUCH_TIMER_FORCE_DONE_S)) 2945 #define RTC_CNTL_TOUCH_TIMER_FORCE_DONE_V 0x3 2946 #define RTC_CNTL_TOUCH_TIMER_FORCE_DONE_S 27 2947 /* RTC_CNTL_TOUCH_SLP_CYC_DIV : R/W ;bitpos:[26:25] ;default: 2'd0 ; */ 2948 /*description: when a touch pad is active sleep cycle could be divided by this number*/ 2949 #define RTC_CNTL_TOUCH_SLP_CYC_DIV 0x00000003 2950 #define RTC_CNTL_TOUCH_SLP_CYC_DIV_M ((RTC_CNTL_TOUCH_SLP_CYC_DIV_V)<<(RTC_CNTL_TOUCH_SLP_CYC_DIV_S)) 2951 #define RTC_CNTL_TOUCH_SLP_CYC_DIV_V 0x3 2952 #define RTC_CNTL_TOUCH_SLP_CYC_DIV_S 25 2953 /* RTC_CNTL_TOUCH_XPD_WAIT : R/W ;bitpos:[24:17] ;default: 8'h4 ; */ 2954 /*description: the waiting cycles (in 8MHz) between TOUCH_START and TOUCH_XPD*/ 2955 #define RTC_CNTL_TOUCH_XPD_WAIT 0x000000FF 2956 #define RTC_CNTL_TOUCH_XPD_WAIT_M ((RTC_CNTL_TOUCH_XPD_WAIT_V)<<(RTC_CNTL_TOUCH_XPD_WAIT_S)) 2957 #define RTC_CNTL_TOUCH_XPD_WAIT_V 0xFF 2958 #define RTC_CNTL_TOUCH_XPD_WAIT_S 17 2959 /* RTC_CNTL_TOUCH_START_FORCE : R/W ;bitpos:[16] ;default: 1'b0 ; */ 2960 /*description: 1: to start touch fsm by SW*/ 2961 #define RTC_CNTL_TOUCH_START_FORCE (BIT(16)) 2962 #define RTC_CNTL_TOUCH_START_FORCE_M (BIT(16)) 2963 #define RTC_CNTL_TOUCH_START_FORCE_V 0x1 2964 #define RTC_CNTL_TOUCH_START_FORCE_S 16 2965 /* RTC_CNTL_TOUCH_START_EN : R/W ;bitpos:[15] ;default: 1'b0 ; */ 2966 /*description: 1: start touch fsm*/ 2967 #define RTC_CNTL_TOUCH_START_EN (BIT(15)) 2968 #define RTC_CNTL_TOUCH_START_EN_M (BIT(15)) 2969 #define RTC_CNTL_TOUCH_START_EN_V 0x1 2970 #define RTC_CNTL_TOUCH_START_EN_S 15 2971 /* RTC_CNTL_TOUCH_START_FSM_EN : R/W ;bitpos:[14] ;default: 1'b1 ; */ 2972 /*description: 1: TOUCH_START & TOUCH_XPD is controlled by touch fsm*/ 2973 #define RTC_CNTL_TOUCH_START_FSM_EN (BIT(14)) 2974 #define RTC_CNTL_TOUCH_START_FSM_EN_M (BIT(14)) 2975 #define RTC_CNTL_TOUCH_START_FSM_EN_V 0x1 2976 #define RTC_CNTL_TOUCH_START_FSM_EN_S 14 2977 /* RTC_CNTL_TOUCH_SLP_TIMER_EN : R/W ;bitpos:[13] ;default: 1'd0 ; */ 2978 /*description: touch timer enable bit*/ 2979 #define RTC_CNTL_TOUCH_SLP_TIMER_EN (BIT(13)) 2980 #define RTC_CNTL_TOUCH_SLP_TIMER_EN_M (BIT(13)) 2981 #define RTC_CNTL_TOUCH_SLP_TIMER_EN_V 0x1 2982 #define RTC_CNTL_TOUCH_SLP_TIMER_EN_S 13 2983 /* RTC_CNTL_TOUCH_DBIAS : R/W ;bitpos:[12] ;default: 1'b0 ; */ 2984 /*description: 1:use self bias 0:use bandgap bias*/ 2985 #define RTC_CNTL_TOUCH_DBIAS (BIT(12)) 2986 #define RTC_CNTL_TOUCH_DBIAS_M (BIT(12)) 2987 #define RTC_CNTL_TOUCH_DBIAS_V 0x1 2988 #define RTC_CNTL_TOUCH_DBIAS_S 12 2989 /* RTC_CNTL_TOUCH_REFC : R/W ;bitpos:[11:9] ;default: 3'h0 ; */ 2990 /*description: TOUCH pad0 reference cap*/ 2991 #define RTC_CNTL_TOUCH_REFC 0x00000007 2992 #define RTC_CNTL_TOUCH_REFC_M ((RTC_CNTL_TOUCH_REFC_V)<<(RTC_CNTL_TOUCH_REFC_S)) 2993 #define RTC_CNTL_TOUCH_REFC_V 0x7 2994 #define RTC_CNTL_TOUCH_REFC_S 9 2995 /* RTC_CNTL_TOUCH_XPD_BIAS : R/W ;bitpos:[8] ;default: 1'd0 ; */ 2996 /*description: TOUCH_XPD_BIAS*/ 2997 #define RTC_CNTL_TOUCH_XPD_BIAS (BIT(8)) 2998 #define RTC_CNTL_TOUCH_XPD_BIAS_M (BIT(8)) 2999 #define RTC_CNTL_TOUCH_XPD_BIAS_V 0x1 3000 #define RTC_CNTL_TOUCH_XPD_BIAS_S 8 3001 /* RTC_CNTL_TOUCH_DREFH : R/W ;bitpos:[7:6] ;default: 2'b11 ; */ 3002 /*description: TOUCH_DREFH*/ 3003 #define RTC_CNTL_TOUCH_DREFH 0x00000003 3004 #define RTC_CNTL_TOUCH_DREFH_M ((RTC_CNTL_TOUCH_DREFH_V)<<(RTC_CNTL_TOUCH_DREFH_S)) 3005 #define RTC_CNTL_TOUCH_DREFH_V 0x3 3006 #define RTC_CNTL_TOUCH_DREFH_S 6 3007 /* RTC_CNTL_TOUCH_DREFL : R/W ;bitpos:[5:4] ;default: 2'b00 ; */ 3008 /*description: TOUCH_DREFL*/ 3009 #define RTC_CNTL_TOUCH_DREFL 0x00000003 3010 #define RTC_CNTL_TOUCH_DREFL_M ((RTC_CNTL_TOUCH_DREFL_V)<<(RTC_CNTL_TOUCH_DREFL_S)) 3011 #define RTC_CNTL_TOUCH_DREFL_V 0x3 3012 #define RTC_CNTL_TOUCH_DREFL_S 4 3013 /* RTC_CNTL_TOUCH_DRANGE : R/W ;bitpos:[3:2] ;default: 2'b11 ; */ 3014 /*description: TOUCH_DRANGE*/ 3015 #define RTC_CNTL_TOUCH_DRANGE 0x00000003 3016 #define RTC_CNTL_TOUCH_DRANGE_M ((RTC_CNTL_TOUCH_DRANGE_V)<<(RTC_CNTL_TOUCH_DRANGE_S)) 3017 #define RTC_CNTL_TOUCH_DRANGE_V 0x3 3018 #define RTC_CNTL_TOUCH_DRANGE_S 2 3019 3020 #define RTC_CNTL_TOUCH_SCAN_CTRL_REG (DR_REG_RTCCNTL_BASE + 0x010C) 3021 /* RTC_CNTL_TOUCH_OUT_RING : R/W ;bitpos:[31:28] ;default: 4'hf ; */ 3022 /*description: select out ring pad*/ 3023 #define RTC_CNTL_TOUCH_OUT_RING 0x0000000F 3024 #define RTC_CNTL_TOUCH_OUT_RING_M ((RTC_CNTL_TOUCH_OUT_RING_V)<<(RTC_CNTL_TOUCH_OUT_RING_S)) 3025 #define RTC_CNTL_TOUCH_OUT_RING_V 0xF 3026 #define RTC_CNTL_TOUCH_OUT_RING_S 28 3027 /* RTC_CNTL_TOUCH_BUFDRV : R/W ;bitpos:[27:25] ;default: 3'h0 ; */ 3028 /*description: touch7 buffer driver strength*/ 3029 #define RTC_CNTL_TOUCH_BUFDRV 0x00000007 3030 #define RTC_CNTL_TOUCH_BUFDRV_M ((RTC_CNTL_TOUCH_BUFDRV_V)<<(RTC_CNTL_TOUCH_BUFDRV_S)) 3031 #define RTC_CNTL_TOUCH_BUFDRV_V 0x7 3032 #define RTC_CNTL_TOUCH_BUFDRV_S 25 3033 /* RTC_CNTL_TOUCH_SCAN_PAD_MAP : R/W ;bitpos:[24:10] ;default: 15'h0 ; */ 3034 /*description: touch scan mode pad enable map*/ 3035 #define RTC_CNTL_TOUCH_SCAN_PAD_MAP 0x00007FFF 3036 #define RTC_CNTL_TOUCH_SCAN_PAD_MAP_M ((RTC_CNTL_TOUCH_SCAN_PAD_MAP_V)<<(RTC_CNTL_TOUCH_SCAN_PAD_MAP_S)) 3037 #define RTC_CNTL_TOUCH_SCAN_PAD_MAP_V 0x7FFF 3038 #define RTC_CNTL_TOUCH_SCAN_PAD_MAP_S 10 3039 /* RTC_CNTL_TOUCH_SHIELD_PAD_EN : R/W ;bitpos:[9] ;default: 1'b0 ; */ 3040 /*description: touch pad14 will be used as shield*/ 3041 #define RTC_CNTL_TOUCH_SHIELD_PAD_EN (BIT(9)) 3042 #define RTC_CNTL_TOUCH_SHIELD_PAD_EN_M (BIT(9)) 3043 #define RTC_CNTL_TOUCH_SHIELD_PAD_EN_V 0x1 3044 #define RTC_CNTL_TOUCH_SHIELD_PAD_EN_S 9 3045 /* RTC_CNTL_TOUCH_INACTIVE_CONNECTION : R/W ;bitpos:[8] ;default: 1'b1 ; */ 3046 /*description: inactive touch pads connect to 1: gnd 0: HighZ*/ 3047 #define RTC_CNTL_TOUCH_INACTIVE_CONNECTION (BIT(8)) 3048 #define RTC_CNTL_TOUCH_INACTIVE_CONNECTION_M (BIT(8)) 3049 #define RTC_CNTL_TOUCH_INACTIVE_CONNECTION_V 0x1 3050 #define RTC_CNTL_TOUCH_INACTIVE_CONNECTION_S 8 3051 /* RTC_CNTL_TOUCH_DENOISE_EN : R/W ;bitpos:[2] ;default: 1'b0 ; */ 3052 /*description: touch pad0 will be used to de-noise*/ 3053 #define RTC_CNTL_TOUCH_DENOISE_EN (BIT(2)) 3054 #define RTC_CNTL_TOUCH_DENOISE_EN_M (BIT(2)) 3055 #define RTC_CNTL_TOUCH_DENOISE_EN_V 0x1 3056 #define RTC_CNTL_TOUCH_DENOISE_EN_S 2 3057 /* RTC_CNTL_TOUCH_DENOISE_RES : R/W ;bitpos:[1:0] ;default: 2'd2 ; */ 3058 /*description: De-noise resolution: 12/10/8/4 bit*/ 3059 #define RTC_CNTL_TOUCH_DENOISE_RES 0x00000003 3060 #define RTC_CNTL_TOUCH_DENOISE_RES_M ((RTC_CNTL_TOUCH_DENOISE_RES_V)<<(RTC_CNTL_TOUCH_DENOISE_RES_S)) 3061 #define RTC_CNTL_TOUCH_DENOISE_RES_V 0x3 3062 #define RTC_CNTL_TOUCH_DENOISE_RES_S 0 3063 3064 #define RTC_CNTL_TOUCH_SLP_THRES_REG (DR_REG_RTCCNTL_BASE + 0x0110) 3065 /* RTC_CNTL_TOUCH_SLP_PAD : R/W ;bitpos:[31:27] ;default: 4'hF ; */ 3066 /*description: */ 3067 #define RTC_CNTL_TOUCH_SLP_PAD 0x0000001F 3068 #define RTC_CNTL_TOUCH_SLP_PAD_M ((RTC_CNTL_TOUCH_SLP_PAD_V)<<(RTC_CNTL_TOUCH_SLP_PAD_S)) 3069 #define RTC_CNTL_TOUCH_SLP_PAD_V 0x1F 3070 #define RTC_CNTL_TOUCH_SLP_PAD_S 27 3071 /* RTC_CNTL_TOUCH_SLP_APPROACH_EN : R/W ;bitpos:[26] ;default: 1'b0 ; */ 3072 /*description: sleep pad approach function enable*/ 3073 #define RTC_CNTL_TOUCH_SLP_APPROACH_EN (BIT(26)) 3074 #define RTC_CNTL_TOUCH_SLP_APPROACH_EN_M (BIT(26)) 3075 #define RTC_CNTL_TOUCH_SLP_APPROACH_EN_V 0x1 3076 #define RTC_CNTL_TOUCH_SLP_APPROACH_EN_S 26 3077 /* RTC_CNTL_TOUCH_SLP_TH : R/W ;bitpos:[21:0] ;default: 22'h0 ; */ 3078 /*description: the threshold for sleep touch pad*/ 3079 #define RTC_CNTL_TOUCH_SLP_TH 0x003FFFFF 3080 #define RTC_CNTL_TOUCH_SLP_TH_M ((RTC_CNTL_TOUCH_SLP_TH_V)<<(RTC_CNTL_TOUCH_SLP_TH_S)) 3081 #define RTC_CNTL_TOUCH_SLP_TH_V 0x3FFFFF 3082 #define RTC_CNTL_TOUCH_SLP_TH_S 0 3083 3084 #define RTC_CNTL_TOUCH_APPROACH_REG (DR_REG_RTCCNTL_BASE + 0x0114) 3085 /* RTC_CNTL_TOUCH_APPROACH_MEAS_TIME : R/W ;bitpos:[31:24] ;default: 8'd80 ; */ 3086 /*description: approach pads total meas times*/ 3087 #define RTC_CNTL_TOUCH_APPROACH_MEAS_TIME 0x000000FF 3088 #define RTC_CNTL_TOUCH_APPROACH_MEAS_TIME_M ((RTC_CNTL_TOUCH_APPROACH_MEAS_TIME_V)<<(RTC_CNTL_TOUCH_APPROACH_MEAS_TIME_S)) 3089 #define RTC_CNTL_TOUCH_APPROACH_MEAS_TIME_V 0xFF 3090 #define RTC_CNTL_TOUCH_APPROACH_MEAS_TIME_S 24 3091 /* RTC_CNTL_TOUCH_SLP_CHANNEL_CLR : WO ;bitpos:[23] ;default: 1'd0 ; */ 3092 /*description: clear touch slp channel*/ 3093 #define RTC_CNTL_TOUCH_SLP_CHANNEL_CLR (BIT(23)) 3094 #define RTC_CNTL_TOUCH_SLP_CHANNEL_CLR_M (BIT(23)) 3095 #define RTC_CNTL_TOUCH_SLP_CHANNEL_CLR_V 0x1 3096 #define RTC_CNTL_TOUCH_SLP_CHANNEL_CLR_S 23 3097 3098 #define RTC_CNTL_TOUCH_FILTER_CTRL_REG (DR_REG_RTCCNTL_BASE + 0x0118) 3099 /* RTC_CNTL_TOUCH_FILTER_EN : R/W ;bitpos:[31] ;default: 1'b1 ; */ 3100 /*description: touch filter enable*/ 3101 #define RTC_CNTL_TOUCH_FILTER_EN (BIT(31)) 3102 #define RTC_CNTL_TOUCH_FILTER_EN_M (BIT(31)) 3103 #define RTC_CNTL_TOUCH_FILTER_EN_V 0x1 3104 #define RTC_CNTL_TOUCH_FILTER_EN_S 31 3105 /* RTC_CNTL_TOUCH_FILTER_MODE : R/W ;bitpos:[30:28] ;default: 3'd1 ; */ 3106 /*description: 0: IIR ? 1: IIR ? 2: IIR 1/8 3: Jitter*/ 3107 #define RTC_CNTL_TOUCH_FILTER_MODE 0x00000007 3108 #define RTC_CNTL_TOUCH_FILTER_MODE_M ((RTC_CNTL_TOUCH_FILTER_MODE_V)<<(RTC_CNTL_TOUCH_FILTER_MODE_S)) 3109 #define RTC_CNTL_TOUCH_FILTER_MODE_V 0x7 3110 #define RTC_CNTL_TOUCH_FILTER_MODE_S 28 3111 /* RTC_CNTL_TOUCH_DEBOUNCE : R/W ;bitpos:[27:25] ;default: 3'd3 ; */ 3112 /*description: debounce counter*/ 3113 #define RTC_CNTL_TOUCH_DEBOUNCE 0x00000007 3114 #define RTC_CNTL_TOUCH_DEBOUNCE_M ((RTC_CNTL_TOUCH_DEBOUNCE_V)<<(RTC_CNTL_TOUCH_DEBOUNCE_S)) 3115 #define RTC_CNTL_TOUCH_DEBOUNCE_V 0x7 3116 #define RTC_CNTL_TOUCH_DEBOUNCE_S 25 3117 /* RTC_CNTL_TOUCH_CONFIG3 : R/W ;bitpos:[24:23] ;default: 2'd1 ; */ 3118 /*description: */ 3119 #define RTC_CNTL_TOUCH_CONFIG3 0x00000003 3120 #define RTC_CNTL_TOUCH_CONFIG3_M ((RTC_CNTL_TOUCH_CONFIG3_V)<<(RTC_CNTL_TOUCH_CONFIG3_S)) 3121 #define RTC_CNTL_TOUCH_CONFIG3_V 0x3 3122 #define RTC_CNTL_TOUCH_CONFIG3_S 23 3123 /* RTC_CNTL_TOUCH_NOISE_THRES : R/W ;bitpos:[22:21] ;default: 2'd1 ; */ 3124 /*description: */ 3125 #define RTC_CNTL_TOUCH_NOISE_THRES 0x00000003 3126 #define RTC_CNTL_TOUCH_NOISE_THRES_M ((RTC_CNTL_TOUCH_NOISE_THRES_V)<<(RTC_CNTL_TOUCH_NOISE_THRES_S)) 3127 #define RTC_CNTL_TOUCH_NOISE_THRES_V 0x3 3128 #define RTC_CNTL_TOUCH_NOISE_THRES_S 21 3129 /* RTC_CNTL_TOUCH_CONFIG2 : R/W ;bitpos:[20:19] ;default: 2'd1 ; */ 3130 /*description: */ 3131 #define RTC_CNTL_TOUCH_CONFIG2 0x00000003 3132 #define RTC_CNTL_TOUCH_CONFIG2_M ((RTC_CNTL_TOUCH_CONFIG2_V)<<(RTC_CNTL_TOUCH_CONFIG2_S)) 3133 #define RTC_CNTL_TOUCH_CONFIG2_V 0x3 3134 #define RTC_CNTL_TOUCH_CONFIG2_S 19 3135 /* RTC_CNTL_TOUCH_CONFIG1 : R/W ;bitpos:[18:15] ;default: 4'd5 ; */ 3136 /*description: */ 3137 #define RTC_CNTL_TOUCH_CONFIG1 0x0000000F 3138 #define RTC_CNTL_TOUCH_CONFIG1_M ((RTC_CNTL_TOUCH_CONFIG1_V)<<(RTC_CNTL_TOUCH_CONFIG1_S)) 3139 #define RTC_CNTL_TOUCH_CONFIG1_V 0xF 3140 #define RTC_CNTL_TOUCH_CONFIG1_S 15 3141 /* RTC_CNTL_TOUCH_JITTER_STEP : R/W ;bitpos:[14:11] ;default: 4'd1 ; */ 3142 /*description: touch jitter step*/ 3143 #define RTC_CNTL_TOUCH_JITTER_STEP 0x0000000F 3144 #define RTC_CNTL_TOUCH_JITTER_STEP_M ((RTC_CNTL_TOUCH_JITTER_STEP_V)<<(RTC_CNTL_TOUCH_JITTER_STEP_S)) 3145 #define RTC_CNTL_TOUCH_JITTER_STEP_V 0xF 3146 #define RTC_CNTL_TOUCH_JITTER_STEP_S 11 3147 /* RTC_CNTL_TOUCH_SMOOTH_LVL : R/W ;bitpos:[10:9] ;default: 2'd0 ; */ 3148 /*description: */ 3149 #define RTC_CNTL_TOUCH_SMOOTH_LVL 0x00000003 3150 #define RTC_CNTL_TOUCH_SMOOTH_LVL_M ((RTC_CNTL_TOUCH_SMOOTH_LVL_V)<<(RTC_CNTL_TOUCH_SMOOTH_LVL_S)) 3151 #define RTC_CNTL_TOUCH_SMOOTH_LVL_V 0x3 3152 #define RTC_CNTL_TOUCH_SMOOTH_LVL_S 9 3153 3154 #define RTC_CNTL_USB_CONF_REG (DR_REG_RTCCNTL_BASE + 0x011C) 3155 /* RTC_CNTL_IO_MUX_RESET_DISABLE : R/W ;bitpos:[18] ;default: 1'd0 ; */ 3156 /*description: */ 3157 #define RTC_CNTL_IO_MUX_RESET_DISABLE (BIT(18)) 3158 #define RTC_CNTL_IO_MUX_RESET_DISABLE_M (BIT(18)) 3159 #define RTC_CNTL_IO_MUX_RESET_DISABLE_V 0x1 3160 #define RTC_CNTL_IO_MUX_RESET_DISABLE_S 18 3161 /* RTC_CNTL_USB_RESET_DISABLE : R/W ;bitpos:[17] ;default: 1'd0 ; */ 3162 /*description: */ 3163 #define RTC_CNTL_USB_RESET_DISABLE (BIT(17)) 3164 #define RTC_CNTL_USB_RESET_DISABLE_M (BIT(17)) 3165 #define RTC_CNTL_USB_RESET_DISABLE_V 0x1 3166 #define RTC_CNTL_USB_RESET_DISABLE_S 17 3167 /* RTC_CNTL_USB_TX_EN_OVERRIDE : R/W ;bitpos:[16] ;default: 1'd0 ; */ 3168 /*description: */ 3169 #define RTC_CNTL_USB_TX_EN_OVERRIDE (BIT(16)) 3170 #define RTC_CNTL_USB_TX_EN_OVERRIDE_M (BIT(16)) 3171 #define RTC_CNTL_USB_TX_EN_OVERRIDE_V 0x1 3172 #define RTC_CNTL_USB_TX_EN_OVERRIDE_S 16 3173 /* RTC_CNTL_USB_TX_EN : R/W ;bitpos:[15] ;default: 1'd0 ; */ 3174 /*description: */ 3175 #define RTC_CNTL_USB_TX_EN (BIT(15)) 3176 #define RTC_CNTL_USB_TX_EN_M (BIT(15)) 3177 #define RTC_CNTL_USB_TX_EN_V 0x1 3178 #define RTC_CNTL_USB_TX_EN_S 15 3179 /* RTC_CNTL_USB_TXP : R/W ;bitpos:[14] ;default: 1'd0 ; */ 3180 /*description: */ 3181 #define RTC_CNTL_USB_TXP (BIT(14)) 3182 #define RTC_CNTL_USB_TXP_M (BIT(14)) 3183 #define RTC_CNTL_USB_TXP_V 0x1 3184 #define RTC_CNTL_USB_TXP_S 14 3185 /* RTC_CNTL_USB_TXM : R/W ;bitpos:[13] ;default: 1'd0 ; */ 3186 /*description: */ 3187 #define RTC_CNTL_USB_TXM (BIT(13)) 3188 #define RTC_CNTL_USB_TXM_M (BIT(13)) 3189 #define RTC_CNTL_USB_TXM_V 0x1 3190 #define RTC_CNTL_USB_TXM_S 13 3191 /* RTC_CNTL_USB_PAD_ENABLE : R/W ;bitpos:[12] ;default: 1'd0 ; */ 3192 /*description: */ 3193 #define RTC_CNTL_USB_PAD_ENABLE (BIT(12)) 3194 #define RTC_CNTL_USB_PAD_ENABLE_M (BIT(12)) 3195 #define RTC_CNTL_USB_PAD_ENABLE_V 0x1 3196 #define RTC_CNTL_USB_PAD_ENABLE_S 12 3197 /* RTC_CNTL_USB_PAD_ENABLE_OVERRIDE : R/W ;bitpos:[11] ;default: 1'd0 ; */ 3198 /*description: */ 3199 #define RTC_CNTL_USB_PAD_ENABLE_OVERRIDE (BIT(11)) 3200 #define RTC_CNTL_USB_PAD_ENABLE_OVERRIDE_M (BIT(11)) 3201 #define RTC_CNTL_USB_PAD_ENABLE_OVERRIDE_V 0x1 3202 #define RTC_CNTL_USB_PAD_ENABLE_OVERRIDE_S 11 3203 /* RTC_CNTL_USB_PULLUP_VALUE : R/W ;bitpos:[10] ;default: 1'd0 ; */ 3204 /*description: */ 3205 #define RTC_CNTL_USB_PULLUP_VALUE (BIT(10)) 3206 #define RTC_CNTL_USB_PULLUP_VALUE_M (BIT(10)) 3207 #define RTC_CNTL_USB_PULLUP_VALUE_V 0x1 3208 #define RTC_CNTL_USB_PULLUP_VALUE_S 10 3209 /* RTC_CNTL_USB_DM_PULLDOWN : R/W ;bitpos:[9] ;default: 1'd0 ; */ 3210 /*description: */ 3211 #define RTC_CNTL_USB_DM_PULLDOWN (BIT(9)) 3212 #define RTC_CNTL_USB_DM_PULLDOWN_M (BIT(9)) 3213 #define RTC_CNTL_USB_DM_PULLDOWN_V 0x1 3214 #define RTC_CNTL_USB_DM_PULLDOWN_S 9 3215 /* RTC_CNTL_USB_DM_PULLUP : R/W ;bitpos:[8] ;default: 1'd0 ; */ 3216 /*description: */ 3217 #define RTC_CNTL_USB_DM_PULLUP (BIT(8)) 3218 #define RTC_CNTL_USB_DM_PULLUP_M (BIT(8)) 3219 #define RTC_CNTL_USB_DM_PULLUP_V 0x1 3220 #define RTC_CNTL_USB_DM_PULLUP_S 8 3221 /* RTC_CNTL_USB_DP_PULLDOWN : R/W ;bitpos:[7] ;default: 1'd0 ; */ 3222 /*description: */ 3223 #define RTC_CNTL_USB_DP_PULLDOWN (BIT(7)) 3224 #define RTC_CNTL_USB_DP_PULLDOWN_M (BIT(7)) 3225 #define RTC_CNTL_USB_DP_PULLDOWN_V 0x1 3226 #define RTC_CNTL_USB_DP_PULLDOWN_S 7 3227 /* RTC_CNTL_USB_DP_PULLUP : R/W ;bitpos:[6] ;default: 1'd0 ; */ 3228 /*description: */ 3229 #define RTC_CNTL_USB_DP_PULLUP (BIT(6)) 3230 #define RTC_CNTL_USB_DP_PULLUP_M (BIT(6)) 3231 #define RTC_CNTL_USB_DP_PULLUP_V 0x1 3232 #define RTC_CNTL_USB_DP_PULLUP_S 6 3233 /* RTC_CNTL_USB_PAD_PULL_OVERRIDE : R/W ;bitpos:[5] ;default: 1'd0 ; */ 3234 /*description: */ 3235 #define RTC_CNTL_USB_PAD_PULL_OVERRIDE (BIT(5)) 3236 #define RTC_CNTL_USB_PAD_PULL_OVERRIDE_M (BIT(5)) 3237 #define RTC_CNTL_USB_PAD_PULL_OVERRIDE_V 0x1 3238 #define RTC_CNTL_USB_PAD_PULL_OVERRIDE_S 5 3239 /* RTC_CNTL_USB_VREF_OVERRIDE : R/W ;bitpos:[4] ;default: 1'd0 ; */ 3240 /*description: */ 3241 #define RTC_CNTL_USB_VREF_OVERRIDE (BIT(4)) 3242 #define RTC_CNTL_USB_VREF_OVERRIDE_M (BIT(4)) 3243 #define RTC_CNTL_USB_VREF_OVERRIDE_V 0x1 3244 #define RTC_CNTL_USB_VREF_OVERRIDE_S 4 3245 /* RTC_CNTL_USB_VREFL : R/W ;bitpos:[3:2] ;default: 2'd0 ; */ 3246 /*description: */ 3247 #define RTC_CNTL_USB_VREFL 0x00000003 3248 #define RTC_CNTL_USB_VREFL_M ((RTC_CNTL_USB_VREFL_V)<<(RTC_CNTL_USB_VREFL_S)) 3249 #define RTC_CNTL_USB_VREFL_V 0x3 3250 #define RTC_CNTL_USB_VREFL_S 2 3251 /* RTC_CNTL_USB_VREFH : R/W ;bitpos:[1:0] ;default: 2'd0 ; */ 3252 /*description: */ 3253 #define RTC_CNTL_USB_VREFH 0x00000003 3254 #define RTC_CNTL_USB_VREFH_M ((RTC_CNTL_USB_VREFH_V)<<(RTC_CNTL_USB_VREFH_S)) 3255 #define RTC_CNTL_USB_VREFH_V 0x3 3256 #define RTC_CNTL_USB_VREFH_S 0 3257 3258 #define RTC_CNTL_TOUCH_TIMEOUT_CTRL_REG (DR_REG_RTCCNTL_BASE + 0x0120) 3259 /* RTC_CNTL_TOUCH_TIMEOUT_EN : R/W ;bitpos:[22] ;default: 1'b1 ; */ 3260 /*description: */ 3261 #define RTC_CNTL_TOUCH_TIMEOUT_EN (BIT(22)) 3262 #define RTC_CNTL_TOUCH_TIMEOUT_EN_M (BIT(22)) 3263 #define RTC_CNTL_TOUCH_TIMEOUT_EN_V 0x1 3264 #define RTC_CNTL_TOUCH_TIMEOUT_EN_S 22 3265 /* RTC_CNTL_TOUCH_TIMEOUT_NUM : R/W ;bitpos:[21:0] ;default: 22'h3fffff ; */ 3266 /*description: */ 3267 #define RTC_CNTL_TOUCH_TIMEOUT_NUM 0x003FFFFF 3268 #define RTC_CNTL_TOUCH_TIMEOUT_NUM_M ((RTC_CNTL_TOUCH_TIMEOUT_NUM_V)<<(RTC_CNTL_TOUCH_TIMEOUT_NUM_S)) 3269 #define RTC_CNTL_TOUCH_TIMEOUT_NUM_V 0x3FFFFF 3270 #define RTC_CNTL_TOUCH_TIMEOUT_NUM_S 0 3271 3272 #define RTC_CNTL_SLP_REJECT_CAUSE_REG (DR_REG_RTCCNTL_BASE + 0x0124) 3273 /* RTC_CNTL_REJECT_CAUSE : RO ;bitpos:[16:0] ;default: 17'd0 ; */ 3274 /*description: sleep reject cause*/ 3275 #define RTC_CNTL_REJECT_CAUSE 0x0001FFFF 3276 #define RTC_CNTL_REJECT_CAUSE_M ((RTC_CNTL_REJECT_CAUSE_V)<<(RTC_CNTL_REJECT_CAUSE_S)) 3277 #define RTC_CNTL_REJECT_CAUSE_V 0x1FFFF 3278 #define RTC_CNTL_REJECT_CAUSE_S 0 3279 3280 #define RTC_CNTL_OPTION1_REG (DR_REG_RTCCNTL_BASE + 0x0128) 3281 /* RTC_CNTL_FORCE_DOWNLOAD_BOOT : R/W ;bitpos:[0] ;default: 1'd0 ; */ 3282 /*description: */ 3283 #define RTC_CNTL_FORCE_DOWNLOAD_BOOT (BIT(0)) 3284 #define RTC_CNTL_FORCE_DOWNLOAD_BOOT_M (BIT(0)) 3285 #define RTC_CNTL_FORCE_DOWNLOAD_BOOT_V 0x1 3286 #define RTC_CNTL_FORCE_DOWNLOAD_BOOT_S 0 3287 3288 #define RTC_CNTL_SLP_WAKEUP_CAUSE_REG (DR_REG_RTCCNTL_BASE + 0x012C) 3289 /* RTC_CNTL_WAKEUP_CAUSE : RO ;bitpos:[16:0] ;default: 17'd0 ; */ 3290 /*description: sleep wakeup cause*/ 3291 #define RTC_CNTL_WAKEUP_CAUSE 0x0001FFFF 3292 #define RTC_CNTL_WAKEUP_CAUSE_M ((RTC_CNTL_WAKEUP_CAUSE_V)<<(RTC_CNTL_WAKEUP_CAUSE_S)) 3293 #define RTC_CNTL_WAKEUP_CAUSE_V 0x1FFFF 3294 #define RTC_CNTL_WAKEUP_CAUSE_S 0 3295 3296 #define RTC_CNTL_ULP_CP_TIMER_1_REG (DR_REG_RTCCNTL_BASE + 0x0130) 3297 /* RTC_CNTL_ULP_CP_TIMER_SLP_CYCLE : R/W ;bitpos:[31:8] ;default: 24'd200 ; */ 3298 /*description: sleep cycles for ULP-coprocessor timer*/ 3299 #define RTC_CNTL_ULP_CP_TIMER_SLP_CYCLE 0x00FFFFFF 3300 #define RTC_CNTL_ULP_CP_TIMER_SLP_CYCLE_M ((RTC_CNTL_ULP_CP_TIMER_SLP_CYCLE_V)<<(RTC_CNTL_ULP_CP_TIMER_SLP_CYCLE_S)) 3301 #define RTC_CNTL_ULP_CP_TIMER_SLP_CYCLE_V 0xFFFFFF 3302 #define RTC_CNTL_ULP_CP_TIMER_SLP_CYCLE_S 8 3303 3304 #define RTC_CNTL_DATE_REG (DR_REG_RTCCNTL_BASE + 0x0138) 3305 /* RTC_CNTL_CNTL_DATE : R/W ;bitpos:[27:0] ;default: 28'h1908130 ; */ 3306 /*description: */ 3307 #define RTC_CNTL_CNTL_DATE 0x0FFFFFFF 3308 #define RTC_CNTL_CNTL_DATE_M ((RTC_CNTL_CNTL_DATE_V)<<(RTC_CNTL_CNTL_DATE_S)) 3309 #define RTC_CNTL_CNTL_DATE_V 0xFFFFFFF 3310 #define RTC_CNTL_CNTL_DATE_S 0 3311 3312 #ifdef __cplusplus 3313 } 3314 #endif 3315 3316 3317 3318 #endif /*_SOC_RTC_CNTL_REG_H_ */ 3319
