1 /* 2 * SPDX-FileCopyrightText: 2015-2021 Espressif Systems (Shanghai) CO LTD 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7 #ifndef _SOC_RTC_CNTL_REG_H_ 8 #define _SOC_RTC_CNTL_REG_H_ 9 10 11 #include "soc.h" 12 #ifdef __cplusplus 13 extern "C" { 14 #endif 15 16 /* The value that needs to be written to RTC_CNTL_SWD_WPROTECT_REG to write-enable the wdt registers */ 17 #define RTC_CNTL_SWD_WKEY_VALUE 0x8F1D312A 18 19 #define RTC_CNTL_TIME0_REG RTC_CNTL_TIME_LOW0_REG 20 #define RTC_CNTL_TIME1_REG RTC_CNTL_TIME_HIGH0_REG 21 22 #define RTC_CNTL_OPTIONS0_REG (DR_REG_RTCCNTL_BASE + 0x0) 23 /* RTC_CNTL_SW_SYS_RST : WO ;bitpos:[31] ;default: 1'd0 ; */ 24 /*description: SW system reset.*/ 25 #define RTC_CNTL_SW_SYS_RST (BIT(31)) 26 #define RTC_CNTL_SW_SYS_RST_M (BIT(31)) 27 #define RTC_CNTL_SW_SYS_RST_V 0x1 28 #define RTC_CNTL_SW_SYS_RST_S 31 29 /* RTC_CNTL_DG_WRAP_FORCE_NORST : R/W ;bitpos:[30] ;default: 1'd0 ; */ 30 /*description: digital core force no reset in deep sleep.*/ 31 #define RTC_CNTL_DG_WRAP_FORCE_NORST (BIT(30)) 32 #define RTC_CNTL_DG_WRAP_FORCE_NORST_M (BIT(30)) 33 #define RTC_CNTL_DG_WRAP_FORCE_NORST_V 0x1 34 #define RTC_CNTL_DG_WRAP_FORCE_NORST_S 30 35 /* RTC_CNTL_DG_WRAP_FORCE_RST : R/W ;bitpos:[29] ;default: 1'd0 ; */ 36 /*description: digital wrap force reset in deep sleep.*/ 37 #define RTC_CNTL_DG_WRAP_FORCE_RST (BIT(29)) 38 #define RTC_CNTL_DG_WRAP_FORCE_RST_M (BIT(29)) 39 #define RTC_CNTL_DG_WRAP_FORCE_RST_V 0x1 40 #define RTC_CNTL_DG_WRAP_FORCE_RST_S 29 41 /* RTC_CNTL_ANALOG_FORCE_NOISO : R/W ;bitpos:[28] ;default: 1'd1 ; */ 42 /*description: .*/ 43 #define RTC_CNTL_ANALOG_FORCE_NOISO (BIT(28)) 44 #define RTC_CNTL_ANALOG_FORCE_NOISO_M (BIT(28)) 45 #define RTC_CNTL_ANALOG_FORCE_NOISO_V 0x1 46 #define RTC_CNTL_ANALOG_FORCE_NOISO_S 28 47 /* RTC_CNTL_PLL_FORCE_NOISO : R/W ;bitpos:[27] ;default: 1'd1 ; */ 48 /*description: .*/ 49 #define RTC_CNTL_PLL_FORCE_NOISO (BIT(27)) 50 #define RTC_CNTL_PLL_FORCE_NOISO_M (BIT(27)) 51 #define RTC_CNTL_PLL_FORCE_NOISO_V 0x1 52 #define RTC_CNTL_PLL_FORCE_NOISO_S 27 53 /* RTC_CNTL_XTL_FORCE_NOISO : R/W ;bitpos:[26] ;default: 1'd1 ; */ 54 /*description: .*/ 55 #define RTC_CNTL_XTL_FORCE_NOISO (BIT(26)) 56 #define RTC_CNTL_XTL_FORCE_NOISO_M (BIT(26)) 57 #define RTC_CNTL_XTL_FORCE_NOISO_V 0x1 58 #define RTC_CNTL_XTL_FORCE_NOISO_S 26 59 /* RTC_CNTL_ANALOG_FORCE_ISO : R/W ;bitpos:[25] ;default: 1'd0 ; */ 60 /*description: .*/ 61 #define RTC_CNTL_ANALOG_FORCE_ISO (BIT(25)) 62 #define RTC_CNTL_ANALOG_FORCE_ISO_M (BIT(25)) 63 #define RTC_CNTL_ANALOG_FORCE_ISO_V 0x1 64 #define RTC_CNTL_ANALOG_FORCE_ISO_S 25 65 /* RTC_CNTL_PLL_FORCE_ISO : R/W ;bitpos:[24] ;default: 1'd0 ; */ 66 /*description: .*/ 67 #define RTC_CNTL_PLL_FORCE_ISO (BIT(24)) 68 #define RTC_CNTL_PLL_FORCE_ISO_M (BIT(24)) 69 #define RTC_CNTL_PLL_FORCE_ISO_V 0x1 70 #define RTC_CNTL_PLL_FORCE_ISO_S 24 71 /* RTC_CNTL_XTL_FORCE_ISO : R/W ;bitpos:[23] ;default: 1'd0 ; */ 72 /*description: .*/ 73 #define RTC_CNTL_XTL_FORCE_ISO (BIT(23)) 74 #define RTC_CNTL_XTL_FORCE_ISO_M (BIT(23)) 75 #define RTC_CNTL_XTL_FORCE_ISO_V 0x1 76 #define RTC_CNTL_XTL_FORCE_ISO_S 23 77 /* RTC_CNTL_XTL_EN_WAIT : R/W ;bitpos:[17:14] ;default: 4'd2 ; */ 78 /*description: wait bias_sleep and current source wakeup.*/ 79 #define RTC_CNTL_XTL_EN_WAIT 0x0000000F 80 #define RTC_CNTL_XTL_EN_WAIT_M ((RTC_CNTL_XTL_EN_WAIT_V)<<(RTC_CNTL_XTL_EN_WAIT_S)) 81 #define RTC_CNTL_XTL_EN_WAIT_V 0xF 82 #define RTC_CNTL_XTL_EN_WAIT_S 14 83 /* RTC_CNTL_XTL_FORCE_PU : R/W ;bitpos:[13] ;default: 1'd1 ; */ 84 /*description: crystall force power up.*/ 85 #define RTC_CNTL_XTL_FORCE_PU (BIT(13)) 86 #define RTC_CNTL_XTL_FORCE_PU_M (BIT(13)) 87 #define RTC_CNTL_XTL_FORCE_PU_V 0x1 88 #define RTC_CNTL_XTL_FORCE_PU_S 13 89 /* RTC_CNTL_XTL_FORCE_PD : R/W ;bitpos:[12] ;default: 1'b0 ; */ 90 /*description: crystall force power down.*/ 91 #define RTC_CNTL_XTL_FORCE_PD (BIT(12)) 92 #define RTC_CNTL_XTL_FORCE_PD_M (BIT(12)) 93 #define RTC_CNTL_XTL_FORCE_PD_V 0x1 94 #define RTC_CNTL_XTL_FORCE_PD_S 12 95 /* RTC_CNTL_BBPLL_FORCE_PU : R/W ;bitpos:[11] ;default: 1'd0 ; */ 96 /*description: BB_PLL force power up.*/ 97 #define RTC_CNTL_BBPLL_FORCE_PU (BIT(11)) 98 #define RTC_CNTL_BBPLL_FORCE_PU_M (BIT(11)) 99 #define RTC_CNTL_BBPLL_FORCE_PU_V 0x1 100 #define RTC_CNTL_BBPLL_FORCE_PU_S 11 101 /* RTC_CNTL_BBPLL_FORCE_PD : R/W ;bitpos:[10] ;default: 1'b0 ; */ 102 /*description: BB_PLL force power down.*/ 103 #define RTC_CNTL_BBPLL_FORCE_PD (BIT(10)) 104 #define RTC_CNTL_BBPLL_FORCE_PD_M (BIT(10)) 105 #define RTC_CNTL_BBPLL_FORCE_PD_V 0x1 106 #define RTC_CNTL_BBPLL_FORCE_PD_S 10 107 /* RTC_CNTL_BBPLL_I2C_FORCE_PU : R/W ;bitpos:[9] ;default: 1'd0 ; */ 108 /*description: BB_PLL_I2C force power up.*/ 109 #define RTC_CNTL_BBPLL_I2C_FORCE_PU (BIT(9)) 110 #define RTC_CNTL_BBPLL_I2C_FORCE_PU_M (BIT(9)) 111 #define RTC_CNTL_BBPLL_I2C_FORCE_PU_V 0x1 112 #define RTC_CNTL_BBPLL_I2C_FORCE_PU_S 9 113 /* RTC_CNTL_BBPLL_I2C_FORCE_PD : R/W ;bitpos:[8] ;default: 1'b0 ; */ 114 /*description: BB_PLL _I2C force power down.*/ 115 #define RTC_CNTL_BBPLL_I2C_FORCE_PD (BIT(8)) 116 #define RTC_CNTL_BBPLL_I2C_FORCE_PD_M (BIT(8)) 117 #define RTC_CNTL_BBPLL_I2C_FORCE_PD_V 0x1 118 #define RTC_CNTL_BBPLL_I2C_FORCE_PD_S 8 119 /* RTC_CNTL_BB_I2C_FORCE_PU : R/W ;bitpos:[7] ;default: 1'd0 ; */ 120 /*description: BB_I2C force power up.*/ 121 #define RTC_CNTL_BB_I2C_FORCE_PU (BIT(7)) 122 #define RTC_CNTL_BB_I2C_FORCE_PU_M (BIT(7)) 123 #define RTC_CNTL_BB_I2C_FORCE_PU_V 0x1 124 #define RTC_CNTL_BB_I2C_FORCE_PU_S 7 125 /* RTC_CNTL_BB_I2C_FORCE_PD : R/W ;bitpos:[6] ;default: 1'b0 ; */ 126 /*description: BB_I2C force power down.*/ 127 #define RTC_CNTL_BB_I2C_FORCE_PD (BIT(6)) 128 #define RTC_CNTL_BB_I2C_FORCE_PD_M (BIT(6)) 129 #define RTC_CNTL_BB_I2C_FORCE_PD_V 0x1 130 #define RTC_CNTL_BB_I2C_FORCE_PD_S 6 131 /* RTC_CNTL_SW_PROCPU_RST : WO ;bitpos:[5] ;default: 1'b0 ; */ 132 /*description: PRO CPU SW reset.*/ 133 #define RTC_CNTL_SW_PROCPU_RST (BIT(5)) 134 #define RTC_CNTL_SW_PROCPU_RST_M (BIT(5)) 135 #define RTC_CNTL_SW_PROCPU_RST_V 0x1 136 #define RTC_CNTL_SW_PROCPU_RST_S 5 137 /* RTC_CNTL_SW_APPCPU_RST : WO ;bitpos:[4] ;default: 1'b0 ; */ 138 /*description: APP CPU SW reset.*/ 139 #define RTC_CNTL_SW_APPCPU_RST (BIT(4)) 140 #define RTC_CNTL_SW_APPCPU_RST_M (BIT(4)) 141 #define RTC_CNTL_SW_APPCPU_RST_V 0x1 142 #define RTC_CNTL_SW_APPCPU_RST_S 4 143 /* RTC_CNTL_SW_STALL_PROCPU_C0 : R/W ;bitpos:[3:2] ;default: 2'b0 ; */ 144 /*description: {reg_sw_stall_procpu_c1[5:0], reg_sw_stall_procpu_c0[1:0]} == 0x86 will stall P 145 RO CPU.*/ 146 #define RTC_CNTL_SW_STALL_PROCPU_C0 0x00000003 147 #define RTC_CNTL_SW_STALL_PROCPU_C0_M ((RTC_CNTL_SW_STALL_PROCPU_C0_V)<<(RTC_CNTL_SW_STALL_PROCPU_C0_S)) 148 #define RTC_CNTL_SW_STALL_PROCPU_C0_V 0x3 149 #define RTC_CNTL_SW_STALL_PROCPU_C0_S 2 150 /* RTC_CNTL_SW_STALL_APPCPU_C0 : R/W ;bitpos:[1:0] ;default: 2'b0 ; */ 151 /*description: {reg_sw_stall_appcpu_c1[5:0], reg_sw_stall_appcpu_c0[1:0]} == 0x86 will stall A 152 PP CPU.*/ 153 #define RTC_CNTL_SW_STALL_APPCPU_C0 0x00000003 154 #define RTC_CNTL_SW_STALL_APPCPU_C0_M ((RTC_CNTL_SW_STALL_APPCPU_C0_V)<<(RTC_CNTL_SW_STALL_APPCPU_C0_S)) 155 #define RTC_CNTL_SW_STALL_APPCPU_C0_V 0x3 156 #define RTC_CNTL_SW_STALL_APPCPU_C0_S 0 157 158 #define RTC_CNTL_SLP_TIMER0_REG (DR_REG_RTCCNTL_BASE + 0x4) 159 /* RTC_CNTL_SLP_VAL_LO : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ 160 /*description: .*/ 161 #define RTC_CNTL_SLP_VAL_LO 0xFFFFFFFF 162 #define RTC_CNTL_SLP_VAL_LO_M ((RTC_CNTL_SLP_VAL_LO_V)<<(RTC_CNTL_SLP_VAL_LO_S)) 163 #define RTC_CNTL_SLP_VAL_LO_V 0xFFFFFFFF 164 #define RTC_CNTL_SLP_VAL_LO_S 0 165 166 #define RTC_CNTL_SLP_TIMER1_REG (DR_REG_RTCCNTL_BASE + 0x8) 167 /* RTC_CNTL_MAIN_TIMER_ALARM_EN : WO ;bitpos:[16] ;default: 1'h0 ; */ 168 /*description: timer alarm enable bit.*/ 169 #define RTC_CNTL_MAIN_TIMER_ALARM_EN (BIT(16)) 170 #define RTC_CNTL_MAIN_TIMER_ALARM_EN_M (BIT(16)) 171 #define RTC_CNTL_MAIN_TIMER_ALARM_EN_V 0x1 172 #define RTC_CNTL_MAIN_TIMER_ALARM_EN_S 16 173 /* RTC_CNTL_SLP_VAL_HI : R/W ;bitpos:[15:0] ;default: 16'h0 ; */ 174 /*description: RTC sleep timer high 16 bits.*/ 175 #define RTC_CNTL_SLP_VAL_HI 0x0000FFFF 176 #define RTC_CNTL_SLP_VAL_HI_M ((RTC_CNTL_SLP_VAL_HI_V)<<(RTC_CNTL_SLP_VAL_HI_S)) 177 #define RTC_CNTL_SLP_VAL_HI_V 0xFFFF 178 #define RTC_CNTL_SLP_VAL_HI_S 0 179 180 #define RTC_CNTL_TIME_UPDATE_REG (DR_REG_RTCCNTL_BASE + 0xC) 181 /* RTC_CNTL_TIME_UPDATE : WO ;bitpos:[31] ;default: 1'h0 ; */ 182 /*description: Set 1: to update register with RTC timer.*/ 183 #define RTC_CNTL_TIME_UPDATE (BIT(31)) 184 #define RTC_CNTL_TIME_UPDATE_M (BIT(31)) 185 #define RTC_CNTL_TIME_UPDATE_V 0x1 186 #define RTC_CNTL_TIME_UPDATE_S 31 187 /* RTC_CNTL_TIMER_SYS_RST : R/W ;bitpos:[29] ;default: 1'b0 ; */ 188 /*description: enable to record system reset time.*/ 189 #define RTC_CNTL_TIMER_SYS_RST (BIT(29)) 190 #define RTC_CNTL_TIMER_SYS_RST_M (BIT(29)) 191 #define RTC_CNTL_TIMER_SYS_RST_V 0x1 192 #define RTC_CNTL_TIMER_SYS_RST_S 29 193 /* RTC_CNTL_TIMER_XTL_OFF : R/W ;bitpos:[28] ;default: 1'b0 ; */ 194 /*description: Enable to record 40M XTAL OFF time.*/ 195 #define RTC_CNTL_TIMER_XTL_OFF (BIT(28)) 196 #define RTC_CNTL_TIMER_XTL_OFF_M (BIT(28)) 197 #define RTC_CNTL_TIMER_XTL_OFF_V 0x1 198 #define RTC_CNTL_TIMER_XTL_OFF_S 28 199 /* RTC_CNTL_TIMER_SYS_STALL : R/W ;bitpos:[27] ;default: 1'b0 ; */ 200 /*description: Enable to record system stall time.*/ 201 #define RTC_CNTL_TIMER_SYS_STALL (BIT(27)) 202 #define RTC_CNTL_TIMER_SYS_STALL_M (BIT(27)) 203 #define RTC_CNTL_TIMER_SYS_STALL_V 0x1 204 #define RTC_CNTL_TIMER_SYS_STALL_S 27 205 206 #define RTC_CNTL_TIME_LOW0_REG (DR_REG_RTCCNTL_BASE + 0x10) 207 /* RTC_CNTL_TIMER_VALUE0_LOW : RO ;bitpos:[31:0] ;default: 32'h0 ; */ 208 /*description: RTC timer low 32 bits.*/ 209 #define RTC_CNTL_TIMER_VALUE0_LOW 0xFFFFFFFF 210 #define RTC_CNTL_TIMER_VALUE0_LOW_M ((RTC_CNTL_TIMER_VALUE0_LOW_V)<<(RTC_CNTL_TIMER_VALUE0_LOW_S)) 211 #define RTC_CNTL_TIMER_VALUE0_LOW_V 0xFFFFFFFF 212 #define RTC_CNTL_TIMER_VALUE0_LOW_S 0 213 214 #define RTC_CNTL_TIME_HIGH0_REG (DR_REG_RTCCNTL_BASE + 0x14) 215 /* RTC_CNTL_TIMER_VALUE0_HIGH : RO ;bitpos:[15:0] ;default: 16'h0 ; */ 216 /*description: RTC timer high 16 bits.*/ 217 #define RTC_CNTL_TIMER_VALUE0_HIGH 0x0000FFFF 218 #define RTC_CNTL_TIMER_VALUE0_HIGH_M ((RTC_CNTL_TIMER_VALUE0_HIGH_V)<<(RTC_CNTL_TIMER_VALUE0_HIGH_S)) 219 #define RTC_CNTL_TIMER_VALUE0_HIGH_V 0xFFFF 220 #define RTC_CNTL_TIMER_VALUE0_HIGH_S 0 221 222 #define RTC_CNTL_STATE0_REG (DR_REG_RTCCNTL_BASE + 0x18) 223 /* RTC_CNTL_SLEEP_EN : R/W ;bitpos:[31] ;default: 1'd0 ; */ 224 /*description: sleep enable bit.*/ 225 #define RTC_CNTL_SLEEP_EN (BIT(31)) 226 #define RTC_CNTL_SLEEP_EN_M (BIT(31)) 227 #define RTC_CNTL_SLEEP_EN_V 0x1 228 #define RTC_CNTL_SLEEP_EN_S 31 229 /* RTC_CNTL_SLP_REJECT : R/W ;bitpos:[30] ;default: 1'd0 ; */ 230 /*description: leep reject bit.*/ 231 #define RTC_CNTL_SLP_REJECT (BIT(30)) 232 #define RTC_CNTL_SLP_REJECT_M (BIT(30)) 233 #define RTC_CNTL_SLP_REJECT_V 0x1 234 #define RTC_CNTL_SLP_REJECT_S 30 235 /* RTC_CNTL_SLP_WAKEUP : R/W ;bitpos:[29] ;default: 1'd0 ; */ 236 /*description: leep wakeup bit.*/ 237 #define RTC_CNTL_SLP_WAKEUP (BIT(29)) 238 #define RTC_CNTL_SLP_WAKEUP_M (BIT(29)) 239 #define RTC_CNTL_SLP_WAKEUP_V 0x1 240 #define RTC_CNTL_SLP_WAKEUP_S 29 241 /* RTC_CNTL_SDIO_ACTIVE_IND : RO ;bitpos:[28] ;default: 1'd0 ; */ 242 /*description: SDIO active indication.*/ 243 #define RTC_CNTL_SDIO_ACTIVE_IND (BIT(28)) 244 #define RTC_CNTL_SDIO_ACTIVE_IND_M (BIT(28)) 245 #define RTC_CNTL_SDIO_ACTIVE_IND_V 0x1 246 #define RTC_CNTL_SDIO_ACTIVE_IND_S 28 247 /* RTC_CNTL_APB2RTC_BRIDGE_SEL : R/W ;bitpos:[22] ;default: 1'd0 ; */ 248 /*description: 1: APB to RTC using bridge.*/ 249 #define RTC_CNTL_APB2RTC_BRIDGE_SEL (BIT(22)) 250 #define RTC_CNTL_APB2RTC_BRIDGE_SEL_M (BIT(22)) 251 #define RTC_CNTL_APB2RTC_BRIDGE_SEL_V 0x1 252 #define RTC_CNTL_APB2RTC_BRIDGE_SEL_S 22 253 /* RTC_CNTL_SLP_REJECT_CAUSE_CLR : WO ;bitpos:[1] ;default: 1'b0 ; */ 254 /*description: clear rtc sleep reject cause.*/ 255 #define RTC_CNTL_SLP_REJECT_CAUSE_CLR (BIT(1)) 256 #define RTC_CNTL_SLP_REJECT_CAUSE_CLR_M (BIT(1)) 257 #define RTC_CNTL_SLP_REJECT_CAUSE_CLR_V 0x1 258 #define RTC_CNTL_SLP_REJECT_CAUSE_CLR_S 1 259 /* RTC_CNTL_SW_CPU_INT : WO ;bitpos:[0] ;default: 1'b0 ; */ 260 /*description: rtc software interrupt to main cpu.*/ 261 #define RTC_CNTL_SW_CPU_INT (BIT(0)) 262 #define RTC_CNTL_SW_CPU_INT_M (BIT(0)) 263 #define RTC_CNTL_SW_CPU_INT_V 0x1 264 #define RTC_CNTL_SW_CPU_INT_S 0 265 266 #define RTC_CNTL_TIMER1_REG (DR_REG_RTCCNTL_BASE + 0x1C) 267 /* RTC_CNTL_PLL_BUF_WAIT : R/W ;bitpos:[31:24] ;default: 8'd40 ; */ 268 /*description: PLL wait cycles in slow_clk_rtc.*/ 269 #define RTC_CNTL_PLL_BUF_WAIT 0x000000FF 270 #define RTC_CNTL_PLL_BUF_WAIT_M ((RTC_CNTL_PLL_BUF_WAIT_V)<<(RTC_CNTL_PLL_BUF_WAIT_S)) 271 #define RTC_CNTL_PLL_BUF_WAIT_V 0xFF 272 #define RTC_CNTL_PLL_BUF_WAIT_S 24 273 /* RTC_CNTL_XTL_BUF_WAIT : R/W ;bitpos:[23:14] ;default: 10'd80 ; */ 274 /*description: XTAL wait cycles in slow_clk_rtc.*/ 275 #define RTC_CNTL_XTL_BUF_WAIT 0x000003FF 276 #define RTC_CNTL_XTL_BUF_WAIT_M ((RTC_CNTL_XTL_BUF_WAIT_V)<<(RTC_CNTL_XTL_BUF_WAIT_S)) 277 #define RTC_CNTL_XTL_BUF_WAIT_V 0x3FF 278 #define RTC_CNTL_XTL_BUF_WAIT_S 14 279 /* RTC_CNTL_CK8M_WAIT : R/W ;bitpos:[13:6] ;default: 8'h10 ; */ 280 /*description: CK8M wait cycles in slow_clk_rtc.*/ 281 #define RTC_CNTL_CK8M_WAIT 0x000000FF 282 #define RTC_CNTL_CK8M_WAIT_M ((RTC_CNTL_CK8M_WAIT_V)<<(RTC_CNTL_CK8M_WAIT_S)) 283 #define RTC_CNTL_CK8M_WAIT_V 0xFF 284 #define RTC_CNTL_CK8M_WAIT_S 6 285 /* RTC_CNTL_CPU_STALL_WAIT : R/W ;bitpos:[5:1] ;default: 5'd1 ; */ 286 /*description: CPU stall wait cycles in fast_clk_rtc.*/ 287 #define RTC_CNTL_CPU_STALL_WAIT 0x0000001F 288 #define RTC_CNTL_CPU_STALL_WAIT_M ((RTC_CNTL_CPU_STALL_WAIT_V)<<(RTC_CNTL_CPU_STALL_WAIT_S)) 289 #define RTC_CNTL_CPU_STALL_WAIT_V 0x1F 290 #define RTC_CNTL_CPU_STALL_WAIT_S 1 291 /* RTC_CNTL_CPU_STALL_EN : R/W ;bitpos:[0] ;default: 1'd1 ; */ 292 /*description: CPU stall enable bit.*/ 293 #define RTC_CNTL_CPU_STALL_EN (BIT(0)) 294 #define RTC_CNTL_CPU_STALL_EN_M (BIT(0)) 295 #define RTC_CNTL_CPU_STALL_EN_V 0x1 296 #define RTC_CNTL_CPU_STALL_EN_S 0 297 298 #define RTC_CNTL_TIMER2_REG (DR_REG_RTCCNTL_BASE + 0x20) 299 /* RTC_CNTL_MIN_TIME_CK8M_OFF : R/W ;bitpos:[31:24] ;default: 8'h1 ; */ 300 /*description: minimal cycles in slow_clk_rtc for CK8M in power down state.*/ 301 #define RTC_CNTL_MIN_TIME_CK8M_OFF 0x000000FF 302 #define RTC_CNTL_MIN_TIME_CK8M_OFF_M ((RTC_CNTL_MIN_TIME_CK8M_OFF_V)<<(RTC_CNTL_MIN_TIME_CK8M_OFF_S)) 303 #define RTC_CNTL_MIN_TIME_CK8M_OFF_V 0xFF 304 #define RTC_CNTL_MIN_TIME_CK8M_OFF_S 24 305 /* RTC_CNTL_ULPCP_TOUCH_START_WAIT : R/W ;bitpos:[23:15] ;default: 9'h10 ; */ 306 /*description: wait cycles in slow_clk_rtc before ULP-coprocessor / touch controller start to w 307 ork.*/ 308 #define RTC_CNTL_ULPCP_TOUCH_START_WAIT 0x000001FF 309 #define RTC_CNTL_ULPCP_TOUCH_START_WAIT_M ((RTC_CNTL_ULPCP_TOUCH_START_WAIT_V)<<(RTC_CNTL_ULPCP_TOUCH_START_WAIT_S)) 310 #define RTC_CNTL_ULPCP_TOUCH_START_WAIT_V 0x1FF 311 #define RTC_CNTL_ULPCP_TOUCH_START_WAIT_S 15 312 313 #define RTC_CNTL_TIMER3_REG (DR_REG_RTCCNTL_BASE + 0x24) 314 /* RTC_CNTL_BT_POWERUP_TIMER : R/W ;bitpos:[31:25] ;default: 7'd10 ; */ 315 /*description: .*/ 316 #define RTC_CNTL_BT_POWERUP_TIMER 0x0000007F 317 #define RTC_CNTL_BT_POWERUP_TIMER_M ((RTC_CNTL_BT_POWERUP_TIMER_V)<<(RTC_CNTL_BT_POWERUP_TIMER_S)) 318 #define RTC_CNTL_BT_POWERUP_TIMER_V 0x7F 319 #define RTC_CNTL_BT_POWERUP_TIMER_S 25 320 /* RTC_CNTL_BT_WAIT_TIMER : R/W ;bitpos:[24:16] ;default: 9'h16 ; */ 321 /*description: .*/ 322 #define RTC_CNTL_BT_WAIT_TIMER 0x000001FF 323 #define RTC_CNTL_BT_WAIT_TIMER_M ((RTC_CNTL_BT_WAIT_TIMER_V)<<(RTC_CNTL_BT_WAIT_TIMER_S)) 324 #define RTC_CNTL_BT_WAIT_TIMER_V 0x1FF 325 #define RTC_CNTL_BT_WAIT_TIMER_S 16 326 /* RTC_CNTL_WIFI_POWERUP_TIMER : R/W ;bitpos:[15:9] ;default: 7'h5 ; */ 327 /*description: .*/ 328 #define RTC_CNTL_WIFI_POWERUP_TIMER 0x0000007F 329 #define RTC_CNTL_WIFI_POWERUP_TIMER_M ((RTC_CNTL_WIFI_POWERUP_TIMER_V)<<(RTC_CNTL_WIFI_POWERUP_TIMER_S)) 330 #define RTC_CNTL_WIFI_POWERUP_TIMER_V 0x7F 331 #define RTC_CNTL_WIFI_POWERUP_TIMER_S 9 332 /* RTC_CNTL_WIFI_WAIT_TIMER : R/W ;bitpos:[8:0] ;default: 9'h8 ; */ 333 /*description: .*/ 334 #define RTC_CNTL_WIFI_WAIT_TIMER 0x000001FF 335 #define RTC_CNTL_WIFI_WAIT_TIMER_M ((RTC_CNTL_WIFI_WAIT_TIMER_V)<<(RTC_CNTL_WIFI_WAIT_TIMER_S)) 336 #define RTC_CNTL_WIFI_WAIT_TIMER_V 0x1FF 337 #define RTC_CNTL_WIFI_WAIT_TIMER_S 0 338 339 #define RTC_CNTL_TIMER4_REG (DR_REG_RTCCNTL_BASE + 0x28) 340 /* RTC_CNTL_DG_WRAP_POWERUP_TIMER : R/W ;bitpos:[31:25] ;default: 7'h8 ; */ 341 /*description: .*/ 342 #define RTC_CNTL_DG_WRAP_POWERUP_TIMER 0x0000007F 343 #define RTC_CNTL_DG_WRAP_POWERUP_TIMER_M ((RTC_CNTL_DG_WRAP_POWERUP_TIMER_V)<<(RTC_CNTL_DG_WRAP_POWERUP_TIMER_S)) 344 #define RTC_CNTL_DG_WRAP_POWERUP_TIMER_V 0x7F 345 #define RTC_CNTL_DG_WRAP_POWERUP_TIMER_S 25 346 /* RTC_CNTL_DG_WRAP_WAIT_TIMER : R/W ;bitpos:[24:16] ;default: 9'h20 ; */ 347 /*description: .*/ 348 #define RTC_CNTL_DG_WRAP_WAIT_TIMER 0x000001FF 349 #define RTC_CNTL_DG_WRAP_WAIT_TIMER_M ((RTC_CNTL_DG_WRAP_WAIT_TIMER_V)<<(RTC_CNTL_DG_WRAP_WAIT_TIMER_S)) 350 #define RTC_CNTL_DG_WRAP_WAIT_TIMER_V 0x1FF 351 #define RTC_CNTL_DG_WRAP_WAIT_TIMER_S 16 352 /* RTC_CNTL_POWERUP_TIMER : R/W ;bitpos:[15:9] ;default: 7'h5 ; */ 353 /*description: .*/ 354 #define RTC_CNTL_POWERUP_TIMER 0x0000007F 355 #define RTC_CNTL_POWERUP_TIMER_M ((RTC_CNTL_POWERUP_TIMER_V)<<(RTC_CNTL_POWERUP_TIMER_S)) 356 #define RTC_CNTL_POWERUP_TIMER_V 0x7F 357 #define RTC_CNTL_POWERUP_TIMER_S 9 358 /* RTC_CNTL_WAIT_TIMER : R/W ;bitpos:[8:0] ;default: 9'h8 ; */ 359 /*description: .*/ 360 #define RTC_CNTL_WAIT_TIMER 0x000001FF 361 #define RTC_CNTL_WAIT_TIMER_M ((RTC_CNTL_WAIT_TIMER_V)<<(RTC_CNTL_WAIT_TIMER_S)) 362 #define RTC_CNTL_WAIT_TIMER_V 0x1FF 363 #define RTC_CNTL_WAIT_TIMER_S 0 364 365 #define RTC_CNTL_TIMER5_REG (DR_REG_RTCCNTL_BASE + 0x2C) 366 /* RTC_CNTL_MIN_SLP_VAL : R/W ;bitpos:[15:8] ;default: 8'h80 ; */ 367 /*description: minimal sleep cycles in slow_clk_rtc.*/ 368 #define RTC_CNTL_MIN_SLP_VAL 0x000000FF 369 #define RTC_CNTL_MIN_SLP_VAL_M ((RTC_CNTL_MIN_SLP_VAL_V)<<(RTC_CNTL_MIN_SLP_VAL_S)) 370 #define RTC_CNTL_MIN_SLP_VAL_V 0xFF 371 #define RTC_CNTL_MIN_SLP_VAL_S 8 372 373 #define RTC_CNTL_TIMER6_REG (DR_REG_RTCCNTL_BASE + 0x30) 374 /* RTC_CNTL_DG_PERI_POWERUP_TIMER : R/W ;bitpos:[31:25] ;default: 7'h8 ; */ 375 /*description: .*/ 376 #define RTC_CNTL_DG_PERI_POWERUP_TIMER 0x0000007F 377 #define RTC_CNTL_DG_PERI_POWERUP_TIMER_M ((RTC_CNTL_DG_PERI_POWERUP_TIMER_V)<<(RTC_CNTL_DG_PERI_POWERUP_TIMER_S)) 378 #define RTC_CNTL_DG_PERI_POWERUP_TIMER_V 0x7F 379 #define RTC_CNTL_DG_PERI_POWERUP_TIMER_S 25 380 /* RTC_CNTL_DG_PERI_WAIT_TIMER : R/W ;bitpos:[24:16] ;default: 9'h20 ; */ 381 /*description: .*/ 382 #define RTC_CNTL_DG_PERI_WAIT_TIMER 0x000001FF 383 #define RTC_CNTL_DG_PERI_WAIT_TIMER_M ((RTC_CNTL_DG_PERI_WAIT_TIMER_V)<<(RTC_CNTL_DG_PERI_WAIT_TIMER_S)) 384 #define RTC_CNTL_DG_PERI_WAIT_TIMER_V 0x1FF 385 #define RTC_CNTL_DG_PERI_WAIT_TIMER_S 16 386 /* RTC_CNTL_CPU_TOP_POWERUP_TIMER : R/W ;bitpos:[15:9] ;default: 7'h5 ; */ 387 /*description: .*/ 388 #define RTC_CNTL_CPU_TOP_POWERUP_TIMER 0x0000007F 389 #define RTC_CNTL_CPU_TOP_POWERUP_TIMER_M ((RTC_CNTL_CPU_TOP_POWERUP_TIMER_V)<<(RTC_CNTL_CPU_TOP_POWERUP_TIMER_S)) 390 #define RTC_CNTL_CPU_TOP_POWERUP_TIMER_V 0x7F 391 #define RTC_CNTL_CPU_TOP_POWERUP_TIMER_S 9 392 /* RTC_CNTL_CPU_TOP_WAIT_TIMER : R/W ;bitpos:[8:0] ;default: 9'h8 ; */ 393 /*description: .*/ 394 #define RTC_CNTL_CPU_TOP_WAIT_TIMER 0x000001FF 395 #define RTC_CNTL_CPU_TOP_WAIT_TIMER_M ((RTC_CNTL_CPU_TOP_WAIT_TIMER_V)<<(RTC_CNTL_CPU_TOP_WAIT_TIMER_S)) 396 #define RTC_CNTL_CPU_TOP_WAIT_TIMER_V 0x1FF 397 #define RTC_CNTL_CPU_TOP_WAIT_TIMER_S 0 398 399 #define RTC_CNTL_ANA_CONF_REG (DR_REG_RTCCNTL_BASE + 0x34) 400 /* RTC_CNTL_PLL_I2C_PU : R/W ;bitpos:[31] ;default: 1'd0 ; */ 401 /*description: .*/ 402 #define RTC_CNTL_PLL_I2C_PU (BIT(31)) 403 #define RTC_CNTL_PLL_I2C_PU_M (BIT(31)) 404 #define RTC_CNTL_PLL_I2C_PU_V 0x1 405 #define RTC_CNTL_PLL_I2C_PU_S 31 406 /* RTC_CNTL_CKGEN_I2C_PU : R/W ;bitpos:[30] ;default: 1'd0 ; */ 407 /*description: 1: CKGEN_I2C power up.*/ 408 #define RTC_CNTL_CKGEN_I2C_PU (BIT(30)) 409 #define RTC_CNTL_CKGEN_I2C_PU_M (BIT(30)) 410 #define RTC_CNTL_CKGEN_I2C_PU_V 0x1 411 #define RTC_CNTL_CKGEN_I2C_PU_S 30 412 /* RTC_CNTL_RFRX_PBUS_PU : R/W ;bitpos:[28] ;default: 1'd0 ; */ 413 /*description: 1: RFRX_PBUS power up.*/ 414 #define RTC_CNTL_RFRX_PBUS_PU (BIT(28)) 415 #define RTC_CNTL_RFRX_PBUS_PU_M (BIT(28)) 416 #define RTC_CNTL_RFRX_PBUS_PU_V 0x1 417 #define RTC_CNTL_RFRX_PBUS_PU_S 28 418 /* RTC_CNTL_TXRF_I2C_PU : R/W ;bitpos:[27] ;default: 1'd0 ; */ 419 /*description: 1: TXRF_I2C power up.*/ 420 #define RTC_CNTL_TXRF_I2C_PU (BIT(27)) 421 #define RTC_CNTL_TXRF_I2C_PU_M (BIT(27)) 422 #define RTC_CNTL_TXRF_I2C_PU_V 0x1 423 #define RTC_CNTL_TXRF_I2C_PU_S 27 424 /* RTC_CNTL_PVTMON_PU : R/W ;bitpos:[26] ;default: 1'b0 ; */ 425 /*description: 1: PVTMON power up.*/ 426 #define RTC_CNTL_PVTMON_PU (BIT(26)) 427 #define RTC_CNTL_PVTMON_PU_M (BIT(26)) 428 #define RTC_CNTL_PVTMON_PU_V 0x1 429 #define RTC_CNTL_PVTMON_PU_S 26 430 /* RTC_CNTL_BBPLL_CAL_SLP_START : R/W ;bitpos:[25] ;default: 1'b0 ; */ 431 /*description: start BBPLL calibration during sleep.*/ 432 #define RTC_CNTL_BBPLL_CAL_SLP_START (BIT(25)) 433 #define RTC_CNTL_BBPLL_CAL_SLP_START_M (BIT(25)) 434 #define RTC_CNTL_BBPLL_CAL_SLP_START_V 0x1 435 #define RTC_CNTL_BBPLL_CAL_SLP_START_S 25 436 /* RTC_CNTL_ANALOG_TOP_ISO_MONITOR : R/W ;bitpos:[24] ;default: 1'b0 ; */ 437 /*description: PLLA force power up.*/ 438 #define RTC_CNTL_ANALOG_TOP_ISO_MONITOR (BIT(24)) 439 #define RTC_CNTL_ANALOG_TOP_ISO_MONITOR_M (BIT(24)) 440 #define RTC_CNTL_ANALOG_TOP_ISO_MONITOR_V 0x1 441 #define RTC_CNTL_ANALOG_TOP_ISO_MONITOR_S 24 442 /* RTC_CNTL_ANALOG_TOP_ISO_SLEEP : R/W ;bitpos:[23] ;default: 1'b0 ; */ 443 /*description: PLLA force power down.*/ 444 #define RTC_CNTL_ANALOG_TOP_ISO_SLEEP (BIT(23)) 445 #define RTC_CNTL_ANALOG_TOP_ISO_SLEEP_M (BIT(23)) 446 #define RTC_CNTL_ANALOG_TOP_ISO_SLEEP_V 0x1 447 #define RTC_CNTL_ANALOG_TOP_ISO_SLEEP_S 23 448 /* RTC_CNTL_SAR_I2C_PU : R/W ;bitpos:[22] ;default: 1'b1 ; */ 449 /*description: PLLA force power up.*/ 450 #define RTC_CNTL_SAR_I2C_PU (BIT(22)) 451 #define RTC_CNTL_SAR_I2C_PU_M (BIT(22)) 452 #define RTC_CNTL_SAR_I2C_PU_V 0x1 453 #define RTC_CNTL_SAR_I2C_PU_S 22 454 /* RTC_CNTL_GLITCH_RST_EN : R/W ;bitpos:[20] ;default: 1'b0 ; */ 455 /*description: .*/ 456 #define RTC_CNTL_GLITCH_RST_EN (BIT(20)) 457 #define RTC_CNTL_GLITCH_RST_EN_M (BIT(20)) 458 #define RTC_CNTL_GLITCH_RST_EN_V 0x1 459 #define RTC_CNTL_GLITCH_RST_EN_S 20 460 /* RTC_CNTL_I2C_RESET_POR_FORCE_PU : R/W ;bitpos:[19] ;default: 1'b0 ; */ 461 /*description: .*/ 462 #define RTC_CNTL_I2C_RESET_POR_FORCE_PU (BIT(19)) 463 #define RTC_CNTL_I2C_RESET_POR_FORCE_PU_M (BIT(19)) 464 #define RTC_CNTL_I2C_RESET_POR_FORCE_PU_V 0x1 465 #define RTC_CNTL_I2C_RESET_POR_FORCE_PU_S 19 466 /* RTC_CNTL_I2C_RESET_POR_FORCE_PD : R/W ;bitpos:[18] ;default: 1'b1 ; */ 467 /*description: .*/ 468 #define RTC_CNTL_I2C_RESET_POR_FORCE_PD (BIT(18)) 469 #define RTC_CNTL_I2C_RESET_POR_FORCE_PD_M (BIT(18)) 470 #define RTC_CNTL_I2C_RESET_POR_FORCE_PD_V 0x1 471 #define RTC_CNTL_I2C_RESET_POR_FORCE_PD_S 18 472 473 #define RTC_CNTL_RESET_STATE_REG (DR_REG_RTCCNTL_BASE + 0x38) 474 /* RTC_CNTL_PRO_DRESET_MASK : R/W ;bitpos:[25] ;default: 1'b0 ; */ 475 /*description: .*/ 476 #define RTC_CNTL_PRO_DRESET_MASK (BIT(25)) 477 #define RTC_CNTL_PRO_DRESET_MASK_M (BIT(25)) 478 #define RTC_CNTL_PRO_DRESET_MASK_V 0x1 479 #define RTC_CNTL_PRO_DRESET_MASK_S 25 480 /* RTC_CNTL_APP_DRESET_MASK : R/W ;bitpos:[24] ;default: 1'b0 ; */ 481 /*description: .*/ 482 #define RTC_CNTL_APP_DRESET_MASK (BIT(24)) 483 #define RTC_CNTL_APP_DRESET_MASK_M (BIT(24)) 484 #define RTC_CNTL_APP_DRESET_MASK_V 0x1 485 #define RTC_CNTL_APP_DRESET_MASK_S 24 486 /* RTC_CNTL_RESET_FLAG_JTAG_APPCPU_CLR : WO ;bitpos:[23] ;default: 1'b0 ; */ 487 /*description: .*/ 488 #define RTC_CNTL_RESET_FLAG_JTAG_APPCPU_CLR (BIT(23)) 489 #define RTC_CNTL_RESET_FLAG_JTAG_APPCPU_CLR_M (BIT(23)) 490 #define RTC_CNTL_RESET_FLAG_JTAG_APPCPU_CLR_V 0x1 491 #define RTC_CNTL_RESET_FLAG_JTAG_APPCPU_CLR_S 23 492 /* RTC_CNTL_RESET_FLAG_JTAG_PROCPU_CLR : WO ;bitpos:[22] ;default: 1'b0 ; */ 493 /*description: .*/ 494 #define RTC_CNTL_RESET_FLAG_JTAG_PROCPU_CLR (BIT(22)) 495 #define RTC_CNTL_RESET_FLAG_JTAG_PROCPU_CLR_M (BIT(22)) 496 #define RTC_CNTL_RESET_FLAG_JTAG_PROCPU_CLR_V 0x1 497 #define RTC_CNTL_RESET_FLAG_JTAG_PROCPU_CLR_S 22 498 /* RTC_CNTL_RESET_FLAG_JTAG_APPCPU : RO ;bitpos:[21] ;default: 1'b0 ; */ 499 /*description: .*/ 500 #define RTC_CNTL_RESET_FLAG_JTAG_APPCPU (BIT(21)) 501 #define RTC_CNTL_RESET_FLAG_JTAG_APPCPU_M (BIT(21)) 502 #define RTC_CNTL_RESET_FLAG_JTAG_APPCPU_V 0x1 503 #define RTC_CNTL_RESET_FLAG_JTAG_APPCPU_S 21 504 /* RTC_CNTL_RESET_FLAG_JTAG_PROCPU : RO ;bitpos:[20] ;default: 1'b0 ; */ 505 /*description: .*/ 506 #define RTC_CNTL_RESET_FLAG_JTAG_PROCPU (BIT(20)) 507 #define RTC_CNTL_RESET_FLAG_JTAG_PROCPU_M (BIT(20)) 508 #define RTC_CNTL_RESET_FLAG_JTAG_PROCPU_V 0x1 509 #define RTC_CNTL_RESET_FLAG_JTAG_PROCPU_S 20 510 /* RTC_CNTL_PROCPU_OCD_HALT_ON_RESET : R/W ;bitpos:[19] ;default: 1'b0 ; */ 511 /*description: PROCPU OcdHaltOnReset.*/ 512 #define RTC_CNTL_PROCPU_OCD_HALT_ON_RESET (BIT(19)) 513 #define RTC_CNTL_PROCPU_OCD_HALT_ON_RESET_M (BIT(19)) 514 #define RTC_CNTL_PROCPU_OCD_HALT_ON_RESET_V 0x1 515 #define RTC_CNTL_PROCPU_OCD_HALT_ON_RESET_S 19 516 /* RTC_CNTL_APPCPU_OCD_HALT_ON_RESET : R/W ;bitpos:[18] ;default: 1'b0 ; */ 517 /*description: APPCPU OcdHaltOnReset.*/ 518 #define RTC_CNTL_APPCPU_OCD_HALT_ON_RESET (BIT(18)) 519 #define RTC_CNTL_APPCPU_OCD_HALT_ON_RESET_M (BIT(18)) 520 #define RTC_CNTL_APPCPU_OCD_HALT_ON_RESET_V 0x1 521 #define RTC_CNTL_APPCPU_OCD_HALT_ON_RESET_S 18 522 /* RTC_CNTL_RESET_FLAG_APPCPU_CLR : WO ;bitpos:[17] ;default: 1'b0 ; */ 523 /*description: clear APP CPU reset flag.*/ 524 #define RTC_CNTL_RESET_FLAG_APPCPU_CLR (BIT(17)) 525 #define RTC_CNTL_RESET_FLAG_APPCPU_CLR_M (BIT(17)) 526 #define RTC_CNTL_RESET_FLAG_APPCPU_CLR_V 0x1 527 #define RTC_CNTL_RESET_FLAG_APPCPU_CLR_S 17 528 /* RTC_CNTL_RESET_FLAG_PROCPU_CLR : WO ;bitpos:[16] ;default: 1'b0 ; */ 529 /*description: clear PRO CPU reset_flag.*/ 530 #define RTC_CNTL_RESET_FLAG_PROCPU_CLR (BIT(16)) 531 #define RTC_CNTL_RESET_FLAG_PROCPU_CLR_M (BIT(16)) 532 #define RTC_CNTL_RESET_FLAG_PROCPU_CLR_V 0x1 533 #define RTC_CNTL_RESET_FLAG_PROCPU_CLR_S 16 534 /* RTC_CNTL_RESET_FLAG_APPCPU : RO ;bitpos:[15] ;default: 1'b0 ; */ 535 /*description: APP CPU reset flag.*/ 536 #define RTC_CNTL_RESET_FLAG_APPCPU (BIT(15)) 537 #define RTC_CNTL_RESET_FLAG_APPCPU_M (BIT(15)) 538 #define RTC_CNTL_RESET_FLAG_APPCPU_V 0x1 539 #define RTC_CNTL_RESET_FLAG_APPCPU_S 15 540 /* RTC_CNTL_RESET_FLAG_PROCPU : RO ;bitpos:[14] ;default: 1'b0 ; */ 541 /*description: PRO CPU reset_flag.*/ 542 #define RTC_CNTL_RESET_FLAG_PROCPU (BIT(14)) 543 #define RTC_CNTL_RESET_FLAG_PROCPU_M (BIT(14)) 544 #define RTC_CNTL_RESET_FLAG_PROCPU_V 0x1 545 #define RTC_CNTL_RESET_FLAG_PROCPU_S 14 546 /* RTC_CNTL_PROCPU_STAT_VECTOR_SEL : R/W ;bitpos:[13] ;default: 1'b1 ; */ 547 /*description: PRO CPU state vector sel.*/ 548 #define RTC_CNTL_PROCPU_STAT_VECTOR_SEL (BIT(13)) 549 #define RTC_CNTL_PROCPU_STAT_VECTOR_SEL_M (BIT(13)) 550 #define RTC_CNTL_PROCPU_STAT_VECTOR_SEL_V 0x1 551 #define RTC_CNTL_PROCPU_STAT_VECTOR_SEL_S 13 552 /* RTC_CNTL_APPCPU_STAT_VECTOR_SEL : R/W ;bitpos:[12] ;default: 1'b1 ; */ 553 /*description: APP CPU state vector sel.*/ 554 #define RTC_CNTL_APPCPU_STAT_VECTOR_SEL (BIT(12)) 555 #define RTC_CNTL_APPCPU_STAT_VECTOR_SEL_M (BIT(12)) 556 #define RTC_CNTL_APPCPU_STAT_VECTOR_SEL_V 0x1 557 #define RTC_CNTL_APPCPU_STAT_VECTOR_SEL_S 12 558 /* RTC_CNTL_RESET_CAUSE_APPCPU : RO ;bitpos:[11:6] ;default: 0 ; */ 559 /*description: reset cause of APP CPU.*/ 560 #define RTC_CNTL_RESET_CAUSE_APPCPU 0x0000003F 561 #define RTC_CNTL_RESET_CAUSE_APPCPU_M ((RTC_CNTL_RESET_CAUSE_APPCPU_V)<<(RTC_CNTL_RESET_CAUSE_APPCPU_S)) 562 #define RTC_CNTL_RESET_CAUSE_APPCPU_V 0x3F 563 #define RTC_CNTL_RESET_CAUSE_APPCPU_S 6 564 /* RTC_CNTL_RESET_CAUSE_PROCPU : RO ;bitpos:[5:0] ;default: 0 ; */ 565 /*description: reset cause of PRO CPU.*/ 566 #define RTC_CNTL_RESET_CAUSE_PROCPU 0x0000003F 567 #define RTC_CNTL_RESET_CAUSE_PROCPU_M ((RTC_CNTL_RESET_CAUSE_PROCPU_V)<<(RTC_CNTL_RESET_CAUSE_PROCPU_S)) 568 #define RTC_CNTL_RESET_CAUSE_PROCPU_V 0x3F 569 #define RTC_CNTL_RESET_CAUSE_PROCPU_S 0 570 571 #define RTC_CNTL_WAKEUP_STATE_REG (DR_REG_RTCCNTL_BASE + 0x3C) 572 /* RTC_CNTL_WAKEUP_ENA : R/W ;bitpos:[31:15] ;default: 17'b1100 ; */ 573 /*description: wakeup enable bitmap.*/ 574 #define RTC_CNTL_WAKEUP_ENA 0x0001FFFF 575 #define RTC_CNTL_WAKEUP_ENA_M ((RTC_CNTL_WAKEUP_ENA_V)<<(RTC_CNTL_WAKEUP_ENA_S)) 576 #define RTC_CNTL_WAKEUP_ENA_V 0x1FFFF 577 #define RTC_CNTL_WAKEUP_ENA_S 15 578 579 #define RTC_CNTL_INT_ENA_REG (DR_REG_RTCCNTL_BASE + 0x40) 580 /* RTC_CNTL_TOUCH_APPROACH_LOOP_DONE_INT_ENA : R/W ;bitpos:[20] ;default: 1'b0 ; */ 581 /*description: .*/ 582 #define RTC_CNTL_TOUCH_APPROACH_LOOP_DONE_INT_ENA (BIT(20)) 583 #define RTC_CNTL_TOUCH_APPROACH_LOOP_DONE_INT_ENA_M (BIT(20)) 584 #define RTC_CNTL_TOUCH_APPROACH_LOOP_DONE_INT_ENA_V 0x1 585 #define RTC_CNTL_TOUCH_APPROACH_LOOP_DONE_INT_ENA_S 20 586 /* RTC_CNTL_GLITCH_DET_INT_ENA : R/W ;bitpos:[19] ;default: 1'b0 ; */ 587 /*description: enbale gitch det interrupt.*/ 588 #define RTC_CNTL_GLITCH_DET_INT_ENA (BIT(19)) 589 #define RTC_CNTL_GLITCH_DET_INT_ENA_M (BIT(19)) 590 #define RTC_CNTL_GLITCH_DET_INT_ENA_V 0x1 591 #define RTC_CNTL_GLITCH_DET_INT_ENA_S 19 592 /* RTC_CNTL_TOUCH_TIMEOUT_INT_ENA : R/W ;bitpos:[18] ;default: 1'b0 ; */ 593 /*description: enable touch timeout interrupt.*/ 594 #define RTC_CNTL_TOUCH_TIMEOUT_INT_ENA (BIT(18)) 595 #define RTC_CNTL_TOUCH_TIMEOUT_INT_ENA_M (BIT(18)) 596 #define RTC_CNTL_TOUCH_TIMEOUT_INT_ENA_V 0x1 597 #define RTC_CNTL_TOUCH_TIMEOUT_INT_ENA_S 18 598 /* RTC_CNTL_COCPU_TRAP_INT_ENA : R/W ;bitpos:[17] ;default: 1'b0 ; */ 599 /*description: enable cocpu trap interrupt.*/ 600 #define RTC_CNTL_COCPU_TRAP_INT_ENA (BIT(17)) 601 #define RTC_CNTL_COCPU_TRAP_INT_ENA_M (BIT(17)) 602 #define RTC_CNTL_COCPU_TRAP_INT_ENA_V 0x1 603 #define RTC_CNTL_COCPU_TRAP_INT_ENA_S 17 604 /* RTC_CNTL_XTAL32K_DEAD_INT_ENA : R/W ;bitpos:[16] ;default: 1'b0 ; */ 605 /*description: enable xtal32k_dead interrupt.*/ 606 #define RTC_CNTL_XTAL32K_DEAD_INT_ENA (BIT(16)) 607 #define RTC_CNTL_XTAL32K_DEAD_INT_ENA_M (BIT(16)) 608 #define RTC_CNTL_XTAL32K_DEAD_INT_ENA_V 0x1 609 #define RTC_CNTL_XTAL32K_DEAD_INT_ENA_S 16 610 /* RTC_CNTL_SWD_INT_ENA : R/W ;bitpos:[15] ;default: 1'b0 ; */ 611 /*description: enable super watch dog interrupt.*/ 612 #define RTC_CNTL_SWD_INT_ENA (BIT(15)) 613 #define RTC_CNTL_SWD_INT_ENA_M (BIT(15)) 614 #define RTC_CNTL_SWD_INT_ENA_V 0x1 615 #define RTC_CNTL_SWD_INT_ENA_S 15 616 /* RTC_CNTL_SARADC2_INT_ENA : R/W ;bitpos:[14] ;default: 1'b0 ; */ 617 /*description: enable saradc2 interrupt.*/ 618 #define RTC_CNTL_SARADC2_INT_ENA (BIT(14)) 619 #define RTC_CNTL_SARADC2_INT_ENA_M (BIT(14)) 620 #define RTC_CNTL_SARADC2_INT_ENA_V 0x1 621 #define RTC_CNTL_SARADC2_INT_ENA_S 14 622 /* RTC_CNTL_COCPU_INT_ENA : R/W ;bitpos:[13] ;default: 1'b0 ; */ 623 /*description: enable riscV cocpu interrupt.*/ 624 #define RTC_CNTL_COCPU_INT_ENA (BIT(13)) 625 #define RTC_CNTL_COCPU_INT_ENA_M (BIT(13)) 626 #define RTC_CNTL_COCPU_INT_ENA_V 0x1 627 #define RTC_CNTL_COCPU_INT_ENA_S 13 628 /* RTC_CNTL_TSENS_INT_ENA : R/W ;bitpos:[12] ;default: 1'b0 ; */ 629 /*description: enable tsens interrupt.*/ 630 #define RTC_CNTL_TSENS_INT_ENA (BIT(12)) 631 #define RTC_CNTL_TSENS_INT_ENA_M (BIT(12)) 632 #define RTC_CNTL_TSENS_INT_ENA_V 0x1 633 #define RTC_CNTL_TSENS_INT_ENA_S 12 634 /* RTC_CNTL_SARADC1_INT_ENA : R/W ;bitpos:[11] ;default: 1'b0 ; */ 635 /*description: enable saradc1 interrupt.*/ 636 #define RTC_CNTL_SARADC1_INT_ENA (BIT(11)) 637 #define RTC_CNTL_SARADC1_INT_ENA_M (BIT(11)) 638 #define RTC_CNTL_SARADC1_INT_ENA_V 0x1 639 #define RTC_CNTL_SARADC1_INT_ENA_S 11 640 /* RTC_CNTL_MAIN_TIMER_INT_ENA : R/W ;bitpos:[10] ;default: 1'b0 ; */ 641 /*description: enable RTC main timer interrupt.*/ 642 #define RTC_CNTL_MAIN_TIMER_INT_ENA (BIT(10)) 643 #define RTC_CNTL_MAIN_TIMER_INT_ENA_M (BIT(10)) 644 #define RTC_CNTL_MAIN_TIMER_INT_ENA_V 0x1 645 #define RTC_CNTL_MAIN_TIMER_INT_ENA_S 10 646 /* RTC_CNTL_BROWN_OUT_INT_ENA : R/W ;bitpos:[9] ;default: 1'b0 ; */ 647 /*description: enable brown out interrupt.*/ 648 #define RTC_CNTL_BROWN_OUT_INT_ENA (BIT(9)) 649 #define RTC_CNTL_BROWN_OUT_INT_ENA_M (BIT(9)) 650 #define RTC_CNTL_BROWN_OUT_INT_ENA_V 0x1 651 #define RTC_CNTL_BROWN_OUT_INT_ENA_S 9 652 /* RTC_CNTL_TOUCH_INACTIVE_INT_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */ 653 /*description: enable touch inactive interrupt.*/ 654 #define RTC_CNTL_TOUCH_INACTIVE_INT_ENA (BIT(8)) 655 #define RTC_CNTL_TOUCH_INACTIVE_INT_ENA_M (BIT(8)) 656 #define RTC_CNTL_TOUCH_INACTIVE_INT_ENA_V 0x1 657 #define RTC_CNTL_TOUCH_INACTIVE_INT_ENA_S 8 658 /* RTC_CNTL_TOUCH_ACTIVE_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */ 659 /*description: enable touch active interrupt.*/ 660 #define RTC_CNTL_TOUCH_ACTIVE_INT_ENA (BIT(7)) 661 #define RTC_CNTL_TOUCH_ACTIVE_INT_ENA_M (BIT(7)) 662 #define RTC_CNTL_TOUCH_ACTIVE_INT_ENA_V 0x1 663 #define RTC_CNTL_TOUCH_ACTIVE_INT_ENA_S 7 664 /* RTC_CNTL_TOUCH_DONE_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */ 665 /*description: enable touch done interrupt.*/ 666 #define RTC_CNTL_TOUCH_DONE_INT_ENA (BIT(6)) 667 #define RTC_CNTL_TOUCH_DONE_INT_ENA_M (BIT(6)) 668 #define RTC_CNTL_TOUCH_DONE_INT_ENA_V 0x1 669 #define RTC_CNTL_TOUCH_DONE_INT_ENA_S 6 670 /* RTC_CNTL_ULP_CP_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */ 671 /*description: enable ULP-coprocessor interrupt.*/ 672 #define RTC_CNTL_ULP_CP_INT_ENA (BIT(5)) 673 #define RTC_CNTL_ULP_CP_INT_ENA_M (BIT(5)) 674 #define RTC_CNTL_ULP_CP_INT_ENA_V 0x1 675 #define RTC_CNTL_ULP_CP_INT_ENA_S 5 676 /* RTC_CNTL_TOUCH_SCAN_DONE_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */ 677 /*description: enable touch scan done interrupt.*/ 678 #define RTC_CNTL_TOUCH_SCAN_DONE_INT_ENA (BIT(4)) 679 #define RTC_CNTL_TOUCH_SCAN_DONE_INT_ENA_M (BIT(4)) 680 #define RTC_CNTL_TOUCH_SCAN_DONE_INT_ENA_V 0x1 681 #define RTC_CNTL_TOUCH_SCAN_DONE_INT_ENA_S 4 682 /* RTC_CNTL_WDT_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */ 683 /*description: enable RTC WDT interrupt.*/ 684 #define RTC_CNTL_WDT_INT_ENA (BIT(3)) 685 #define RTC_CNTL_WDT_INT_ENA_M (BIT(3)) 686 #define RTC_CNTL_WDT_INT_ENA_V 0x1 687 #define RTC_CNTL_WDT_INT_ENA_S 3 688 /* RTC_CNTL_SDIO_IDLE_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */ 689 /*description: enable SDIO idle interrupt.*/ 690 #define RTC_CNTL_SDIO_IDLE_INT_ENA (BIT(2)) 691 #define RTC_CNTL_SDIO_IDLE_INT_ENA_M (BIT(2)) 692 #define RTC_CNTL_SDIO_IDLE_INT_ENA_V 0x1 693 #define RTC_CNTL_SDIO_IDLE_INT_ENA_S 2 694 /* RTC_CNTL_SLP_REJECT_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */ 695 /*description: enable sleep reject interrupt.*/ 696 #define RTC_CNTL_SLP_REJECT_INT_ENA (BIT(1)) 697 #define RTC_CNTL_SLP_REJECT_INT_ENA_M (BIT(1)) 698 #define RTC_CNTL_SLP_REJECT_INT_ENA_V 0x1 699 #define RTC_CNTL_SLP_REJECT_INT_ENA_S 1 700 /* RTC_CNTL_SLP_WAKEUP_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ 701 /*description: enable sleep wakeup interrupt.*/ 702 #define RTC_CNTL_SLP_WAKEUP_INT_ENA (BIT(0)) 703 #define RTC_CNTL_SLP_WAKEUP_INT_ENA_M (BIT(0)) 704 #define RTC_CNTL_SLP_WAKEUP_INT_ENA_V 0x1 705 #define RTC_CNTL_SLP_WAKEUP_INT_ENA_S 0 706 707 #define RTC_CNTL_INT_RAW_REG (DR_REG_RTCCNTL_BASE + 0x44) 708 /* RTC_CNTL_TOUCH_APPROACH_LOOP_DONE_INT_RAW : R/W ;bitpos:[20] ;default: 1'b0 ; */ 709 /*description: .*/ 710 #define RTC_CNTL_TOUCH_APPROACH_LOOP_DONE_INT_RAW (BIT(20)) 711 #define RTC_CNTL_TOUCH_APPROACH_LOOP_DONE_INT_RAW_M (BIT(20)) 712 #define RTC_CNTL_TOUCH_APPROACH_LOOP_DONE_INT_RAW_V 0x1 713 #define RTC_CNTL_TOUCH_APPROACH_LOOP_DONE_INT_RAW_S 20 714 /* RTC_CNTL_GLITCH_DET_INT_RAW : RO ;bitpos:[19] ;default: 1'b0 ; */ 715 /*description: glitch_det_interrupt_raw.*/ 716 #define RTC_CNTL_GLITCH_DET_INT_RAW (BIT(19)) 717 #define RTC_CNTL_GLITCH_DET_INT_RAW_M (BIT(19)) 718 #define RTC_CNTL_GLITCH_DET_INT_RAW_V 0x1 719 #define RTC_CNTL_GLITCH_DET_INT_RAW_S 19 720 /* RTC_CNTL_TOUCH_TIMEOUT_INT_RAW : RO ;bitpos:[18] ;default: 1'b0 ; */ 721 /*description: touch timeout interrupt raw.*/ 722 #define RTC_CNTL_TOUCH_TIMEOUT_INT_RAW (BIT(18)) 723 #define RTC_CNTL_TOUCH_TIMEOUT_INT_RAW_M (BIT(18)) 724 #define RTC_CNTL_TOUCH_TIMEOUT_INT_RAW_V 0x1 725 #define RTC_CNTL_TOUCH_TIMEOUT_INT_RAW_S 18 726 /* RTC_CNTL_COCPU_TRAP_INT_RAW : RO ;bitpos:[17] ;default: 1'b0 ; */ 727 /*description: cocpu trap interrupt raw.*/ 728 #define RTC_CNTL_COCPU_TRAP_INT_RAW (BIT(17)) 729 #define RTC_CNTL_COCPU_TRAP_INT_RAW_M (BIT(17)) 730 #define RTC_CNTL_COCPU_TRAP_INT_RAW_V 0x1 731 #define RTC_CNTL_COCPU_TRAP_INT_RAW_S 17 732 /* RTC_CNTL_XTAL32K_DEAD_INT_RAW : RO ;bitpos:[16] ;default: 1'b0 ; */ 733 /*description: xtal32k dead detection interrupt raw.*/ 734 #define RTC_CNTL_XTAL32K_DEAD_INT_RAW (BIT(16)) 735 #define RTC_CNTL_XTAL32K_DEAD_INT_RAW_M (BIT(16)) 736 #define RTC_CNTL_XTAL32K_DEAD_INT_RAW_V 0x1 737 #define RTC_CNTL_XTAL32K_DEAD_INT_RAW_S 16 738 /* RTC_CNTL_SWD_INT_RAW : RO ;bitpos:[15] ;default: 1'b0 ; */ 739 /*description: super watch dog interrupt raw.*/ 740 #define RTC_CNTL_SWD_INT_RAW (BIT(15)) 741 #define RTC_CNTL_SWD_INT_RAW_M (BIT(15)) 742 #define RTC_CNTL_SWD_INT_RAW_V 0x1 743 #define RTC_CNTL_SWD_INT_RAW_S 15 744 /* RTC_CNTL_SARADC2_INT_RAW : RO ;bitpos:[14] ;default: 1'b0 ; */ 745 /*description: saradc2 interrupt raw.*/ 746 #define RTC_CNTL_SARADC2_INT_RAW (BIT(14)) 747 #define RTC_CNTL_SARADC2_INT_RAW_M (BIT(14)) 748 #define RTC_CNTL_SARADC2_INT_RAW_V 0x1 749 #define RTC_CNTL_SARADC2_INT_RAW_S 14 750 /* RTC_CNTL_COCPU_INT_RAW : RO ;bitpos:[13] ;default: 1'b0 ; */ 751 /*description: riscV cocpu interrupt raw.*/ 752 #define RTC_CNTL_COCPU_INT_RAW (BIT(13)) 753 #define RTC_CNTL_COCPU_INT_RAW_M (BIT(13)) 754 #define RTC_CNTL_COCPU_INT_RAW_V 0x1 755 #define RTC_CNTL_COCPU_INT_RAW_S 13 756 /* RTC_CNTL_TSENS_INT_RAW : RO ;bitpos:[12] ;default: 1'b0 ; */ 757 /*description: tsens interrupt raw.*/ 758 #define RTC_CNTL_TSENS_INT_RAW (BIT(12)) 759 #define RTC_CNTL_TSENS_INT_RAW_M (BIT(12)) 760 #define RTC_CNTL_TSENS_INT_RAW_V 0x1 761 #define RTC_CNTL_TSENS_INT_RAW_S 12 762 /* RTC_CNTL_SARADC1_INT_RAW : RO ;bitpos:[11] ;default: 1'b0 ; */ 763 /*description: saradc1 interrupt raw.*/ 764 #define RTC_CNTL_SARADC1_INT_RAW (BIT(11)) 765 #define RTC_CNTL_SARADC1_INT_RAW_M (BIT(11)) 766 #define RTC_CNTL_SARADC1_INT_RAW_V 0x1 767 #define RTC_CNTL_SARADC1_INT_RAW_S 11 768 /* RTC_CNTL_MAIN_TIMER_INT_RAW : RO ;bitpos:[10] ;default: 1'b0 ; */ 769 /*description: RTC main timer interrupt raw.*/ 770 #define RTC_CNTL_MAIN_TIMER_INT_RAW (BIT(10)) 771 #define RTC_CNTL_MAIN_TIMER_INT_RAW_M (BIT(10)) 772 #define RTC_CNTL_MAIN_TIMER_INT_RAW_V 0x1 773 #define RTC_CNTL_MAIN_TIMER_INT_RAW_S 10 774 /* RTC_CNTL_BROWN_OUT_INT_RAW : RO ;bitpos:[9] ;default: 1'b0 ; */ 775 /*description: brown out interrupt raw.*/ 776 #define RTC_CNTL_BROWN_OUT_INT_RAW (BIT(9)) 777 #define RTC_CNTL_BROWN_OUT_INT_RAW_M (BIT(9)) 778 #define RTC_CNTL_BROWN_OUT_INT_RAW_V 0x1 779 #define RTC_CNTL_BROWN_OUT_INT_RAW_S 9 780 /* RTC_CNTL_TOUCH_INACTIVE_INT_RAW : RO ;bitpos:[8] ;default: 1'b0 ; */ 781 /*description: touch inactive interrupt raw.*/ 782 #define RTC_CNTL_TOUCH_INACTIVE_INT_RAW (BIT(8)) 783 #define RTC_CNTL_TOUCH_INACTIVE_INT_RAW_M (BIT(8)) 784 #define RTC_CNTL_TOUCH_INACTIVE_INT_RAW_V 0x1 785 #define RTC_CNTL_TOUCH_INACTIVE_INT_RAW_S 8 786 /* RTC_CNTL_TOUCH_ACTIVE_INT_RAW : RO ;bitpos:[7] ;default: 1'b0 ; */ 787 /*description: touch active interrupt raw.*/ 788 #define RTC_CNTL_TOUCH_ACTIVE_INT_RAW (BIT(7)) 789 #define RTC_CNTL_TOUCH_ACTIVE_INT_RAW_M (BIT(7)) 790 #define RTC_CNTL_TOUCH_ACTIVE_INT_RAW_V 0x1 791 #define RTC_CNTL_TOUCH_ACTIVE_INT_RAW_S 7 792 /* RTC_CNTL_TOUCH_DONE_INT_RAW : RO ;bitpos:[6] ;default: 1'b0 ; */ 793 /*description: touch interrupt raw.*/ 794 #define RTC_CNTL_TOUCH_DONE_INT_RAW (BIT(6)) 795 #define RTC_CNTL_TOUCH_DONE_INT_RAW_M (BIT(6)) 796 #define RTC_CNTL_TOUCH_DONE_INT_RAW_V 0x1 797 #define RTC_CNTL_TOUCH_DONE_INT_RAW_S 6 798 /* RTC_CNTL_ULP_CP_INT_RAW : RO ;bitpos:[5] ;default: 1'b0 ; */ 799 /*description: ULP-coprocessor interrupt raw.*/ 800 #define RTC_CNTL_ULP_CP_INT_RAW (BIT(5)) 801 #define RTC_CNTL_ULP_CP_INT_RAW_M (BIT(5)) 802 #define RTC_CNTL_ULP_CP_INT_RAW_V 0x1 803 #define RTC_CNTL_ULP_CP_INT_RAW_S 5 804 /* RTC_CNTL_TOUCH_SCAN_DONE_INT_RAW : RO ;bitpos:[4] ;default: 1'b0 ; */ 805 /*description: .*/ 806 #define RTC_CNTL_TOUCH_SCAN_DONE_INT_RAW (BIT(4)) 807 #define RTC_CNTL_TOUCH_SCAN_DONE_INT_RAW_M (BIT(4)) 808 #define RTC_CNTL_TOUCH_SCAN_DONE_INT_RAW_V 0x1 809 #define RTC_CNTL_TOUCH_SCAN_DONE_INT_RAW_S 4 810 /* RTC_CNTL_WDT_INT_RAW : RO ;bitpos:[3] ;default: 1'b0 ; */ 811 /*description: RTC WDT interrupt raw.*/ 812 #define RTC_CNTL_WDT_INT_RAW (BIT(3)) 813 #define RTC_CNTL_WDT_INT_RAW_M (BIT(3)) 814 #define RTC_CNTL_WDT_INT_RAW_V 0x1 815 #define RTC_CNTL_WDT_INT_RAW_S 3 816 /* RTC_CNTL_SDIO_IDLE_INT_RAW : RO ;bitpos:[2] ;default: 1'b0 ; */ 817 /*description: SDIO idle interrupt raw.*/ 818 #define RTC_CNTL_SDIO_IDLE_INT_RAW (BIT(2)) 819 #define RTC_CNTL_SDIO_IDLE_INT_RAW_M (BIT(2)) 820 #define RTC_CNTL_SDIO_IDLE_INT_RAW_V 0x1 821 #define RTC_CNTL_SDIO_IDLE_INT_RAW_S 2 822 /* RTC_CNTL_SLP_REJECT_INT_RAW : RO ;bitpos:[1] ;default: 1'b0 ; */ 823 /*description: sleep reject interrupt raw.*/ 824 #define RTC_CNTL_SLP_REJECT_INT_RAW (BIT(1)) 825 #define RTC_CNTL_SLP_REJECT_INT_RAW_M (BIT(1)) 826 #define RTC_CNTL_SLP_REJECT_INT_RAW_V 0x1 827 #define RTC_CNTL_SLP_REJECT_INT_RAW_S 1 828 /* RTC_CNTL_SLP_WAKEUP_INT_RAW : RO ;bitpos:[0] ;default: 1'b0 ; */ 829 /*description: sleep wakeup interrupt raw.*/ 830 #define RTC_CNTL_SLP_WAKEUP_INT_RAW (BIT(0)) 831 #define RTC_CNTL_SLP_WAKEUP_INT_RAW_M (BIT(0)) 832 #define RTC_CNTL_SLP_WAKEUP_INT_RAW_V 0x1 833 #define RTC_CNTL_SLP_WAKEUP_INT_RAW_S 0 834 835 #define RTC_CNTL_INT_ST_REG (DR_REG_RTCCNTL_BASE + 0x48) 836 /* RTC_CNTL_TOUCH_APPROACH_LOOP_DONE_INT_ST : RO ;bitpos:[20] ;default: 1'b0 ; */ 837 /*description: .*/ 838 #define RTC_CNTL_TOUCH_APPROACH_LOOP_DONE_INT_ST (BIT(20)) 839 #define RTC_CNTL_TOUCH_APPROACH_LOOP_DONE_INT_ST_M (BIT(20)) 840 #define RTC_CNTL_TOUCH_APPROACH_LOOP_DONE_INT_ST_V 0x1 841 #define RTC_CNTL_TOUCH_APPROACH_LOOP_DONE_INT_ST_S 20 842 /* RTC_CNTL_GLITCH_DET_INT_ST : RO ;bitpos:[19] ;default: 1'b0 ; */ 843 /*description: glitch_det_interrupt state.*/ 844 #define RTC_CNTL_GLITCH_DET_INT_ST (BIT(19)) 845 #define RTC_CNTL_GLITCH_DET_INT_ST_M (BIT(19)) 846 #define RTC_CNTL_GLITCH_DET_INT_ST_V 0x1 847 #define RTC_CNTL_GLITCH_DET_INT_ST_S 19 848 /* RTC_CNTL_TOUCH_TIMEOUT_INT_ST : RO ;bitpos:[18] ;default: 1'b0 ; */ 849 /*description: Touch timeout interrupt state.*/ 850 #define RTC_CNTL_TOUCH_TIMEOUT_INT_ST (BIT(18)) 851 #define RTC_CNTL_TOUCH_TIMEOUT_INT_ST_M (BIT(18)) 852 #define RTC_CNTL_TOUCH_TIMEOUT_INT_ST_V 0x1 853 #define RTC_CNTL_TOUCH_TIMEOUT_INT_ST_S 18 854 /* RTC_CNTL_COCPU_TRAP_INT_ST : RO ;bitpos:[17] ;default: 1'b0 ; */ 855 /*description: cocpu trap interrupt state.*/ 856 #define RTC_CNTL_COCPU_TRAP_INT_ST (BIT(17)) 857 #define RTC_CNTL_COCPU_TRAP_INT_ST_M (BIT(17)) 858 #define RTC_CNTL_COCPU_TRAP_INT_ST_V 0x1 859 #define RTC_CNTL_COCPU_TRAP_INT_ST_S 17 860 /* RTC_CNTL_XTAL32K_DEAD_INT_ST : RO ;bitpos:[16] ;default: 1'b0 ; */ 861 /*description: xtal32k dead detection interrupt state.*/ 862 #define RTC_CNTL_XTAL32K_DEAD_INT_ST (BIT(16)) 863 #define RTC_CNTL_XTAL32K_DEAD_INT_ST_M (BIT(16)) 864 #define RTC_CNTL_XTAL32K_DEAD_INT_ST_V 0x1 865 #define RTC_CNTL_XTAL32K_DEAD_INT_ST_S 16 866 /* RTC_CNTL_SWD_INT_ST : RO ;bitpos:[15] ;default: 1'b0 ; */ 867 /*description: super watch dog interrupt state.*/ 868 #define RTC_CNTL_SWD_INT_ST (BIT(15)) 869 #define RTC_CNTL_SWD_INT_ST_M (BIT(15)) 870 #define RTC_CNTL_SWD_INT_ST_V 0x1 871 #define RTC_CNTL_SWD_INT_ST_S 15 872 /* RTC_CNTL_SARADC2_INT_ST : RO ;bitpos:[14] ;default: 1'b0 ; */ 873 /*description: saradc2 interrupt state.*/ 874 #define RTC_CNTL_SARADC2_INT_ST (BIT(14)) 875 #define RTC_CNTL_SARADC2_INT_ST_M (BIT(14)) 876 #define RTC_CNTL_SARADC2_INT_ST_V 0x1 877 #define RTC_CNTL_SARADC2_INT_ST_S 14 878 /* RTC_CNTL_COCPU_INT_ST : RO ;bitpos:[13] ;default: 1'b0 ; */ 879 /*description: riscV cocpu interrupt state.*/ 880 #define RTC_CNTL_COCPU_INT_ST (BIT(13)) 881 #define RTC_CNTL_COCPU_INT_ST_M (BIT(13)) 882 #define RTC_CNTL_COCPU_INT_ST_V 0x1 883 #define RTC_CNTL_COCPU_INT_ST_S 13 884 /* RTC_CNTL_TSENS_INT_ST : RO ;bitpos:[12] ;default: 1'b0 ; */ 885 /*description: tsens interrupt state.*/ 886 #define RTC_CNTL_TSENS_INT_ST (BIT(12)) 887 #define RTC_CNTL_TSENS_INT_ST_M (BIT(12)) 888 #define RTC_CNTL_TSENS_INT_ST_V 0x1 889 #define RTC_CNTL_TSENS_INT_ST_S 12 890 /* RTC_CNTL_SARADC1_INT_ST : RO ;bitpos:[11] ;default: 1'b0 ; */ 891 /*description: saradc1 interrupt state.*/ 892 #define RTC_CNTL_SARADC1_INT_ST (BIT(11)) 893 #define RTC_CNTL_SARADC1_INT_ST_M (BIT(11)) 894 #define RTC_CNTL_SARADC1_INT_ST_V 0x1 895 #define RTC_CNTL_SARADC1_INT_ST_S 11 896 /* RTC_CNTL_MAIN_TIMER_INT_ST : RO ;bitpos:[10] ;default: 1'b0 ; */ 897 /*description: RTC main timer interrupt state.*/ 898 #define RTC_CNTL_MAIN_TIMER_INT_ST (BIT(10)) 899 #define RTC_CNTL_MAIN_TIMER_INT_ST_M (BIT(10)) 900 #define RTC_CNTL_MAIN_TIMER_INT_ST_V 0x1 901 #define RTC_CNTL_MAIN_TIMER_INT_ST_S 10 902 /* RTC_CNTL_BROWN_OUT_INT_ST : RO ;bitpos:[9] ;default: 1'b0 ; */ 903 /*description: brown out interrupt state.*/ 904 #define RTC_CNTL_BROWN_OUT_INT_ST (BIT(9)) 905 #define RTC_CNTL_BROWN_OUT_INT_ST_M (BIT(9)) 906 #define RTC_CNTL_BROWN_OUT_INT_ST_V 0x1 907 #define RTC_CNTL_BROWN_OUT_INT_ST_S 9 908 /* RTC_CNTL_TOUCH_INACTIVE_INT_ST : RO ;bitpos:[8] ;default: 1'b0 ; */ 909 /*description: touch inactive interrupt state.*/ 910 #define RTC_CNTL_TOUCH_INACTIVE_INT_ST (BIT(8)) 911 #define RTC_CNTL_TOUCH_INACTIVE_INT_ST_M (BIT(8)) 912 #define RTC_CNTL_TOUCH_INACTIVE_INT_ST_V 0x1 913 #define RTC_CNTL_TOUCH_INACTIVE_INT_ST_S 8 914 /* RTC_CNTL_TOUCH_ACTIVE_INT_ST : RO ;bitpos:[7] ;default: 1'b0 ; */ 915 /*description: touch active interrupt state.*/ 916 #define RTC_CNTL_TOUCH_ACTIVE_INT_ST (BIT(7)) 917 #define RTC_CNTL_TOUCH_ACTIVE_INT_ST_M (BIT(7)) 918 #define RTC_CNTL_TOUCH_ACTIVE_INT_ST_V 0x1 919 #define RTC_CNTL_TOUCH_ACTIVE_INT_ST_S 7 920 /* RTC_CNTL_TOUCH_DONE_INT_ST : RO ;bitpos:[6] ;default: 1'b0 ; */ 921 /*description: touch done interrupt state.*/ 922 #define RTC_CNTL_TOUCH_DONE_INT_ST (BIT(6)) 923 #define RTC_CNTL_TOUCH_DONE_INT_ST_M (BIT(6)) 924 #define RTC_CNTL_TOUCH_DONE_INT_ST_V 0x1 925 #define RTC_CNTL_TOUCH_DONE_INT_ST_S 6 926 /* RTC_CNTL_ULP_CP_INT_ST : RO ;bitpos:[5] ;default: 1'b0 ; */ 927 /*description: ULP-coprocessor interrupt state.*/ 928 #define RTC_CNTL_ULP_CP_INT_ST (BIT(5)) 929 #define RTC_CNTL_ULP_CP_INT_ST_M (BIT(5)) 930 #define RTC_CNTL_ULP_CP_INT_ST_V 0x1 931 #define RTC_CNTL_ULP_CP_INT_ST_S 5 932 /* RTC_CNTL_TOUCH_SCAN_DONE_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */ 933 /*description: .*/ 934 #define RTC_CNTL_TOUCH_SCAN_DONE_INT_ST (BIT(4)) 935 #define RTC_CNTL_TOUCH_SCAN_DONE_INT_ST_M (BIT(4)) 936 #define RTC_CNTL_TOUCH_SCAN_DONE_INT_ST_V 0x1 937 #define RTC_CNTL_TOUCH_SCAN_DONE_INT_ST_S 4 938 /* RTC_CNTL_WDT_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */ 939 /*description: RTC WDT interrupt state.*/ 940 #define RTC_CNTL_WDT_INT_ST (BIT(3)) 941 #define RTC_CNTL_WDT_INT_ST_M (BIT(3)) 942 #define RTC_CNTL_WDT_INT_ST_V 0x1 943 #define RTC_CNTL_WDT_INT_ST_S 3 944 /* RTC_CNTL_SDIO_IDLE_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */ 945 /*description: SDIO idle interrupt state.*/ 946 #define RTC_CNTL_SDIO_IDLE_INT_ST (BIT(2)) 947 #define RTC_CNTL_SDIO_IDLE_INT_ST_M (BIT(2)) 948 #define RTC_CNTL_SDIO_IDLE_INT_ST_V 0x1 949 #define RTC_CNTL_SDIO_IDLE_INT_ST_S 2 950 /* RTC_CNTL_SLP_REJECT_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */ 951 /*description: sleep reject interrupt state.*/ 952 #define RTC_CNTL_SLP_REJECT_INT_ST (BIT(1)) 953 #define RTC_CNTL_SLP_REJECT_INT_ST_M (BIT(1)) 954 #define RTC_CNTL_SLP_REJECT_INT_ST_V 0x1 955 #define RTC_CNTL_SLP_REJECT_INT_ST_S 1 956 /* RTC_CNTL_SLP_WAKEUP_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */ 957 /*description: sleep wakeup interrupt state.*/ 958 #define RTC_CNTL_SLP_WAKEUP_INT_ST (BIT(0)) 959 #define RTC_CNTL_SLP_WAKEUP_INT_ST_M (BIT(0)) 960 #define RTC_CNTL_SLP_WAKEUP_INT_ST_V 0x1 961 #define RTC_CNTL_SLP_WAKEUP_INT_ST_S 0 962 963 #define RTC_CNTL_INT_CLR_REG (DR_REG_RTCCNTL_BASE + 0x4C) 964 /* RTC_CNTL_TOUCH_APPROACH_LOOP_DONE_INT_CLR : WO ;bitpos:[20] ;default: 1'b0 ; */ 965 /*description: .*/ 966 #define RTC_CNTL_TOUCH_APPROACH_LOOP_DONE_INT_CLR (BIT(20)) 967 #define RTC_CNTL_TOUCH_APPROACH_LOOP_DONE_INT_CLR_M (BIT(20)) 968 #define RTC_CNTL_TOUCH_APPROACH_LOOP_DONE_INT_CLR_V 0x1 969 #define RTC_CNTL_TOUCH_APPROACH_LOOP_DONE_INT_CLR_S 20 970 /* RTC_CNTL_GLITCH_DET_INT_CLR : WO ;bitpos:[19] ;default: 1'b0 ; */ 971 /*description: Clear glitch det interrupt state.*/ 972 #define RTC_CNTL_GLITCH_DET_INT_CLR (BIT(19)) 973 #define RTC_CNTL_GLITCH_DET_INT_CLR_M (BIT(19)) 974 #define RTC_CNTL_GLITCH_DET_INT_CLR_V 0x1 975 #define RTC_CNTL_GLITCH_DET_INT_CLR_S 19 976 /* RTC_CNTL_TOUCH_TIMEOUT_INT_CLR : WO ;bitpos:[18] ;default: 1'b0 ; */ 977 /*description: Clear touch timeout interrupt state.*/ 978 #define RTC_CNTL_TOUCH_TIMEOUT_INT_CLR (BIT(18)) 979 #define RTC_CNTL_TOUCH_TIMEOUT_INT_CLR_M (BIT(18)) 980 #define RTC_CNTL_TOUCH_TIMEOUT_INT_CLR_V 0x1 981 #define RTC_CNTL_TOUCH_TIMEOUT_INT_CLR_S 18 982 /* RTC_CNTL_COCPU_TRAP_INT_CLR : WO ;bitpos:[17] ;default: 1'b0 ; */ 983 /*description: Clear cocpu trap interrupt state.*/ 984 #define RTC_CNTL_COCPU_TRAP_INT_CLR (BIT(17)) 985 #define RTC_CNTL_COCPU_TRAP_INT_CLR_M (BIT(17)) 986 #define RTC_CNTL_COCPU_TRAP_INT_CLR_V 0x1 987 #define RTC_CNTL_COCPU_TRAP_INT_CLR_S 17 988 /* RTC_CNTL_XTAL32K_DEAD_INT_CLR : WO ;bitpos:[16] ;default: 1'b0 ; */ 989 /*description: Clear RTC WDT interrupt state.*/ 990 #define RTC_CNTL_XTAL32K_DEAD_INT_CLR (BIT(16)) 991 #define RTC_CNTL_XTAL32K_DEAD_INT_CLR_M (BIT(16)) 992 #define RTC_CNTL_XTAL32K_DEAD_INT_CLR_V 0x1 993 #define RTC_CNTL_XTAL32K_DEAD_INT_CLR_S 16 994 /* RTC_CNTL_SWD_INT_CLR : WO ;bitpos:[15] ;default: 1'b0 ; */ 995 /*description: Clear super watch dog interrupt state.*/ 996 #define RTC_CNTL_SWD_INT_CLR (BIT(15)) 997 #define RTC_CNTL_SWD_INT_CLR_M (BIT(15)) 998 #define RTC_CNTL_SWD_INT_CLR_V 0x1 999 #define RTC_CNTL_SWD_INT_CLR_S 15 1000 /* RTC_CNTL_SARADC2_INT_CLR : WO ;bitpos:[14] ;default: 1'b0 ; */ 1001 /*description: Clear saradc2 interrupt state.*/ 1002 #define RTC_CNTL_SARADC2_INT_CLR (BIT(14)) 1003 #define RTC_CNTL_SARADC2_INT_CLR_M (BIT(14)) 1004 #define RTC_CNTL_SARADC2_INT_CLR_V 0x1 1005 #define RTC_CNTL_SARADC2_INT_CLR_S 14 1006 /* RTC_CNTL_COCPU_INT_CLR : WO ;bitpos:[13] ;default: 1'b0 ; */ 1007 /*description: Clear riscV cocpu interrupt state.*/ 1008 #define RTC_CNTL_COCPU_INT_CLR (BIT(13)) 1009 #define RTC_CNTL_COCPU_INT_CLR_M (BIT(13)) 1010 #define RTC_CNTL_COCPU_INT_CLR_V 0x1 1011 #define RTC_CNTL_COCPU_INT_CLR_S 13 1012 /* RTC_CNTL_TSENS_INT_CLR : WO ;bitpos:[12] ;default: 1'b0 ; */ 1013 /*description: Clear tsens interrupt state.*/ 1014 #define RTC_CNTL_TSENS_INT_CLR (BIT(12)) 1015 #define RTC_CNTL_TSENS_INT_CLR_M (BIT(12)) 1016 #define RTC_CNTL_TSENS_INT_CLR_V 0x1 1017 #define RTC_CNTL_TSENS_INT_CLR_S 12 1018 /* RTC_CNTL_SARADC1_INT_CLR : WO ;bitpos:[11] ;default: 1'b0 ; */ 1019 /*description: Clear saradc1 interrupt state.*/ 1020 #define RTC_CNTL_SARADC1_INT_CLR (BIT(11)) 1021 #define RTC_CNTL_SARADC1_INT_CLR_M (BIT(11)) 1022 #define RTC_CNTL_SARADC1_INT_CLR_V 0x1 1023 #define RTC_CNTL_SARADC1_INT_CLR_S 11 1024 /* RTC_CNTL_MAIN_TIMER_INT_CLR : WO ;bitpos:[10] ;default: 1'b0 ; */ 1025 /*description: Clear RTC main timer interrupt state.*/ 1026 #define RTC_CNTL_MAIN_TIMER_INT_CLR (BIT(10)) 1027 #define RTC_CNTL_MAIN_TIMER_INT_CLR_M (BIT(10)) 1028 #define RTC_CNTL_MAIN_TIMER_INT_CLR_V 0x1 1029 #define RTC_CNTL_MAIN_TIMER_INT_CLR_S 10 1030 /* RTC_CNTL_BROWN_OUT_INT_CLR : WO ;bitpos:[9] ;default: 1'b0 ; */ 1031 /*description: Clear brown out interrupt state.*/ 1032 #define RTC_CNTL_BROWN_OUT_INT_CLR (BIT(9)) 1033 #define RTC_CNTL_BROWN_OUT_INT_CLR_M (BIT(9)) 1034 #define RTC_CNTL_BROWN_OUT_INT_CLR_V 0x1 1035 #define RTC_CNTL_BROWN_OUT_INT_CLR_S 9 1036 /* RTC_CNTL_TOUCH_INACTIVE_INT_CLR : WO ;bitpos:[8] ;default: 1'b0 ; */ 1037 /*description: Clear touch inactive interrupt state.*/ 1038 #define RTC_CNTL_TOUCH_INACTIVE_INT_CLR (BIT(8)) 1039 #define RTC_CNTL_TOUCH_INACTIVE_INT_CLR_M (BIT(8)) 1040 #define RTC_CNTL_TOUCH_INACTIVE_INT_CLR_V 0x1 1041 #define RTC_CNTL_TOUCH_INACTIVE_INT_CLR_S 8 1042 /* RTC_CNTL_TOUCH_ACTIVE_INT_CLR : WO ;bitpos:[7] ;default: 1'b0 ; */ 1043 /*description: Clear touch active interrupt state.*/ 1044 #define RTC_CNTL_TOUCH_ACTIVE_INT_CLR (BIT(7)) 1045 #define RTC_CNTL_TOUCH_ACTIVE_INT_CLR_M (BIT(7)) 1046 #define RTC_CNTL_TOUCH_ACTIVE_INT_CLR_V 0x1 1047 #define RTC_CNTL_TOUCH_ACTIVE_INT_CLR_S 7 1048 /* RTC_CNTL_TOUCH_DONE_INT_CLR : WO ;bitpos:[6] ;default: 1'b0 ; */ 1049 /*description: Clear touch done interrupt state.*/ 1050 #define RTC_CNTL_TOUCH_DONE_INT_CLR (BIT(6)) 1051 #define RTC_CNTL_TOUCH_DONE_INT_CLR_M (BIT(6)) 1052 #define RTC_CNTL_TOUCH_DONE_INT_CLR_V 0x1 1053 #define RTC_CNTL_TOUCH_DONE_INT_CLR_S 6 1054 /* RTC_CNTL_ULP_CP_INT_CLR : WO ;bitpos:[5] ;default: 1'b0 ; */ 1055 /*description: Clear ULP-coprocessor interrupt state.*/ 1056 #define RTC_CNTL_ULP_CP_INT_CLR (BIT(5)) 1057 #define RTC_CNTL_ULP_CP_INT_CLR_M (BIT(5)) 1058 #define RTC_CNTL_ULP_CP_INT_CLR_V 0x1 1059 #define RTC_CNTL_ULP_CP_INT_CLR_S 5 1060 /* RTC_CNTL_TOUCH_SCAN_DONE_INT_CLR : WO ;bitpos:[4] ;default: 1'b0 ; */ 1061 /*description: .*/ 1062 #define RTC_CNTL_TOUCH_SCAN_DONE_INT_CLR (BIT(4)) 1063 #define RTC_CNTL_TOUCH_SCAN_DONE_INT_CLR_M (BIT(4)) 1064 #define RTC_CNTL_TOUCH_SCAN_DONE_INT_CLR_V 0x1 1065 #define RTC_CNTL_TOUCH_SCAN_DONE_INT_CLR_S 4 1066 /* RTC_CNTL_WDT_INT_CLR : WO ;bitpos:[3] ;default: 1'b0 ; */ 1067 /*description: Clear RTC WDT interrupt state.*/ 1068 #define RTC_CNTL_WDT_INT_CLR (BIT(3)) 1069 #define RTC_CNTL_WDT_INT_CLR_M (BIT(3)) 1070 #define RTC_CNTL_WDT_INT_CLR_V 0x1 1071 #define RTC_CNTL_WDT_INT_CLR_S 3 1072 /* RTC_CNTL_SDIO_IDLE_INT_CLR : WO ;bitpos:[2] ;default: 1'b0 ; */ 1073 /*description: Clear SDIO idle interrupt state.*/ 1074 #define RTC_CNTL_SDIO_IDLE_INT_CLR (BIT(2)) 1075 #define RTC_CNTL_SDIO_IDLE_INT_CLR_M (BIT(2)) 1076 #define RTC_CNTL_SDIO_IDLE_INT_CLR_V 0x1 1077 #define RTC_CNTL_SDIO_IDLE_INT_CLR_S 2 1078 /* RTC_CNTL_SLP_REJECT_INT_CLR : WO ;bitpos:[1] ;default: 1'b0 ; */ 1079 /*description: Clear sleep reject interrupt state.*/ 1080 #define RTC_CNTL_SLP_REJECT_INT_CLR (BIT(1)) 1081 #define RTC_CNTL_SLP_REJECT_INT_CLR_M (BIT(1)) 1082 #define RTC_CNTL_SLP_REJECT_INT_CLR_V 0x1 1083 #define RTC_CNTL_SLP_REJECT_INT_CLR_S 1 1084 /* RTC_CNTL_SLP_WAKEUP_INT_CLR : WO ;bitpos:[0] ;default: 1'b0 ; */ 1085 /*description: Clear sleep wakeup interrupt state.*/ 1086 #define RTC_CNTL_SLP_WAKEUP_INT_CLR (BIT(0)) 1087 #define RTC_CNTL_SLP_WAKEUP_INT_CLR_M (BIT(0)) 1088 #define RTC_CNTL_SLP_WAKEUP_INT_CLR_V 0x1 1089 #define RTC_CNTL_SLP_WAKEUP_INT_CLR_S 0 1090 1091 #define RTC_CNTL_STORE0_REG (DR_REG_RTCCNTL_BASE + 0x50) 1092 /* RTC_CNTL_SCRATCH0 : R/W ;bitpos:[31:0] ;default: 0 ; */ 1093 /*description: .*/ 1094 #define RTC_CNTL_SCRATCH0 0xFFFFFFFF 1095 #define RTC_CNTL_SCRATCH0_M ((RTC_CNTL_SCRATCH0_V)<<(RTC_CNTL_SCRATCH0_S)) 1096 #define RTC_CNTL_SCRATCH0_V 0xFFFFFFFF 1097 #define RTC_CNTL_SCRATCH0_S 0 1098 1099 #define RTC_CNTL_STORE1_REG (DR_REG_RTCCNTL_BASE + 0x54) 1100 /* RTC_CNTL_SCRATCH1 : R/W ;bitpos:[31:0] ;default: 0 ; */ 1101 /*description: .*/ 1102 #define RTC_CNTL_SCRATCH1 0xFFFFFFFF 1103 #define RTC_CNTL_SCRATCH1_M ((RTC_CNTL_SCRATCH1_V)<<(RTC_CNTL_SCRATCH1_S)) 1104 #define RTC_CNTL_SCRATCH1_V 0xFFFFFFFF 1105 #define RTC_CNTL_SCRATCH1_S 0 1106 1107 #define RTC_CNTL_STORE2_REG (DR_REG_RTCCNTL_BASE + 0x58) 1108 /* RTC_CNTL_SCRATCH2 : R/W ;bitpos:[31:0] ;default: 0 ; */ 1109 /*description: .*/ 1110 #define RTC_CNTL_SCRATCH2 0xFFFFFFFF 1111 #define RTC_CNTL_SCRATCH2_M ((RTC_CNTL_SCRATCH2_V)<<(RTC_CNTL_SCRATCH2_S)) 1112 #define RTC_CNTL_SCRATCH2_V 0xFFFFFFFF 1113 #define RTC_CNTL_SCRATCH2_S 0 1114 1115 #define RTC_CNTL_STORE3_REG (DR_REG_RTCCNTL_BASE + 0x5C) 1116 /* RTC_CNTL_SCRATCH3 : R/W ;bitpos:[31:0] ;default: 0 ; */ 1117 /*description: .*/ 1118 #define RTC_CNTL_SCRATCH3 0xFFFFFFFF 1119 #define RTC_CNTL_SCRATCH3_M ((RTC_CNTL_SCRATCH3_V)<<(RTC_CNTL_SCRATCH3_S)) 1120 #define RTC_CNTL_SCRATCH3_V 0xFFFFFFFF 1121 #define RTC_CNTL_SCRATCH3_S 0 1122 1123 #define RTC_CNTL_EXT_XTL_CONF_REG (DR_REG_RTCCNTL_BASE + 0x60) 1124 /* RTC_CNTL_XTL_EXT_CTR_EN : R/W ;bitpos:[31] ;default: 1'b0 ; */ 1125 /*description: .*/ 1126 #define RTC_CNTL_XTL_EXT_CTR_EN (BIT(31)) 1127 #define RTC_CNTL_XTL_EXT_CTR_EN_M (BIT(31)) 1128 #define RTC_CNTL_XTL_EXT_CTR_EN_V 0x1 1129 #define RTC_CNTL_XTL_EXT_CTR_EN_S 31 1130 /* RTC_CNTL_XTL_EXT_CTR_LV : R/W ;bitpos:[30] ;default: 1'b0 ; */ 1131 /*description: 0: power down XTAL at high level.*/ 1132 #define RTC_CNTL_XTL_EXT_CTR_LV (BIT(30)) 1133 #define RTC_CNTL_XTL_EXT_CTR_LV_M (BIT(30)) 1134 #define RTC_CNTL_XTL_EXT_CTR_LV_V 0x1 1135 #define RTC_CNTL_XTL_EXT_CTR_LV_S 30 1136 /* RTC_CNTL_XTAL32K_GPIO_SEL : R/W ;bitpos:[23] ;default: 1'b0 ; */ 1137 /*description: XTAL_32K sel. 0: external XTAL_32K.*/ 1138 #define RTC_CNTL_XTAL32K_GPIO_SEL (BIT(23)) 1139 #define RTC_CNTL_XTAL32K_GPIO_SEL_M (BIT(23)) 1140 #define RTC_CNTL_XTAL32K_GPIO_SEL_V 0x1 1141 #define RTC_CNTL_XTAL32K_GPIO_SEL_S 23 1142 /* RTC_CNTL_WDT_STATE : RO ;bitpos:[22:20] ;default: 3'h0 ; */ 1143 /*description: state of 32k_wdt.*/ 1144 #define RTC_CNTL_WDT_STATE 0x00000007 1145 #define RTC_CNTL_WDT_STATE_M ((RTC_CNTL_WDT_STATE_V)<<(RTC_CNTL_WDT_STATE_S)) 1146 #define RTC_CNTL_WDT_STATE_V 0x7 1147 #define RTC_CNTL_WDT_STATE_S 20 1148 /* RTC_CNTL_DAC_XTAL_32K : R/W ;bitpos:[19:17] ;default: 3'd3 ; */ 1149 /*description: DAC_XTAL_32K.*/ 1150 #define RTC_CNTL_DAC_XTAL_32K 0x00000007 1151 #define RTC_CNTL_DAC_XTAL_32K_M ((RTC_CNTL_DAC_XTAL_32K_V)<<(RTC_CNTL_DAC_XTAL_32K_S)) 1152 #define RTC_CNTL_DAC_XTAL_32K_V 0x7 1153 #define RTC_CNTL_DAC_XTAL_32K_S 17 1154 /* RTC_CNTL_XPD_XTAL_32K : R/W ;bitpos:[16] ;default: 1'd0 ; */ 1155 /*description: XPD_XTAL_32K.*/ 1156 #define RTC_CNTL_XPD_XTAL_32K (BIT(16)) 1157 #define RTC_CNTL_XPD_XTAL_32K_M (BIT(16)) 1158 #define RTC_CNTL_XPD_XTAL_32K_V 0x1 1159 #define RTC_CNTL_XPD_XTAL_32K_S 16 1160 /* RTC_CNTL_DRES_XTAL_32K : R/W ;bitpos:[15:13] ;default: 3'd3 ; */ 1161 /*description: DRES_XTAL_32K.*/ 1162 #define RTC_CNTL_DRES_XTAL_32K 0x00000007 1163 #define RTC_CNTL_DRES_XTAL_32K_M ((RTC_CNTL_DRES_XTAL_32K_V)<<(RTC_CNTL_DRES_XTAL_32K_S)) 1164 #define RTC_CNTL_DRES_XTAL_32K_V 0x7 1165 #define RTC_CNTL_DRES_XTAL_32K_S 13 1166 /* RTC_CNTL_DGM_XTAL_32K : R/W ;bitpos:[12:10] ;default: 3'd3 ; */ 1167 /*description: xtal_32k gm control.*/ 1168 #define RTC_CNTL_DGM_XTAL_32K 0x00000007 1169 #define RTC_CNTL_DGM_XTAL_32K_M ((RTC_CNTL_DGM_XTAL_32K_V)<<(RTC_CNTL_DGM_XTAL_32K_S)) 1170 #define RTC_CNTL_DGM_XTAL_32K_V 0x7 1171 #define RTC_CNTL_DGM_XTAL_32K_S 10 1172 /* RTC_CNTL_DBUF_XTAL_32K : R/W ;bitpos:[9] ;default: 1'b0 ; */ 1173 /*description: 0: single-end buffer 1: differential buffer.*/ 1174 #define RTC_CNTL_DBUF_XTAL_32K (BIT(9)) 1175 #define RTC_CNTL_DBUF_XTAL_32K_M (BIT(9)) 1176 #define RTC_CNTL_DBUF_XTAL_32K_V 0x1 1177 #define RTC_CNTL_DBUF_XTAL_32K_S 9 1178 /* RTC_CNTL_ENCKINIT_XTAL_32K : R/W ;bitpos:[8] ;default: 1'b0 ; */ 1179 /*description: apply an internal clock to help xtal 32k to start.*/ 1180 #define RTC_CNTL_ENCKINIT_XTAL_32K (BIT(8)) 1181 #define RTC_CNTL_ENCKINIT_XTAL_32K_M (BIT(8)) 1182 #define RTC_CNTL_ENCKINIT_XTAL_32K_V 0x1 1183 #define RTC_CNTL_ENCKINIT_XTAL_32K_S 8 1184 /* RTC_CNTL_XTAL32K_XPD_FORCE : R/W ;bitpos:[7] ;default: 1'b1 ; */ 1185 /*description: Xtal 32k xpd control by sw or fsm.*/ 1186 #define RTC_CNTL_XTAL32K_XPD_FORCE (BIT(7)) 1187 #define RTC_CNTL_XTAL32K_XPD_FORCE_M (BIT(7)) 1188 #define RTC_CNTL_XTAL32K_XPD_FORCE_V 0x1 1189 #define RTC_CNTL_XTAL32K_XPD_FORCE_S 7 1190 /* RTC_CNTL_XTAL32K_AUTO_RETURN : R/W ;bitpos:[6] ;default: 1'b0 ; */ 1191 /*description: xtal 32k switch back xtal when xtal is restarted.*/ 1192 #define RTC_CNTL_XTAL32K_AUTO_RETURN (BIT(6)) 1193 #define RTC_CNTL_XTAL32K_AUTO_RETURN_M (BIT(6)) 1194 #define RTC_CNTL_XTAL32K_AUTO_RETURN_V 0x1 1195 #define RTC_CNTL_XTAL32K_AUTO_RETURN_S 6 1196 /* RTC_CNTL_XTAL32K_AUTO_RESTART : R/W ;bitpos:[5] ;default: 1'b0 ; */ 1197 /*description: xtal 32k restart xtal when xtal is dead.*/ 1198 #define RTC_CNTL_XTAL32K_AUTO_RESTART (BIT(5)) 1199 #define RTC_CNTL_XTAL32K_AUTO_RESTART_M (BIT(5)) 1200 #define RTC_CNTL_XTAL32K_AUTO_RESTART_V 0x1 1201 #define RTC_CNTL_XTAL32K_AUTO_RESTART_S 5 1202 /* RTC_CNTL_XTAL32K_AUTO_BACKUP : R/W ;bitpos:[4] ;default: 1'b0 ; */ 1203 /*description: xtal 32k switch to back up clock when xtal is dead.*/ 1204 #define RTC_CNTL_XTAL32K_AUTO_BACKUP (BIT(4)) 1205 #define RTC_CNTL_XTAL32K_AUTO_BACKUP_M (BIT(4)) 1206 #define RTC_CNTL_XTAL32K_AUTO_BACKUP_V 0x1 1207 #define RTC_CNTL_XTAL32K_AUTO_BACKUP_S 4 1208 /* RTC_CNTL_XTAL32K_EXT_CLK_FO : R/W ;bitpos:[3] ;default: 1'b0 ; */ 1209 /*description: xtal 32k external xtal clock force on.*/ 1210 #define RTC_CNTL_XTAL32K_EXT_CLK_FO (BIT(3)) 1211 #define RTC_CNTL_XTAL32K_EXT_CLK_FO_M (BIT(3)) 1212 #define RTC_CNTL_XTAL32K_EXT_CLK_FO_V 0x1 1213 #define RTC_CNTL_XTAL32K_EXT_CLK_FO_S 3 1214 /* RTC_CNTL_XTAL32K_WDT_RESET : R/W ;bitpos:[2] ;default: 1'b0 ; */ 1215 /*description: xtal 32k watch dog sw reset.*/ 1216 #define RTC_CNTL_XTAL32K_WDT_RESET (BIT(2)) 1217 #define RTC_CNTL_XTAL32K_WDT_RESET_M (BIT(2)) 1218 #define RTC_CNTL_XTAL32K_WDT_RESET_V 0x1 1219 #define RTC_CNTL_XTAL32K_WDT_RESET_S 2 1220 /* RTC_CNTL_XTAL32K_WDT_CLK_FO : R/W ;bitpos:[1] ;default: 1'b0 ; */ 1221 /*description: xtal 32k watch dog clock force on.*/ 1222 #define RTC_CNTL_XTAL32K_WDT_CLK_FO (BIT(1)) 1223 #define RTC_CNTL_XTAL32K_WDT_CLK_FO_M (BIT(1)) 1224 #define RTC_CNTL_XTAL32K_WDT_CLK_FO_V 0x1 1225 #define RTC_CNTL_XTAL32K_WDT_CLK_FO_S 1 1226 /* RTC_CNTL_XTAL32K_WDT_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */ 1227 /*description: xtal 32k watch dog enable.*/ 1228 #define RTC_CNTL_XTAL32K_WDT_EN (BIT(0)) 1229 #define RTC_CNTL_XTAL32K_WDT_EN_M (BIT(0)) 1230 #define RTC_CNTL_XTAL32K_WDT_EN_V 0x1 1231 #define RTC_CNTL_XTAL32K_WDT_EN_S 0 1232 1233 #define RTC_CNTL_EXT_WAKEUP_CONF_REG (DR_REG_RTCCNTL_BASE + 0x64) 1234 /* RTC_CNTL_EXT_WAKEUP1_LV : R/W ;bitpos:[31] ;default: 1'b0 ; */ 1235 /*description: .*/ 1236 #define RTC_CNTL_EXT_WAKEUP1_LV (BIT(31)) 1237 #define RTC_CNTL_EXT_WAKEUP1_LV_M (BIT(31)) 1238 #define RTC_CNTL_EXT_WAKEUP1_LV_V 0x1 1239 #define RTC_CNTL_EXT_WAKEUP1_LV_S 31 1240 /* RTC_CNTL_EXT_WAKEUP0_LV : R/W ;bitpos:[30] ;default: 1'b0 ; */ 1241 /*description: 0: external wakeup at low level.*/ 1242 #define RTC_CNTL_EXT_WAKEUP0_LV (BIT(30)) 1243 #define RTC_CNTL_EXT_WAKEUP0_LV_M (BIT(30)) 1244 #define RTC_CNTL_EXT_WAKEUP0_LV_V 0x1 1245 #define RTC_CNTL_EXT_WAKEUP0_LV_S 30 1246 /* RTC_CNTL_GPIO_WAKEUP_FILTER : R/W ;bitpos:[29] ;default: 1'd0 ; */ 1247 /*description: enable filter for gpio wakeup event.*/ 1248 #define RTC_CNTL_GPIO_WAKEUP_FILTER (BIT(29)) 1249 #define RTC_CNTL_GPIO_WAKEUP_FILTER_M (BIT(29)) 1250 #define RTC_CNTL_GPIO_WAKEUP_FILTER_V 0x1 1251 #define RTC_CNTL_GPIO_WAKEUP_FILTER_S 29 1252 1253 #define RTC_CNTL_SLP_REJECT_CONF_REG (DR_REG_RTCCNTL_BASE + 0x68) 1254 /* RTC_CNTL_DEEP_SLP_REJECT_EN : R/W ;bitpos:[31] ;default: 1'b0 ; */ 1255 /*description: enable reject for deep sleep.*/ 1256 #define RTC_CNTL_DEEP_SLP_REJECT_EN (BIT(31)) 1257 #define RTC_CNTL_DEEP_SLP_REJECT_EN_M (BIT(31)) 1258 #define RTC_CNTL_DEEP_SLP_REJECT_EN_V 0x1 1259 #define RTC_CNTL_DEEP_SLP_REJECT_EN_S 31 1260 /* RTC_CNTL_LIGHT_SLP_REJECT_EN : R/W ;bitpos:[30] ;default: 1'b0 ; */ 1261 /*description: enable reject for light sleep.*/ 1262 #define RTC_CNTL_LIGHT_SLP_REJECT_EN (BIT(30)) 1263 #define RTC_CNTL_LIGHT_SLP_REJECT_EN_M (BIT(30)) 1264 #define RTC_CNTL_LIGHT_SLP_REJECT_EN_V 0x1 1265 #define RTC_CNTL_LIGHT_SLP_REJECT_EN_S 30 1266 /* RTC_CNTL_SLEEP_REJECT_ENA : R/W ;bitpos:[29:12] ;default: 17'd0 ; */ 1267 /*description: sleep reject enable.*/ 1268 #define RTC_CNTL_SLEEP_REJECT_ENA 0x0003FFFF 1269 #define RTC_CNTL_SLEEP_REJECT_ENA_M ((RTC_CNTL_SLEEP_REJECT_ENA_V)<<(RTC_CNTL_SLEEP_REJECT_ENA_S)) 1270 #define RTC_CNTL_SLEEP_REJECT_ENA_V 0x3FFFF 1271 #define RTC_CNTL_SLEEP_REJECT_ENA_S 12 1272 1273 #define RTC_CNTL_CPU_PERIOD_CONF_REG (DR_REG_RTCCNTL_BASE + 0x6C) 1274 /* RTC_CNTL_CPUPERIOD_SEL : R/W ;bitpos:[31:30] ;default: 2'b00 ; */ 1275 /*description: .*/ 1276 #define RTC_CNTL_CPUPERIOD_SEL 0x00000003 1277 #define RTC_CNTL_CPUPERIOD_SEL_M ((RTC_CNTL_CPUPERIOD_SEL_V)<<(RTC_CNTL_CPUPERIOD_SEL_S)) 1278 #define RTC_CNTL_CPUPERIOD_SEL_V 0x3 1279 #define RTC_CNTL_CPUPERIOD_SEL_S 30 1280 /* RTC_CNTL_CPUSEL_CONF : R/W ;bitpos:[29] ;default: 1'b0 ; */ 1281 /*description: CPU sel option.*/ 1282 #define RTC_CNTL_CPUSEL_CONF (BIT(29)) 1283 #define RTC_CNTL_CPUSEL_CONF_M (BIT(29)) 1284 #define RTC_CNTL_CPUSEL_CONF_V 0x1 1285 #define RTC_CNTL_CPUSEL_CONF_S 29 1286 1287 #define RTC_CNTL_SDIO_ACT_CONF_REG (DR_REG_RTCCNTL_BASE + 0x70) 1288 /* RTC_CNTL_SDIO_ACT_DNUM : R/W ;bitpos:[31:22] ;default: 10'b0 ; */ 1289 /*description: .*/ 1290 #define RTC_CNTL_SDIO_ACT_DNUM 0x000003FF 1291 #define RTC_CNTL_SDIO_ACT_DNUM_M ((RTC_CNTL_SDIO_ACT_DNUM_V)<<(RTC_CNTL_SDIO_ACT_DNUM_S)) 1292 #define RTC_CNTL_SDIO_ACT_DNUM_V 0x3FF 1293 #define RTC_CNTL_SDIO_ACT_DNUM_S 22 1294 1295 #define RTC_CNTL_CLK_CONF_REG (DR_REG_RTCCNTL_BASE + 0x74) 1296 /* RTC_CNTL_ANA_CLK_RTC_SEL : R/W ;bitpos:[31:30] ;default: 2'd0 ; */ 1297 /*description: .*/ 1298 #define RTC_CNTL_ANA_CLK_RTC_SEL 0x00000003 1299 #define RTC_CNTL_ANA_CLK_RTC_SEL_M ((RTC_CNTL_ANA_CLK_RTC_SEL_V)<<(RTC_CNTL_ANA_CLK_RTC_SEL_S)) 1300 #define RTC_CNTL_ANA_CLK_RTC_SEL_V 0x3 1301 #define RTC_CNTL_ANA_CLK_RTC_SEL_S 30 1302 /* RTC_CNTL_FAST_CLK_RTC_SEL : R/W ;bitpos:[29] ;default: 1'b0 ; */ 1303 /*description: fast_clk_rtc sel. 0: XTAL div 2.*/ 1304 #define RTC_CNTL_FAST_CLK_RTC_SEL (BIT(29)) 1305 #define RTC_CNTL_FAST_CLK_RTC_SEL_M (BIT(29)) 1306 #define RTC_CNTL_FAST_CLK_RTC_SEL_V 0x1 1307 #define RTC_CNTL_FAST_CLK_RTC_SEL_S 29 1308 /* RTC_CNTL_XTAL_GLOBAL_FORCE_NOGATING : R/W ;bitpos:[28] ;default: 1'b1 ; */ 1309 /*description: .*/ 1310 #define RTC_CNTL_XTAL_GLOBAL_FORCE_NOGATING (BIT(28)) 1311 #define RTC_CNTL_XTAL_GLOBAL_FORCE_NOGATING_M (BIT(28)) 1312 #define RTC_CNTL_XTAL_GLOBAL_FORCE_NOGATING_V 0x1 1313 #define RTC_CNTL_XTAL_GLOBAL_FORCE_NOGATING_S 28 1314 /* RTC_CNTL_XTAL_GLOBAL_FORCE_GATING : R/W ;bitpos:[27] ;default: 1'b0 ; */ 1315 /*description: .*/ 1316 #define RTC_CNTL_XTAL_GLOBAL_FORCE_GATING (BIT(27)) 1317 #define RTC_CNTL_XTAL_GLOBAL_FORCE_GATING_M (BIT(27)) 1318 #define RTC_CNTL_XTAL_GLOBAL_FORCE_GATING_V 0x1 1319 #define RTC_CNTL_XTAL_GLOBAL_FORCE_GATING_S 27 1320 /* RTC_CNTL_CK8M_FORCE_PU : R/W ;bitpos:[26] ;default: 1'd0 ; */ 1321 /*description: CK8M force power up.*/ 1322 #define RTC_CNTL_CK8M_FORCE_PU (BIT(26)) 1323 #define RTC_CNTL_CK8M_FORCE_PU_M (BIT(26)) 1324 #define RTC_CNTL_CK8M_FORCE_PU_V 0x1 1325 #define RTC_CNTL_CK8M_FORCE_PU_S 26 1326 /* RTC_CNTL_CK8M_FORCE_PD : R/W ;bitpos:[25] ;default: 1'd0 ; */ 1327 /*description: CK8M force power down.*/ 1328 #define RTC_CNTL_CK8M_FORCE_PD (BIT(25)) 1329 #define RTC_CNTL_CK8M_FORCE_PD_M (BIT(25)) 1330 #define RTC_CNTL_CK8M_FORCE_PD_V 0x1 1331 #define RTC_CNTL_CK8M_FORCE_PD_S 25 1332 /* RTC_CNTL_CK8M_DFREQ : R/W ;bitpos:[24:17] ;default: 8'd172 ; */ 1333 /*description: CK8M_DFREQ.*/ 1334 #define RTC_CNTL_CK8M_DFREQ 0x000000FF 1335 #define RTC_CNTL_CK8M_DFREQ_M ((RTC_CNTL_CK8M_DFREQ_V)<<(RTC_CNTL_CK8M_DFREQ_S)) 1336 #define RTC_CNTL_CK8M_DFREQ_V 0xFF 1337 #define RTC_CNTL_CK8M_DFREQ_S 17 1338 /* RTC_CNTL_CK8M_FORCE_NOGATING : R/W ;bitpos:[16] ;default: 1'd0 ; */ 1339 /*description: CK8M force no gating during sleep.*/ 1340 #define RTC_CNTL_CK8M_FORCE_NOGATING (BIT(16)) 1341 #define RTC_CNTL_CK8M_FORCE_NOGATING_M (BIT(16)) 1342 #define RTC_CNTL_CK8M_FORCE_NOGATING_V 0x1 1343 #define RTC_CNTL_CK8M_FORCE_NOGATING_S 16 1344 /* RTC_CNTL_XTAL_FORCE_NOGATING : R/W ;bitpos:[15] ;default: 1'd0 ; */ 1345 /*description: XTAL force no gating during sleep.*/ 1346 #define RTC_CNTL_XTAL_FORCE_NOGATING (BIT(15)) 1347 #define RTC_CNTL_XTAL_FORCE_NOGATING_M (BIT(15)) 1348 #define RTC_CNTL_XTAL_FORCE_NOGATING_V 0x1 1349 #define RTC_CNTL_XTAL_FORCE_NOGATING_S 15 1350 /* RTC_CNTL_CK8M_DIV_SEL : R/W ;bitpos:[14:12] ;default: 3'd3 ; */ 1351 /*description: divider = reg_ck8m_div_sel + 1.*/ 1352 #define RTC_CNTL_CK8M_DIV_SEL 0x00000007 1353 #define RTC_CNTL_CK8M_DIV_SEL_M ((RTC_CNTL_CK8M_DIV_SEL_V)<<(RTC_CNTL_CK8M_DIV_SEL_S)) 1354 #define RTC_CNTL_CK8M_DIV_SEL_V 0x7 1355 #define RTC_CNTL_CK8M_DIV_SEL_S 12 1356 /* RTC_CNTL_DIG_CLK8M_EN : R/W ;bitpos:[10] ;default: 1'd0 ; */ 1357 /*description: enable CK8M for digital core (no relationship with RTC core).*/ 1358 #define RTC_CNTL_DIG_CLK8M_EN (BIT(10)) 1359 #define RTC_CNTL_DIG_CLK8M_EN_M (BIT(10)) 1360 #define RTC_CNTL_DIG_CLK8M_EN_V 0x1 1361 #define RTC_CNTL_DIG_CLK8M_EN_S 10 1362 /* RTC_CNTL_DIG_CLK8M_D256_EN : R/W ;bitpos:[9] ;default: 1'd1 ; */ 1363 /*description: enable CK8M_D256_OUT for digital core (no relationship with RTC core).*/ 1364 #define RTC_CNTL_DIG_CLK8M_D256_EN (BIT(9)) 1365 #define RTC_CNTL_DIG_CLK8M_D256_EN_M (BIT(9)) 1366 #define RTC_CNTL_DIG_CLK8M_D256_EN_V 0x1 1367 #define RTC_CNTL_DIG_CLK8M_D256_EN_S 9 1368 /* RTC_CNTL_DIG_XTAL32K_EN : R/W ;bitpos:[8] ;default: 1'd0 ; */ 1369 /*description: enable CK_XTAL_32K for digital core (no relationship with RTC core).*/ 1370 #define RTC_CNTL_DIG_XTAL32K_EN (BIT(8)) 1371 #define RTC_CNTL_DIG_XTAL32K_EN_M (BIT(8)) 1372 #define RTC_CNTL_DIG_XTAL32K_EN_V 0x1 1373 #define RTC_CNTL_DIG_XTAL32K_EN_S 8 1374 /* RTC_CNTL_ENB_CK8M_DIV : R/W ;bitpos:[7] ;default: 1'd0 ; */ 1375 /*description: 1: CK8M_D256_OUT is actually CK8M.*/ 1376 #define RTC_CNTL_ENB_CK8M_DIV (BIT(7)) 1377 #define RTC_CNTL_ENB_CK8M_DIV_M (BIT(7)) 1378 #define RTC_CNTL_ENB_CK8M_DIV_V 0x1 1379 #define RTC_CNTL_ENB_CK8M_DIV_S 7 1380 /* RTC_CNTL_ENB_CK8M : R/W ;bitpos:[6] ;default: 1'd0 ; */ 1381 /*description: disable CK8M and CK8M_D256_OUT.*/ 1382 #define RTC_CNTL_ENB_CK8M (BIT(6)) 1383 #define RTC_CNTL_ENB_CK8M_M (BIT(6)) 1384 #define RTC_CNTL_ENB_CK8M_V 0x1 1385 #define RTC_CNTL_ENB_CK8M_S 6 1386 /* RTC_CNTL_CK8M_DIV : R/W ;bitpos:[5:4] ;default: 2'b01 ; */ 1387 /*description: CK8M_D256_OUT divider. 00: div128.*/ 1388 #define RTC_CNTL_CK8M_DIV 0x00000003 1389 #define RTC_CNTL_CK8M_DIV_M ((RTC_CNTL_CK8M_DIV_V)<<(RTC_CNTL_CK8M_DIV_S)) 1390 #define RTC_CNTL_CK8M_DIV_V 0x3 1391 #define RTC_CNTL_CK8M_DIV_S 4 1392 /* RTC_CNTL_CK8M_DIV_SEL_VLD : R/W ;bitpos:[3] ;default: 1'b1 ; */ 1393 /*description: used to sync reg_ck8m_div_sel bus. Clear vld before set reg_ck8m_div_sel.*/ 1394 #define RTC_CNTL_CK8M_DIV_SEL_VLD (BIT(3)) 1395 #define RTC_CNTL_CK8M_DIV_SEL_VLD_M (BIT(3)) 1396 #define RTC_CNTL_CK8M_DIV_SEL_VLD_V 0x1 1397 #define RTC_CNTL_CK8M_DIV_SEL_VLD_S 3 1398 /* RTC_CNTL_EFUSE_CLK_FORCE_NOGATING : R/W ;bitpos:[2] ;default: 1'b1 ; */ 1399 /*description: .*/ 1400 #define RTC_CNTL_EFUSE_CLK_FORCE_NOGATING (BIT(2)) 1401 #define RTC_CNTL_EFUSE_CLK_FORCE_NOGATING_M (BIT(2)) 1402 #define RTC_CNTL_EFUSE_CLK_FORCE_NOGATING_V 0x1 1403 #define RTC_CNTL_EFUSE_CLK_FORCE_NOGATING_S 2 1404 /* RTC_CNTL_EFUSE_CLK_FORCE_GATING : R/W ;bitpos:[1] ;default: 1'b0 ; */ 1405 /*description: .*/ 1406 #define RTC_CNTL_EFUSE_CLK_FORCE_GATING (BIT(1)) 1407 #define RTC_CNTL_EFUSE_CLK_FORCE_GATING_M (BIT(1)) 1408 #define RTC_CNTL_EFUSE_CLK_FORCE_GATING_V 0x1 1409 #define RTC_CNTL_EFUSE_CLK_FORCE_GATING_S 1 1410 1411 #define RTC_CNTL_SLOW_CLK_CONF_REG (DR_REG_RTCCNTL_BASE + 0x78) 1412 /* RTC_CNTL_SLOW_CLK_NEXT_EDGE : R/W ;bitpos:[31] ;default: 1'b0 ; */ 1413 /*description: .*/ 1414 #define RTC_CNTL_SLOW_CLK_NEXT_EDGE (BIT(31)) 1415 #define RTC_CNTL_SLOW_CLK_NEXT_EDGE_M (BIT(31)) 1416 #define RTC_CNTL_SLOW_CLK_NEXT_EDGE_V 0x1 1417 #define RTC_CNTL_SLOW_CLK_NEXT_EDGE_S 31 1418 /* RTC_CNTL_ANA_CLK_DIV : R/W ;bitpos:[30:23] ;default: 8'd0 ; */ 1419 /*description: .*/ 1420 #define RTC_CNTL_ANA_CLK_DIV 0x000000FF 1421 #define RTC_CNTL_ANA_CLK_DIV_M ((RTC_CNTL_ANA_CLK_DIV_V)<<(RTC_CNTL_ANA_CLK_DIV_S)) 1422 #define RTC_CNTL_ANA_CLK_DIV_V 0xFF 1423 #define RTC_CNTL_ANA_CLK_DIV_S 23 1424 /* RTC_CNTL_ANA_CLK_DIV_VLD : R/W ;bitpos:[22] ;default: 1'b1 ; */ 1425 /*description: used to sync div bus. clear vld before set reg_rtc_ana_clk_div.*/ 1426 #define RTC_CNTL_ANA_CLK_DIV_VLD (BIT(22)) 1427 #define RTC_CNTL_ANA_CLK_DIV_VLD_M (BIT(22)) 1428 #define RTC_CNTL_ANA_CLK_DIV_VLD_V 0x1 1429 #define RTC_CNTL_ANA_CLK_DIV_VLD_S 22 1430 1431 #define RTC_CNTL_SDIO_CONF_REG (DR_REG_RTCCNTL_BASE + 0x7C) 1432 /* RTC_CNTL_XPD_SDIO_REG : R/W ;bitpos:[31] ;default: 1'd0 ; */ 1433 /*description: .*/ 1434 #define RTC_CNTL_XPD_SDIO_REG (BIT(31)) 1435 #define RTC_CNTL_XPD_SDIO_REG_M (BIT(31)) 1436 #define RTC_CNTL_XPD_SDIO_REG_V 0x1 1437 #define RTC_CNTL_XPD_SDIO_REG_S 31 1438 /* RTC_CNTL_DREFH_SDIO : R/W ;bitpos:[30:29] ;default: 2'b00 ; */ 1439 /*description: SW option for DREFH_SDIO. Only active when reg_sdio_force = 1.*/ 1440 #define RTC_CNTL_DREFH_SDIO 0x00000003 1441 #define RTC_CNTL_DREFH_SDIO_M ((RTC_CNTL_DREFH_SDIO_V)<<(RTC_CNTL_DREFH_SDIO_S)) 1442 #define RTC_CNTL_DREFH_SDIO_V 0x3 1443 #define RTC_CNTL_DREFH_SDIO_S 29 1444 /* RTC_CNTL_DREFM_SDIO : R/W ;bitpos:[28:27] ;default: 2'b01 ; */ 1445 /*description: SW option for DREFM_SDIO. Only active when reg_sdio_force = 1.*/ 1446 #define RTC_CNTL_DREFM_SDIO 0x00000003 1447 #define RTC_CNTL_DREFM_SDIO_M ((RTC_CNTL_DREFM_SDIO_V)<<(RTC_CNTL_DREFM_SDIO_S)) 1448 #define RTC_CNTL_DREFM_SDIO_V 0x3 1449 #define RTC_CNTL_DREFM_SDIO_S 27 1450 /* RTC_CNTL_DREFL_SDIO : R/W ;bitpos:[26:25] ;default: 2'b01 ; */ 1451 /*description: SW option for DREFL_SDIO. Only active when reg_sdio_force = 1.*/ 1452 #define RTC_CNTL_DREFL_SDIO 0x00000003 1453 #define RTC_CNTL_DREFL_SDIO_M ((RTC_CNTL_DREFL_SDIO_V)<<(RTC_CNTL_DREFL_SDIO_S)) 1454 #define RTC_CNTL_DREFL_SDIO_V 0x3 1455 #define RTC_CNTL_DREFL_SDIO_S 25 1456 /* RTC_CNTL_REG1P8_READY : RO ;bitpos:[24] ;default: 1'd0 ; */ 1457 /*description: read only register for REG1P8_READY.*/ 1458 #define RTC_CNTL_REG1P8_READY (BIT(24)) 1459 #define RTC_CNTL_REG1P8_READY_M (BIT(24)) 1460 #define RTC_CNTL_REG1P8_READY_V 0x1 1461 #define RTC_CNTL_REG1P8_READY_S 24 1462 /* RTC_CNTL_SDIO_TIEH : R/W ;bitpos:[23] ;default: 1'd1 ; */ 1463 /*description: SW option for SDIO_TIEH. Only active when reg_sdio_force = 1.*/ 1464 #define RTC_CNTL_SDIO_TIEH (BIT(23)) 1465 #define RTC_CNTL_SDIO_TIEH_M (BIT(23)) 1466 #define RTC_CNTL_SDIO_TIEH_V 0x1 1467 #define RTC_CNTL_SDIO_TIEH_S 23 1468 /* RTC_CNTL_SDIO_FORCE : R/W ;bitpos:[22] ;default: 1'd0 ; */ 1469 /*description: 1: use SW option to control SDIO_REG.*/ 1470 #define RTC_CNTL_SDIO_FORCE (BIT(22)) 1471 #define RTC_CNTL_SDIO_FORCE_M (BIT(22)) 1472 #define RTC_CNTL_SDIO_FORCE_V 0x1 1473 #define RTC_CNTL_SDIO_FORCE_S 22 1474 /* RTC_CNTL_SDIO_PD_EN : R/W ;bitpos:[21] ;default: 1'd1 ; */ 1475 /*description: power down SDIO_REG in sleep. Only active when reg_sdio_force = 0.*/ 1476 #define RTC_CNTL_SDIO_PD_EN (BIT(21)) 1477 #define RTC_CNTL_SDIO_PD_EN_M (BIT(21)) 1478 #define RTC_CNTL_SDIO_PD_EN_V 0x1 1479 #define RTC_CNTL_SDIO_PD_EN_S 21 1480 /* RTC_CNTL_SDIO_ENCURLIM : R/W ;bitpos:[20] ;default: 1'd1 ; */ 1481 /*description: enable current limit.*/ 1482 #define RTC_CNTL_SDIO_ENCURLIM (BIT(20)) 1483 #define RTC_CNTL_SDIO_ENCURLIM_M (BIT(20)) 1484 #define RTC_CNTL_SDIO_ENCURLIM_V 0x1 1485 #define RTC_CNTL_SDIO_ENCURLIM_S 20 1486 /* RTC_CNTL_SDIO_MODECURLIM : R/W ;bitpos:[19] ;default: 1'd0 ; */ 1487 /*description: select current limit mode.*/ 1488 #define RTC_CNTL_SDIO_MODECURLIM (BIT(19)) 1489 #define RTC_CNTL_SDIO_MODECURLIM_M (BIT(19)) 1490 #define RTC_CNTL_SDIO_MODECURLIM_V 0x1 1491 #define RTC_CNTL_SDIO_MODECURLIM_S 19 1492 /* RTC_CNTL_SDIO_DCURLIM : R/W ;bitpos:[18:16] ;default: 3'd0 ; */ 1493 /*description: tune current limit threshold when tieh = 0. About 800mA/(8+d).*/ 1494 #define RTC_CNTL_SDIO_DCURLIM 0x00000007 1495 #define RTC_CNTL_SDIO_DCURLIM_M ((RTC_CNTL_SDIO_DCURLIM_V)<<(RTC_CNTL_SDIO_DCURLIM_S)) 1496 #define RTC_CNTL_SDIO_DCURLIM_V 0x7 1497 #define RTC_CNTL_SDIO_DCURLIM_S 16 1498 /* RTC_CNTL_SDIO_EN_INITI : R/W ;bitpos:[15] ;default: 1'd1 ; */ 1499 /*description: 0 to set init[1:0]=0.*/ 1500 #define RTC_CNTL_SDIO_EN_INITI (BIT(15)) 1501 #define RTC_CNTL_SDIO_EN_INITI_M (BIT(15)) 1502 #define RTC_CNTL_SDIO_EN_INITI_V 0x1 1503 #define RTC_CNTL_SDIO_EN_INITI_S 15 1504 /* RTC_CNTL_SDIO_INITI : R/W ;bitpos:[14:13] ;default: 2'd1 ; */ 1505 /*description: add resistor from ldo output to ground. 0: no res.*/ 1506 #define RTC_CNTL_SDIO_INITI 0x00000003 1507 #define RTC_CNTL_SDIO_INITI_M ((RTC_CNTL_SDIO_INITI_V)<<(RTC_CNTL_SDIO_INITI_S)) 1508 #define RTC_CNTL_SDIO_INITI_V 0x3 1509 #define RTC_CNTL_SDIO_INITI_S 13 1510 /* RTC_CNTL_SDIO_DCAP : R/W ;bitpos:[12:11] ;default: 2'b11 ; */ 1511 /*description: ability to prevent LDO from overshoot.*/ 1512 #define RTC_CNTL_SDIO_DCAP 0x00000003 1513 #define RTC_CNTL_SDIO_DCAP_M ((RTC_CNTL_SDIO_DCAP_V)<<(RTC_CNTL_SDIO_DCAP_S)) 1514 #define RTC_CNTL_SDIO_DCAP_V 0x3 1515 #define RTC_CNTL_SDIO_DCAP_S 11 1516 /* RTC_CNTL_SDIO_DTHDRV : R/W ;bitpos:[10:9] ;default: 2'b11 ; */ 1517 /*description: Tieh = 1 mode drive ability. Initially set to 0 to limit charge current.*/ 1518 #define RTC_CNTL_SDIO_DTHDRV 0x00000003 1519 #define RTC_CNTL_SDIO_DTHDRV_M ((RTC_CNTL_SDIO_DTHDRV_V)<<(RTC_CNTL_SDIO_DTHDRV_S)) 1520 #define RTC_CNTL_SDIO_DTHDRV_V 0x3 1521 #define RTC_CNTL_SDIO_DTHDRV_S 9 1522 /* RTC_CNTL_SDIO_TIMER_TARGET : R/W ;bitpos:[7:0] ;default: 8'd10 ; */ 1523 /*description: timer count to apply reg_sdio_dcap after sdio power on.*/ 1524 #define RTC_CNTL_SDIO_TIMER_TARGET 0x000000FF 1525 #define RTC_CNTL_SDIO_TIMER_TARGET_M ((RTC_CNTL_SDIO_TIMER_TARGET_V)<<(RTC_CNTL_SDIO_TIMER_TARGET_S)) 1526 #define RTC_CNTL_SDIO_TIMER_TARGET_V 0xFF 1527 #define RTC_CNTL_SDIO_TIMER_TARGET_S 0 1528 1529 #define RTC_CNTL_BIAS_CONF_REG (DR_REG_RTCCNTL_BASE + 0x80) 1530 /* RTC_CNTL_DBG_ATTEN_WAKEUP : R/W ;bitpos:[29:26] ;default: 4'd0 ; */ 1531 /*description: .*/ 1532 #define RTC_CNTL_DBG_ATTEN_WAKEUP 0x0000000F 1533 #define RTC_CNTL_DBG_ATTEN_WAKEUP_M ((RTC_CNTL_DBG_ATTEN_WAKEUP_V)<<(RTC_CNTL_DBG_ATTEN_WAKEUP_S)) 1534 #define RTC_CNTL_DBG_ATTEN_WAKEUP_V 0xF 1535 #define RTC_CNTL_DBG_ATTEN_WAKEUP_S 26 1536 /* RTC_CNTL_DBG_ATTEN_MONITOR : R/W ;bitpos:[25:22] ;default: 4'd0 ; */ 1537 /*description: DBG_ATTEN when rtc in monitor state.*/ 1538 #define RTC_CNTL_DBG_ATTEN_MONITOR 0x0000000F 1539 #define RTC_CNTL_DBG_ATTEN_MONITOR_M ((RTC_CNTL_DBG_ATTEN_MONITOR_V)<<(RTC_CNTL_DBG_ATTEN_MONITOR_S)) 1540 #define RTC_CNTL_DBG_ATTEN_MONITOR_V 0xF 1541 #define RTC_CNTL_DBG_ATTEN_MONITOR_S 22 1542 /* RTC_CNTL_DBG_ATTEN_DEEP_SLP : R/W ;bitpos:[21:18] ;default: 4'd0 ; */ 1543 /*description: DBG_ATTEN when rtc in sleep state.*/ 1544 #define RTC_CNTL_DBG_ATTEN_DEEP_SLP 0x0000000F 1545 #define RTC_CNTL_DBG_ATTEN_DEEP_SLP_M ((RTC_CNTL_DBG_ATTEN_DEEP_SLP_V)<<(RTC_CNTL_DBG_ATTEN_DEEP_SLP_S)) 1546 #define RTC_CNTL_DBG_ATTEN_DEEP_SLP_V 0xF 1547 #define RTC_CNTL_DBG_ATTEN_DEEP_SLP_S 18 1548 /* RTC_CNTL_BIAS_SLEEP_MONITOR : R/W ;bitpos:[17] ;default: 1'b0 ; */ 1549 /*description: bias_sleep when rtc in monitor state.*/ 1550 #define RTC_CNTL_BIAS_SLEEP_MONITOR (BIT(17)) 1551 #define RTC_CNTL_BIAS_SLEEP_MONITOR_M (BIT(17)) 1552 #define RTC_CNTL_BIAS_SLEEP_MONITOR_V 0x1 1553 #define RTC_CNTL_BIAS_SLEEP_MONITOR_S 17 1554 /* RTC_CNTL_BIAS_SLEEP_DEEP_SLP : R/W ;bitpos:[16] ;default: 1'b1 ; */ 1555 /*description: bias_sleep when rtc in sleep_state.*/ 1556 #define RTC_CNTL_BIAS_SLEEP_DEEP_SLP (BIT(16)) 1557 #define RTC_CNTL_BIAS_SLEEP_DEEP_SLP_M (BIT(16)) 1558 #define RTC_CNTL_BIAS_SLEEP_DEEP_SLP_V 0x1 1559 #define RTC_CNTL_BIAS_SLEEP_DEEP_SLP_S 16 1560 /* RTC_CNTL_PD_CUR_MONITOR : R/W ;bitpos:[15] ;default: 1'b0 ; */ 1561 /*description: xpd cur when rtc in monitor state.*/ 1562 #define RTC_CNTL_PD_CUR_MONITOR (BIT(15)) 1563 #define RTC_CNTL_PD_CUR_MONITOR_M (BIT(15)) 1564 #define RTC_CNTL_PD_CUR_MONITOR_V 0x1 1565 #define RTC_CNTL_PD_CUR_MONITOR_S 15 1566 /* RTC_CNTL_PD_CUR_DEEP_SLP : R/W ;bitpos:[14] ;default: 1'b0 ; */ 1567 /*description: xpd cur when rtc in sleep_state.*/ 1568 #define RTC_CNTL_PD_CUR_DEEP_SLP (BIT(14)) 1569 #define RTC_CNTL_PD_CUR_DEEP_SLP_M (BIT(14)) 1570 #define RTC_CNTL_PD_CUR_DEEP_SLP_V 0x1 1571 #define RTC_CNTL_PD_CUR_DEEP_SLP_S 14 1572 /* RTC_CNTL_BIAS_BUF_MONITOR : R/W ;bitpos:[13] ;default: 1'b0 ; */ 1573 /*description: .*/ 1574 #define RTC_CNTL_BIAS_BUF_MONITOR (BIT(13)) 1575 #define RTC_CNTL_BIAS_BUF_MONITOR_M (BIT(13)) 1576 #define RTC_CNTL_BIAS_BUF_MONITOR_V 0x1 1577 #define RTC_CNTL_BIAS_BUF_MONITOR_S 13 1578 /* RTC_CNTL_BIAS_BUF_DEEP_SLP : R/W ;bitpos:[12] ;default: 1'b0 ; */ 1579 /*description: .*/ 1580 #define RTC_CNTL_BIAS_BUF_DEEP_SLP (BIT(12)) 1581 #define RTC_CNTL_BIAS_BUF_DEEP_SLP_M (BIT(12)) 1582 #define RTC_CNTL_BIAS_BUF_DEEP_SLP_V 0x1 1583 #define RTC_CNTL_BIAS_BUF_DEEP_SLP_S 12 1584 /* RTC_CNTL_BIAS_BUF_WAKE : R/W ;bitpos:[11] ;default: 1'b1 ; */ 1585 /*description: .*/ 1586 #define RTC_CNTL_BIAS_BUF_WAKE (BIT(11)) 1587 #define RTC_CNTL_BIAS_BUF_WAKE_M (BIT(11)) 1588 #define RTC_CNTL_BIAS_BUF_WAKE_V 0x1 1589 #define RTC_CNTL_BIAS_BUF_WAKE_S 11 1590 /* RTC_CNTL_BIAS_BUF_IDLE : R/W ;bitpos:[10] ;default: 1'b0 ; */ 1591 /*description: .*/ 1592 #define RTC_CNTL_BIAS_BUF_IDLE (BIT(10)) 1593 #define RTC_CNTL_BIAS_BUF_IDLE_M (BIT(10)) 1594 #define RTC_CNTL_BIAS_BUF_IDLE_V 0x1 1595 #define RTC_CNTL_BIAS_BUF_IDLE_S 10 1596 1597 #define RTC_CNTL_REG (DR_REG_RTCCNTL_BASE + 0x84) 1598 /* RTC_CNTL_REGULATOR_FORCE_PU : R/W ;bitpos:[31] ;default: 1'd1 ; */ 1599 /*description: .*/ 1600 #define RTC_CNTL_REGULATOR_FORCE_PU (BIT(31)) 1601 #define RTC_CNTL_REGULATOR_FORCE_PU_M (BIT(31)) 1602 #define RTC_CNTL_REGULATOR_FORCE_PU_V 0x1 1603 #define RTC_CNTL_REGULATOR_FORCE_PU_S 31 1604 /* RTC_CNTL_REGULATOR_FORCE_PD : R/W ;bitpos:[30] ;default: 1'd0 ; */ 1605 /*description: RTC_REG force power down (for RTC_REG power down means decrease the voltage to 0 1606 .8v or lower ).*/ 1607 #define RTC_CNTL_REGULATOR_FORCE_PD (BIT(30)) 1608 #define RTC_CNTL_REGULATOR_FORCE_PD_M (BIT(30)) 1609 #define RTC_CNTL_REGULATOR_FORCE_PD_V 0x1 1610 #define RTC_CNTL_REGULATOR_FORCE_PD_S 30 1611 /* RTC_CNTL_DBOOST_FORCE_PU : R/W ;bitpos:[29] ;default: 1'd1 ; */ 1612 /*description: RTC_DBOOST force power up.*/ 1613 #define RTC_CNTL_DBOOST_FORCE_PU (BIT(29)) 1614 #define RTC_CNTL_DBOOST_FORCE_PU_M (BIT(29)) 1615 #define RTC_CNTL_DBOOST_FORCE_PU_V 0x1 1616 #define RTC_CNTL_DBOOST_FORCE_PU_S 29 1617 /* RTC_CNTL_DBOOST_FORCE_PD : R/W ;bitpos:[28] ;default: 1'd0 ; */ 1618 /*description: RTC_DBOOST force power down.*/ 1619 #define RTC_CNTL_DBOOST_FORCE_PD (BIT(28)) 1620 #define RTC_CNTL_DBOOST_FORCE_PD_M (BIT(28)) 1621 #define RTC_CNTL_DBOOST_FORCE_PD_V 0x1 1622 #define RTC_CNTL_DBOOST_FORCE_PD_S 28 1623 /* Approximate mapping of voltages to RTC_CNTL_DBIAS_WAK, RTC_CNTL_DBIAS_SLP, 1624 * RTC_CNTL_DIG_DBIAS_WAK, RTC_CNTL_DIG_DBIAS_SLP values. 1625 * Valid if RTC_CNTL_DBG_ATTEN is 0. 1626 */ 1627 #define RTC_CNTL_DIG_DBIAS_0V85 0 1628 #define RTC_CNTL_DIG_DBIAS_0V90 1 1629 #define RTC_CNTL_DIG_DBIAS_0V95 2 1630 #define RTC_CNTL_DIG_DBIAS_1V00 3 1631 #define RTC_CNTL_DIG_DBIAS_1V05 4 1632 #define RTC_CNTL_DIG_DBIAS_1V10 5 1633 #define RTC_CNTL_DIG_DBIAS_1V15 6 1634 #define RTC_CNTL_DIG_DBIAS_1V20 7 1635 1636 1637 /* RTC_CNTL_SCK_DCAP : R/W ;bitpos:[21:14] ;default: 8'd0 ; */ 1638 /*description: SCK_DCAP.*/ 1639 #define RTC_CNTL_SCK_DCAP 0x000000FF 1640 #define RTC_CNTL_SCK_DCAP_M ((RTC_CNTL_SCK_DCAP_V)<<(RTC_CNTL_SCK_DCAP_S)) 1641 #define RTC_CNTL_SCK_DCAP_V 0xFF 1642 #define RTC_CNTL_SCK_DCAP_S 14 1643 /* RTC_CNTL_DIG_CAL_EN : R/W ;bitpos:[7] ;default: 1'b0 ; */ 1644 /*description: .*/ 1645 #define RTC_CNTL_DIG_CAL_EN (BIT(7)) 1646 #define RTC_CNTL_DIG_CAL_EN_M (BIT(7)) 1647 #define RTC_CNTL_DIG_CAL_EN_V 0x1 1648 #define RTC_CNTL_DIG_CAL_EN_S 7 1649 1650 #define RTC_CNTL_PWC_REG (DR_REG_RTCCNTL_BASE + 0x88) 1651 /* RTC_CNTL_PAD_FORCE_HOLD : R/W ;bitpos:[21] ;default: 1'd0 ; */ 1652 /*description: rtc pad force hold.*/ 1653 #define RTC_CNTL_PAD_FORCE_HOLD (BIT(21)) 1654 #define RTC_CNTL_PAD_FORCE_HOLD_M (BIT(21)) 1655 #define RTC_CNTL_PAD_FORCE_HOLD_V 0x1 1656 #define RTC_CNTL_PAD_FORCE_HOLD_S 21 1657 /* RTC_CNTL_PD_EN : R/W ;bitpos:[20] ;default: 1'd0 ; */ 1658 /*description: enable power down rtc_peri in sleep .*/ 1659 #define RTC_CNTL_PD_EN (BIT(20)) 1660 #define RTC_CNTL_PD_EN_M (BIT(20)) 1661 #define RTC_CNTL_PD_EN_V 0x1 1662 #define RTC_CNTL_PD_EN_S 20 1663 /* RTC_CNTL_FORCE_PU : R/W ;bitpos:[19] ;default: 1'd0 ; */ 1664 /*description: rtc_peri force power up.*/ 1665 #define RTC_CNTL_FORCE_PU (BIT(19)) 1666 #define RTC_CNTL_FORCE_PU_M (BIT(19)) 1667 #define RTC_CNTL_FORCE_PU_V 0x1 1668 #define RTC_CNTL_FORCE_PU_S 19 1669 /* RTC_CNTL_FORCE_PD : R/W ;bitpos:[18] ;default: 1'b0 ; */ 1670 /*description: rtc_peri force power down.*/ 1671 #define RTC_CNTL_FORCE_PD (BIT(18)) 1672 #define RTC_CNTL_FORCE_PD_M (BIT(18)) 1673 #define RTC_CNTL_FORCE_PD_V 0x1 1674 #define RTC_CNTL_FORCE_PD_S 18 1675 /* RTC_CNTL_SLOWMEM_FORCE_LPU : R/W ;bitpos:[11] ;default: 1'b1 ; */ 1676 /*description: RTC memory force no PD.*/ 1677 #define RTC_CNTL_SLOWMEM_FORCE_LPU (BIT(11)) 1678 #define RTC_CNTL_SLOWMEM_FORCE_LPU_M (BIT(11)) 1679 #define RTC_CNTL_SLOWMEM_FORCE_LPU_V 0x1 1680 #define RTC_CNTL_SLOWMEM_FORCE_LPU_S 11 1681 /* RTC_CNTL_SLOWMEM_FORCE_LPD : R/W ;bitpos:[10] ;default: 1'b0 ; */ 1682 /*description: RTC memory force PD.*/ 1683 #define RTC_CNTL_SLOWMEM_FORCE_LPD (BIT(10)) 1684 #define RTC_CNTL_SLOWMEM_FORCE_LPD_M (BIT(10)) 1685 #define RTC_CNTL_SLOWMEM_FORCE_LPD_V 0x1 1686 #define RTC_CNTL_SLOWMEM_FORCE_LPD_S 10 1687 /* RTC_CNTL_SLOWMEM_FOLW_CPU : R/W ;bitpos:[9] ;default: 1'b0 ; */ 1688 /*description: 1: RTC memory PD following CPU.*/ 1689 #define RTC_CNTL_SLOWMEM_FOLW_CPU (BIT(9)) 1690 #define RTC_CNTL_SLOWMEM_FOLW_CPU_M (BIT(9)) 1691 #define RTC_CNTL_SLOWMEM_FOLW_CPU_V 0x1 1692 #define RTC_CNTL_SLOWMEM_FOLW_CPU_S 9 1693 /* RTC_CNTL_FASTMEM_FORCE_LPU : R/W ;bitpos:[8] ;default: 1'b1 ; */ 1694 /*description: Fast RTC memory force no PD.*/ 1695 #define RTC_CNTL_FASTMEM_FORCE_LPU (BIT(8)) 1696 #define RTC_CNTL_FASTMEM_FORCE_LPU_M (BIT(8)) 1697 #define RTC_CNTL_FASTMEM_FORCE_LPU_V 0x1 1698 #define RTC_CNTL_FASTMEM_FORCE_LPU_S 8 1699 /* RTC_CNTL_FASTMEM_FORCE_LPD : R/W ;bitpos:[7] ;default: 1'b0 ; */ 1700 /*description: Fast RTC memory force PD.*/ 1701 #define RTC_CNTL_FASTMEM_FORCE_LPD (BIT(7)) 1702 #define RTC_CNTL_FASTMEM_FORCE_LPD_M (BIT(7)) 1703 #define RTC_CNTL_FASTMEM_FORCE_LPD_V 0x1 1704 #define RTC_CNTL_FASTMEM_FORCE_LPD_S 7 1705 /* RTC_CNTL_FASTMEM_FOLW_CPU : R/W ;bitpos:[6] ;default: 1'b0 ; */ 1706 /*description: 1: Fast RTC memory PD following CPU.*/ 1707 #define RTC_CNTL_FASTMEM_FOLW_CPU (BIT(6)) 1708 #define RTC_CNTL_FASTMEM_FOLW_CPU_M (BIT(6)) 1709 #define RTC_CNTL_FASTMEM_FOLW_CPU_V 0x1 1710 #define RTC_CNTL_FASTMEM_FOLW_CPU_S 6 1711 /* RTC_CNTL_FORCE_NOISO : R/W ;bitpos:[5] ;default: 1'd1 ; */ 1712 /*description: rtc_peri force no ISO.*/ 1713 #define RTC_CNTL_FORCE_NOISO (BIT(5)) 1714 #define RTC_CNTL_FORCE_NOISO_M (BIT(5)) 1715 #define RTC_CNTL_FORCE_NOISO_V 0x1 1716 #define RTC_CNTL_FORCE_NOISO_S 5 1717 /* RTC_CNTL_FORCE_ISO : R/W ;bitpos:[4] ;default: 1'd0 ; */ 1718 /*description: rtc_peri force ISO.*/ 1719 #define RTC_CNTL_FORCE_ISO (BIT(4)) 1720 #define RTC_CNTL_FORCE_ISO_M (BIT(4)) 1721 #define RTC_CNTL_FORCE_ISO_V 0x1 1722 #define RTC_CNTL_FORCE_ISO_S 4 1723 /* RTC_CNTL_SLOWMEM_FORCE_ISO : R/W ;bitpos:[3] ;default: 1'b0 ; */ 1724 /*description: RTC memory force ISO.*/ 1725 #define RTC_CNTL_SLOWMEM_FORCE_ISO (BIT(3)) 1726 #define RTC_CNTL_SLOWMEM_FORCE_ISO_M (BIT(3)) 1727 #define RTC_CNTL_SLOWMEM_FORCE_ISO_V 0x1 1728 #define RTC_CNTL_SLOWMEM_FORCE_ISO_S 3 1729 /* RTC_CNTL_SLOWMEM_FORCE_NOISO : R/W ;bitpos:[2] ;default: 1'b1 ; */ 1730 /*description: RTC memory force no ISO.*/ 1731 #define RTC_CNTL_SLOWMEM_FORCE_NOISO (BIT(2)) 1732 #define RTC_CNTL_SLOWMEM_FORCE_NOISO_M (BIT(2)) 1733 #define RTC_CNTL_SLOWMEM_FORCE_NOISO_V 0x1 1734 #define RTC_CNTL_SLOWMEM_FORCE_NOISO_S 2 1735 /* RTC_CNTL_FASTMEM_FORCE_ISO : R/W ;bitpos:[1] ;default: 1'b0 ; */ 1736 /*description: Fast RTC memory force ISO.*/ 1737 #define RTC_CNTL_FASTMEM_FORCE_ISO (BIT(1)) 1738 #define RTC_CNTL_FASTMEM_FORCE_ISO_M (BIT(1)) 1739 #define RTC_CNTL_FASTMEM_FORCE_ISO_V 0x1 1740 #define RTC_CNTL_FASTMEM_FORCE_ISO_S 1 1741 /* RTC_CNTL_FASTMEM_FORCE_NOISO : R/W ;bitpos:[0] ;default: 1'b1 ; */ 1742 /*description: Fast RTC memory force no ISO.*/ 1743 #define RTC_CNTL_FASTMEM_FORCE_NOISO (BIT(0)) 1744 #define RTC_CNTL_FASTMEM_FORCE_NOISO_M (BIT(0)) 1745 #define RTC_CNTL_FASTMEM_FORCE_NOISO_V 0x1 1746 #define RTC_CNTL_FASTMEM_FORCE_NOISO_S 0 1747 1748 #define RTC_CNTL_REGULATOR_DRV_CTRL_REG (DR_REG_RTCCNTL_BASE + 0x8C) 1749 /* RTC_CNTL_DG_VDD_DRV_B_MONITOR : R/W ;bitpos:[27:20] ;default: 8'h0 ; */ 1750 /*description: .*/ 1751 #define RTC_CNTL_DG_VDD_DRV_B_MONITOR 0x000000FF 1752 #define RTC_CNTL_DG_VDD_DRV_B_MONITOR_M ((RTC_CNTL_DG_VDD_DRV_B_MONITOR_V)<<(RTC_CNTL_DG_VDD_DRV_B_MONITOR_S)) 1753 #define RTC_CNTL_DG_VDD_DRV_B_MONITOR_V 0xFF 1754 #define RTC_CNTL_DG_VDD_DRV_B_MONITOR_S 20 1755 /* RTC_CNTL_DG_VDD_DRV_B_SLP : R/W ;bitpos:[19:12] ;default: 8'h0 ; */ 1756 /*description: .*/ 1757 #define RTC_CNTL_DG_VDD_DRV_B_SLP 0x000000FF 1758 #define RTC_CNTL_DG_VDD_DRV_B_SLP_M ((RTC_CNTL_DG_VDD_DRV_B_SLP_V)<<(RTC_CNTL_DG_VDD_DRV_B_SLP_S)) 1759 #define RTC_CNTL_DG_VDD_DRV_B_SLP_V 0xFF 1760 #define RTC_CNTL_DG_VDD_DRV_B_SLP_S 12 1761 /* RTC_CNTL_REGULATOR_DRV_B_SLP : R/W ;bitpos:[11:6] ;default: 6'b0 ; */ 1762 /*description: .*/ 1763 #define RTC_CNTL_REGULATOR_DRV_B_SLP 0x0000003F 1764 #define RTC_CNTL_REGULATOR_DRV_B_SLP_M ((RTC_CNTL_REGULATOR_DRV_B_SLP_V)<<(RTC_CNTL_REGULATOR_DRV_B_SLP_S)) 1765 #define RTC_CNTL_REGULATOR_DRV_B_SLP_V 0x3F 1766 #define RTC_CNTL_REGULATOR_DRV_B_SLP_S 6 1767 /* RTC_CNTL_REGULATOR_DRV_B_MONITOR : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ 1768 /*description: .*/ 1769 #define RTC_CNTL_REGULATOR_DRV_B_MONITOR 0x0000003F 1770 #define RTC_CNTL_REGULATOR_DRV_B_MONITOR_M ((RTC_CNTL_REGULATOR_DRV_B_MONITOR_V)<<(RTC_CNTL_REGULATOR_DRV_B_MONITOR_S)) 1771 #define RTC_CNTL_REGULATOR_DRV_B_MONITOR_V 0x3F 1772 #define RTC_CNTL_REGULATOR_DRV_B_MONITOR_S 0 1773 1774 #define RTC_CNTL_DIG_PWC_REG (DR_REG_RTCCNTL_BASE + 0x90) 1775 /* RTC_CNTL_DG_WRAP_PD_EN : R/W ;bitpos:[31] ;default: 0 ; */ 1776 /*description: .*/ 1777 #define RTC_CNTL_DG_WRAP_PD_EN (BIT(31)) 1778 #define RTC_CNTL_DG_WRAP_PD_EN_M (BIT(31)) 1779 #define RTC_CNTL_DG_WRAP_PD_EN_V 0x1 1780 #define RTC_CNTL_DG_WRAP_PD_EN_S 31 1781 /* RTC_CNTL_WIFI_PD_EN : R/W ;bitpos:[30] ;default: 0 ; */ 1782 /*description: enable power down wifi in sleep.*/ 1783 #define RTC_CNTL_WIFI_PD_EN (BIT(30)) 1784 #define RTC_CNTL_WIFI_PD_EN_M (BIT(30)) 1785 #define RTC_CNTL_WIFI_PD_EN_V 0x1 1786 #define RTC_CNTL_WIFI_PD_EN_S 30 1787 /* RTC_CNTL_CPU_TOP_PD_EN : R/W ;bitpos:[29] ;default: 0 ; */ 1788 /*description: enable power down internal SRAM 4 in sleep.*/ 1789 #define RTC_CNTL_CPU_TOP_PD_EN (BIT(29)) 1790 #define RTC_CNTL_CPU_TOP_PD_EN_M (BIT(29)) 1791 #define RTC_CNTL_CPU_TOP_PD_EN_V 0x1 1792 #define RTC_CNTL_CPU_TOP_PD_EN_S 29 1793 /* RTC_CNTL_DG_PERI_PD_EN : R/W ;bitpos:[28] ;default: 0 ; */ 1794 /*description: enable power down internal SRAM 3 in sleep.*/ 1795 #define RTC_CNTL_DG_PERI_PD_EN (BIT(28)) 1796 #define RTC_CNTL_DG_PERI_PD_EN_M (BIT(28)) 1797 #define RTC_CNTL_DG_PERI_PD_EN_V 0x1 1798 #define RTC_CNTL_DG_PERI_PD_EN_S 28 1799 /* RTC_CNTL_CPU_TOP_FORCE_PU : R/W ;bitpos:[22] ;default: 1'd1 ; */ 1800 /*description: digital dcdc force power up.*/ 1801 #define RTC_CNTL_CPU_TOP_FORCE_PU (BIT(22)) 1802 #define RTC_CNTL_CPU_TOP_FORCE_PU_M (BIT(22)) 1803 #define RTC_CNTL_CPU_TOP_FORCE_PU_V 0x1 1804 #define RTC_CNTL_CPU_TOP_FORCE_PU_S 22 1805 /* RTC_CNTL_CPU_TOP_FORCE_PD : R/W ;bitpos:[21] ;default: 1'b0 ; */ 1806 /*description: digital dcdc force power down.*/ 1807 #define RTC_CNTL_CPU_TOP_FORCE_PD (BIT(21)) 1808 #define RTC_CNTL_CPU_TOP_FORCE_PD_M (BIT(21)) 1809 #define RTC_CNTL_CPU_TOP_FORCE_PD_V 0x1 1810 #define RTC_CNTL_CPU_TOP_FORCE_PD_S 21 1811 /* RTC_CNTL_DG_WRAP_FORCE_PU : R/W ;bitpos:[20] ;default: 1'd1 ; */ 1812 /*description: digital core force power up.*/ 1813 #define RTC_CNTL_DG_WRAP_FORCE_PU (BIT(20)) 1814 #define RTC_CNTL_DG_WRAP_FORCE_PU_M (BIT(20)) 1815 #define RTC_CNTL_DG_WRAP_FORCE_PU_V 0x1 1816 #define RTC_CNTL_DG_WRAP_FORCE_PU_S 20 1817 /* RTC_CNTL_DG_WRAP_FORCE_PD : R/W ;bitpos:[19] ;default: 1'b0 ; */ 1818 /*description: digital core force power down.*/ 1819 #define RTC_CNTL_DG_WRAP_FORCE_PD (BIT(19)) 1820 #define RTC_CNTL_DG_WRAP_FORCE_PD_M (BIT(19)) 1821 #define RTC_CNTL_DG_WRAP_FORCE_PD_V 0x1 1822 #define RTC_CNTL_DG_WRAP_FORCE_PD_S 19 1823 /* RTC_CNTL_WIFI_FORCE_PU : R/W ;bitpos:[18] ;default: 1'd1 ; */ 1824 /*description: wifi force power up.*/ 1825 #define RTC_CNTL_WIFI_FORCE_PU (BIT(18)) 1826 #define RTC_CNTL_WIFI_FORCE_PU_M (BIT(18)) 1827 #define RTC_CNTL_WIFI_FORCE_PU_V 0x1 1828 #define RTC_CNTL_WIFI_FORCE_PU_S 18 1829 /* RTC_CNTL_WIFI_FORCE_PD : R/W ;bitpos:[17] ;default: 1'b0 ; */ 1830 /*description: wifi force power down.*/ 1831 #define RTC_CNTL_WIFI_FORCE_PD (BIT(17)) 1832 #define RTC_CNTL_WIFI_FORCE_PD_M (BIT(17)) 1833 #define RTC_CNTL_WIFI_FORCE_PD_V 0x1 1834 #define RTC_CNTL_WIFI_FORCE_PD_S 17 1835 /* RTC_CNTL_DG_PERI_FORCE_PU : R/W ;bitpos:[14] ;default: 1'd1 ; */ 1836 /*description: internal SRAM 3 force power up.*/ 1837 #define RTC_CNTL_DG_PERI_FORCE_PU (BIT(14)) 1838 #define RTC_CNTL_DG_PERI_FORCE_PU_M (BIT(14)) 1839 #define RTC_CNTL_DG_PERI_FORCE_PU_V 0x1 1840 #define RTC_CNTL_DG_PERI_FORCE_PU_S 14 1841 /* RTC_CNTL_DG_PERI_FORCE_PD : R/W ;bitpos:[13] ;default: 1'b0 ; */ 1842 /*description: internal SRAM 3 force power down.*/ 1843 #define RTC_CNTL_DG_PERI_FORCE_PD (BIT(13)) 1844 #define RTC_CNTL_DG_PERI_FORCE_PD_M (BIT(13)) 1845 #define RTC_CNTL_DG_PERI_FORCE_PD_V 0x1 1846 #define RTC_CNTL_DG_PERI_FORCE_PD_S 13 1847 /* RTC_CNTL_BT_FORCE_PU : R/W ;bitpos:[12] ;default: 1'd1 ; */ 1848 /*description: internal SRAM 2 force power up.*/ 1849 #define RTC_CNTL_BT_FORCE_PU (BIT(12)) 1850 #define RTC_CNTL_BT_FORCE_PU_M (BIT(12)) 1851 #define RTC_CNTL_BT_FORCE_PU_V 0x1 1852 #define RTC_CNTL_BT_FORCE_PU_S 12 1853 /* RTC_CNTL_BT_FORCE_PD : R/W ;bitpos:[11] ;default: 1'b0 ; */ 1854 /*description: internal SRAM 2 force power down.*/ 1855 #define RTC_CNTL_BT_FORCE_PD (BIT(11)) 1856 #define RTC_CNTL_BT_FORCE_PD_M (BIT(11)) 1857 #define RTC_CNTL_BT_FORCE_PD_V 0x1 1858 #define RTC_CNTL_BT_FORCE_PD_S 11 1859 /* RTC_CNTL_LSLP_MEM_FORCE_PU : R/W ;bitpos:[4] ;default: 1'b1 ; */ 1860 /*description: memories in digital core force no PD in sleep.*/ 1861 #define RTC_CNTL_LSLP_MEM_FORCE_PU (BIT(4)) 1862 #define RTC_CNTL_LSLP_MEM_FORCE_PU_M (BIT(4)) 1863 #define RTC_CNTL_LSLP_MEM_FORCE_PU_V 0x1 1864 #define RTC_CNTL_LSLP_MEM_FORCE_PU_S 4 1865 /* RTC_CNTL_LSLP_MEM_FORCE_PD : R/W ;bitpos:[3] ;default: 1'b0 ; */ 1866 /*description: memories in digital core force PD in sleep.*/ 1867 #define RTC_CNTL_LSLP_MEM_FORCE_PD (BIT(3)) 1868 #define RTC_CNTL_LSLP_MEM_FORCE_PD_M (BIT(3)) 1869 #define RTC_CNTL_LSLP_MEM_FORCE_PD_V 0x1 1870 #define RTC_CNTL_LSLP_MEM_FORCE_PD_S 3 1871 1872 #define RTC_CNTL_DIG_ISO_REG (DR_REG_RTCCNTL_BASE + 0x94) 1873 /* RTC_CNTL_DG_WRAP_FORCE_NOISO : R/W ;bitpos:[31] ;default: 1'd1 ; */ 1874 /*description: .*/ 1875 #define RTC_CNTL_DG_WRAP_FORCE_NOISO (BIT(31)) 1876 #define RTC_CNTL_DG_WRAP_FORCE_NOISO_M (BIT(31)) 1877 #define RTC_CNTL_DG_WRAP_FORCE_NOISO_V 0x1 1878 #define RTC_CNTL_DG_WRAP_FORCE_NOISO_S 31 1879 /* RTC_CNTL_DG_WRAP_FORCE_ISO : R/W ;bitpos:[30] ;default: 1'd0 ; */ 1880 /*description: digital core force ISO.*/ 1881 #define RTC_CNTL_DG_WRAP_FORCE_ISO (BIT(30)) 1882 #define RTC_CNTL_DG_WRAP_FORCE_ISO_M (BIT(30)) 1883 #define RTC_CNTL_DG_WRAP_FORCE_ISO_V 0x1 1884 #define RTC_CNTL_DG_WRAP_FORCE_ISO_S 30 1885 /* RTC_CNTL_WIFI_FORCE_NOISO : R/W ;bitpos:[29] ;default: 1'd1 ; */ 1886 /*description: wifi force no ISO.*/ 1887 #define RTC_CNTL_WIFI_FORCE_NOISO (BIT(29)) 1888 #define RTC_CNTL_WIFI_FORCE_NOISO_M (BIT(29)) 1889 #define RTC_CNTL_WIFI_FORCE_NOISO_V 0x1 1890 #define RTC_CNTL_WIFI_FORCE_NOISO_S 29 1891 /* RTC_CNTL_WIFI_FORCE_ISO : R/W ;bitpos:[28] ;default: 1'd0 ; */ 1892 /*description: wifi force ISO.*/ 1893 #define RTC_CNTL_WIFI_FORCE_ISO (BIT(28)) 1894 #define RTC_CNTL_WIFI_FORCE_ISO_M (BIT(28)) 1895 #define RTC_CNTL_WIFI_FORCE_ISO_V 0x1 1896 #define RTC_CNTL_WIFI_FORCE_ISO_S 28 1897 /* RTC_CNTL_CPU_TOP_FORCE_NOISO : R/W ;bitpos:[27] ;default: 1'd1 ; */ 1898 /*description: internal SRAM 4 force no ISO.*/ 1899 #define RTC_CNTL_CPU_TOP_FORCE_NOISO (BIT(27)) 1900 #define RTC_CNTL_CPU_TOP_FORCE_NOISO_M (BIT(27)) 1901 #define RTC_CNTL_CPU_TOP_FORCE_NOISO_V 0x1 1902 #define RTC_CNTL_CPU_TOP_FORCE_NOISO_S 27 1903 /* RTC_CNTL_CPU_TOP_FORCE_ISO : R/W ;bitpos:[26] ;default: 1'd0 ; */ 1904 /*description: internal SRAM 4 force ISO.*/ 1905 #define RTC_CNTL_CPU_TOP_FORCE_ISO (BIT(26)) 1906 #define RTC_CNTL_CPU_TOP_FORCE_ISO_M (BIT(26)) 1907 #define RTC_CNTL_CPU_TOP_FORCE_ISO_V 0x1 1908 #define RTC_CNTL_CPU_TOP_FORCE_ISO_S 26 1909 /* RTC_CNTL_DG_PERI_FORCE_NOISO : R/W ;bitpos:[25] ;default: 1'd1 ; */ 1910 /*description: internal SRAM 3 force no ISO.*/ 1911 #define RTC_CNTL_DG_PERI_FORCE_NOISO (BIT(25)) 1912 #define RTC_CNTL_DG_PERI_FORCE_NOISO_M (BIT(25)) 1913 #define RTC_CNTL_DG_PERI_FORCE_NOISO_V 0x1 1914 #define RTC_CNTL_DG_PERI_FORCE_NOISO_S 25 1915 /* RTC_CNTL_DG_PERI_FORCE_ISO : R/W ;bitpos:[24] ;default: 1'd0 ; */ 1916 /*description: internal SRAM 3 force ISO.*/ 1917 #define RTC_CNTL_DG_PERI_FORCE_ISO (BIT(24)) 1918 #define RTC_CNTL_DG_PERI_FORCE_ISO_M (BIT(24)) 1919 #define RTC_CNTL_DG_PERI_FORCE_ISO_V 0x1 1920 #define RTC_CNTL_DG_PERI_FORCE_ISO_S 24 1921 /* RTC_CNTL_BT_FORCE_NOISO : R/W ;bitpos:[23] ;default: 1'd1 ; */ 1922 /*description: internal SRAM 2 force no ISO.*/ 1923 #define RTC_CNTL_BT_FORCE_NOISO (BIT(23)) 1924 #define RTC_CNTL_BT_FORCE_NOISO_M (BIT(23)) 1925 #define RTC_CNTL_BT_FORCE_NOISO_V 0x1 1926 #define RTC_CNTL_BT_FORCE_NOISO_S 23 1927 /* RTC_CNTL_BT_FORCE_ISO : R/W ;bitpos:[22] ;default: 1'd0 ; */ 1928 /*description: internal SRAM 2 force ISO.*/ 1929 #define RTC_CNTL_BT_FORCE_ISO (BIT(22)) 1930 #define RTC_CNTL_BT_FORCE_ISO_M (BIT(22)) 1931 #define RTC_CNTL_BT_FORCE_ISO_V 0x1 1932 #define RTC_CNTL_BT_FORCE_ISO_S 22 1933 /* RTC_CNTL_DG_PAD_FORCE_HOLD : R/W ;bitpos:[15] ;default: 1'd0 ; */ 1934 /*description: digital pad force hold.*/ 1935 #define RTC_CNTL_DG_PAD_FORCE_HOLD (BIT(15)) 1936 #define RTC_CNTL_DG_PAD_FORCE_HOLD_M (BIT(15)) 1937 #define RTC_CNTL_DG_PAD_FORCE_HOLD_V 0x1 1938 #define RTC_CNTL_DG_PAD_FORCE_HOLD_S 15 1939 /* RTC_CNTL_DG_PAD_FORCE_UNHOLD : R/W ;bitpos:[14] ;default: 1'd1 ; */ 1940 /*description: digital pad force un-hold.*/ 1941 #define RTC_CNTL_DG_PAD_FORCE_UNHOLD (BIT(14)) 1942 #define RTC_CNTL_DG_PAD_FORCE_UNHOLD_M (BIT(14)) 1943 #define RTC_CNTL_DG_PAD_FORCE_UNHOLD_V 0x1 1944 #define RTC_CNTL_DG_PAD_FORCE_UNHOLD_S 14 1945 /* RTC_CNTL_DG_PAD_FORCE_ISO : R/W ;bitpos:[13] ;default: 1'd0 ; */ 1946 /*description: digital pad force ISO.*/ 1947 #define RTC_CNTL_DG_PAD_FORCE_ISO (BIT(13)) 1948 #define RTC_CNTL_DG_PAD_FORCE_ISO_M (BIT(13)) 1949 #define RTC_CNTL_DG_PAD_FORCE_ISO_V 0x1 1950 #define RTC_CNTL_DG_PAD_FORCE_ISO_S 13 1951 /* RTC_CNTL_DG_PAD_FORCE_NOISO : R/W ;bitpos:[12] ;default: 1'd1 ; */ 1952 /*description: digital pad force no ISO.*/ 1953 #define RTC_CNTL_DG_PAD_FORCE_NOISO (BIT(12)) 1954 #define RTC_CNTL_DG_PAD_FORCE_NOISO_M (BIT(12)) 1955 #define RTC_CNTL_DG_PAD_FORCE_NOISO_V 0x1 1956 #define RTC_CNTL_DG_PAD_FORCE_NOISO_S 12 1957 /* RTC_CNTL_DG_PAD_AUTOHOLD_EN : R/W ;bitpos:[11] ;default: 1'd0 ; */ 1958 /*description: digital pad enable auto-hold.*/ 1959 #define RTC_CNTL_DG_PAD_AUTOHOLD_EN (BIT(11)) 1960 #define RTC_CNTL_DG_PAD_AUTOHOLD_EN_M (BIT(11)) 1961 #define RTC_CNTL_DG_PAD_AUTOHOLD_EN_V 0x1 1962 #define RTC_CNTL_DG_PAD_AUTOHOLD_EN_S 11 1963 /* RTC_CNTL_CLR_DG_PAD_AUTOHOLD : WO ;bitpos:[10] ;default: 1'd0 ; */ 1964 /*description: wtite only register to clear digital pad auto-hold.*/ 1965 #define RTC_CNTL_CLR_DG_PAD_AUTOHOLD (BIT(10)) 1966 #define RTC_CNTL_CLR_DG_PAD_AUTOHOLD_M (BIT(10)) 1967 #define RTC_CNTL_CLR_DG_PAD_AUTOHOLD_V 0x1 1968 #define RTC_CNTL_CLR_DG_PAD_AUTOHOLD_S 10 1969 /* RTC_CNTL_DG_PAD_AUTOHOLD : RO ;bitpos:[9] ;default: 1'd0 ; */ 1970 /*description: read only register to indicate digital pad auto-hold status.*/ 1971 #define RTC_CNTL_DG_PAD_AUTOHOLD (BIT(9)) 1972 #define RTC_CNTL_DG_PAD_AUTOHOLD_M (BIT(9)) 1973 #define RTC_CNTL_DG_PAD_AUTOHOLD_V 0x1 1974 #define RTC_CNTL_DG_PAD_AUTOHOLD_S 9 1975 /* RTC_CNTL_DIG_ISO_FORCE_ON : R/W ;bitpos:[8] ;default: 1'd0 ; */ 1976 /*description: .*/ 1977 #define RTC_CNTL_DIG_ISO_FORCE_ON (BIT(8)) 1978 #define RTC_CNTL_DIG_ISO_FORCE_ON_M (BIT(8)) 1979 #define RTC_CNTL_DIG_ISO_FORCE_ON_V 0x1 1980 #define RTC_CNTL_DIG_ISO_FORCE_ON_S 8 1981 /* RTC_CNTL_DIG_ISO_FORCE_OFF : R/W ;bitpos:[7] ;default: 1'd1 ; */ 1982 /*description: .*/ 1983 #define RTC_CNTL_DIG_ISO_FORCE_OFF (BIT(7)) 1984 #define RTC_CNTL_DIG_ISO_FORCE_OFF_M (BIT(7)) 1985 #define RTC_CNTL_DIG_ISO_FORCE_OFF_V 0x1 1986 #define RTC_CNTL_DIG_ISO_FORCE_OFF_S 7 1987 1988 #define RTC_CNTL_WDTCONFIG0_REG (DR_REG_RTCCNTL_BASE + 0x98) 1989 /* RTC_CNTL_WDT_EN : R/W ;bitpos:[31] ;default: 1'h0 ; */ 1990 /*description: .*/ 1991 #define RTC_CNTL_WDT_EN (BIT(31)) 1992 #define RTC_CNTL_WDT_EN_M (BIT(31)) 1993 #define RTC_CNTL_WDT_EN_V 0x1 1994 #define RTC_CNTL_WDT_EN_S 31 1995 /* RTC_CNTL_WDT_STG0 : R/W ;bitpos:[30:28] ;default: 3'h0 ; */ 1996 /*description: 1: interrupt stage en.*/ 1997 #define RTC_CNTL_WDT_STG0 0x00000007 1998 #define RTC_CNTL_WDT_STG0_M ((RTC_CNTL_WDT_STG0_V)<<(RTC_CNTL_WDT_STG0_S)) 1999 #define RTC_CNTL_WDT_STG0_V 0x7 2000 #define RTC_CNTL_WDT_STG0_S 28 2001 /* RTC_CNTL_WDT_STG1 : R/W ;bitpos:[27:25] ;default: 3'h0 ; */ 2002 /*description: 1: interrupt stage en.*/ 2003 #define RTC_CNTL_WDT_STG1 0x00000007 2004 #define RTC_CNTL_WDT_STG1_M ((RTC_CNTL_WDT_STG1_V)<<(RTC_CNTL_WDT_STG1_S)) 2005 #define RTC_CNTL_WDT_STG1_V 0x7 2006 #define RTC_CNTL_WDT_STG1_S 25 2007 /* RTC_CNTL_WDT_STG2 : R/W ;bitpos:[24:22] ;default: 3'h0 ; */ 2008 /*description: 1: interrupt stage en.*/ 2009 #define RTC_CNTL_WDT_STG2 0x00000007 2010 #define RTC_CNTL_WDT_STG2_M ((RTC_CNTL_WDT_STG2_V)<<(RTC_CNTL_WDT_STG2_S)) 2011 #define RTC_CNTL_WDT_STG2_V 0x7 2012 #define RTC_CNTL_WDT_STG2_S 22 2013 /* RTC_CNTL_WDT_STG3 : R/W ;bitpos:[21:19] ;default: 3'h0 ; */ 2014 /*description: 1: interrupt stage en.*/ 2015 #define RTC_CNTL_WDT_STG3 0x00000007 2016 #define RTC_CNTL_WDT_STG3_M ((RTC_CNTL_WDT_STG3_V)<<(RTC_CNTL_WDT_STG3_S)) 2017 #define RTC_CNTL_WDT_STG3_V 0x7 2018 #define RTC_CNTL_WDT_STG3_S 19 2019 2020 /* RTC_CNTL_WDT_CPU_RESET_LENGTH : R/W ;bitpos:[18:16] ;default: 3'h1 ; */ 2021 /*description: CPU reset counter length.*/ 2022 #define RTC_CNTL_WDT_CPU_RESET_LENGTH 0x00000007 2023 #define RTC_CNTL_WDT_CPU_RESET_LENGTH_M ((RTC_CNTL_WDT_CPU_RESET_LENGTH_V)<<(RTC_CNTL_WDT_CPU_RESET_LENGTH_S)) 2024 #define RTC_CNTL_WDT_CPU_RESET_LENGTH_V 0x7 2025 #define RTC_CNTL_WDT_CPU_RESET_LENGTH_S 16 2026 /* RTC_CNTL_WDT_SYS_RESET_LENGTH : R/W ;bitpos:[15:13] ;default: 3'h1 ; */ 2027 /*description: system reset counter length.*/ 2028 #define RTC_CNTL_WDT_SYS_RESET_LENGTH 0x00000007 2029 #define RTC_CNTL_WDT_SYS_RESET_LENGTH_M ((RTC_CNTL_WDT_SYS_RESET_LENGTH_V)<<(RTC_CNTL_WDT_SYS_RESET_LENGTH_S)) 2030 #define RTC_CNTL_WDT_SYS_RESET_LENGTH_V 0x7 2031 #define RTC_CNTL_WDT_SYS_RESET_LENGTH_S 13 2032 /* RTC_CNTL_WDT_FLASHBOOT_MOD_EN : R/W ;bitpos:[12] ;default: 1'h1 ; */ 2033 /*description: enable WDT in flash boot.*/ 2034 #define RTC_CNTL_WDT_FLASHBOOT_MOD_EN (BIT(12)) 2035 #define RTC_CNTL_WDT_FLASHBOOT_MOD_EN_M (BIT(12)) 2036 #define RTC_CNTL_WDT_FLASHBOOT_MOD_EN_V 0x1 2037 #define RTC_CNTL_WDT_FLASHBOOT_MOD_EN_S 12 2038 /* RTC_CNTL_WDT_PROCPU_RESET_EN : R/W ;bitpos:[11] ;default: 1'd0 ; */ 2039 /*description: enable WDT reset PRO CPU.*/ 2040 #define RTC_CNTL_WDT_PROCPU_RESET_EN (BIT(11)) 2041 #define RTC_CNTL_WDT_PROCPU_RESET_EN_M (BIT(11)) 2042 #define RTC_CNTL_WDT_PROCPU_RESET_EN_V 0x1 2043 #define RTC_CNTL_WDT_PROCPU_RESET_EN_S 11 2044 /* RTC_CNTL_WDT_APPCPU_RESET_EN : R/W ;bitpos:[10] ;default: 1'd0 ; */ 2045 /*description: enable WDT reset APP CPU.*/ 2046 #define RTC_CNTL_WDT_APPCPU_RESET_EN (BIT(10)) 2047 #define RTC_CNTL_WDT_APPCPU_RESET_EN_M (BIT(10)) 2048 #define RTC_CNTL_WDT_APPCPU_RESET_EN_V 0x1 2049 #define RTC_CNTL_WDT_APPCPU_RESET_EN_S 10 2050 /* RTC_CNTL_WDT_PAUSE_IN_SLP : R/W ;bitpos:[9] ;default: 1'd1 ; */ 2051 /*description: pause WDT in sleep.*/ 2052 #define RTC_CNTL_WDT_PAUSE_IN_SLP (BIT(9)) 2053 #define RTC_CNTL_WDT_PAUSE_IN_SLP_M (BIT(9)) 2054 #define RTC_CNTL_WDT_PAUSE_IN_SLP_V 0x1 2055 #define RTC_CNTL_WDT_PAUSE_IN_SLP_S 9 2056 /* RTC_CNTL_WDT_CHIP_RESET_EN : R/W ;bitpos:[8] ;default: 1'b0 ; */ 2057 /*description: wdt reset whole chip enable.*/ 2058 #define RTC_CNTL_WDT_CHIP_RESET_EN (BIT(8)) 2059 #define RTC_CNTL_WDT_CHIP_RESET_EN_M (BIT(8)) 2060 #define RTC_CNTL_WDT_CHIP_RESET_EN_V 0x1 2061 #define RTC_CNTL_WDT_CHIP_RESET_EN_S 8 2062 /* RTC_CNTL_WDT_CHIP_RESET_WIDTH : R/W ;bitpos:[7:0] ;default: 8'd20 ; */ 2063 /*description: chip reset siginal pulse width.*/ 2064 #define RTC_CNTL_WDT_CHIP_RESET_WIDTH 0x000000FF 2065 #define RTC_CNTL_WDT_CHIP_RESET_WIDTH_M ((RTC_CNTL_WDT_CHIP_RESET_WIDTH_V)<<(RTC_CNTL_WDT_CHIP_RESET_WIDTH_S)) 2066 #define RTC_CNTL_WDT_CHIP_RESET_WIDTH_V 0xFF 2067 #define RTC_CNTL_WDT_CHIP_RESET_WIDTH_S 0 2068 2069 #define RTC_CNTL_WDTCONFIG1_REG (DR_REG_RTCCNTL_BASE + 0x9C) 2070 /* RTC_CNTL_WDT_STG0_HOLD : R/W ;bitpos:[31:0] ;default: 32'd200000 ; */ 2071 /*description: .*/ 2072 #define RTC_CNTL_WDT_STG0_HOLD 0xFFFFFFFF 2073 #define RTC_CNTL_WDT_STG0_HOLD_M ((RTC_CNTL_WDT_STG0_HOLD_V)<<(RTC_CNTL_WDT_STG0_HOLD_S)) 2074 #define RTC_CNTL_WDT_STG0_HOLD_V 0xFFFFFFFF 2075 #define RTC_CNTL_WDT_STG0_HOLD_S 0 2076 2077 #define RTC_CNTL_WDTCONFIG2_REG (DR_REG_RTCCNTL_BASE + 0xA0) 2078 /* RTC_CNTL_WDT_STG1_HOLD : R/W ;bitpos:[31:0] ;default: 32'd80000 ; */ 2079 /*description: .*/ 2080 #define RTC_CNTL_WDT_STG1_HOLD 0xFFFFFFFF 2081 #define RTC_CNTL_WDT_STG1_HOLD_M ((RTC_CNTL_WDT_STG1_HOLD_V)<<(RTC_CNTL_WDT_STG1_HOLD_S)) 2082 #define RTC_CNTL_WDT_STG1_HOLD_V 0xFFFFFFFF 2083 #define RTC_CNTL_WDT_STG1_HOLD_S 0 2084 2085 #define RTC_CNTL_WDTCONFIG3_REG (DR_REG_RTCCNTL_BASE + 0xA4) 2086 /* RTC_CNTL_WDT_STG2_HOLD : R/W ;bitpos:[31:0] ;default: 32'hfff ; */ 2087 /*description: .*/ 2088 #define RTC_CNTL_WDT_STG2_HOLD 0xFFFFFFFF 2089 #define RTC_CNTL_WDT_STG2_HOLD_M ((RTC_CNTL_WDT_STG2_HOLD_V)<<(RTC_CNTL_WDT_STG2_HOLD_S)) 2090 #define RTC_CNTL_WDT_STG2_HOLD_V 0xFFFFFFFF 2091 #define RTC_CNTL_WDT_STG2_HOLD_S 0 2092 2093 #define RTC_CNTL_WDTCONFIG4_REG (DR_REG_RTCCNTL_BASE + 0xA8) 2094 /* RTC_CNTL_WDT_STG3_HOLD : R/W ;bitpos:[31:0] ;default: 32'hfff ; */ 2095 /*description: .*/ 2096 #define RTC_CNTL_WDT_STG3_HOLD 0xFFFFFFFF 2097 #define RTC_CNTL_WDT_STG3_HOLD_M ((RTC_CNTL_WDT_STG3_HOLD_V)<<(RTC_CNTL_WDT_STG3_HOLD_S)) 2098 #define RTC_CNTL_WDT_STG3_HOLD_V 0xFFFFFFFF 2099 #define RTC_CNTL_WDT_STG3_HOLD_S 0 2100 2101 #define RTC_CNTL_WDTFEED_REG (DR_REG_RTCCNTL_BASE + 0xAC) 2102 /* RTC_CNTL_WDT_FEED : WO ;bitpos:[31] ;default: 1'd0 ; */ 2103 /*description: .*/ 2104 #define RTC_CNTL_WDT_FEED (BIT(31)) 2105 #define RTC_CNTL_WDT_FEED_M (BIT(31)) 2106 #define RTC_CNTL_WDT_FEED_V 0x1 2107 #define RTC_CNTL_WDT_FEED_S 31 2108 2109 #define RTC_CNTL_WDTWPROTECT_REG (DR_REG_RTCCNTL_BASE + 0xB0) 2110 /* RTC_CNTL_WDT_WKEY : R/W ;bitpos:[31:0] ;default: 32'h50d83aa1 ; */ 2111 /*description: .*/ 2112 #define RTC_CNTL_WDT_WKEY 0xFFFFFFFF 2113 #define RTC_CNTL_WDT_WKEY_M ((RTC_CNTL_WDT_WKEY_V)<<(RTC_CNTL_WDT_WKEY_S)) 2114 #define RTC_CNTL_WDT_WKEY_V 0xFFFFFFFF 2115 #define RTC_CNTL_WDT_WKEY_S 0 2116 2117 #define RTC_CNTL_SWD_CONF_REG (DR_REG_RTCCNTL_BASE + 0xB4) 2118 /* RTC_CNTL_SWD_AUTO_FEED_EN : R/W ;bitpos:[31] ;default: 1'b0 ; */ 2119 /*description: automatically feed swd when int comes.*/ 2120 #define RTC_CNTL_SWD_AUTO_FEED_EN (BIT(31)) 2121 #define RTC_CNTL_SWD_AUTO_FEED_EN_M (BIT(31)) 2122 #define RTC_CNTL_SWD_AUTO_FEED_EN_V 0x1 2123 #define RTC_CNTL_SWD_AUTO_FEED_EN_S 31 2124 /* RTC_CNTL_SWD_DISABLE : R/W ;bitpos:[30] ;default: 1'b0 ; */ 2125 /*description: disabel SWD.*/ 2126 #define RTC_CNTL_SWD_DISABLE (BIT(30)) 2127 #define RTC_CNTL_SWD_DISABLE_M (BIT(30)) 2128 #define RTC_CNTL_SWD_DISABLE_V 0x1 2129 #define RTC_CNTL_SWD_DISABLE_S 30 2130 /* RTC_CNTL_SWD_FEED : WO ;bitpos:[29] ;default: 1'b0 ; */ 2131 /*description: Sw feed swd.*/ 2132 #define RTC_CNTL_SWD_FEED (BIT(29)) 2133 #define RTC_CNTL_SWD_FEED_M (BIT(29)) 2134 #define RTC_CNTL_SWD_FEED_V 0x1 2135 #define RTC_CNTL_SWD_FEED_S 29 2136 /* RTC_CNTL_SWD_RST_FLAG_CLR : WO ;bitpos:[28] ;default: 1'b0 ; */ 2137 /*description: reset swd reset flag.*/ 2138 #define RTC_CNTL_SWD_RST_FLAG_CLR (BIT(28)) 2139 #define RTC_CNTL_SWD_RST_FLAG_CLR_M (BIT(28)) 2140 #define RTC_CNTL_SWD_RST_FLAG_CLR_V 0x1 2141 #define RTC_CNTL_SWD_RST_FLAG_CLR_S 28 2142 /* RTC_CNTL_SWD_SIGNAL_WIDTH : R/W ;bitpos:[27:18] ;default: 10'd300 ; */ 2143 /*description: adjust signal width send to swd.*/ 2144 #define RTC_CNTL_SWD_SIGNAL_WIDTH 0x000003FF 2145 #define RTC_CNTL_SWD_SIGNAL_WIDTH_M ((RTC_CNTL_SWD_SIGNAL_WIDTH_V)<<(RTC_CNTL_SWD_SIGNAL_WIDTH_S)) 2146 #define RTC_CNTL_SWD_SIGNAL_WIDTH_V 0x3FF 2147 #define RTC_CNTL_SWD_SIGNAL_WIDTH_S 18 2148 /* RTC_CNTL_SWD_BYPASS_RST : R/W ;bitpos:[17] ;default: 1'b0 ; */ 2149 /*description: .*/ 2150 #define RTC_CNTL_SWD_BYPASS_RST (BIT(17)) 2151 #define RTC_CNTL_SWD_BYPASS_RST_M (BIT(17)) 2152 #define RTC_CNTL_SWD_BYPASS_RST_V 0x1 2153 #define RTC_CNTL_SWD_BYPASS_RST_S 17 2154 /* RTC_CNTL_SWD_FEED_INT : RO ;bitpos:[1] ;default: 1'b0 ; */ 2155 /*description: swd interrupt for feeding.*/ 2156 #define RTC_CNTL_SWD_FEED_INT (BIT(1)) 2157 #define RTC_CNTL_SWD_FEED_INT_M (BIT(1)) 2158 #define RTC_CNTL_SWD_FEED_INT_V 0x1 2159 #define RTC_CNTL_SWD_FEED_INT_S 1 2160 /* RTC_CNTL_SWD_RESET_FLAG : RO ;bitpos:[0] ;default: 1'b0 ; */ 2161 /*description: swd reset flag.*/ 2162 #define RTC_CNTL_SWD_RESET_FLAG (BIT(0)) 2163 #define RTC_CNTL_SWD_RESET_FLAG_M (BIT(0)) 2164 #define RTC_CNTL_SWD_RESET_FLAG_V 0x1 2165 #define RTC_CNTL_SWD_RESET_FLAG_S 0 2166 2167 #define RTC_CNTL_SWD_WPROTECT_REG (DR_REG_RTCCNTL_BASE + 0xB8) 2168 /* RTC_CNTL_SWD_WKEY : R/W ;bitpos:[31:0] ;default: 32'h8f1d312a ; */ 2169 /*description: .*/ 2170 #define RTC_CNTL_SWD_WKEY 0xFFFFFFFF 2171 #define RTC_CNTL_SWD_WKEY_M ((RTC_CNTL_SWD_WKEY_V)<<(RTC_CNTL_SWD_WKEY_S)) 2172 #define RTC_CNTL_SWD_WKEY_V 0xFFFFFFFF 2173 #define RTC_CNTL_SWD_WKEY_S 0 2174 2175 #define RTC_CNTL_SW_CPU_STALL_REG (DR_REG_RTCCNTL_BASE + 0xBC) 2176 /* RTC_CNTL_SW_STALL_PROCPU_C1 : R/W ;bitpos:[31:26] ;default: 6'b0 ; */ 2177 /*description: .*/ 2178 #define RTC_CNTL_SW_STALL_PROCPU_C1 0x0000003F 2179 #define RTC_CNTL_SW_STALL_PROCPU_C1_M ((RTC_CNTL_SW_STALL_PROCPU_C1_V)<<(RTC_CNTL_SW_STALL_PROCPU_C1_S)) 2180 #define RTC_CNTL_SW_STALL_PROCPU_C1_V 0x3F 2181 #define RTC_CNTL_SW_STALL_PROCPU_C1_S 26 2182 /* RTC_CNTL_SW_STALL_APPCPU_C1 : R/W ;bitpos:[25:20] ;default: 6'b0 ; */ 2183 /*description: {reg_sw_stall_appcpu_c1[5:0].*/ 2184 #define RTC_CNTL_SW_STALL_APPCPU_C1 0x0000003F 2185 #define RTC_CNTL_SW_STALL_APPCPU_C1_M ((RTC_CNTL_SW_STALL_APPCPU_C1_V)<<(RTC_CNTL_SW_STALL_APPCPU_C1_S)) 2186 #define RTC_CNTL_SW_STALL_APPCPU_C1_V 0x3F 2187 #define RTC_CNTL_SW_STALL_APPCPU_C1_S 20 2188 2189 #define RTC_CNTL_STORE4_REG (DR_REG_RTCCNTL_BASE + 0xC0) 2190 /* RTC_CNTL_SCRATCH4 : R/W ;bitpos:[31:0] ;default: 0 ; */ 2191 /*description: .*/ 2192 #define RTC_CNTL_SCRATCH4 0xFFFFFFFF 2193 #define RTC_CNTL_SCRATCH4_M ((RTC_CNTL_SCRATCH4_V)<<(RTC_CNTL_SCRATCH4_S)) 2194 #define RTC_CNTL_SCRATCH4_V 0xFFFFFFFF 2195 #define RTC_CNTL_SCRATCH4_S 0 2196 2197 #define RTC_CNTL_STORE5_REG (DR_REG_RTCCNTL_BASE + 0xC4) 2198 /* RTC_CNTL_SCRATCH5 : R/W ;bitpos:[31:0] ;default: 0 ; */ 2199 /*description: .*/ 2200 #define RTC_CNTL_SCRATCH5 0xFFFFFFFF 2201 #define RTC_CNTL_SCRATCH5_M ((RTC_CNTL_SCRATCH5_V)<<(RTC_CNTL_SCRATCH5_S)) 2202 #define RTC_CNTL_SCRATCH5_V 0xFFFFFFFF 2203 #define RTC_CNTL_SCRATCH5_S 0 2204 2205 #define RTC_CNTL_STORE6_REG (DR_REG_RTCCNTL_BASE + 0xC8) 2206 /* RTC_CNTL_SCRATCH6 : R/W ;bitpos:[31:0] ;default: 0 ; */ 2207 /*description: .*/ 2208 #define RTC_CNTL_SCRATCH6 0xFFFFFFFF 2209 #define RTC_CNTL_SCRATCH6_M ((RTC_CNTL_SCRATCH6_V)<<(RTC_CNTL_SCRATCH6_S)) 2210 #define RTC_CNTL_SCRATCH6_V 0xFFFFFFFF 2211 #define RTC_CNTL_SCRATCH6_S 0 2212 2213 #define RTC_CNTL_STORE7_REG (DR_REG_RTCCNTL_BASE + 0xCC) 2214 /* RTC_CNTL_SCRATCH7 : R/W ;bitpos:[31:0] ;default: 0 ; */ 2215 /*description: .*/ 2216 #define RTC_CNTL_SCRATCH7 0xFFFFFFFF 2217 #define RTC_CNTL_SCRATCH7_M ((RTC_CNTL_SCRATCH7_V)<<(RTC_CNTL_SCRATCH7_S)) 2218 #define RTC_CNTL_SCRATCH7_V 0xFFFFFFFF 2219 #define RTC_CNTL_SCRATCH7_S 0 2220 2221 #define RTC_CNTL_LOW_POWER_ST_REG (DR_REG_RTCCNTL_BASE + 0xD0) 2222 /* RTC_CNTL_MAIN_STATE : RO ;bitpos:[31:28] ;default: 4'd0 ; */ 2223 /*description: rtc main state machine status.*/ 2224 #define RTC_CNTL_MAIN_STATE 0x0000000F 2225 #define RTC_CNTL_MAIN_STATE_M ((RTC_CNTL_MAIN_STATE_V)<<(RTC_CNTL_MAIN_STATE_S)) 2226 #define RTC_CNTL_MAIN_STATE_V 0xF 2227 #define RTC_CNTL_MAIN_STATE_S 28 2228 /* RTC_CNTL_MAIN_STATE_IN_IDLE : RO ;bitpos:[27] ;default: 1'b0 ; */ 2229 /*description: rtc main state machine is in idle state.*/ 2230 #define RTC_CNTL_MAIN_STATE_IN_IDLE (BIT(27)) 2231 #define RTC_CNTL_MAIN_STATE_IN_IDLE_M (BIT(27)) 2232 #define RTC_CNTL_MAIN_STATE_IN_IDLE_V 0x1 2233 #define RTC_CNTL_MAIN_STATE_IN_IDLE_S 27 2234 /* RTC_CNTL_MAIN_STATE_IN_SLP : RO ;bitpos:[26] ;default: 1'b0 ; */ 2235 /*description: rtc main state machine is in sleep state.*/ 2236 #define RTC_CNTL_MAIN_STATE_IN_SLP (BIT(26)) 2237 #define RTC_CNTL_MAIN_STATE_IN_SLP_M (BIT(26)) 2238 #define RTC_CNTL_MAIN_STATE_IN_SLP_V 0x1 2239 #define RTC_CNTL_MAIN_STATE_IN_SLP_S 26 2240 /* RTC_CNTL_MAIN_STATE_IN_WAIT_XTL : RO ;bitpos:[25] ;default: 1'b0 ; */ 2241 /*description: rtc main state machine is in wait xtal state.*/ 2242 #define RTC_CNTL_MAIN_STATE_IN_WAIT_XTL (BIT(25)) 2243 #define RTC_CNTL_MAIN_STATE_IN_WAIT_XTL_M (BIT(25)) 2244 #define RTC_CNTL_MAIN_STATE_IN_WAIT_XTL_V 0x1 2245 #define RTC_CNTL_MAIN_STATE_IN_WAIT_XTL_S 25 2246 /* RTC_CNTL_MAIN_STATE_IN_WAIT_PLL : RO ;bitpos:[24] ;default: 1'b0 ; */ 2247 /*description: rtc main state machine is in wait pll state.*/ 2248 #define RTC_CNTL_MAIN_STATE_IN_WAIT_PLL (BIT(24)) 2249 #define RTC_CNTL_MAIN_STATE_IN_WAIT_PLL_M (BIT(24)) 2250 #define RTC_CNTL_MAIN_STATE_IN_WAIT_PLL_V 0x1 2251 #define RTC_CNTL_MAIN_STATE_IN_WAIT_PLL_S 24 2252 /* RTC_CNTL_MAIN_STATE_IN_WAIT_8M : RO ;bitpos:[23] ;default: 1'b0 ; */ 2253 /*description: rtc main state machine is in wait 8m state.*/ 2254 #define RTC_CNTL_MAIN_STATE_IN_WAIT_8M (BIT(23)) 2255 #define RTC_CNTL_MAIN_STATE_IN_WAIT_8M_M (BIT(23)) 2256 #define RTC_CNTL_MAIN_STATE_IN_WAIT_8M_V 0x1 2257 #define RTC_CNTL_MAIN_STATE_IN_WAIT_8M_S 23 2258 /* RTC_CNTL_IN_LOW_POWER_STATE : RO ;bitpos:[22] ;default: 1'b0 ; */ 2259 /*description: rtc main state machine is in the states of low power.*/ 2260 #define RTC_CNTL_IN_LOW_POWER_STATE (BIT(22)) 2261 #define RTC_CNTL_IN_LOW_POWER_STATE_M (BIT(22)) 2262 #define RTC_CNTL_IN_LOW_POWER_STATE_V 0x1 2263 #define RTC_CNTL_IN_LOW_POWER_STATE_S 22 2264 /* RTC_CNTL_IN_WAKEUP_STATE : RO ;bitpos:[21] ;default: 1'b0 ; */ 2265 /*description: rtc main state machine is in the states of wakeup process.*/ 2266 #define RTC_CNTL_IN_WAKEUP_STATE (BIT(21)) 2267 #define RTC_CNTL_IN_WAKEUP_STATE_M (BIT(21)) 2268 #define RTC_CNTL_IN_WAKEUP_STATE_V 0x1 2269 #define RTC_CNTL_IN_WAKEUP_STATE_S 21 2270 /* RTC_CNTL_MAIN_STATE_WAIT_END : RO ;bitpos:[20] ;default: 1'b0 ; */ 2271 /*description: rtc main state machine has been waited for some cycles.*/ 2272 #define RTC_CNTL_MAIN_STATE_WAIT_END (BIT(20)) 2273 #define RTC_CNTL_MAIN_STATE_WAIT_END_M (BIT(20)) 2274 #define RTC_CNTL_MAIN_STATE_WAIT_END_V 0x1 2275 #define RTC_CNTL_MAIN_STATE_WAIT_END_S 20 2276 /* RTC_CNTL_RDY_FOR_WAKEUP : RO ;bitpos:[19] ;default: 1'b0 ; */ 2277 /*description: rtc is ready to receive wake up trigger from wake up source.*/ 2278 #define RTC_CNTL_RDY_FOR_WAKEUP (BIT(19)) 2279 #define RTC_CNTL_RDY_FOR_WAKEUP_M (BIT(19)) 2280 #define RTC_CNTL_RDY_FOR_WAKEUP_V 0x1 2281 #define RTC_CNTL_RDY_FOR_WAKEUP_S 19 2282 /* RTC_CNTL_MAIN_STATE_PLL_ON : RO ;bitpos:[18] ;default: 1'b0 ; */ 2283 /*description: rtc main state machine is in states that pll should be running.*/ 2284 #define RTC_CNTL_MAIN_STATE_PLL_ON (BIT(18)) 2285 #define RTC_CNTL_MAIN_STATE_PLL_ON_M (BIT(18)) 2286 #define RTC_CNTL_MAIN_STATE_PLL_ON_V 0x1 2287 #define RTC_CNTL_MAIN_STATE_PLL_ON_S 18 2288 /* RTC_CNTL_MAIN_STATE_XTAL_ISO : RO ;bitpos:[17] ;default: 1'b0 ; */ 2289 /*description: no use any more.*/ 2290 #define RTC_CNTL_MAIN_STATE_XTAL_ISO (BIT(17)) 2291 #define RTC_CNTL_MAIN_STATE_XTAL_ISO_M (BIT(17)) 2292 #define RTC_CNTL_MAIN_STATE_XTAL_ISO_V 0x1 2293 #define RTC_CNTL_MAIN_STATE_XTAL_ISO_S 17 2294 /* RTC_CNTL_COCPU_STATE_DONE : RO ;bitpos:[16] ;default: 1'b0 ; */ 2295 /*description: ulp/cocpu is done.*/ 2296 #define RTC_CNTL_COCPU_STATE_DONE (BIT(16)) 2297 #define RTC_CNTL_COCPU_STATE_DONE_M (BIT(16)) 2298 #define RTC_CNTL_COCPU_STATE_DONE_V 0x1 2299 #define RTC_CNTL_COCPU_STATE_DONE_S 16 2300 /* RTC_CNTL_COCPU_STATE_SLP : RO ;bitpos:[15] ;default: 1'b0 ; */ 2301 /*description: ulp/cocpu is in sleep state.*/ 2302 #define RTC_CNTL_COCPU_STATE_SLP (BIT(15)) 2303 #define RTC_CNTL_COCPU_STATE_SLP_M (BIT(15)) 2304 #define RTC_CNTL_COCPU_STATE_SLP_V 0x1 2305 #define RTC_CNTL_COCPU_STATE_SLP_S 15 2306 /* RTC_CNTL_COCPU_STATE_SWITCH : RO ;bitpos:[14] ;default: 1'b0 ; */ 2307 /*description: ulp/cocpu is about to working. Switch rtc main state.*/ 2308 #define RTC_CNTL_COCPU_STATE_SWITCH (BIT(14)) 2309 #define RTC_CNTL_COCPU_STATE_SWITCH_M (BIT(14)) 2310 #define RTC_CNTL_COCPU_STATE_SWITCH_V 0x1 2311 #define RTC_CNTL_COCPU_STATE_SWITCH_S 14 2312 /* RTC_CNTL_COCPU_STATE_START : RO ;bitpos:[13] ;default: 1'b0 ; */ 2313 /*description: ulp/cocpu should start to work.*/ 2314 #define RTC_CNTL_COCPU_STATE_START (BIT(13)) 2315 #define RTC_CNTL_COCPU_STATE_START_M (BIT(13)) 2316 #define RTC_CNTL_COCPU_STATE_START_V 0x1 2317 #define RTC_CNTL_COCPU_STATE_START_S 13 2318 /* RTC_CNTL_TOUCH_STATE_DONE : RO ;bitpos:[12] ;default: 1'b0 ; */ 2319 /*description: touch is done.*/ 2320 #define RTC_CNTL_TOUCH_STATE_DONE (BIT(12)) 2321 #define RTC_CNTL_TOUCH_STATE_DONE_M (BIT(12)) 2322 #define RTC_CNTL_TOUCH_STATE_DONE_V 0x1 2323 #define RTC_CNTL_TOUCH_STATE_DONE_S 12 2324 /* RTC_CNTL_TOUCH_STATE_SLP : RO ;bitpos:[11] ;default: 1'b0 ; */ 2325 /*description: touch is in sleep state.*/ 2326 #define RTC_CNTL_TOUCH_STATE_SLP (BIT(11)) 2327 #define RTC_CNTL_TOUCH_STATE_SLP_M (BIT(11)) 2328 #define RTC_CNTL_TOUCH_STATE_SLP_V 0x1 2329 #define RTC_CNTL_TOUCH_STATE_SLP_S 11 2330 /* RTC_CNTL_TOUCH_STATE_SWITCH : RO ;bitpos:[10] ;default: 1'b0 ; */ 2331 /*description: touch is about to working. Switch rtc main state.*/ 2332 #define RTC_CNTL_TOUCH_STATE_SWITCH (BIT(10)) 2333 #define RTC_CNTL_TOUCH_STATE_SWITCH_M (BIT(10)) 2334 #define RTC_CNTL_TOUCH_STATE_SWITCH_V 0x1 2335 #define RTC_CNTL_TOUCH_STATE_SWITCH_S 10 2336 /* RTC_CNTL_TOUCH_STATE_START : RO ;bitpos:[9] ;default: 1'b0 ; */ 2337 /*description: touch should start to work.*/ 2338 #define RTC_CNTL_TOUCH_STATE_START (BIT(9)) 2339 #define RTC_CNTL_TOUCH_STATE_START_M (BIT(9)) 2340 #define RTC_CNTL_TOUCH_STATE_START_V 0x1 2341 #define RTC_CNTL_TOUCH_STATE_START_S 9 2342 /* RTC_CNTL_XPD_DIG : RO ;bitpos:[8] ;default: 1'b0 ; */ 2343 /*description: digital wrap power down.*/ 2344 #define RTC_CNTL_XPD_DIG (BIT(8)) 2345 #define RTC_CNTL_XPD_DIG_M (BIT(8)) 2346 #define RTC_CNTL_XPD_DIG_V 0x1 2347 #define RTC_CNTL_XPD_DIG_S 8 2348 /* RTC_CNTL_DIG_ISO : RO ;bitpos:[7] ;default: 1'b0 ; */ 2349 /*description: digital wrap iso.*/ 2350 #define RTC_CNTL_DIG_ISO (BIT(7)) 2351 #define RTC_CNTL_DIG_ISO_M (BIT(7)) 2352 #define RTC_CNTL_DIG_ISO_V 0x1 2353 #define RTC_CNTL_DIG_ISO_S 7 2354 /* RTC_CNTL_XPD_WIFI : RO ;bitpos:[6] ;default: 1'b0 ; */ 2355 /*description: wifi wrap power down.*/ 2356 #define RTC_CNTL_XPD_WIFI (BIT(6)) 2357 #define RTC_CNTL_XPD_WIFI_M (BIT(6)) 2358 #define RTC_CNTL_XPD_WIFI_V 0x1 2359 #define RTC_CNTL_XPD_WIFI_S 6 2360 /* RTC_CNTL_WIFI_ISO : RO ;bitpos:[5] ;default: 1'b0 ; */ 2361 /*description: wifi iso.*/ 2362 #define RTC_CNTL_WIFI_ISO (BIT(5)) 2363 #define RTC_CNTL_WIFI_ISO_M (BIT(5)) 2364 #define RTC_CNTL_WIFI_ISO_V 0x1 2365 #define RTC_CNTL_WIFI_ISO_S 5 2366 /* RTC_CNTL_XPD_RTC_PERI : RO ;bitpos:[4] ;default: 1'b0 ; */ 2367 /*description: rtc peripheral power down .*/ 2368 #define RTC_CNTL_XPD_RTC_PERI (BIT(4)) 2369 #define RTC_CNTL_XPD_RTC_PERI_M (BIT(4)) 2370 #define RTC_CNTL_XPD_RTC_PERI_V 0x1 2371 #define RTC_CNTL_XPD_RTC_PERI_S 4 2372 /* RTC_CNTL_PERI_ISO : RO ;bitpos:[3] ;default: 1'b0 ; */ 2373 /*description: rtc peripheral iso.*/ 2374 #define RTC_CNTL_PERI_ISO (BIT(3)) 2375 #define RTC_CNTL_PERI_ISO_M (BIT(3)) 2376 #define RTC_CNTL_PERI_ISO_V 0x1 2377 #define RTC_CNTL_PERI_ISO_S 3 2378 /* RTC_CNTL_XPD_DIG_DCDC : RO ;bitpos:[2] ;default: 1'b0 ; */ 2379 /*description: External DCDC power down.*/ 2380 #define RTC_CNTL_XPD_DIG_DCDC (BIT(2)) 2381 #define RTC_CNTL_XPD_DIG_DCDC_M (BIT(2)) 2382 #define RTC_CNTL_XPD_DIG_DCDC_V 0x1 2383 #define RTC_CNTL_XPD_DIG_DCDC_S 2 2384 /* RTC_CNTL_XPD_ROM0 : RO ;bitpos:[0] ;default: 1'b0 ; */ 2385 /*description: rom0 power down.*/ 2386 #define RTC_CNTL_XPD_ROM0 (BIT(0)) 2387 #define RTC_CNTL_XPD_ROM0_M (BIT(0)) 2388 #define RTC_CNTL_XPD_ROM0_V 0x1 2389 #define RTC_CNTL_XPD_ROM0_S 0 2390 2391 #define RTC_CNTL_DIAG0_REG (DR_REG_RTCCNTL_BASE + 0xD4) 2392 /* RTC_CNTL_LOW_POWER_DIAG1 : RO ;bitpos:[31:0] ;default: 0 ; */ 2393 /*description: .*/ 2394 #define RTC_CNTL_LOW_POWER_DIAG1 0xFFFFFFFF 2395 #define RTC_CNTL_LOW_POWER_DIAG1_M ((RTC_CNTL_LOW_POWER_DIAG1_V)<<(RTC_CNTL_LOW_POWER_DIAG1_S)) 2396 #define RTC_CNTL_LOW_POWER_DIAG1_V 0xFFFFFFFF 2397 #define RTC_CNTL_LOW_POWER_DIAG1_S 0 2398 2399 #define RTC_CNTL_PAD_HOLD_REG (DR_REG_RTCCNTL_BASE + 0xD8) 2400 /* RTC_CNTL_PAD21_HOLD : R/W ;bitpos:[21] ;default: 1'b0 ; */ 2401 /*description: .*/ 2402 #define RTC_CNTL_PAD21_HOLD (BIT(21)) 2403 #define RTC_CNTL_PAD21_HOLD_M (BIT(21)) 2404 #define RTC_CNTL_PAD21_HOLD_V 0x1 2405 #define RTC_CNTL_PAD21_HOLD_S 21 2406 /* RTC_CNTL_PAD20_HOLD : R/W ;bitpos:[20] ;default: 1'b0 ; */ 2407 /*description: .*/ 2408 #define RTC_CNTL_PAD20_HOLD (BIT(20)) 2409 #define RTC_CNTL_PAD20_HOLD_M (BIT(20)) 2410 #define RTC_CNTL_PAD20_HOLD_V 0x1 2411 #define RTC_CNTL_PAD20_HOLD_S 20 2412 /* RTC_CNTL_PAD19_HOLD : R/W ;bitpos:[19] ;default: 1'b0 ; */ 2413 /*description: .*/ 2414 #define RTC_CNTL_PAD19_HOLD (BIT(19)) 2415 #define RTC_CNTL_PAD19_HOLD_M (BIT(19)) 2416 #define RTC_CNTL_PAD19_HOLD_V 0x1 2417 #define RTC_CNTL_PAD19_HOLD_S 19 2418 /* RTC_CNTL_PDAC2_HOLD : R/W ;bitpos:[18] ;default: 1'b0 ; */ 2419 /*description: .*/ 2420 #define RTC_CNTL_PDAC2_HOLD (BIT(18)) 2421 #define RTC_CNTL_PDAC2_HOLD_M (BIT(18)) 2422 #define RTC_CNTL_PDAC2_HOLD_V 0x1 2423 #define RTC_CNTL_PDAC2_HOLD_S 18 2424 /* RTC_CNTL_PDAC1_HOLD : R/W ;bitpos:[17] ;default: 1'b0 ; */ 2425 /*description: .*/ 2426 #define RTC_CNTL_PDAC1_HOLD (BIT(17)) 2427 #define RTC_CNTL_PDAC1_HOLD_M (BIT(17)) 2428 #define RTC_CNTL_PDAC1_HOLD_V 0x1 2429 #define RTC_CNTL_PDAC1_HOLD_S 17 2430 /* RTC_CNTL_X32N_HOLD : R/W ;bitpos:[16] ;default: 1'b0 ; */ 2431 /*description: .*/ 2432 #define RTC_CNTL_X32N_HOLD (BIT(16)) 2433 #define RTC_CNTL_X32N_HOLD_M (BIT(16)) 2434 #define RTC_CNTL_X32N_HOLD_V 0x1 2435 #define RTC_CNTL_X32N_HOLD_S 16 2436 /* RTC_CNTL_X32P_HOLD : R/W ;bitpos:[15] ;default: 1'b0 ; */ 2437 /*description: .*/ 2438 #define RTC_CNTL_X32P_HOLD (BIT(15)) 2439 #define RTC_CNTL_X32P_HOLD_M (BIT(15)) 2440 #define RTC_CNTL_X32P_HOLD_V 0x1 2441 #define RTC_CNTL_X32P_HOLD_S 15 2442 /* RTC_CNTL_TOUCH_PAD14_HOLD : R/W ;bitpos:[14] ;default: 1'b0 ; */ 2443 /*description: .*/ 2444 #define RTC_CNTL_TOUCH_PAD14_HOLD (BIT(14)) 2445 #define RTC_CNTL_TOUCH_PAD14_HOLD_M (BIT(14)) 2446 #define RTC_CNTL_TOUCH_PAD14_HOLD_V 0x1 2447 #define RTC_CNTL_TOUCH_PAD14_HOLD_S 14 2448 /* RTC_CNTL_TOUCH_PAD13_HOLD : R/W ;bitpos:[13] ;default: 1'b0 ; */ 2449 /*description: .*/ 2450 #define RTC_CNTL_TOUCH_PAD13_HOLD (BIT(13)) 2451 #define RTC_CNTL_TOUCH_PAD13_HOLD_M (BIT(13)) 2452 #define RTC_CNTL_TOUCH_PAD13_HOLD_V 0x1 2453 #define RTC_CNTL_TOUCH_PAD13_HOLD_S 13 2454 /* RTC_CNTL_TOUCH_PAD12_HOLD : R/W ;bitpos:[12] ;default: 1'b0 ; */ 2455 /*description: .*/ 2456 #define RTC_CNTL_TOUCH_PAD12_HOLD (BIT(12)) 2457 #define RTC_CNTL_TOUCH_PAD12_HOLD_M (BIT(12)) 2458 #define RTC_CNTL_TOUCH_PAD12_HOLD_V 0x1 2459 #define RTC_CNTL_TOUCH_PAD12_HOLD_S 12 2460 /* RTC_CNTL_TOUCH_PAD11_HOLD : R/W ;bitpos:[11] ;default: 1'b0 ; */ 2461 /*description: .*/ 2462 #define RTC_CNTL_TOUCH_PAD11_HOLD (BIT(11)) 2463 #define RTC_CNTL_TOUCH_PAD11_HOLD_M (BIT(11)) 2464 #define RTC_CNTL_TOUCH_PAD11_HOLD_V 0x1 2465 #define RTC_CNTL_TOUCH_PAD11_HOLD_S 11 2466 /* RTC_CNTL_TOUCH_PAD10_HOLD : R/W ;bitpos:[10] ;default: 1'b0 ; */ 2467 /*description: .*/ 2468 #define RTC_CNTL_TOUCH_PAD10_HOLD (BIT(10)) 2469 #define RTC_CNTL_TOUCH_PAD10_HOLD_M (BIT(10)) 2470 #define RTC_CNTL_TOUCH_PAD10_HOLD_V 0x1 2471 #define RTC_CNTL_TOUCH_PAD10_HOLD_S 10 2472 /* RTC_CNTL_TOUCH_PAD9_HOLD : R/W ;bitpos:[9] ;default: 1'b0 ; */ 2473 /*description: .*/ 2474 #define RTC_CNTL_TOUCH_PAD9_HOLD (BIT(9)) 2475 #define RTC_CNTL_TOUCH_PAD9_HOLD_M (BIT(9)) 2476 #define RTC_CNTL_TOUCH_PAD9_HOLD_V 0x1 2477 #define RTC_CNTL_TOUCH_PAD9_HOLD_S 9 2478 /* RTC_CNTL_TOUCH_PAD8_HOLD : R/W ;bitpos:[8] ;default: 1'b0 ; */ 2479 /*description: .*/ 2480 #define RTC_CNTL_TOUCH_PAD8_HOLD (BIT(8)) 2481 #define RTC_CNTL_TOUCH_PAD8_HOLD_M (BIT(8)) 2482 #define RTC_CNTL_TOUCH_PAD8_HOLD_V 0x1 2483 #define RTC_CNTL_TOUCH_PAD8_HOLD_S 8 2484 /* RTC_CNTL_TOUCH_PAD7_HOLD : R/W ;bitpos:[7] ;default: 1'b0 ; */ 2485 /*description: .*/ 2486 #define RTC_CNTL_TOUCH_PAD7_HOLD (BIT(7)) 2487 #define RTC_CNTL_TOUCH_PAD7_HOLD_M (BIT(7)) 2488 #define RTC_CNTL_TOUCH_PAD7_HOLD_V 0x1 2489 #define RTC_CNTL_TOUCH_PAD7_HOLD_S 7 2490 /* RTC_CNTL_TOUCH_PAD6_HOLD : R/W ;bitpos:[6] ;default: 1'b0 ; */ 2491 /*description: .*/ 2492 #define RTC_CNTL_TOUCH_PAD6_HOLD (BIT(6)) 2493 #define RTC_CNTL_TOUCH_PAD6_HOLD_M (BIT(6)) 2494 #define RTC_CNTL_TOUCH_PAD6_HOLD_V 0x1 2495 #define RTC_CNTL_TOUCH_PAD6_HOLD_S 6 2496 /* RTC_CNTL_TOUCH_PAD5_HOLD : R/W ;bitpos:[5] ;default: 1'b0 ; */ 2497 /*description: .*/ 2498 #define RTC_CNTL_TOUCH_PAD5_HOLD (BIT(5)) 2499 #define RTC_CNTL_TOUCH_PAD5_HOLD_M (BIT(5)) 2500 #define RTC_CNTL_TOUCH_PAD5_HOLD_V 0x1 2501 #define RTC_CNTL_TOUCH_PAD5_HOLD_S 5 2502 /* RTC_CNTL_TOUCH_PAD4_HOLD : R/W ;bitpos:[4] ;default: 1'b0 ; */ 2503 /*description: .*/ 2504 #define RTC_CNTL_TOUCH_PAD4_HOLD (BIT(4)) 2505 #define RTC_CNTL_TOUCH_PAD4_HOLD_M (BIT(4)) 2506 #define RTC_CNTL_TOUCH_PAD4_HOLD_V 0x1 2507 #define RTC_CNTL_TOUCH_PAD4_HOLD_S 4 2508 /* RTC_CNTL_TOUCH_PAD3_HOLD : R/W ;bitpos:[3] ;default: 1'b0 ; */ 2509 /*description: .*/ 2510 #define RTC_CNTL_TOUCH_PAD3_HOLD (BIT(3)) 2511 #define RTC_CNTL_TOUCH_PAD3_HOLD_M (BIT(3)) 2512 #define RTC_CNTL_TOUCH_PAD3_HOLD_V 0x1 2513 #define RTC_CNTL_TOUCH_PAD3_HOLD_S 3 2514 /* RTC_CNTL_TOUCH_PAD2_HOLD : R/W ;bitpos:[2] ;default: 1'b0 ; */ 2515 /*description: .*/ 2516 #define RTC_CNTL_TOUCH_PAD2_HOLD (BIT(2)) 2517 #define RTC_CNTL_TOUCH_PAD2_HOLD_M (BIT(2)) 2518 #define RTC_CNTL_TOUCH_PAD2_HOLD_V 0x1 2519 #define RTC_CNTL_TOUCH_PAD2_HOLD_S 2 2520 /* RTC_CNTL_TOUCH_PAD1_HOLD : R/W ;bitpos:[1] ;default: 1'b0 ; */ 2521 /*description: .*/ 2522 #define RTC_CNTL_TOUCH_PAD1_HOLD (BIT(1)) 2523 #define RTC_CNTL_TOUCH_PAD1_HOLD_M (BIT(1)) 2524 #define RTC_CNTL_TOUCH_PAD1_HOLD_V 0x1 2525 #define RTC_CNTL_TOUCH_PAD1_HOLD_S 1 2526 /* RTC_CNTL_TOUCH_PAD0_HOLD : R/W ;bitpos:[0] ;default: 1'b0 ; */ 2527 /*description: .*/ 2528 #define RTC_CNTL_TOUCH_PAD0_HOLD (BIT(0)) 2529 #define RTC_CNTL_TOUCH_PAD0_HOLD_M (BIT(0)) 2530 #define RTC_CNTL_TOUCH_PAD0_HOLD_V 0x1 2531 #define RTC_CNTL_TOUCH_PAD0_HOLD_S 0 2532 2533 #define RTC_CNTL_DIG_PAD_HOLD_REG (DR_REG_RTCCNTL_BASE + 0xDC) 2534 /* RTC_CNTL_DIG_PAD_HOLD : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ 2535 /*description: .*/ 2536 #define RTC_CNTL_DIG_PAD_HOLD 0xFFFFFFFF 2537 #define RTC_CNTL_DIG_PAD_HOLD_M ((RTC_CNTL_DIG_PAD_HOLD_V)<<(RTC_CNTL_DIG_PAD_HOLD_S)) 2538 #define RTC_CNTL_DIG_PAD_HOLD_V 0xFFFFFFFF 2539 #define RTC_CNTL_DIG_PAD_HOLD_S 0 2540 2541 #define RTC_CNTL_EXT_WAKEUP1_REG (DR_REG_RTCCNTL_BASE + 0xE0) 2542 /* RTC_CNTL_EXT_WAKEUP1_STATUS_CLR : WO ;bitpos:[22] ;default: 1'd0 ; */ 2543 /*description: clear ext wakeup1 status.*/ 2544 #define RTC_CNTL_EXT_WAKEUP1_STATUS_CLR (BIT(22)) 2545 #define RTC_CNTL_EXT_WAKEUP1_STATUS_CLR_M (BIT(22)) 2546 #define RTC_CNTL_EXT_WAKEUP1_STATUS_CLR_V 0x1 2547 #define RTC_CNTL_EXT_WAKEUP1_STATUS_CLR_S 22 2548 /* RTC_CNTL_EXT_WAKEUP1_SEL : R/W ;bitpos:[21:0] ;default: 22'd0 ; */ 2549 /*description: Bitmap to select RTC pads for ext wakeup1.*/ 2550 #define RTC_CNTL_EXT_WAKEUP1_SEL 0x003FFFFF 2551 #define RTC_CNTL_EXT_WAKEUP1_SEL_M ((RTC_CNTL_EXT_WAKEUP1_SEL_V)<<(RTC_CNTL_EXT_WAKEUP1_SEL_S)) 2552 #define RTC_CNTL_EXT_WAKEUP1_SEL_V 0x3FFFFF 2553 #define RTC_CNTL_EXT_WAKEUP1_SEL_S 0 2554 2555 #define RTC_CNTL_EXT_WAKEUP1_STATUS_REG (DR_REG_RTCCNTL_BASE + 0xE4) 2556 /* RTC_CNTL_EXT_WAKEUP1_STATUS : RO ;bitpos:[21:0] ;default: 22'd0 ; */ 2557 /*description: ext wakeup1 status.*/ 2558 #define RTC_CNTL_EXT_WAKEUP1_STATUS 0x003FFFFF 2559 #define RTC_CNTL_EXT_WAKEUP1_STATUS_M ((RTC_CNTL_EXT_WAKEUP1_STATUS_V)<<(RTC_CNTL_EXT_WAKEUP1_STATUS_S)) 2560 #define RTC_CNTL_EXT_WAKEUP1_STATUS_V 0x3FFFFF 2561 #define RTC_CNTL_EXT_WAKEUP1_STATUS_S 0 2562 2563 #define RTC_CNTL_BROWN_OUT_REG (DR_REG_RTCCNTL_BASE + 0xE8) 2564 /* RTC_CNTL_BROWN_OUT_DET : RO ;bitpos:[31] ;default: 1'b0 ; */ 2565 /*description: .*/ 2566 #define RTC_CNTL_BROWN_OUT_DET (BIT(31)) 2567 #define RTC_CNTL_BROWN_OUT_DET_M (BIT(31)) 2568 #define RTC_CNTL_BROWN_OUT_DET_V 0x1 2569 #define RTC_CNTL_BROWN_OUT_DET_S 31 2570 /* RTC_CNTL_BROWN_OUT_ENA : R/W ;bitpos:[30] ;default: 1'b1 ; */ 2571 /*description: enable brown out.*/ 2572 #define RTC_CNTL_BROWN_OUT_ENA (BIT(30)) 2573 #define RTC_CNTL_BROWN_OUT_ENA_M (BIT(30)) 2574 #define RTC_CNTL_BROWN_OUT_ENA_V 0x1 2575 #define RTC_CNTL_BROWN_OUT_ENA_S 30 2576 /* RTC_CNTL_BROWN_OUT_CNT_CLR : WO ;bitpos:[29] ;default: 1'b0 ; */ 2577 /*description: clear brown out counter.*/ 2578 #define RTC_CNTL_BROWN_OUT_CNT_CLR (BIT(29)) 2579 #define RTC_CNTL_BROWN_OUT_CNT_CLR_M (BIT(29)) 2580 #define RTC_CNTL_BROWN_OUT_CNT_CLR_V 0x1 2581 #define RTC_CNTL_BROWN_OUT_CNT_CLR_S 29 2582 /* RTC_CNTL_BROWN_OUT_ANA_RST_EN : R/W ;bitpos:[28] ;default: 1'b0 ; */ 2583 /*description: .*/ 2584 #define RTC_CNTL_BROWN_OUT_ANA_RST_EN (BIT(28)) 2585 #define RTC_CNTL_BROWN_OUT_ANA_RST_EN_M (BIT(28)) 2586 #define RTC_CNTL_BROWN_OUT_ANA_RST_EN_V 0x1 2587 #define RTC_CNTL_BROWN_OUT_ANA_RST_EN_S 28 2588 /* RTC_CNTL_BROWN_OUT_RST_SEL : R/W ;bitpos:[27] ;default: 1'b0 ; */ 2589 /*description: 1: 4-pos reset.*/ 2590 #define RTC_CNTL_BROWN_OUT_RST_SEL (BIT(27)) 2591 #define RTC_CNTL_BROWN_OUT_RST_SEL_M (BIT(27)) 2592 #define RTC_CNTL_BROWN_OUT_RST_SEL_V 0x1 2593 #define RTC_CNTL_BROWN_OUT_RST_SEL_S 27 2594 /* RTC_CNTL_BROWN_OUT_RST_ENA : R/W ;bitpos:[26] ;default: 1'b0 ; */ 2595 /*description: enable brown out reset.*/ 2596 #define RTC_CNTL_BROWN_OUT_RST_ENA (BIT(26)) 2597 #define RTC_CNTL_BROWN_OUT_RST_ENA_M (BIT(26)) 2598 #define RTC_CNTL_BROWN_OUT_RST_ENA_V 0x1 2599 #define RTC_CNTL_BROWN_OUT_RST_ENA_S 26 2600 /* RTC_CNTL_BROWN_OUT_RST_WAIT : R/W ;bitpos:[25:16] ;default: 10'h3ff ; */ 2601 /*description: brown out reset wait cycles.*/ 2602 #define RTC_CNTL_BROWN_OUT_RST_WAIT 0x000003FF 2603 #define RTC_CNTL_BROWN_OUT_RST_WAIT_M ((RTC_CNTL_BROWN_OUT_RST_WAIT_V)<<(RTC_CNTL_BROWN_OUT_RST_WAIT_S)) 2604 #define RTC_CNTL_BROWN_OUT_RST_WAIT_V 0x3FF 2605 #define RTC_CNTL_BROWN_OUT_RST_WAIT_S 16 2606 /* RTC_CNTL_BROWN_OUT_PD_RF_ENA : R/W ;bitpos:[15] ;default: 1'b0 ; */ 2607 /*description: enable power down RF when brown out happens.*/ 2608 #define RTC_CNTL_BROWN_OUT_PD_RF_ENA (BIT(15)) 2609 #define RTC_CNTL_BROWN_OUT_PD_RF_ENA_M (BIT(15)) 2610 #define RTC_CNTL_BROWN_OUT_PD_RF_ENA_V 0x1 2611 #define RTC_CNTL_BROWN_OUT_PD_RF_ENA_S 15 2612 /* RTC_CNTL_BROWN_OUT_CLOSE_FLASH_ENA : R/W ;bitpos:[14] ;default: 1'b0 ; */ 2613 /*description: enable close flash when brown out happens.*/ 2614 #define RTC_CNTL_BROWN_OUT_CLOSE_FLASH_ENA (BIT(14)) 2615 #define RTC_CNTL_BROWN_OUT_CLOSE_FLASH_ENA_M (BIT(14)) 2616 #define RTC_CNTL_BROWN_OUT_CLOSE_FLASH_ENA_V 0x1 2617 #define RTC_CNTL_BROWN_OUT_CLOSE_FLASH_ENA_S 14 2618 /* RTC_CNTL_BROWN_OUT_INT_WAIT : R/W ;bitpos:[13:4] ;default: 10'h1 ; */ 2619 /*description: brown out interrupt wait cycles.*/ 2620 #define RTC_CNTL_BROWN_OUT_INT_WAIT 0x000003FF 2621 #define RTC_CNTL_BROWN_OUT_INT_WAIT_M ((RTC_CNTL_BROWN_OUT_INT_WAIT_V)<<(RTC_CNTL_BROWN_OUT_INT_WAIT_S)) 2622 #define RTC_CNTL_BROWN_OUT_INT_WAIT_V 0x3FF 2623 #define RTC_CNTL_BROWN_OUT_INT_WAIT_S 4 2624 2625 #define RTC_CNTL_TIME_LOW1_REG (DR_REG_RTCCNTL_BASE + 0xEC) 2626 /* RTC_CNTL_TIMER_VALUE1_LOW : RO ;bitpos:[31:0] ;default: 32'h0 ; */ 2627 /*description: RTC timer low 32 bits.*/ 2628 #define RTC_CNTL_TIMER_VALUE1_LOW 0xFFFFFFFF 2629 #define RTC_CNTL_TIMER_VALUE1_LOW_M ((RTC_CNTL_TIMER_VALUE1_LOW_V)<<(RTC_CNTL_TIMER_VALUE1_LOW_S)) 2630 #define RTC_CNTL_TIMER_VALUE1_LOW_V 0xFFFFFFFF 2631 #define RTC_CNTL_TIMER_VALUE1_LOW_S 0 2632 2633 #define RTC_CNTL_TIME_HIGH1_REG (DR_REG_RTCCNTL_BASE + 0xF0) 2634 /* RTC_CNTL_TIMER_VALUE1_HIGH : RO ;bitpos:[15:0] ;default: 16'h0 ; */ 2635 /*description: RTC timer high 16 bits.*/ 2636 #define RTC_CNTL_TIMER_VALUE1_HIGH 0x0000FFFF 2637 #define RTC_CNTL_TIMER_VALUE1_HIGH_M ((RTC_CNTL_TIMER_VALUE1_HIGH_V)<<(RTC_CNTL_TIMER_VALUE1_HIGH_S)) 2638 #define RTC_CNTL_TIMER_VALUE1_HIGH_V 0xFFFF 2639 #define RTC_CNTL_TIMER_VALUE1_HIGH_S 0 2640 2641 #define RTC_CNTL_XTAL32K_CLK_FACTOR_REG (DR_REG_RTCCNTL_BASE + 0xF4) 2642 /* RTC_CNTL_XTAL32K_CLK_FACTOR : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ 2643 /*description: xtal 32k watch dog backup clock factor.*/ 2644 #define RTC_CNTL_XTAL32K_CLK_FACTOR 0xFFFFFFFF 2645 #define RTC_CNTL_XTAL32K_CLK_FACTOR_M ((RTC_CNTL_XTAL32K_CLK_FACTOR_V)<<(RTC_CNTL_XTAL32K_CLK_FACTOR_S)) 2646 #define RTC_CNTL_XTAL32K_CLK_FACTOR_V 0xFFFFFFFF 2647 #define RTC_CNTL_XTAL32K_CLK_FACTOR_S 0 2648 2649 #define RTC_CNTL_XTAL32K_CONF_REG (DR_REG_RTCCNTL_BASE + 0xF8) 2650 /* RTC_CNTL_XTAL32K_STABLE_THRES : R/W ;bitpos:[31:28] ;default: 4'h0 ; */ 2651 /*description: if restarted xtal32k period is smaller than this.*/ 2652 #define RTC_CNTL_XTAL32K_STABLE_THRES 0x0000000F 2653 #define RTC_CNTL_XTAL32K_STABLE_THRES_M ((RTC_CNTL_XTAL32K_STABLE_THRES_V)<<(RTC_CNTL_XTAL32K_STABLE_THRES_S)) 2654 #define RTC_CNTL_XTAL32K_STABLE_THRES_V 0xF 2655 #define RTC_CNTL_XTAL32K_STABLE_THRES_S 28 2656 /* RTC_CNTL_XTAL32K_WDT_TIMEOUT : R/W ;bitpos:[27:20] ;default: 8'hff ; */ 2657 /*description: If no clock detected for this amount of time.*/ 2658 #define RTC_CNTL_XTAL32K_WDT_TIMEOUT 0x000000FF 2659 #define RTC_CNTL_XTAL32K_WDT_TIMEOUT_M ((RTC_CNTL_XTAL32K_WDT_TIMEOUT_V)<<(RTC_CNTL_XTAL32K_WDT_TIMEOUT_S)) 2660 #define RTC_CNTL_XTAL32K_WDT_TIMEOUT_V 0xFF 2661 #define RTC_CNTL_XTAL32K_WDT_TIMEOUT_S 20 2662 /* RTC_CNTL_XTAL32K_RESTART_WAIT : R/W ;bitpos:[19:4] ;default: 16'h0 ; */ 2663 /*description: cycles to wait to repower on xtal 32k.*/ 2664 #define RTC_CNTL_XTAL32K_RESTART_WAIT 0x0000FFFF 2665 #define RTC_CNTL_XTAL32K_RESTART_WAIT_M ((RTC_CNTL_XTAL32K_RESTART_WAIT_V)<<(RTC_CNTL_XTAL32K_RESTART_WAIT_S)) 2666 #define RTC_CNTL_XTAL32K_RESTART_WAIT_V 0xFFFF 2667 #define RTC_CNTL_XTAL32K_RESTART_WAIT_S 4 2668 /* RTC_CNTL_XTAL32K_RETURN_WAIT : R/W ;bitpos:[3:0] ;default: 4'h0 ; */ 2669 /*description: cycles to wait to return noral xtal 32k.*/ 2670 #define RTC_CNTL_XTAL32K_RETURN_WAIT 0x0000000F 2671 #define RTC_CNTL_XTAL32K_RETURN_WAIT_M ((RTC_CNTL_XTAL32K_RETURN_WAIT_V)<<(RTC_CNTL_XTAL32K_RETURN_WAIT_S)) 2672 #define RTC_CNTL_XTAL32K_RETURN_WAIT_V 0xF 2673 #define RTC_CNTL_XTAL32K_RETURN_WAIT_S 0 2674 2675 #define RTC_CNTL_ULP_CP_TIMER_REG (DR_REG_RTCCNTL_BASE + 0xFC) 2676 /* RTC_CNTL_ULP_CP_SLP_TIMER_EN : R/W ;bitpos:[31] ;default: 1'd0 ; */ 2677 /*description: ULP-coprocessor timer enable bit.*/ 2678 #define RTC_CNTL_ULP_CP_SLP_TIMER_EN (BIT(31)) 2679 #define RTC_CNTL_ULP_CP_SLP_TIMER_EN_M (BIT(31)) 2680 #define RTC_CNTL_ULP_CP_SLP_TIMER_EN_V 0x1 2681 #define RTC_CNTL_ULP_CP_SLP_TIMER_EN_S 31 2682 /* RTC_CNTL_ULP_CP_GPIO_WAKEUP_CLR : WO ;bitpos:[30] ;default: 1'd0 ; */ 2683 /*description: ULP-coprocessor wakeup by GPIO state clear.*/ 2684 #define RTC_CNTL_ULP_CP_GPIO_WAKEUP_CLR (BIT(30)) 2685 #define RTC_CNTL_ULP_CP_GPIO_WAKEUP_CLR_M (BIT(30)) 2686 #define RTC_CNTL_ULP_CP_GPIO_WAKEUP_CLR_V 0x1 2687 #define RTC_CNTL_ULP_CP_GPIO_WAKEUP_CLR_S 30 2688 /* RTC_CNTL_ULP_CP_GPIO_WAKEUP_ENA : R/W ;bitpos:[29] ;default: 1'd0 ; */ 2689 /*description: ULP-coprocessor wakeup by GPIO enable.*/ 2690 #define RTC_CNTL_ULP_CP_GPIO_WAKEUP_ENA (BIT(29)) 2691 #define RTC_CNTL_ULP_CP_GPIO_WAKEUP_ENA_M (BIT(29)) 2692 #define RTC_CNTL_ULP_CP_GPIO_WAKEUP_ENA_V 0x1 2693 #define RTC_CNTL_ULP_CP_GPIO_WAKEUP_ENA_S 29 2694 /* RTC_CNTL_ULP_CP_PC_INIT : R/W ;bitpos:[10:0] ;default: 11'b0 ; */ 2695 /*description: ULP-coprocessor PC initial address.*/ 2696 #define RTC_CNTL_ULP_CP_PC_INIT 0x000007FF 2697 #define RTC_CNTL_ULP_CP_PC_INIT_M ((RTC_CNTL_ULP_CP_PC_INIT_V)<<(RTC_CNTL_ULP_CP_PC_INIT_S)) 2698 #define RTC_CNTL_ULP_CP_PC_INIT_V 0x7FF 2699 #define RTC_CNTL_ULP_CP_PC_INIT_S 0 2700 2701 #define RTC_CNTL_ULP_CP_CTRL_REG (DR_REG_RTCCNTL_BASE + 0x100) 2702 /* RTC_CNTL_ULP_CP_START_TOP : R/W ;bitpos:[31] ;default: 1'd0 ; */ 2703 /*description: Write 1 to start ULP-coprocessor.*/ 2704 #define RTC_CNTL_ULP_CP_START_TOP (BIT(31)) 2705 #define RTC_CNTL_ULP_CP_START_TOP_M (BIT(31)) 2706 #define RTC_CNTL_ULP_CP_START_TOP_V 0x1 2707 #define RTC_CNTL_ULP_CP_START_TOP_S 31 2708 /* RTC_CNTL_ULP_CP_FORCE_START_TOP : R/W ;bitpos:[30] ;default: 1'd0 ; */ 2709 /*description: 1: ULP-coprocessor is started by SW.*/ 2710 #define RTC_CNTL_ULP_CP_FORCE_START_TOP (BIT(30)) 2711 #define RTC_CNTL_ULP_CP_FORCE_START_TOP_M (BIT(30)) 2712 #define RTC_CNTL_ULP_CP_FORCE_START_TOP_V 0x1 2713 #define RTC_CNTL_ULP_CP_FORCE_START_TOP_S 30 2714 /* RTC_CNTL_ULP_CP_RESET : R/W ;bitpos:[29] ;default: 1'd0 ; */ 2715 /*description: ulp coprocessor clk software reset.*/ 2716 #define RTC_CNTL_ULP_CP_RESET (BIT(29)) 2717 #define RTC_CNTL_ULP_CP_RESET_M (BIT(29)) 2718 #define RTC_CNTL_ULP_CP_RESET_V 0x1 2719 #define RTC_CNTL_ULP_CP_RESET_S 29 2720 /* RTC_CNTL_ULP_CP_CLK_FO : R/W ;bitpos:[28] ;default: 1'd0 ; */ 2721 /*description: ulp coprocessor clk force on.*/ 2722 #define RTC_CNTL_ULP_CP_CLK_FO (BIT(28)) 2723 #define RTC_CNTL_ULP_CP_CLK_FO_M (BIT(28)) 2724 #define RTC_CNTL_ULP_CP_CLK_FO_V 0x1 2725 #define RTC_CNTL_ULP_CP_CLK_FO_S 28 2726 /* RTC_CNTL_ULP_CP_MEM_OFFST_CLR : WO ;bitpos:[22] ;default: 1'd0 ; */ 2727 /*description: .*/ 2728 #define RTC_CNTL_ULP_CP_MEM_OFFST_CLR (BIT(22)) 2729 #define RTC_CNTL_ULP_CP_MEM_OFFST_CLR_M (BIT(22)) 2730 #define RTC_CNTL_ULP_CP_MEM_OFFST_CLR_V 0x1 2731 #define RTC_CNTL_ULP_CP_MEM_OFFST_CLR_S 22 2732 /* RTC_CNTL_ULP_CP_MEM_ADDR_SIZE : R/W ;bitpos:[21:11] ;default: 11'd512 ; */ 2733 /*description: .*/ 2734 #define RTC_CNTL_ULP_CP_MEM_ADDR_SIZE 0x000007FF 2735 #define RTC_CNTL_ULP_CP_MEM_ADDR_SIZE_M ((RTC_CNTL_ULP_CP_MEM_ADDR_SIZE_V)<<(RTC_CNTL_ULP_CP_MEM_ADDR_SIZE_S)) 2736 #define RTC_CNTL_ULP_CP_MEM_ADDR_SIZE_V 0x7FF 2737 #define RTC_CNTL_ULP_CP_MEM_ADDR_SIZE_S 11 2738 /* RTC_CNTL_ULP_CP_MEM_ADDR_INIT : R/W ;bitpos:[10:0] ;default: 11'd512 ; */ 2739 /*description: .*/ 2740 #define RTC_CNTL_ULP_CP_MEM_ADDR_INIT 0x000007FF 2741 #define RTC_CNTL_ULP_CP_MEM_ADDR_INIT_M ((RTC_CNTL_ULP_CP_MEM_ADDR_INIT_V)<<(RTC_CNTL_ULP_CP_MEM_ADDR_INIT_S)) 2742 #define RTC_CNTL_ULP_CP_MEM_ADDR_INIT_V 0x7FF 2743 #define RTC_CNTL_ULP_CP_MEM_ADDR_INIT_S 0 2744 2745 #define RTC_CNTL_COCPU_CTRL_REG (DR_REG_RTCCNTL_BASE + 0x104) 2746 /* RTC_CNTL_COCPU_CLKGATE_EN : R/W ;bitpos:[27] ;default: 1'b0 ; */ 2747 /*description: .*/ 2748 #define RTC_CNTL_COCPU_CLKGATE_EN (BIT(27)) 2749 #define RTC_CNTL_COCPU_CLKGATE_EN_M (BIT(27)) 2750 #define RTC_CNTL_COCPU_CLKGATE_EN_V 0x1 2751 #define RTC_CNTL_COCPU_CLKGATE_EN_S 27 2752 /* RTC_CNTL_COCPU_SW_INT_TRIGGER : WO ;bitpos:[26] ;default: 1'b0 ; */ 2753 /*description: trigger cocpu register interrupt.*/ 2754 #define RTC_CNTL_COCPU_SW_INT_TRIGGER (BIT(26)) 2755 #define RTC_CNTL_COCPU_SW_INT_TRIGGER_M (BIT(26)) 2756 #define RTC_CNTL_COCPU_SW_INT_TRIGGER_V 0x1 2757 #define RTC_CNTL_COCPU_SW_INT_TRIGGER_S 26 2758 /* RTC_CNTL_COCPU_DONE : R/W ;bitpos:[25] ;default: 1'b0 ; */ 2759 /*description: done signal used by riscv to control timer. .*/ 2760 #define RTC_CNTL_COCPU_DONE (BIT(25)) 2761 #define RTC_CNTL_COCPU_DONE_M (BIT(25)) 2762 #define RTC_CNTL_COCPU_DONE_V 0x1 2763 #define RTC_CNTL_COCPU_DONE_S 25 2764 /* RTC_CNTL_COCPU_DONE_FORCE : R/W ;bitpos:[24] ;default: 1'b0 ; */ 2765 /*description: 1: select riscv done 0: select ulp done.*/ 2766 #define RTC_CNTL_COCPU_DONE_FORCE (BIT(24)) 2767 #define RTC_CNTL_COCPU_DONE_FORCE_M (BIT(24)) 2768 #define RTC_CNTL_COCPU_DONE_FORCE_V 0x1 2769 #define RTC_CNTL_COCPU_DONE_FORCE_S 24 2770 /* RTC_CNTL_COCPU_SEL : R/W ;bitpos:[23] ;default: 1'b1 ; */ 2771 /*description: 1: old ULP 0: new riscV.*/ 2772 #define RTC_CNTL_COCPU_SEL (BIT(23)) 2773 #define RTC_CNTL_COCPU_SEL_M (BIT(23)) 2774 #define RTC_CNTL_COCPU_SEL_V 0x1 2775 #define RTC_CNTL_COCPU_SEL_S 23 2776 /* RTC_CNTL_COCPU_SHUT_RESET_EN : R/W ;bitpos:[22] ;default: 1'b0 ; */ 2777 /*description: to reset cocpu.*/ 2778 #define RTC_CNTL_COCPU_SHUT_RESET_EN (BIT(22)) 2779 #define RTC_CNTL_COCPU_SHUT_RESET_EN_M (BIT(22)) 2780 #define RTC_CNTL_COCPU_SHUT_RESET_EN_V 0x1 2781 #define RTC_CNTL_COCPU_SHUT_RESET_EN_S 22 2782 /* RTC_CNTL_COCPU_SHUT_2_CLK_DIS : R/W ;bitpos:[21:14] ;default: 8'd40 ; */ 2783 /*description: time from shut cocpu to disable clk.*/ 2784 #define RTC_CNTL_COCPU_SHUT_2_CLK_DIS 0x000000FF 2785 #define RTC_CNTL_COCPU_SHUT_2_CLK_DIS_M ((RTC_CNTL_COCPU_SHUT_2_CLK_DIS_V)<<(RTC_CNTL_COCPU_SHUT_2_CLK_DIS_S)) 2786 #define RTC_CNTL_COCPU_SHUT_2_CLK_DIS_V 0xFF 2787 #define RTC_CNTL_COCPU_SHUT_2_CLK_DIS_S 14 2788 /* RTC_CNTL_COCPU_SHUT : R/W ;bitpos:[13] ;default: 1'b0 ; */ 2789 /*description: to shut cocpu.*/ 2790 #define RTC_CNTL_COCPU_SHUT (BIT(13)) 2791 #define RTC_CNTL_COCPU_SHUT_M (BIT(13)) 2792 #define RTC_CNTL_COCPU_SHUT_V 0x1 2793 #define RTC_CNTL_COCPU_SHUT_S 13 2794 /* RTC_CNTL_COCPU_START_2_INTR_EN : R/W ;bitpos:[12:7] ;default: 6'd16 ; */ 2795 /*description: time from start cocpu to give start interrupt.*/ 2796 #define RTC_CNTL_COCPU_START_2_INTR_EN 0x0000003F 2797 #define RTC_CNTL_COCPU_START_2_INTR_EN_M ((RTC_CNTL_COCPU_START_2_INTR_EN_V)<<(RTC_CNTL_COCPU_START_2_INTR_EN_S)) 2798 #define RTC_CNTL_COCPU_START_2_INTR_EN_V 0x3F 2799 #define RTC_CNTL_COCPU_START_2_INTR_EN_S 7 2800 /* RTC_CNTL_COCPU_START_2_RESET_DIS : R/W ;bitpos:[6:1] ;default: 6'd8 ; */ 2801 /*description: time from start cocpu to pull down reset.*/ 2802 #define RTC_CNTL_COCPU_START_2_RESET_DIS 0x0000003F 2803 #define RTC_CNTL_COCPU_START_2_RESET_DIS_M ((RTC_CNTL_COCPU_START_2_RESET_DIS_V)<<(RTC_CNTL_COCPU_START_2_RESET_DIS_S)) 2804 #define RTC_CNTL_COCPU_START_2_RESET_DIS_V 0x3F 2805 #define RTC_CNTL_COCPU_START_2_RESET_DIS_S 1 2806 /* RTC_CNTL_COCPU_CLK_FO : R/W ;bitpos:[0] ;default: 1'b0 ; */ 2807 /*description: cocpu clk force on.*/ 2808 #define RTC_CNTL_COCPU_CLK_FO (BIT(0)) 2809 #define RTC_CNTL_COCPU_CLK_FO_M (BIT(0)) 2810 #define RTC_CNTL_COCPU_CLK_FO_V 0x1 2811 #define RTC_CNTL_COCPU_CLK_FO_S 0 2812 2813 #define RTC_CNTL_TOUCH_CTRL1_REG (DR_REG_RTCCNTL_BASE + 0x108) 2814 /* RTC_CNTL_TOUCH_MEAS_NUM : R/W ;bitpos:[31:16] ;default: 16'h1000 ; */ 2815 /*description: the meas length (in 8MHz).*/ 2816 #define RTC_CNTL_TOUCH_MEAS_NUM 0x0000FFFF 2817 #define RTC_CNTL_TOUCH_MEAS_NUM_M ((RTC_CNTL_TOUCH_MEAS_NUM_V)<<(RTC_CNTL_TOUCH_MEAS_NUM_S)) 2818 #define RTC_CNTL_TOUCH_MEAS_NUM_V 0xFFFF 2819 #define RTC_CNTL_TOUCH_MEAS_NUM_S 16 2820 /* RTC_CNTL_TOUCH_SLEEP_CYCLES : R/W ;bitpos:[15:0] ;default: 16'h100 ; */ 2821 /*description: sleep cycles for timer.*/ 2822 #define RTC_CNTL_TOUCH_SLEEP_CYCLES 0x0000FFFF 2823 #define RTC_CNTL_TOUCH_SLEEP_CYCLES_M ((RTC_CNTL_TOUCH_SLEEP_CYCLES_V)<<(RTC_CNTL_TOUCH_SLEEP_CYCLES_S)) 2824 #define RTC_CNTL_TOUCH_SLEEP_CYCLES_V 0xFFFF 2825 #define RTC_CNTL_TOUCH_SLEEP_CYCLES_S 0 2826 2827 #define RTC_CNTL_TOUCH_CTRL2_REG (DR_REG_RTCCNTL_BASE + 0x10C) 2828 /* RTC_CNTL_TOUCH_CLKGATE_EN : R/W ;bitpos:[31] ;default: 1'b0 ; */ 2829 /*description: touch clock enable.*/ 2830 #define RTC_CNTL_TOUCH_CLKGATE_EN (BIT(31)) 2831 #define RTC_CNTL_TOUCH_CLKGATE_EN_M (BIT(31)) 2832 #define RTC_CNTL_TOUCH_CLKGATE_EN_V 0x1 2833 #define RTC_CNTL_TOUCH_CLKGATE_EN_S 31 2834 /* RTC_CNTL_TOUCH_CLK_FO : R/W ;bitpos:[30] ;default: 1'b0 ; */ 2835 /*description: touch clock force on.*/ 2836 #define RTC_CNTL_TOUCH_CLK_FO (BIT(30)) 2837 #define RTC_CNTL_TOUCH_CLK_FO_M (BIT(30)) 2838 #define RTC_CNTL_TOUCH_CLK_FO_V 0x1 2839 #define RTC_CNTL_TOUCH_CLK_FO_S 30 2840 /* RTC_CNTL_TOUCH_RESET : R/W ;bitpos:[29] ;default: 1'b0 ; */ 2841 /*description: reset upgrade touch.*/ 2842 #define RTC_CNTL_TOUCH_RESET (BIT(29)) 2843 #define RTC_CNTL_TOUCH_RESET_M (BIT(29)) 2844 #define RTC_CNTL_TOUCH_RESET_V 0x1 2845 #define RTC_CNTL_TOUCH_RESET_S 29 2846 /* RTC_CNTL_TOUCH_TIMER_FORCE_DONE : R/W ;bitpos:[28:27] ;default: 2'b0 ; */ 2847 /*description: force touch timer done.*/ 2848 #define RTC_CNTL_TOUCH_TIMER_FORCE_DONE 0x00000003 2849 #define RTC_CNTL_TOUCH_TIMER_FORCE_DONE_M ((RTC_CNTL_TOUCH_TIMER_FORCE_DONE_V)<<(RTC_CNTL_TOUCH_TIMER_FORCE_DONE_S)) 2850 #define RTC_CNTL_TOUCH_TIMER_FORCE_DONE_V 0x3 2851 #define RTC_CNTL_TOUCH_TIMER_FORCE_DONE_S 27 2852 /* RTC_CNTL_TOUCH_SLP_CYC_DIV : R/W ;bitpos:[26:25] ;default: 2'd0 ; */ 2853 /*description: when a touch pad is active.*/ 2854 #define RTC_CNTL_TOUCH_SLP_CYC_DIV 0x00000003 2855 #define RTC_CNTL_TOUCH_SLP_CYC_DIV_M ((RTC_CNTL_TOUCH_SLP_CYC_DIV_V)<<(RTC_CNTL_TOUCH_SLP_CYC_DIV_S)) 2856 #define RTC_CNTL_TOUCH_SLP_CYC_DIV_V 0x3 2857 #define RTC_CNTL_TOUCH_SLP_CYC_DIV_S 25 2858 /* RTC_CNTL_TOUCH_XPD_WAIT : R/W ;bitpos:[24:17] ;default: 8'h4 ; */ 2859 /*description: the waiting cycles (in 8MHz) between TOUCH_START and TOUCH_XPD.*/ 2860 #define RTC_CNTL_TOUCH_XPD_WAIT 0x000000FF 2861 #define RTC_CNTL_TOUCH_XPD_WAIT_M ((RTC_CNTL_TOUCH_XPD_WAIT_V)<<(RTC_CNTL_TOUCH_XPD_WAIT_S)) 2862 #define RTC_CNTL_TOUCH_XPD_WAIT_V 0xFF 2863 #define RTC_CNTL_TOUCH_XPD_WAIT_S 17 2864 /* RTC_CNTL_TOUCH_START_FORCE : R/W ;bitpos:[16] ;default: 1'b0 ; */ 2865 /*description: 1: to start touch fsm by SW.*/ 2866 #define RTC_CNTL_TOUCH_START_FORCE (BIT(16)) 2867 #define RTC_CNTL_TOUCH_START_FORCE_M (BIT(16)) 2868 #define RTC_CNTL_TOUCH_START_FORCE_V 0x1 2869 #define RTC_CNTL_TOUCH_START_FORCE_S 16 2870 /* RTC_CNTL_TOUCH_START_EN : R/W ;bitpos:[15] ;default: 1'b0 ; */ 2871 /*description: 1: start touch fsm.*/ 2872 #define RTC_CNTL_TOUCH_START_EN (BIT(15)) 2873 #define RTC_CNTL_TOUCH_START_EN_M (BIT(15)) 2874 #define RTC_CNTL_TOUCH_START_EN_V 0x1 2875 #define RTC_CNTL_TOUCH_START_EN_S 15 2876 /* RTC_CNTL_TOUCH_START_FSM_EN : R/W ;bitpos:[14] ;default: 1'b1 ; */ 2877 /*description: 1: TOUCH_START & TOUCH_XPD is controlled by touch fsm.*/ 2878 #define RTC_CNTL_TOUCH_START_FSM_EN (BIT(14)) 2879 #define RTC_CNTL_TOUCH_START_FSM_EN_M (BIT(14)) 2880 #define RTC_CNTL_TOUCH_START_FSM_EN_V 0x1 2881 #define RTC_CNTL_TOUCH_START_FSM_EN_S 14 2882 /* RTC_CNTL_TOUCH_SLP_TIMER_EN : R/W ;bitpos:[13] ;default: 1'd0 ; */ 2883 /*description: touch timer enable bit.*/ 2884 #define RTC_CNTL_TOUCH_SLP_TIMER_EN (BIT(13)) 2885 #define RTC_CNTL_TOUCH_SLP_TIMER_EN_M (BIT(13)) 2886 #define RTC_CNTL_TOUCH_SLP_TIMER_EN_V 0x1 2887 #define RTC_CNTL_TOUCH_SLP_TIMER_EN_S 13 2888 /* RTC_CNTL_TOUCH_DBIAS : R/W ;bitpos:[12] ;default: 1'b0 ; */ 2889 /*description: 1:use self bias 0:use bandgap bias.*/ 2890 #define RTC_CNTL_TOUCH_DBIAS (BIT(12)) 2891 #define RTC_CNTL_TOUCH_DBIAS_M (BIT(12)) 2892 #define RTC_CNTL_TOUCH_DBIAS_V 0x1 2893 #define RTC_CNTL_TOUCH_DBIAS_S 12 2894 /* RTC_CNTL_TOUCH_REFC : R/W ;bitpos:[11:9] ;default: 3'h0 ; */ 2895 /*description: TOUCH pad0 reference cap.*/ 2896 #define RTC_CNTL_TOUCH_REFC 0x00000007 2897 #define RTC_CNTL_TOUCH_REFC_M ((RTC_CNTL_TOUCH_REFC_V)<<(RTC_CNTL_TOUCH_REFC_S)) 2898 #define RTC_CNTL_TOUCH_REFC_V 0x7 2899 #define RTC_CNTL_TOUCH_REFC_S 9 2900 /* RTC_CNTL_TOUCH_XPD_BIAS : R/W ;bitpos:[8] ;default: 1'd0 ; */ 2901 /*description: TOUCH_XPD_BIAS.*/ 2902 #define RTC_CNTL_TOUCH_XPD_BIAS (BIT(8)) 2903 #define RTC_CNTL_TOUCH_XPD_BIAS_M (BIT(8)) 2904 #define RTC_CNTL_TOUCH_XPD_BIAS_V 0x1 2905 #define RTC_CNTL_TOUCH_XPD_BIAS_S 8 2906 /* RTC_CNTL_TOUCH_DREFH : R/W ;bitpos:[7:6] ;default: 2'b11 ; */ 2907 /*description: TOUCH_DREFH.*/ 2908 #define RTC_CNTL_TOUCH_DREFH 0x00000003 2909 #define RTC_CNTL_TOUCH_DREFH_M ((RTC_CNTL_TOUCH_DREFH_V)<<(RTC_CNTL_TOUCH_DREFH_S)) 2910 #define RTC_CNTL_TOUCH_DREFH_V 0x3 2911 #define RTC_CNTL_TOUCH_DREFH_S 6 2912 /* RTC_CNTL_TOUCH_DREFL : R/W ;bitpos:[5:4] ;default: 2'b00 ; */ 2913 /*description: TOUCH_DREFL.*/ 2914 #define RTC_CNTL_TOUCH_DREFL 0x00000003 2915 #define RTC_CNTL_TOUCH_DREFL_M ((RTC_CNTL_TOUCH_DREFL_V)<<(RTC_CNTL_TOUCH_DREFL_S)) 2916 #define RTC_CNTL_TOUCH_DREFL_V 0x3 2917 #define RTC_CNTL_TOUCH_DREFL_S 4 2918 /* RTC_CNTL_TOUCH_DRANGE : R/W ;bitpos:[3:2] ;default: 2'b11 ; */ 2919 /*description: TOUCH_DRANGE.*/ 2920 #define RTC_CNTL_TOUCH_DRANGE 0x00000003 2921 #define RTC_CNTL_TOUCH_DRANGE_M ((RTC_CNTL_TOUCH_DRANGE_V)<<(RTC_CNTL_TOUCH_DRANGE_S)) 2922 #define RTC_CNTL_TOUCH_DRANGE_V 0x3 2923 #define RTC_CNTL_TOUCH_DRANGE_S 2 2924 2925 #define RTC_CNTL_TOUCH_SCAN_CTRL_REG (DR_REG_RTCCNTL_BASE + 0x110) 2926 /* RTC_CNTL_TOUCH_OUT_RING : R/W ;bitpos:[31:28] ;default: 4'hf ; */ 2927 /*description: select out ring pad.*/ 2928 #define RTC_CNTL_TOUCH_OUT_RING 0x0000000F 2929 #define RTC_CNTL_TOUCH_OUT_RING_M ((RTC_CNTL_TOUCH_OUT_RING_V)<<(RTC_CNTL_TOUCH_OUT_RING_S)) 2930 #define RTC_CNTL_TOUCH_OUT_RING_V 0xF 2931 #define RTC_CNTL_TOUCH_OUT_RING_S 28 2932 /* RTC_CNTL_TOUCH_BUFDRV : R/W ;bitpos:[27:25] ;default: 3'h0 ; */ 2933 /*description: touch7 buffer driver strength.*/ 2934 #define RTC_CNTL_TOUCH_BUFDRV 0x00000007 2935 #define RTC_CNTL_TOUCH_BUFDRV_M ((RTC_CNTL_TOUCH_BUFDRV_V)<<(RTC_CNTL_TOUCH_BUFDRV_S)) 2936 #define RTC_CNTL_TOUCH_BUFDRV_V 0x7 2937 #define RTC_CNTL_TOUCH_BUFDRV_S 25 2938 /* RTC_CNTL_TOUCH_SCAN_PAD_MAP : R/W ;bitpos:[24:10] ;default: 15'h0 ; */ 2939 /*description: touch scan mode pad enable map.*/ 2940 #define RTC_CNTL_TOUCH_SCAN_PAD_MAP 0x00007FFF 2941 #define RTC_CNTL_TOUCH_SCAN_PAD_MAP_M ((RTC_CNTL_TOUCH_SCAN_PAD_MAP_V)<<(RTC_CNTL_TOUCH_SCAN_PAD_MAP_S)) 2942 #define RTC_CNTL_TOUCH_SCAN_PAD_MAP_V 0x7FFF 2943 #define RTC_CNTL_TOUCH_SCAN_PAD_MAP_S 10 2944 /* RTC_CNTL_TOUCH_SHIELD_PAD_EN : R/W ;bitpos:[9] ;default: 1'b0 ; */ 2945 /*description: touch pad14 will be used as shield.*/ 2946 #define RTC_CNTL_TOUCH_SHIELD_PAD_EN (BIT(9)) 2947 #define RTC_CNTL_TOUCH_SHIELD_PAD_EN_M (BIT(9)) 2948 #define RTC_CNTL_TOUCH_SHIELD_PAD_EN_V 0x1 2949 #define RTC_CNTL_TOUCH_SHIELD_PAD_EN_S 9 2950 /* RTC_CNTL_TOUCH_INACTIVE_CONNECTION : R/W ;bitpos:[8] ;default: 1'b1 ; */ 2951 /*description: inactive touch pads connect to 1: gnd 0: HighZ.*/ 2952 #define RTC_CNTL_TOUCH_INACTIVE_CONNECTION (BIT(8)) 2953 #define RTC_CNTL_TOUCH_INACTIVE_CONNECTION_M (BIT(8)) 2954 #define RTC_CNTL_TOUCH_INACTIVE_CONNECTION_V 0x1 2955 #define RTC_CNTL_TOUCH_INACTIVE_CONNECTION_S 8 2956 /* RTC_CNTL_TOUCH_DENOISE_EN : R/W ;bitpos:[2] ;default: 1'b0 ; */ 2957 /*description: touch pad0 will be used to de-noise.*/ 2958 #define RTC_CNTL_TOUCH_DENOISE_EN (BIT(2)) 2959 #define RTC_CNTL_TOUCH_DENOISE_EN_M (BIT(2)) 2960 #define RTC_CNTL_TOUCH_DENOISE_EN_V 0x1 2961 #define RTC_CNTL_TOUCH_DENOISE_EN_S 2 2962 /* RTC_CNTL_TOUCH_DENOISE_RES : R/W ;bitpos:[1:0] ;default: 2'd2 ; */ 2963 /*description: De-noise resolution: 12/10/8/4 bit.*/ 2964 #define RTC_CNTL_TOUCH_DENOISE_RES 0x00000003 2965 #define RTC_CNTL_TOUCH_DENOISE_RES_M ((RTC_CNTL_TOUCH_DENOISE_RES_V)<<(RTC_CNTL_TOUCH_DENOISE_RES_S)) 2966 #define RTC_CNTL_TOUCH_DENOISE_RES_V 0x3 2967 #define RTC_CNTL_TOUCH_DENOISE_RES_S 0 2968 2969 #define RTC_CNTL_TOUCH_SLP_THRES_REG (DR_REG_RTCCNTL_BASE + 0x114) 2970 /* RTC_CNTL_TOUCH_SLP_PAD : R/W ;bitpos:[31:27] ;default: 4'hf ; */ 2971 /*description: .*/ 2972 #define RTC_CNTL_TOUCH_SLP_PAD 0x0000001F 2973 #define RTC_CNTL_TOUCH_SLP_PAD_M ((RTC_CNTL_TOUCH_SLP_PAD_V)<<(RTC_CNTL_TOUCH_SLP_PAD_S)) 2974 #define RTC_CNTL_TOUCH_SLP_PAD_V 0x1F 2975 #define RTC_CNTL_TOUCH_SLP_PAD_S 27 2976 /* RTC_CNTL_TOUCH_SLP_APPROACH_EN : R/W ;bitpos:[26] ;default: 1'b0 ; */ 2977 /*description: sleep pad approach function enable.*/ 2978 #define RTC_CNTL_TOUCH_SLP_APPROACH_EN (BIT(26)) 2979 #define RTC_CNTL_TOUCH_SLP_APPROACH_EN_M (BIT(26)) 2980 #define RTC_CNTL_TOUCH_SLP_APPROACH_EN_V 0x1 2981 #define RTC_CNTL_TOUCH_SLP_APPROACH_EN_S 26 2982 /* RTC_CNTL_TOUCH_SLP_TH : R/W ;bitpos:[21:0] ;default: 22'h0 ; */ 2983 /*description: the threshold for sleep touch pad.*/ 2984 #define RTC_CNTL_TOUCH_SLP_TH 0x003FFFFF 2985 #define RTC_CNTL_TOUCH_SLP_TH_M ((RTC_CNTL_TOUCH_SLP_TH_V)<<(RTC_CNTL_TOUCH_SLP_TH_S)) 2986 #define RTC_CNTL_TOUCH_SLP_TH_V 0x3FFFFF 2987 #define RTC_CNTL_TOUCH_SLP_TH_S 0 2988 2989 #define RTC_CNTL_TOUCH_APPROACH_REG (DR_REG_RTCCNTL_BASE + 0x118) 2990 /* RTC_CNTL_TOUCH_APPROACH_MEAS_TIME : R/W ;bitpos:[31:24] ;default: 8'd80 ; */ 2991 /*description: approach pads total meas times.*/ 2992 #define RTC_CNTL_TOUCH_APPROACH_MEAS_TIME 0x000000FF 2993 #define RTC_CNTL_TOUCH_APPROACH_MEAS_TIME_M ((RTC_CNTL_TOUCH_APPROACH_MEAS_TIME_V)<<(RTC_CNTL_TOUCH_APPROACH_MEAS_TIME_S)) 2994 #define RTC_CNTL_TOUCH_APPROACH_MEAS_TIME_V 0xFF 2995 #define RTC_CNTL_TOUCH_APPROACH_MEAS_TIME_S 24 2996 /* RTC_CNTL_TOUCH_SLP_CHANNEL_CLR : WO ;bitpos:[23] ;default: 1'd0 ; */ 2997 /*description: clear touch slp channel.*/ 2998 #define RTC_CNTL_TOUCH_SLP_CHANNEL_CLR (BIT(23)) 2999 #define RTC_CNTL_TOUCH_SLP_CHANNEL_CLR_M (BIT(23)) 3000 #define RTC_CNTL_TOUCH_SLP_CHANNEL_CLR_V 0x1 3001 #define RTC_CNTL_TOUCH_SLP_CHANNEL_CLR_S 23 3002 3003 #define RTC_CNTL_TOUCH_FILTER_CTRL_REG (DR_REG_RTCCNTL_BASE + 0x11C) 3004 /* RTC_CNTL_TOUCH_FILTER_EN : R/W ;bitpos:[31] ;default: 1'b1 ; */ 3005 /*description: touch filter enable.*/ 3006 #define RTC_CNTL_TOUCH_FILTER_EN (BIT(31)) 3007 #define RTC_CNTL_TOUCH_FILTER_EN_M (BIT(31)) 3008 #define RTC_CNTL_TOUCH_FILTER_EN_V 0x1 3009 #define RTC_CNTL_TOUCH_FILTER_EN_S 31 3010 /* RTC_CNTL_TOUCH_FILTER_MODE : R/W ;bitpos:[30:28] ;default: 3'd1 ; */ 3011 /*description: 0: IIR ? 1: IIR ? 2: IIR 1/8 3: Jitter.*/ 3012 #define RTC_CNTL_TOUCH_FILTER_MODE 0x00000007 3013 #define RTC_CNTL_TOUCH_FILTER_MODE_M ((RTC_CNTL_TOUCH_FILTER_MODE_V)<<(RTC_CNTL_TOUCH_FILTER_MODE_S)) 3014 #define RTC_CNTL_TOUCH_FILTER_MODE_V 0x7 3015 #define RTC_CNTL_TOUCH_FILTER_MODE_S 28 3016 /* RTC_CNTL_TOUCH_DEBOUNCE : R/W ;bitpos:[27:25] ;default: 3'd3 ; */ 3017 /*description: debounce counter.*/ 3018 #define RTC_CNTL_TOUCH_DEBOUNCE 0x00000007 3019 #define RTC_CNTL_TOUCH_DEBOUNCE_M ((RTC_CNTL_TOUCH_DEBOUNCE_V)<<(RTC_CNTL_TOUCH_DEBOUNCE_S)) 3020 #define RTC_CNTL_TOUCH_DEBOUNCE_V 0x7 3021 #define RTC_CNTL_TOUCH_DEBOUNCE_S 25 3022 /* RTC_CNTL_TOUCH_CONFIG3 : R/W ;bitpos:[24:23] ;default: 2'd1 ; */ 3023 /*description: */ 3024 #define RTC_CNTL_TOUCH_CONFIG3 0x00000003 3025 #define RTC_CNTL_TOUCH_CONFIG3_M ((RTC_CNTL_TOUCH_CONFIG3_V) << (RTC_CNTL_TOUCH_CONFIG3_S)) 3026 #define RTC_CNTL_TOUCH_CONFIG3_V 0x3 3027 #define RTC_CNTL_TOUCH_CONFIG3_S 23 3028 /* RTC_CNTL_TOUCH_NOISE_THRES : R/W ;bitpos:[22:21] ;default: 2'd1 ; */ 3029 /*description: .*/ 3030 #define RTC_CNTL_TOUCH_NOISE_THRES 0x00000003 3031 #define RTC_CNTL_TOUCH_NOISE_THRES_M ((RTC_CNTL_TOUCH_NOISE_THRES_V)<<(RTC_CNTL_TOUCH_NOISE_THRES_S)) 3032 #define RTC_CNTL_TOUCH_NOISE_THRES_V 0x3 3033 #define RTC_CNTL_TOUCH_NOISE_THRES_S 21 3034 /* RTC_CNTL_TOUCH_CONFIG2 : R/W ;bitpos:[20:19] ;default: 2'd1 ; */ 3035 /*description: */ 3036 #define RTC_CNTL_TOUCH_CONFIG2 0x00000003 3037 #define RTC_CNTL_TOUCH_CONFIG2_M ((RTC_CNTL_TOUCH_CONFIG2_V) << (RTC_CNTL_TOUCH_CONFIG2_S)) 3038 #define RTC_CNTL_TOUCH_CONFIG2_V 0x3 3039 #define RTC_CNTL_TOUCH_CONFIG2_S 19 3040 /* RTC_CNTL_TOUCH_CONFIG1 : R/W ;bitpos:[18:15] ;default: 4'd5 ; */ 3041 /*description: */ 3042 #define RTC_CNTL_TOUCH_CONFIG1 0x0000000F 3043 #define RTC_CNTL_TOUCH_CONFIG1_M ((RTC_CNTL_TOUCH_CONFIG1_V) << (RTC_CNTL_TOUCH_CONFIG1_S)) 3044 #define RTC_CNTL_TOUCH_CONFIG1_V 0xF 3045 #define RTC_CNTL_TOUCH_CONFIG1_S 15 3046 /* RTC_CNTL_TOUCH_JITTER_STEP : R/W ;bitpos:[14:11] ;default: 4'd1 ; */ 3047 /*description: touch jitter step.*/ 3048 #define RTC_CNTL_TOUCH_JITTER_STEP 0x0000000F 3049 #define RTC_CNTL_TOUCH_JITTER_STEP_M ((RTC_CNTL_TOUCH_JITTER_STEP_V)<<(RTC_CNTL_TOUCH_JITTER_STEP_S)) 3050 #define RTC_CNTL_TOUCH_JITTER_STEP_V 0xF 3051 #define RTC_CNTL_TOUCH_JITTER_STEP_S 11 3052 /* RTC_CNTL_TOUCH_SMOOTH_LVL : R/W ;bitpos:[10:9] ;default: 2'd0 ; */ 3053 /*description: .*/ 3054 #define RTC_CNTL_TOUCH_SMOOTH_LVL 0x00000003 3055 #define RTC_CNTL_TOUCH_SMOOTH_LVL_M ((RTC_CNTL_TOUCH_SMOOTH_LVL_V)<<(RTC_CNTL_TOUCH_SMOOTH_LVL_S)) 3056 #define RTC_CNTL_TOUCH_SMOOTH_LVL_V 0x3 3057 #define RTC_CNTL_TOUCH_SMOOTH_LVL_S 9 3058 /* RTC_CNTL_TOUCH_BYPASS_NOISE_THRES : R/W ;bitpos:[8] ;default: 1'b0 ; */ 3059 /*description: .*/ 3060 #define RTC_CNTL_TOUCH_BYPASS_NOISE_THRES (BIT(8)) 3061 #define RTC_CNTL_TOUCH_BYPASS_NOISE_THRES_M (BIT(8)) 3062 #define RTC_CNTL_TOUCH_BYPASS_NOISE_THRES_V 0x1 3063 #define RTC_CNTL_TOUCH_BYPASS_NOISE_THRES_S 8 3064 /* RTC_CNTL_TOUCH_BYPASS_NEG_THRES : R/W ;bitpos:[7] ;default: 1'b0 ; */ 3065 /*description: */ 3066 #define RTC_CNTL_TOUCH_BYPASS_NEG_THRES (BIT(7)) 3067 #define RTC_CNTL_TOUCH_BYPASS_NEG_THRES_M (BIT(7)) 3068 #define RTC_CNTL_TOUCH_BYPASS_NEG_THRES_V 0x1 3069 #define RTC_CNTL_TOUCH_BYPASS_NEG_THRES_S 7 3070 3071 #define RTC_CNTL_USB_CONF_REG (DR_REG_RTCCNTL_BASE + 0x120) 3072 /* RTC_CNTL_SW_HW_USB_PHY_SEL : R/W ;bitpos:[20] ;default: 1'b0 ; */ 3073 /*description: .*/ 3074 #define RTC_CNTL_SW_HW_USB_PHY_SEL (BIT(20)) 3075 #define RTC_CNTL_SW_HW_USB_PHY_SEL_M (BIT(20)) 3076 #define RTC_CNTL_SW_HW_USB_PHY_SEL_V 0x1 3077 #define RTC_CNTL_SW_HW_USB_PHY_SEL_S 20 3078 /* RTC_CNTL_SW_USB_PHY_SEL : R/W ;bitpos:[19] ;default: 1'b0 ; */ 3079 /*description: .*/ 3080 #define RTC_CNTL_SW_USB_PHY_SEL (BIT(19)) 3081 #define RTC_CNTL_SW_USB_PHY_SEL_M (BIT(19)) 3082 #define RTC_CNTL_SW_USB_PHY_SEL_V 0x1 3083 #define RTC_CNTL_SW_USB_PHY_SEL_S 19 3084 /* RTC_CNTL_IO_MUX_RESET_DISABLE : R/W ;bitpos:[18] ;default: 1'd0 ; */ 3085 /*description: .*/ 3086 #define RTC_CNTL_IO_MUX_RESET_DISABLE (BIT(18)) 3087 #define RTC_CNTL_IO_MUX_RESET_DISABLE_M (BIT(18)) 3088 #define RTC_CNTL_IO_MUX_RESET_DISABLE_V 0x1 3089 #define RTC_CNTL_IO_MUX_RESET_DISABLE_S 18 3090 /* RTC_CNTL_USB_RESET_DISABLE : R/W ;bitpos:[17] ;default: 1'd0 ; */ 3091 /*description: .*/ 3092 #define RTC_CNTL_USB_RESET_DISABLE (BIT(17)) 3093 #define RTC_CNTL_USB_RESET_DISABLE_M (BIT(17)) 3094 #define RTC_CNTL_USB_RESET_DISABLE_V 0x1 3095 #define RTC_CNTL_USB_RESET_DISABLE_S 17 3096 /* RTC_CNTL_USB_TX_EN_OVERRIDE : R/W ;bitpos:[16] ;default: 1'd0 ; */ 3097 /*description: .*/ 3098 #define RTC_CNTL_USB_TX_EN_OVERRIDE (BIT(16)) 3099 #define RTC_CNTL_USB_TX_EN_OVERRIDE_M (BIT(16)) 3100 #define RTC_CNTL_USB_TX_EN_OVERRIDE_V 0x1 3101 #define RTC_CNTL_USB_TX_EN_OVERRIDE_S 16 3102 /* RTC_CNTL_USB_TX_EN : R/W ;bitpos:[15] ;default: 1'd0 ; */ 3103 /*description: .*/ 3104 #define RTC_CNTL_USB_TX_EN (BIT(15)) 3105 #define RTC_CNTL_USB_TX_EN_M (BIT(15)) 3106 #define RTC_CNTL_USB_TX_EN_V 0x1 3107 #define RTC_CNTL_USB_TX_EN_S 15 3108 /* RTC_CNTL_USB_TXP : R/W ;bitpos:[14] ;default: 1'd0 ; */ 3109 /*description: .*/ 3110 #define RTC_CNTL_USB_TXP (BIT(14)) 3111 #define RTC_CNTL_USB_TXP_M (BIT(14)) 3112 #define RTC_CNTL_USB_TXP_V 0x1 3113 #define RTC_CNTL_USB_TXP_S 14 3114 /* RTC_CNTL_USB_TXM : R/W ;bitpos:[13] ;default: 1'd0 ; */ 3115 /*description: .*/ 3116 #define RTC_CNTL_USB_TXM (BIT(13)) 3117 #define RTC_CNTL_USB_TXM_M (BIT(13)) 3118 #define RTC_CNTL_USB_TXM_V 0x1 3119 #define RTC_CNTL_USB_TXM_S 13 3120 /* RTC_CNTL_USB_PAD_ENABLE : R/W ;bitpos:[12] ;default: 1'd0 ; */ 3121 /*description: .*/ 3122 #define RTC_CNTL_USB_PAD_ENABLE (BIT(12)) 3123 #define RTC_CNTL_USB_PAD_ENABLE_M (BIT(12)) 3124 #define RTC_CNTL_USB_PAD_ENABLE_V 0x1 3125 #define RTC_CNTL_USB_PAD_ENABLE_S 12 3126 /* RTC_CNTL_USB_PAD_ENABLE_OVERRIDE : R/W ;bitpos:[11] ;default: 1'd0 ; */ 3127 /*description: .*/ 3128 #define RTC_CNTL_USB_PAD_ENABLE_OVERRIDE (BIT(11)) 3129 #define RTC_CNTL_USB_PAD_ENABLE_OVERRIDE_M (BIT(11)) 3130 #define RTC_CNTL_USB_PAD_ENABLE_OVERRIDE_V 0x1 3131 #define RTC_CNTL_USB_PAD_ENABLE_OVERRIDE_S 11 3132 /* RTC_CNTL_USB_PULLUP_VALUE : R/W ;bitpos:[10] ;default: 1'd0 ; */ 3133 /*description: .*/ 3134 #define RTC_CNTL_USB_PULLUP_VALUE (BIT(10)) 3135 #define RTC_CNTL_USB_PULLUP_VALUE_M (BIT(10)) 3136 #define RTC_CNTL_USB_PULLUP_VALUE_V 0x1 3137 #define RTC_CNTL_USB_PULLUP_VALUE_S 10 3138 /* RTC_CNTL_USB_DM_PULLDOWN : R/W ;bitpos:[9] ;default: 1'd0 ; */ 3139 /*description: .*/ 3140 #define RTC_CNTL_USB_DM_PULLDOWN (BIT(9)) 3141 #define RTC_CNTL_USB_DM_PULLDOWN_M (BIT(9)) 3142 #define RTC_CNTL_USB_DM_PULLDOWN_V 0x1 3143 #define RTC_CNTL_USB_DM_PULLDOWN_S 9 3144 /* RTC_CNTL_USB_DM_PULLUP : R/W ;bitpos:[8] ;default: 1'd0 ; */ 3145 /*description: .*/ 3146 #define RTC_CNTL_USB_DM_PULLUP (BIT(8)) 3147 #define RTC_CNTL_USB_DM_PULLUP_M (BIT(8)) 3148 #define RTC_CNTL_USB_DM_PULLUP_V 0x1 3149 #define RTC_CNTL_USB_DM_PULLUP_S 8 3150 /* RTC_CNTL_USB_DP_PULLDOWN : R/W ;bitpos:[7] ;default: 1'd0 ; */ 3151 /*description: .*/ 3152 #define RTC_CNTL_USB_DP_PULLDOWN (BIT(7)) 3153 #define RTC_CNTL_USB_DP_PULLDOWN_M (BIT(7)) 3154 #define RTC_CNTL_USB_DP_PULLDOWN_V 0x1 3155 #define RTC_CNTL_USB_DP_PULLDOWN_S 7 3156 /* RTC_CNTL_USB_DP_PULLUP : R/W ;bitpos:[6] ;default: 1'd0 ; */ 3157 /*description: .*/ 3158 #define RTC_CNTL_USB_DP_PULLUP (BIT(6)) 3159 #define RTC_CNTL_USB_DP_PULLUP_M (BIT(6)) 3160 #define RTC_CNTL_USB_DP_PULLUP_V 0x1 3161 #define RTC_CNTL_USB_DP_PULLUP_S 6 3162 /* RTC_CNTL_USB_PAD_PULL_OVERRIDE : R/W ;bitpos:[5] ;default: 1'd0 ; */ 3163 /*description: .*/ 3164 #define RTC_CNTL_USB_PAD_PULL_OVERRIDE (BIT(5)) 3165 #define RTC_CNTL_USB_PAD_PULL_OVERRIDE_M (BIT(5)) 3166 #define RTC_CNTL_USB_PAD_PULL_OVERRIDE_V 0x1 3167 #define RTC_CNTL_USB_PAD_PULL_OVERRIDE_S 5 3168 /* RTC_CNTL_USB_VREF_OVERRIDE : R/W ;bitpos:[4] ;default: 1'd0 ; */ 3169 /*description: .*/ 3170 #define RTC_CNTL_USB_VREF_OVERRIDE (BIT(4)) 3171 #define RTC_CNTL_USB_VREF_OVERRIDE_M (BIT(4)) 3172 #define RTC_CNTL_USB_VREF_OVERRIDE_V 0x1 3173 #define RTC_CNTL_USB_VREF_OVERRIDE_S 4 3174 /* RTC_CNTL_USB_VREFL : R/W ;bitpos:[3:2] ;default: 2'd0 ; */ 3175 /*description: .*/ 3176 #define RTC_CNTL_USB_VREFL 0x00000003 3177 #define RTC_CNTL_USB_VREFL_M ((RTC_CNTL_USB_VREFL_V)<<(RTC_CNTL_USB_VREFL_S)) 3178 #define RTC_CNTL_USB_VREFL_V 0x3 3179 #define RTC_CNTL_USB_VREFL_S 2 3180 /* RTC_CNTL_USB_VREFH : R/W ;bitpos:[1:0] ;default: 2'd0 ; */ 3181 /*description: .*/ 3182 #define RTC_CNTL_USB_VREFH 0x00000003 3183 #define RTC_CNTL_USB_VREFH_M ((RTC_CNTL_USB_VREFH_V)<<(RTC_CNTL_USB_VREFH_S)) 3184 #define RTC_CNTL_USB_VREFH_V 0x3 3185 #define RTC_CNTL_USB_VREFH_S 0 3186 3187 #define RTC_CNTL_TOUCH_TIMEOUT_CTRL_REG (DR_REG_RTCCNTL_BASE + 0x124) 3188 /* RTC_CNTL_TOUCH_TIMEOUT_EN : R/W ;bitpos:[22] ;default: 1'b1 ; */ 3189 /*description: .*/ 3190 #define RTC_CNTL_TOUCH_TIMEOUT_EN (BIT(22)) 3191 #define RTC_CNTL_TOUCH_TIMEOUT_EN_M (BIT(22)) 3192 #define RTC_CNTL_TOUCH_TIMEOUT_EN_V 0x1 3193 #define RTC_CNTL_TOUCH_TIMEOUT_EN_S 22 3194 /* RTC_CNTL_TOUCH_TIMEOUT_NUM : R/W ;bitpos:[21:0] ;default: 22'h3fffff ; */ 3195 /*description: .*/ 3196 #define RTC_CNTL_TOUCH_TIMEOUT_NUM 0x003FFFFF 3197 #define RTC_CNTL_TOUCH_TIMEOUT_NUM_M ((RTC_CNTL_TOUCH_TIMEOUT_NUM_V)<<(RTC_CNTL_TOUCH_TIMEOUT_NUM_S)) 3198 #define RTC_CNTL_TOUCH_TIMEOUT_NUM_V 0x3FFFFF 3199 #define RTC_CNTL_TOUCH_TIMEOUT_NUM_S 0 3200 3201 #define RTC_CNTL_SLP_REJECT_CAUSE_REG (DR_REG_RTCCNTL_BASE + 0x128) 3202 /* RTC_CNTL_REJECT_CAUSE : RO ;bitpos:[17:0] ;default: 18'd0 ; */ 3203 /*description: sleep reject cause.*/ 3204 #define RTC_CNTL_REJECT_CAUSE 0x0003FFFF 3205 #define RTC_CNTL_REJECT_CAUSE_M ((RTC_CNTL_REJECT_CAUSE_V)<<(RTC_CNTL_REJECT_CAUSE_S)) 3206 #define RTC_CNTL_REJECT_CAUSE_V 0x3FFFF 3207 #define RTC_CNTL_REJECT_CAUSE_S 0 3208 3209 #define RTC_CNTL_OPTION1_REG (DR_REG_RTCCNTL_BASE + 0x12C) 3210 /* RTC_CNTL_FORCE_DOWNLOAD_BOOT : R/W ;bitpos:[0] ;default: 1'd0 ; */ 3211 /*description: .*/ 3212 #define RTC_CNTL_FORCE_DOWNLOAD_BOOT (BIT(0)) 3213 #define RTC_CNTL_FORCE_DOWNLOAD_BOOT_M (BIT(0)) 3214 #define RTC_CNTL_FORCE_DOWNLOAD_BOOT_V 0x1 3215 #define RTC_CNTL_FORCE_DOWNLOAD_BOOT_S 0 3216 3217 #define RTC_CNTL_SLP_WAKEUP_CAUSE_REG (DR_REG_RTCCNTL_BASE + 0x130) 3218 /* RTC_CNTL_WAKEUP_CAUSE : RO ;bitpos:[16:0] ;default: 17'd0 ; */ 3219 /*description: sleep wakeup cause.*/ 3220 #define RTC_CNTL_WAKEUP_CAUSE 0x0001FFFF 3221 #define RTC_CNTL_WAKEUP_CAUSE_M ((RTC_CNTL_WAKEUP_CAUSE_V)<<(RTC_CNTL_WAKEUP_CAUSE_S)) 3222 #define RTC_CNTL_WAKEUP_CAUSE_V 0x1FFFF 3223 #define RTC_CNTL_WAKEUP_CAUSE_S 0 3224 3225 #define RTC_CNTL_ULP_CP_TIMER_1_REG (DR_REG_RTCCNTL_BASE + 0x134) 3226 /* RTC_CNTL_ULP_CP_TIMER_SLP_CYCLE : R/W ;bitpos:[31:8] ;default: 24'd200 ; */ 3227 /*description: sleep cycles for ULP-coprocessor timer.*/ 3228 #define RTC_CNTL_ULP_CP_TIMER_SLP_CYCLE 0x00FFFFFF 3229 #define RTC_CNTL_ULP_CP_TIMER_SLP_CYCLE_M ((RTC_CNTL_ULP_CP_TIMER_SLP_CYCLE_V)<<(RTC_CNTL_ULP_CP_TIMER_SLP_CYCLE_S)) 3230 #define RTC_CNTL_ULP_CP_TIMER_SLP_CYCLE_V 0xFFFFFF 3231 #define RTC_CNTL_ULP_CP_TIMER_SLP_CYCLE_S 8 3232 3233 #define RTC_CNTL_INT_ENA_W1TS_REG (DR_REG_RTCCNTL_BASE + 0x138) 3234 /* RTC_CNTL_TOUCH_APPROACH_LOOP_DONE_INT_ENA_W1TS : WO ;bitpos:[20] ;default: 1'b0 ; */ 3235 /*description: .*/ 3236 #define RTC_CNTL_TOUCH_APPROACH_LOOP_DONE_INT_ENA_W1TS (BIT(20)) 3237 #define RTC_CNTL_TOUCH_APPROACH_LOOP_DONE_INT_ENA_W1TS_M (BIT(20)) 3238 #define RTC_CNTL_TOUCH_APPROACH_LOOP_DONE_INT_ENA_W1TS_V 0x1 3239 #define RTC_CNTL_TOUCH_APPROACH_LOOP_DONE_INT_ENA_W1TS_S 20 3240 /* RTC_CNTL_GLITCH_DET_INT_ENA_W1TS : WO ;bitpos:[19] ;default: 1'b0 ; */ 3241 /*description: enbale gitch det interrupt.*/ 3242 #define RTC_CNTL_GLITCH_DET_INT_ENA_W1TS (BIT(19)) 3243 #define RTC_CNTL_GLITCH_DET_INT_ENA_W1TS_M (BIT(19)) 3244 #define RTC_CNTL_GLITCH_DET_INT_ENA_W1TS_V 0x1 3245 #define RTC_CNTL_GLITCH_DET_INT_ENA_W1TS_S 19 3246 /* RTC_CNTL_TOUCH_TIMEOUT_INT_ENA_W1TS : WO ;bitpos:[18] ;default: 1'b0 ; */ 3247 /*description: enable touch timeout interrupt.*/ 3248 #define RTC_CNTL_TOUCH_TIMEOUT_INT_ENA_W1TS (BIT(18)) 3249 #define RTC_CNTL_TOUCH_TIMEOUT_INT_ENA_W1TS_M (BIT(18)) 3250 #define RTC_CNTL_TOUCH_TIMEOUT_INT_ENA_W1TS_V 0x1 3251 #define RTC_CNTL_TOUCH_TIMEOUT_INT_ENA_W1TS_S 18 3252 /* RTC_CNTL_COCPU_TRAP_INT_ENA_W1TS : WO ;bitpos:[17] ;default: 1'b0 ; */ 3253 /*description: enable cocpu trap interrupt.*/ 3254 #define RTC_CNTL_COCPU_TRAP_INT_ENA_W1TS (BIT(17)) 3255 #define RTC_CNTL_COCPU_TRAP_INT_ENA_W1TS_M (BIT(17)) 3256 #define RTC_CNTL_COCPU_TRAP_INT_ENA_W1TS_V 0x1 3257 #define RTC_CNTL_COCPU_TRAP_INT_ENA_W1TS_S 17 3258 /* RTC_CNTL_XTAL32K_DEAD_INT_ENA_W1TS : WO ;bitpos:[16] ;default: 1'b0 ; */ 3259 /*description: enable xtal32k_dead interrupt.*/ 3260 #define RTC_CNTL_XTAL32K_DEAD_INT_ENA_W1TS (BIT(16)) 3261 #define RTC_CNTL_XTAL32K_DEAD_INT_ENA_W1TS_M (BIT(16)) 3262 #define RTC_CNTL_XTAL32K_DEAD_INT_ENA_W1TS_V 0x1 3263 #define RTC_CNTL_XTAL32K_DEAD_INT_ENA_W1TS_S 16 3264 /* RTC_CNTL_SWD_INT_ENA_W1TS : WO ;bitpos:[15] ;default: 1'b0 ; */ 3265 /*description: enable super watch dog interrupt.*/ 3266 #define RTC_CNTL_SWD_INT_ENA_W1TS (BIT(15)) 3267 #define RTC_CNTL_SWD_INT_ENA_W1TS_M (BIT(15)) 3268 #define RTC_CNTL_SWD_INT_ENA_W1TS_V 0x1 3269 #define RTC_CNTL_SWD_INT_ENA_W1TS_S 15 3270 /* RTC_CNTL_SARADC2_INT_ENA_W1TS : WO ;bitpos:[14] ;default: 1'b0 ; */ 3271 /*description: enable saradc2 interrupt.*/ 3272 #define RTC_CNTL_SARADC2_INT_ENA_W1TS (BIT(14)) 3273 #define RTC_CNTL_SARADC2_INT_ENA_W1TS_M (BIT(14)) 3274 #define RTC_CNTL_SARADC2_INT_ENA_W1TS_V 0x1 3275 #define RTC_CNTL_SARADC2_INT_ENA_W1TS_S 14 3276 /* RTC_CNTL_COCPU_INT_ENA_W1TS : WO ;bitpos:[13] ;default: 1'b0 ; */ 3277 /*description: enable riscV cocpu interrupt.*/ 3278 #define RTC_CNTL_COCPU_INT_ENA_W1TS (BIT(13)) 3279 #define RTC_CNTL_COCPU_INT_ENA_W1TS_M (BIT(13)) 3280 #define RTC_CNTL_COCPU_INT_ENA_W1TS_V 0x1 3281 #define RTC_CNTL_COCPU_INT_ENA_W1TS_S 13 3282 /* RTC_CNTL_TSENS_INT_ENA_W1TS : WO ;bitpos:[12] ;default: 1'b0 ; */ 3283 /*description: enable tsens interrupt.*/ 3284 #define RTC_CNTL_TSENS_INT_ENA_W1TS (BIT(12)) 3285 #define RTC_CNTL_TSENS_INT_ENA_W1TS_M (BIT(12)) 3286 #define RTC_CNTL_TSENS_INT_ENA_W1TS_V 0x1 3287 #define RTC_CNTL_TSENS_INT_ENA_W1TS_S 12 3288 /* RTC_CNTL_SARADC1_INT_ENA_W1TS : WO ;bitpos:[11] ;default: 1'b0 ; */ 3289 /*description: enable saradc1 interrupt.*/ 3290 #define RTC_CNTL_SARADC1_INT_ENA_W1TS (BIT(11)) 3291 #define RTC_CNTL_SARADC1_INT_ENA_W1TS_M (BIT(11)) 3292 #define RTC_CNTL_SARADC1_INT_ENA_W1TS_V 0x1 3293 #define RTC_CNTL_SARADC1_INT_ENA_W1TS_S 11 3294 /* RTC_CNTL_MAIN_TIMER_INT_ENA_W1TS : WO ;bitpos:[10] ;default: 1'b0 ; */ 3295 /*description: enable RTC main timer interrupt.*/ 3296 #define RTC_CNTL_MAIN_TIMER_INT_ENA_W1TS (BIT(10)) 3297 #define RTC_CNTL_MAIN_TIMER_INT_ENA_W1TS_M (BIT(10)) 3298 #define RTC_CNTL_MAIN_TIMER_INT_ENA_W1TS_V 0x1 3299 #define RTC_CNTL_MAIN_TIMER_INT_ENA_W1TS_S 10 3300 /* RTC_CNTL_BROWN_OUT_INT_ENA_W1TS : WO ;bitpos:[9] ;default: 1'b0 ; */ 3301 /*description: enable brown out interrupt.*/ 3302 #define RTC_CNTL_BROWN_OUT_INT_ENA_W1TS (BIT(9)) 3303 #define RTC_CNTL_BROWN_OUT_INT_ENA_W1TS_M (BIT(9)) 3304 #define RTC_CNTL_BROWN_OUT_INT_ENA_W1TS_V 0x1 3305 #define RTC_CNTL_BROWN_OUT_INT_ENA_W1TS_S 9 3306 /* RTC_CNTL_TOUCH_INACTIVE_INT_ENA_W1TS : WO ;bitpos:[8] ;default: 1'b0 ; */ 3307 /*description: enable touch inactive interrupt.*/ 3308 #define RTC_CNTL_TOUCH_INACTIVE_INT_ENA_W1TS (BIT(8)) 3309 #define RTC_CNTL_TOUCH_INACTIVE_INT_ENA_W1TS_M (BIT(8)) 3310 #define RTC_CNTL_TOUCH_INACTIVE_INT_ENA_W1TS_V 0x1 3311 #define RTC_CNTL_TOUCH_INACTIVE_INT_ENA_W1TS_S 8 3312 /* RTC_CNTL_TOUCH_ACTIVE_INT_ENA_W1TS : WO ;bitpos:[7] ;default: 1'b0 ; */ 3313 /*description: enable touch active interrupt.*/ 3314 #define RTC_CNTL_TOUCH_ACTIVE_INT_ENA_W1TS (BIT(7)) 3315 #define RTC_CNTL_TOUCH_ACTIVE_INT_ENA_W1TS_M (BIT(7)) 3316 #define RTC_CNTL_TOUCH_ACTIVE_INT_ENA_W1TS_V 0x1 3317 #define RTC_CNTL_TOUCH_ACTIVE_INT_ENA_W1TS_S 7 3318 /* RTC_CNTL_TOUCH_DONE_INT_ENA_W1TS : WO ;bitpos:[6] ;default: 1'b0 ; */ 3319 /*description: enable touch done interrupt.*/ 3320 #define RTC_CNTL_TOUCH_DONE_INT_ENA_W1TS (BIT(6)) 3321 #define RTC_CNTL_TOUCH_DONE_INT_ENA_W1TS_M (BIT(6)) 3322 #define RTC_CNTL_TOUCH_DONE_INT_ENA_W1TS_V 0x1 3323 #define RTC_CNTL_TOUCH_DONE_INT_ENA_W1TS_S 6 3324 /* RTC_CNTL_ULP_CP_INT_ENA_W1TS : WO ;bitpos:[5] ;default: 1'b0 ; */ 3325 /*description: enable ULP-coprocessor interrupt.*/ 3326 #define RTC_CNTL_ULP_CP_INT_ENA_W1TS (BIT(5)) 3327 #define RTC_CNTL_ULP_CP_INT_ENA_W1TS_M (BIT(5)) 3328 #define RTC_CNTL_ULP_CP_INT_ENA_W1TS_V 0x1 3329 #define RTC_CNTL_ULP_CP_INT_ENA_W1TS_S 5 3330 /* RTC_CNTL_TOUCH_SCAN_DONE_INT_ENA_W1TS : WO ;bitpos:[4] ;default: 1'b0 ; */ 3331 /*description: enable touch scan done interrupt.*/ 3332 #define RTC_CNTL_TOUCH_SCAN_DONE_INT_ENA_W1TS (BIT(4)) 3333 #define RTC_CNTL_TOUCH_SCAN_DONE_INT_ENA_W1TS_M (BIT(4)) 3334 #define RTC_CNTL_TOUCH_SCAN_DONE_INT_ENA_W1TS_V 0x1 3335 #define RTC_CNTL_TOUCH_SCAN_DONE_INT_ENA_W1TS_S 4 3336 /* RTC_CNTL_WDT_INT_ENA_W1TS : WO ;bitpos:[3] ;default: 1'b0 ; */ 3337 /*description: enable RTC WDT interrupt.*/ 3338 #define RTC_CNTL_WDT_INT_ENA_W1TS (BIT(3)) 3339 #define RTC_CNTL_WDT_INT_ENA_W1TS_M (BIT(3)) 3340 #define RTC_CNTL_WDT_INT_ENA_W1TS_V 0x1 3341 #define RTC_CNTL_WDT_INT_ENA_W1TS_S 3 3342 /* RTC_CNTL_SDIO_IDLE_INT_ENA_W1TS : WO ;bitpos:[2] ;default: 1'b0 ; */ 3343 /*description: enable SDIO idle interrupt.*/ 3344 #define RTC_CNTL_SDIO_IDLE_INT_ENA_W1TS (BIT(2)) 3345 #define RTC_CNTL_SDIO_IDLE_INT_ENA_W1TS_M (BIT(2)) 3346 #define RTC_CNTL_SDIO_IDLE_INT_ENA_W1TS_V 0x1 3347 #define RTC_CNTL_SDIO_IDLE_INT_ENA_W1TS_S 2 3348 /* RTC_CNTL_SLP_REJECT_INT_ENA_W1TS : WO ;bitpos:[1] ;default: 1'b0 ; */ 3349 /*description: enable sleep reject interrupt.*/ 3350 #define RTC_CNTL_SLP_REJECT_INT_ENA_W1TS (BIT(1)) 3351 #define RTC_CNTL_SLP_REJECT_INT_ENA_W1TS_M (BIT(1)) 3352 #define RTC_CNTL_SLP_REJECT_INT_ENA_W1TS_V 0x1 3353 #define RTC_CNTL_SLP_REJECT_INT_ENA_W1TS_S 1 3354 /* RTC_CNTL_SLP_WAKEUP_INT_ENA_W1TS : WO ;bitpos:[0] ;default: 1'b0 ; */ 3355 /*description: enable sleep wakeup interrupt.*/ 3356 #define RTC_CNTL_SLP_WAKEUP_INT_ENA_W1TS (BIT(0)) 3357 #define RTC_CNTL_SLP_WAKEUP_INT_ENA_W1TS_M (BIT(0)) 3358 #define RTC_CNTL_SLP_WAKEUP_INT_ENA_W1TS_V 0x1 3359 #define RTC_CNTL_SLP_WAKEUP_INT_ENA_W1TS_S 0 3360 3361 #define RTC_CNTL_INT_ENA_W1TC_REG (DR_REG_RTCCNTL_BASE + 0x13C) 3362 /* RTC_CNTL_TOUCH_APPROACH_LOOP_DONE_INT_ENA_W1TC : WO ;bitpos:[20] ;default: 1'b0 ; */ 3363 /*description: .*/ 3364 #define RTC_CNTL_TOUCH_APPROACH_LOOP_DONE_INT_ENA_W1TC (BIT(20)) 3365 #define RTC_CNTL_TOUCH_APPROACH_LOOP_DONE_INT_ENA_W1TC_M (BIT(20)) 3366 #define RTC_CNTL_TOUCH_APPROACH_LOOP_DONE_INT_ENA_W1TC_V 0x1 3367 #define RTC_CNTL_TOUCH_APPROACH_LOOP_DONE_INT_ENA_W1TC_S 20 3368 /* RTC_CNTL_GLITCH_DET_INT_ENA_W1TC : WO ;bitpos:[19] ;default: 1'b0 ; */ 3369 /*description: enbale gitch det interrupt.*/ 3370 #define RTC_CNTL_GLITCH_DET_INT_ENA_W1TC (BIT(19)) 3371 #define RTC_CNTL_GLITCH_DET_INT_ENA_W1TC_M (BIT(19)) 3372 #define RTC_CNTL_GLITCH_DET_INT_ENA_W1TC_V 0x1 3373 #define RTC_CNTL_GLITCH_DET_INT_ENA_W1TC_S 19 3374 /* RTC_CNTL_TOUCH_TIMEOUT_INT_ENA_W1TC : WO ;bitpos:[18] ;default: 1'b0 ; */ 3375 /*description: enable touch timeout interrupt.*/ 3376 #define RTC_CNTL_TOUCH_TIMEOUT_INT_ENA_W1TC (BIT(18)) 3377 #define RTC_CNTL_TOUCH_TIMEOUT_INT_ENA_W1TC_M (BIT(18)) 3378 #define RTC_CNTL_TOUCH_TIMEOUT_INT_ENA_W1TC_V 0x1 3379 #define RTC_CNTL_TOUCH_TIMEOUT_INT_ENA_W1TC_S 18 3380 /* RTC_CNTL_COCPU_TRAP_INT_ENA_W1TC : WO ;bitpos:[17] ;default: 1'b0 ; */ 3381 /*description: enable cocpu trap interrupt.*/ 3382 #define RTC_CNTL_COCPU_TRAP_INT_ENA_W1TC (BIT(17)) 3383 #define RTC_CNTL_COCPU_TRAP_INT_ENA_W1TC_M (BIT(17)) 3384 #define RTC_CNTL_COCPU_TRAP_INT_ENA_W1TC_V 0x1 3385 #define RTC_CNTL_COCPU_TRAP_INT_ENA_W1TC_S 17 3386 /* RTC_CNTL_XTAL32K_DEAD_INT_ENA_W1TC : WO ;bitpos:[16] ;default: 1'b0 ; */ 3387 /*description: enable xtal32k_dead interrupt.*/ 3388 #define RTC_CNTL_XTAL32K_DEAD_INT_ENA_W1TC (BIT(16)) 3389 #define RTC_CNTL_XTAL32K_DEAD_INT_ENA_W1TC_M (BIT(16)) 3390 #define RTC_CNTL_XTAL32K_DEAD_INT_ENA_W1TC_V 0x1 3391 #define RTC_CNTL_XTAL32K_DEAD_INT_ENA_W1TC_S 16 3392 /* RTC_CNTL_SWD_INT_ENA_W1TC : WO ;bitpos:[15] ;default: 1'b0 ; */ 3393 /*description: enable super watch dog interrupt.*/ 3394 #define RTC_CNTL_SWD_INT_ENA_W1TC (BIT(15)) 3395 #define RTC_CNTL_SWD_INT_ENA_W1TC_M (BIT(15)) 3396 #define RTC_CNTL_SWD_INT_ENA_W1TC_V 0x1 3397 #define RTC_CNTL_SWD_INT_ENA_W1TC_S 15 3398 /* RTC_CNTL_SARADC2_INT_ENA_W1TC : WO ;bitpos:[14] ;default: 1'b0 ; */ 3399 /*description: enable saradc2 interrupt.*/ 3400 #define RTC_CNTL_SARADC2_INT_ENA_W1TC (BIT(14)) 3401 #define RTC_CNTL_SARADC2_INT_ENA_W1TC_M (BIT(14)) 3402 #define RTC_CNTL_SARADC2_INT_ENA_W1TC_V 0x1 3403 #define RTC_CNTL_SARADC2_INT_ENA_W1TC_S 14 3404 /* RTC_CNTL_COCPU_INT_ENA_W1TC : WO ;bitpos:[13] ;default: 1'b0 ; */ 3405 /*description: enable riscV cocpu interrupt.*/ 3406 #define RTC_CNTL_COCPU_INT_ENA_W1TC (BIT(13)) 3407 #define RTC_CNTL_COCPU_INT_ENA_W1TC_M (BIT(13)) 3408 #define RTC_CNTL_COCPU_INT_ENA_W1TC_V 0x1 3409 #define RTC_CNTL_COCPU_INT_ENA_W1TC_S 13 3410 /* RTC_CNTL_TSENS_INT_ENA_W1TC : WO ;bitpos:[12] ;default: 1'b0 ; */ 3411 /*description: enable tsens interrupt.*/ 3412 #define RTC_CNTL_TSENS_INT_ENA_W1TC (BIT(12)) 3413 #define RTC_CNTL_TSENS_INT_ENA_W1TC_M (BIT(12)) 3414 #define RTC_CNTL_TSENS_INT_ENA_W1TC_V 0x1 3415 #define RTC_CNTL_TSENS_INT_ENA_W1TC_S 12 3416 /* RTC_CNTL_SARADC1_INT_ENA_W1TC : WO ;bitpos:[11] ;default: 1'b0 ; */ 3417 /*description: enable saradc1 interrupt.*/ 3418 #define RTC_CNTL_SARADC1_INT_ENA_W1TC (BIT(11)) 3419 #define RTC_CNTL_SARADC1_INT_ENA_W1TC_M (BIT(11)) 3420 #define RTC_CNTL_SARADC1_INT_ENA_W1TC_V 0x1 3421 #define RTC_CNTL_SARADC1_INT_ENA_W1TC_S 11 3422 /* RTC_CNTL_MAIN_TIMER_INT_ENA_W1TC : WO ;bitpos:[10] ;default: 1'b0 ; */ 3423 /*description: enable RTC main timer interrupt.*/ 3424 #define RTC_CNTL_MAIN_TIMER_INT_ENA_W1TC (BIT(10)) 3425 #define RTC_CNTL_MAIN_TIMER_INT_ENA_W1TC_M (BIT(10)) 3426 #define RTC_CNTL_MAIN_TIMER_INT_ENA_W1TC_V 0x1 3427 #define RTC_CNTL_MAIN_TIMER_INT_ENA_W1TC_S 10 3428 /* RTC_CNTL_BROWN_OUT_INT_ENA_W1TC : WO ;bitpos:[9] ;default: 1'b0 ; */ 3429 /*description: enable brown out interrupt.*/ 3430 #define RTC_CNTL_BROWN_OUT_INT_ENA_W1TC (BIT(9)) 3431 #define RTC_CNTL_BROWN_OUT_INT_ENA_W1TC_M (BIT(9)) 3432 #define RTC_CNTL_BROWN_OUT_INT_ENA_W1TC_V 0x1 3433 #define RTC_CNTL_BROWN_OUT_INT_ENA_W1TC_S 9 3434 /* RTC_CNTL_TOUCH_INACTIVE_INT_ENA_W1TC : WO ;bitpos:[8] ;default: 1'b0 ; */ 3435 /*description: enable touch inactive interrupt.*/ 3436 #define RTC_CNTL_TOUCH_INACTIVE_INT_ENA_W1TC (BIT(8)) 3437 #define RTC_CNTL_TOUCH_INACTIVE_INT_ENA_W1TC_M (BIT(8)) 3438 #define RTC_CNTL_TOUCH_INACTIVE_INT_ENA_W1TC_V 0x1 3439 #define RTC_CNTL_TOUCH_INACTIVE_INT_ENA_W1TC_S 8 3440 /* RTC_CNTL_TOUCH_ACTIVE_INT_ENA_W1TC : WO ;bitpos:[7] ;default: 1'b0 ; */ 3441 /*description: enable touch active interrupt.*/ 3442 #define RTC_CNTL_TOUCH_ACTIVE_INT_ENA_W1TC (BIT(7)) 3443 #define RTC_CNTL_TOUCH_ACTIVE_INT_ENA_W1TC_M (BIT(7)) 3444 #define RTC_CNTL_TOUCH_ACTIVE_INT_ENA_W1TC_V 0x1 3445 #define RTC_CNTL_TOUCH_ACTIVE_INT_ENA_W1TC_S 7 3446 /* RTC_CNTL_TOUCH_DONE_INT_ENA_W1TC : WO ;bitpos:[6] ;default: 1'b0 ; */ 3447 /*description: enable touch done interrupt.*/ 3448 #define RTC_CNTL_TOUCH_DONE_INT_ENA_W1TC (BIT(6)) 3449 #define RTC_CNTL_TOUCH_DONE_INT_ENA_W1TC_M (BIT(6)) 3450 #define RTC_CNTL_TOUCH_DONE_INT_ENA_W1TC_V 0x1 3451 #define RTC_CNTL_TOUCH_DONE_INT_ENA_W1TC_S 6 3452 /* RTC_CNTL_ULP_CP_INT_ENA_W1TC : WO ;bitpos:[5] ;default: 1'b0 ; */ 3453 /*description: enable ULP-coprocessor interrupt.*/ 3454 #define RTC_CNTL_ULP_CP_INT_ENA_W1TC (BIT(5)) 3455 #define RTC_CNTL_ULP_CP_INT_ENA_W1TC_M (BIT(5)) 3456 #define RTC_CNTL_ULP_CP_INT_ENA_W1TC_V 0x1 3457 #define RTC_CNTL_ULP_CP_INT_ENA_W1TC_S 5 3458 /* RTC_CNTL_TOUCH_SCAN_DONE_INT_ENA_W1TC : WO ;bitpos:[4] ;default: 1'b0 ; */ 3459 /*description: enable touch scan done interrupt.*/ 3460 #define RTC_CNTL_TOUCH_SCAN_DONE_INT_ENA_W1TC (BIT(4)) 3461 #define RTC_CNTL_TOUCH_SCAN_DONE_INT_ENA_W1TC_M (BIT(4)) 3462 #define RTC_CNTL_TOUCH_SCAN_DONE_INT_ENA_W1TC_V 0x1 3463 #define RTC_CNTL_TOUCH_SCAN_DONE_INT_ENA_W1TC_S 4 3464 /* RTC_CNTL_WDT_INT_ENA_W1TC : WO ;bitpos:[3] ;default: 1'b0 ; */ 3465 /*description: enable RTC WDT interrupt.*/ 3466 #define RTC_CNTL_WDT_INT_ENA_W1TC (BIT(3)) 3467 #define RTC_CNTL_WDT_INT_ENA_W1TC_M (BIT(3)) 3468 #define RTC_CNTL_WDT_INT_ENA_W1TC_V 0x1 3469 #define RTC_CNTL_WDT_INT_ENA_W1TC_S 3 3470 /* RTC_CNTL_SDIO_IDLE_INT_ENA_W1TC : WO ;bitpos:[2] ;default: 1'b0 ; */ 3471 /*description: enable SDIO idle interrupt.*/ 3472 #define RTC_CNTL_SDIO_IDLE_INT_ENA_W1TC (BIT(2)) 3473 #define RTC_CNTL_SDIO_IDLE_INT_ENA_W1TC_M (BIT(2)) 3474 #define RTC_CNTL_SDIO_IDLE_INT_ENA_W1TC_V 0x1 3475 #define RTC_CNTL_SDIO_IDLE_INT_ENA_W1TC_S 2 3476 /* RTC_CNTL_SLP_REJECT_INT_ENA_W1TC : WO ;bitpos:[1] ;default: 1'b0 ; */ 3477 /*description: enable sleep reject interrupt.*/ 3478 #define RTC_CNTL_SLP_REJECT_INT_ENA_W1TC (BIT(1)) 3479 #define RTC_CNTL_SLP_REJECT_INT_ENA_W1TC_M (BIT(1)) 3480 #define RTC_CNTL_SLP_REJECT_INT_ENA_W1TC_V 0x1 3481 #define RTC_CNTL_SLP_REJECT_INT_ENA_W1TC_S 1 3482 /* RTC_CNTL_SLP_WAKEUP_INT_ENA_W1TC : WO ;bitpos:[0] ;default: 1'b0 ; */ 3483 /*description: enable sleep wakeup interrupt.*/ 3484 #define RTC_CNTL_SLP_WAKEUP_INT_ENA_W1TC (BIT(0)) 3485 #define RTC_CNTL_SLP_WAKEUP_INT_ENA_W1TC_M (BIT(0)) 3486 #define RTC_CNTL_SLP_WAKEUP_INT_ENA_W1TC_V 0x1 3487 #define RTC_CNTL_SLP_WAKEUP_INT_ENA_W1TC_S 0 3488 3489 #define RTC_CNTL_RETENTION_CTRL_REG (DR_REG_RTCCNTL_BASE + 0x140) 3490 /* RTC_CNTL_RETENTION_WAIT : R/W ;bitpos:[31:25] ;default: 7'd20 ; */ 3491 /*description: wait cycles for rention operation.*/ 3492 #define RTC_CNTL_RETENTION_WAIT 0x0000007F 3493 #define RTC_CNTL_RETENTION_WAIT_M ((RTC_CNTL_RETENTION_WAIT_V)<<(RTC_CNTL_RETENTION_WAIT_S)) 3494 #define RTC_CNTL_RETENTION_WAIT_V 0x7F 3495 #define RTC_CNTL_RETENTION_WAIT_S 25 3496 /* RTC_CNTL_RETENTION_EN : R/W ;bitpos:[24] ;default: 1'd0 ; */ 3497 /*description: .*/ 3498 #define RTC_CNTL_RETENTION_EN (BIT(24)) 3499 #define RTC_CNTL_RETENTION_EN_M (BIT(24)) 3500 #define RTC_CNTL_RETENTION_EN_V 0x1 3501 #define RTC_CNTL_RETENTION_EN_S 24 3502 /* RTC_CNTL_RETENTION_CLKOFF_WAIT : R/W ;bitpos:[23:20] ;default: 4'd3 ; */ 3503 /*description: .*/ 3504 #define RTC_CNTL_RETENTION_CLKOFF_WAIT 0x0000000F 3505 #define RTC_CNTL_RETENTION_CLKOFF_WAIT_M ((RTC_CNTL_RETENTION_CLKOFF_WAIT_V)<<(RTC_CNTL_RETENTION_CLKOFF_WAIT_S)) 3506 #define RTC_CNTL_RETENTION_CLKOFF_WAIT_V 0xF 3507 #define RTC_CNTL_RETENTION_CLKOFF_WAIT_S 20 3508 /* RTC_CNTL_RETENTION_DONE_WAIT : R/W ;bitpos:[19:17] ;default: 3'd2 ; */ 3509 /*description: .*/ 3510 #define RTC_CNTL_RETENTION_DONE_WAIT 0x00000007 3511 #define RTC_CNTL_RETENTION_DONE_WAIT_M ((RTC_CNTL_RETENTION_DONE_WAIT_V)<<(RTC_CNTL_RETENTION_DONE_WAIT_S)) 3512 #define RTC_CNTL_RETENTION_DONE_WAIT_V 0x7 3513 #define RTC_CNTL_RETENTION_DONE_WAIT_S 17 3514 /* RTC_CNTL_RETENTION_CLK_SEL : R/W ;bitpos:[16] ;default: 1'b0 ; */ 3515 /*description: .*/ 3516 #define RTC_CNTL_RETENTION_CLK_SEL (BIT(16)) 3517 #define RTC_CNTL_RETENTION_CLK_SEL_M (BIT(16)) 3518 #define RTC_CNTL_RETENTION_CLK_SEL_V 0x1 3519 #define RTC_CNTL_RETENTION_CLK_SEL_S 16 3520 /* RTC_CNTL_RETENTION_TARGET : R/W ;bitpos:[15:14] ;default: 2'b0 ; */ 3521 /*description: .*/ 3522 #define RTC_CNTL_RETENTION_TARGET 0x00000003 3523 #define RTC_CNTL_RETENTION_TARGET_M ((RTC_CNTL_RETENTION_TARGET_V)<<(RTC_CNTL_RETENTION_TARGET_S)) 3524 #define RTC_CNTL_RETENTION_TARGET_V 0x3 3525 #define RTC_CNTL_RETENTION_TARGET_S 14 3526 /* RTC_CNTL_RETENTION_TAG_MODE : R/W ;bitpos:[13:10] ;default: 4'd0 ; */ 3527 /*description: .*/ 3528 #define RTC_CNTL_RETENTION_TAG_MODE 0x0000000F 3529 #define RTC_CNTL_RETENTION_TAG_MODE_M ((RTC_CNTL_RETENTION_TAG_MODE_V)<<(RTC_CNTL_RETENTION_TAG_MODE_S)) 3530 #define RTC_CNTL_RETENTION_TAG_MODE_V 0xF 3531 #define RTC_CNTL_RETENTION_TAG_MODE_S 10 3532 3533 #define RTC_CNTL_PG_CTRL_REG (DR_REG_RTCCNTL_BASE + 0x144) 3534 /* RTC_CNTL_POWER_GLITCH_EN : R/W ;bitpos:[31] ;default: 1'b0 ; */ 3535 /*description: .*/ 3536 #define RTC_CNTL_POWER_GLITCH_EN (BIT(31)) 3537 #define RTC_CNTL_POWER_GLITCH_EN_M (BIT(31)) 3538 #define RTC_CNTL_POWER_GLITCH_EN_V 0x1 3539 #define RTC_CNTL_POWER_GLITCH_EN_S 31 3540 /* RTC_CNTL_POWER_GLITCH_EFUSE_SEL : R/W ;bitpos:[30] ;default: 1'b0 ; */ 3541 /*description: select use analog fib signal.*/ 3542 #define RTC_CNTL_POWER_GLITCH_EFUSE_SEL (BIT(30)) 3543 #define RTC_CNTL_POWER_GLITCH_EFUSE_SEL_M (BIT(30)) 3544 #define RTC_CNTL_POWER_GLITCH_EFUSE_SEL_V 0x1 3545 #define RTC_CNTL_POWER_GLITCH_EFUSE_SEL_S 30 3546 /* RTC_CNTL_POWER_GLITCH_FORCE_PU : R/W ;bitpos:[29] ;default: 1'b0 ; */ 3547 /*description: .*/ 3548 #define RTC_CNTL_POWER_GLITCH_FORCE_PU (BIT(29)) 3549 #define RTC_CNTL_POWER_GLITCH_FORCE_PU_M (BIT(29)) 3550 #define RTC_CNTL_POWER_GLITCH_FORCE_PU_V 0x1 3551 #define RTC_CNTL_POWER_GLITCH_FORCE_PU_S 29 3552 /* RTC_CNTL_POWER_GLITCH_FORCE_PD : R/W ;bitpos:[28] ;default: 1'b0 ; */ 3553 /*description: .*/ 3554 #define RTC_CNTL_POWER_GLITCH_FORCE_PD (BIT(28)) 3555 #define RTC_CNTL_POWER_GLITCH_FORCE_PD_M (BIT(28)) 3556 #define RTC_CNTL_POWER_GLITCH_FORCE_PD_V 0x1 3557 #define RTC_CNTL_POWER_GLITCH_FORCE_PD_S 28 3558 /* RTC_CNTL_POWER_GLITCH_DSENSE : R/W ;bitpos:[27:26] ;default: 2'b0 ; */ 3559 /*description: .*/ 3560 #define RTC_CNTL_POWER_GLITCH_DSENSE 0x00000003 3561 #define RTC_CNTL_POWER_GLITCH_DSENSE_M ((RTC_CNTL_POWER_GLITCH_DSENSE_V)<<(RTC_CNTL_POWER_GLITCH_DSENSE_S)) 3562 #define RTC_CNTL_POWER_GLITCH_DSENSE_V 0x3 3563 #define RTC_CNTL_POWER_GLITCH_DSENSE_S 26 3564 3565 #define RTC_CNTL_FIB_SEL_REG (DR_REG_RTCCNTL_BASE + 0x148) 3566 /* RTC_CNTL_FIB_SEL : R/W ;bitpos:[2:0] ;default: 3'd7 ; */ 3567 /*description: .*/ 3568 #define RTC_CNTL_FIB_SEL 0x00000007 3569 #define RTC_CNTL_FIB_SEL_M ((RTC_CNTL_FIB_SEL_V)<<(RTC_CNTL_FIB_SEL_S)) 3570 #define RTC_CNTL_FIB_SEL_V 0x7 3571 #define RTC_CNTL_FIB_SEL_S 0 3572 3573 #define RTC_CNTL_FIB_GLITCH_RST BIT(0) 3574 #define RTC_CNTL_FIB_BOD_RST BIT(1) 3575 #define RTC_CNTL_FIB_SUPER_WDT_RST BIT(2) 3576 3577 #define RTC_CNTL_TOUCH_DAC_REG (DR_REG_RTCCNTL_BASE + 0x14C) 3578 /* RTC_CNTL_TOUCH_PAD0_DAC : R/W ;bitpos:[31:29] ;default: 3'd0 ; */ 3579 /*description: .*/ 3580 #define RTC_CNTL_TOUCH_PAD0_DAC 0x00000007 3581 #define RTC_CNTL_TOUCH_PAD0_DAC_M ((RTC_CNTL_TOUCH_PAD0_DAC_V)<<(RTC_CNTL_TOUCH_PAD0_DAC_S)) 3582 #define RTC_CNTL_TOUCH_PAD0_DAC_V 0x7 3583 #define RTC_CNTL_TOUCH_PAD0_DAC_S 29 3584 /* RTC_CNTL_TOUCH_PAD1_DAC : R/W ;bitpos:[28:26] ;default: 3'd0 ; */ 3585 /*description: .*/ 3586 #define RTC_CNTL_TOUCH_PAD1_DAC 0x00000007 3587 #define RTC_CNTL_TOUCH_PAD1_DAC_M ((RTC_CNTL_TOUCH_PAD1_DAC_V)<<(RTC_CNTL_TOUCH_PAD1_DAC_S)) 3588 #define RTC_CNTL_TOUCH_PAD1_DAC_V 0x7 3589 #define RTC_CNTL_TOUCH_PAD1_DAC_S 26 3590 /* RTC_CNTL_TOUCH_PAD2_DAC : R/W ;bitpos:[25:23] ;default: 3'd0 ; */ 3591 /*description: .*/ 3592 #define RTC_CNTL_TOUCH_PAD2_DAC 0x00000007 3593 #define RTC_CNTL_TOUCH_PAD2_DAC_M ((RTC_CNTL_TOUCH_PAD2_DAC_V)<<(RTC_CNTL_TOUCH_PAD2_DAC_S)) 3594 #define RTC_CNTL_TOUCH_PAD2_DAC_V 0x7 3595 #define RTC_CNTL_TOUCH_PAD2_DAC_S 23 3596 /* RTC_CNTL_TOUCH_PAD3_DAC : R/W ;bitpos:[22:20] ;default: 3'd0 ; */ 3597 /*description: .*/ 3598 #define RTC_CNTL_TOUCH_PAD3_DAC 0x00000007 3599 #define RTC_CNTL_TOUCH_PAD3_DAC_M ((RTC_CNTL_TOUCH_PAD3_DAC_V)<<(RTC_CNTL_TOUCH_PAD3_DAC_S)) 3600 #define RTC_CNTL_TOUCH_PAD3_DAC_V 0x7 3601 #define RTC_CNTL_TOUCH_PAD3_DAC_S 20 3602 /* RTC_CNTL_TOUCH_PAD4_DAC : R/W ;bitpos:[19:17] ;default: 3'd0 ; */ 3603 /*description: .*/ 3604 #define RTC_CNTL_TOUCH_PAD4_DAC 0x00000007 3605 #define RTC_CNTL_TOUCH_PAD4_DAC_M ((RTC_CNTL_TOUCH_PAD4_DAC_V)<<(RTC_CNTL_TOUCH_PAD4_DAC_S)) 3606 #define RTC_CNTL_TOUCH_PAD4_DAC_V 0x7 3607 #define RTC_CNTL_TOUCH_PAD4_DAC_S 17 3608 /* RTC_CNTL_TOUCH_PAD5_DAC : R/W ;bitpos:[16:14] ;default: 3'd0 ; */ 3609 /*description: .*/ 3610 #define RTC_CNTL_TOUCH_PAD5_DAC 0x00000007 3611 #define RTC_CNTL_TOUCH_PAD5_DAC_M ((RTC_CNTL_TOUCH_PAD5_DAC_V)<<(RTC_CNTL_TOUCH_PAD5_DAC_S)) 3612 #define RTC_CNTL_TOUCH_PAD5_DAC_V 0x7 3613 #define RTC_CNTL_TOUCH_PAD5_DAC_S 14 3614 /* RTC_CNTL_TOUCH_PAD6_DAC : R/W ;bitpos:[13:11] ;default: 3'd0 ; */ 3615 /*description: .*/ 3616 #define RTC_CNTL_TOUCH_PAD6_DAC 0x00000007 3617 #define RTC_CNTL_TOUCH_PAD6_DAC_M ((RTC_CNTL_TOUCH_PAD6_DAC_V)<<(RTC_CNTL_TOUCH_PAD6_DAC_S)) 3618 #define RTC_CNTL_TOUCH_PAD6_DAC_V 0x7 3619 #define RTC_CNTL_TOUCH_PAD6_DAC_S 11 3620 /* RTC_CNTL_TOUCH_PAD7_DAC : R/W ;bitpos:[10:8] ;default: 3'd0 ; */ 3621 /*description: .*/ 3622 #define RTC_CNTL_TOUCH_PAD7_DAC 0x00000007 3623 #define RTC_CNTL_TOUCH_PAD7_DAC_M ((RTC_CNTL_TOUCH_PAD7_DAC_V)<<(RTC_CNTL_TOUCH_PAD7_DAC_S)) 3624 #define RTC_CNTL_TOUCH_PAD7_DAC_V 0x7 3625 #define RTC_CNTL_TOUCH_PAD7_DAC_S 8 3626 /* RTC_CNTL_TOUCH_PAD8_DAC : R/W ;bitpos:[7:5] ;default: 3'd0 ; */ 3627 /*description: .*/ 3628 #define RTC_CNTL_TOUCH_PAD8_DAC 0x00000007 3629 #define RTC_CNTL_TOUCH_PAD8_DAC_M ((RTC_CNTL_TOUCH_PAD8_DAC_V)<<(RTC_CNTL_TOUCH_PAD8_DAC_S)) 3630 #define RTC_CNTL_TOUCH_PAD8_DAC_V 0x7 3631 #define RTC_CNTL_TOUCH_PAD8_DAC_S 5 3632 /* RTC_CNTL_TOUCH_PAD9_DAC : R/W ;bitpos:[4:2] ;default: 3'd0 ; */ 3633 /*description: .*/ 3634 #define RTC_CNTL_TOUCH_PAD9_DAC 0x00000007 3635 #define RTC_CNTL_TOUCH_PAD9_DAC_M ((RTC_CNTL_TOUCH_PAD9_DAC_V)<<(RTC_CNTL_TOUCH_PAD9_DAC_S)) 3636 #define RTC_CNTL_TOUCH_PAD9_DAC_V 0x7 3637 #define RTC_CNTL_TOUCH_PAD9_DAC_S 2 3638 3639 #define RTC_CNTL_TOUCH_DAC1_REG (DR_REG_RTCCNTL_BASE + 0x150) 3640 /* RTC_CNTL_TOUCH_PAD10_DAC : R/W ;bitpos:[31:29] ;default: 3'd0 ; */ 3641 /*description: .*/ 3642 #define RTC_CNTL_TOUCH_PAD10_DAC 0x00000007 3643 #define RTC_CNTL_TOUCH_PAD10_DAC_M ((RTC_CNTL_TOUCH_PAD10_DAC_V)<<(RTC_CNTL_TOUCH_PAD10_DAC_S)) 3644 #define RTC_CNTL_TOUCH_PAD10_DAC_V 0x7 3645 #define RTC_CNTL_TOUCH_PAD10_DAC_S 29 3646 /* RTC_CNTL_TOUCH_PAD11_DAC : R/W ;bitpos:[28:26] ;default: 3'd0 ; */ 3647 /*description: .*/ 3648 #define RTC_CNTL_TOUCH_PAD11_DAC 0x00000007 3649 #define RTC_CNTL_TOUCH_PAD11_DAC_M ((RTC_CNTL_TOUCH_PAD11_DAC_V)<<(RTC_CNTL_TOUCH_PAD11_DAC_S)) 3650 #define RTC_CNTL_TOUCH_PAD11_DAC_V 0x7 3651 #define RTC_CNTL_TOUCH_PAD11_DAC_S 26 3652 /* RTC_CNTL_TOUCH_PAD12_DAC : R/W ;bitpos:[25:23] ;default: 3'd0 ; */ 3653 /*description: .*/ 3654 #define RTC_CNTL_TOUCH_PAD12_DAC 0x00000007 3655 #define RTC_CNTL_TOUCH_PAD12_DAC_M ((RTC_CNTL_TOUCH_PAD12_DAC_V)<<(RTC_CNTL_TOUCH_PAD12_DAC_S)) 3656 #define RTC_CNTL_TOUCH_PAD12_DAC_V 0x7 3657 #define RTC_CNTL_TOUCH_PAD12_DAC_S 23 3658 /* RTC_CNTL_TOUCH_PAD13_DAC : R/W ;bitpos:[22:20] ;default: 3'd0 ; */ 3659 /*description: .*/ 3660 #define RTC_CNTL_TOUCH_PAD13_DAC 0x00000007 3661 #define RTC_CNTL_TOUCH_PAD13_DAC_M ((RTC_CNTL_TOUCH_PAD13_DAC_V)<<(RTC_CNTL_TOUCH_PAD13_DAC_S)) 3662 #define RTC_CNTL_TOUCH_PAD13_DAC_V 0x7 3663 #define RTC_CNTL_TOUCH_PAD13_DAC_S 20 3664 /* RTC_CNTL_TOUCH_PAD14_DAC : R/W ;bitpos:[19:17] ;default: 3'd0 ; */ 3665 /*description: .*/ 3666 #define RTC_CNTL_TOUCH_PAD14_DAC 0x00000007 3667 #define RTC_CNTL_TOUCH_PAD14_DAC_M ((RTC_CNTL_TOUCH_PAD14_DAC_V)<<(RTC_CNTL_TOUCH_PAD14_DAC_S)) 3668 #define RTC_CNTL_TOUCH_PAD14_DAC_V 0x7 3669 #define RTC_CNTL_TOUCH_PAD14_DAC_S 17 3670 3671 #define RTC_CNTL_COCPU_DISABLE_REG (DR_REG_RTCCNTL_BASE + 0x154) 3672 /* RTC_CNTL_DISABLE_RTC_CPU : R/W ;bitpos:[31] ;default: 1'b0 ; */ 3673 /*description: .*/ 3674 #define RTC_CNTL_DISABLE_RTC_CPU (BIT(31)) 3675 #define RTC_CNTL_DISABLE_RTC_CPU_M (BIT(31)) 3676 #define RTC_CNTL_DISABLE_RTC_CPU_V 0x1 3677 #define RTC_CNTL_DISABLE_RTC_CPU_S 31 3678 3679 /* 3680 Due to the LDO slaves, RTC_CNTL_DATE_REG[18:13] can only be used for LDO adjustment. 3681 */ 3682 #define RTC_CNTL_DATE_REG (DR_REG_RTCCNTL_BASE + 0x1FC) 3683 /* RTC_CNTL_DATE : R/W ;bitpos:[27:0] ;default: 28'h2101271 ; */ 3684 /*description: .*/ 3685 #define RTC_CNTL_DATE 0x0FFFFFFF 3686 #define RTC_CNTL_DATE_M ((RTC_CNTL_DATE_V)<<(RTC_CNTL_DATE_S)) 3687 #define RTC_CNTL_DATE_V 0xFFFFFFF 3688 #define RTC_CNTL_DATE_S 0 3689 /*LDO SLAVE : R/W ;bitpos:[18:13] ; default: 6'd0 ;*/ 3690 /*description: .*/ 3691 #define RTC_CNTL_SLAVE_PD 0x0000003F 3692 #define RTC_CNTL_SLAVE_PD_M ((RTC_CNTL_SLAVE_PD_V)<<(RTC_CNTL_SLAVE_PD_S)) 3693 #define RTC_CNTL_SLAVE_PD_V 0x3F 3694 #define RTC_CNTL_SLAVE_PD_S 13 3695 3696 #ifdef __cplusplus 3697 } 3698 #endif 3699 3700 3701 3702 #endif /*_SOC_RTC_CNTL_REG_H_ */ 3703
