1 /* 2 * SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 #ifndef _SOC_RTC_CNTL_REG_H_ 7 #define _SOC_RTC_CNTL_REG_H_ 8 9 /* The value that needs to be written to RTC_CNTL_WDT_WKEY to write-enable the wdt registers */ 10 #define RTC_CNTL_WDT_WKEY_VALUE 0x50D83AA1 11 /* The value that needs to be written to RTC_CNTL_SWD_WPROTECT_REG to write-enable the wdt registers */ 12 #define RTC_CNTL_SWD_WKEY_VALUE 0x8F1D312A 13 14 /* Possible values for RTC_CNTL_WDT_CPU_RESET_LENGTH and RTC_CNTL_WDT_SYS_RESET_LENGTH */ 15 #define RTC_WDT_RESET_LENGTH_100_NS 0 16 #define RTC_WDT_RESET_LENGTH_200_NS 1 17 #define RTC_WDT_RESET_LENGTH_300_NS 2 18 #define RTC_WDT_RESET_LENGTH_400_NS 3 19 #define RTC_WDT_RESET_LENGTH_500_NS 4 20 #define RTC_WDT_RESET_LENGTH_800_NS 5 21 #define RTC_WDT_RESET_LENGTH_1600_NS 6 22 #define RTC_WDT_RESET_LENGTH_3200_NS 7 23 24 25 #ifdef __cplusplus 26 extern "C" { 27 #endif 28 #include "soc.h" 29 #define RTC_CNTL_TIME0_REG RTC_CNTL_TIME_LOW0_REG 30 #define RTC_CNTL_TIME1_REG RTC_CNTL_TIME_HIGH0_REG 31 32 #define RTC_CNTL_OPTIONS0_REG (DR_REG_RTCCNTL_BASE + 0x0000) 33 /* RTC_CNTL_SW_SYS_RST : WO ;bitpos:[31] ;default: 1'd0 ; */ 34 /*description: SW system reset*/ 35 #define RTC_CNTL_SW_SYS_RST (BIT(31)) 36 #define RTC_CNTL_SW_SYS_RST_M (BIT(31)) 37 #define RTC_CNTL_SW_SYS_RST_V 0x1 38 #define RTC_CNTL_SW_SYS_RST_S 31 39 /* RTC_CNTL_DG_WRAP_FORCE_NORST : R/W ;bitpos:[30] ;default: 1'd0 ; */ 40 /*description: digital core force no reset in deep sleep*/ 41 #define RTC_CNTL_DG_WRAP_FORCE_NORST (BIT(30)) 42 #define RTC_CNTL_DG_WRAP_FORCE_NORST_M (BIT(30)) 43 #define RTC_CNTL_DG_WRAP_FORCE_NORST_V 0x1 44 #define RTC_CNTL_DG_WRAP_FORCE_NORST_S 30 45 /* RTC_CNTL_DG_WRAP_FORCE_RST : R/W ;bitpos:[29] ;default: 1'd0 ; */ 46 /*description: digital wrap force reset in deep sleep*/ 47 #define RTC_CNTL_DG_WRAP_FORCE_RST (BIT(29)) 48 #define RTC_CNTL_DG_WRAP_FORCE_RST_M (BIT(29)) 49 #define RTC_CNTL_DG_WRAP_FORCE_RST_V 0x1 50 #define RTC_CNTL_DG_WRAP_FORCE_RST_S 29 51 /* RTC_CNTL_ANALOG_FORCE_NOISO : R/W ;bitpos:[28] ;default: 1'd1 ; */ 52 /*description: */ 53 #define RTC_CNTL_ANALOG_FORCE_NOISO (BIT(28)) 54 #define RTC_CNTL_ANALOG_FORCE_NOISO_M (BIT(28)) 55 #define RTC_CNTL_ANALOG_FORCE_NOISO_V 0x1 56 #define RTC_CNTL_ANALOG_FORCE_NOISO_S 28 57 /* RTC_CNTL_PLL_FORCE_NOISO : R/W ;bitpos:[27] ;default: 1'd1 ; */ 58 /*description: */ 59 #define RTC_CNTL_PLL_FORCE_NOISO (BIT(27)) 60 #define RTC_CNTL_PLL_FORCE_NOISO_M (BIT(27)) 61 #define RTC_CNTL_PLL_FORCE_NOISO_V 0x1 62 #define RTC_CNTL_PLL_FORCE_NOISO_S 27 63 /* RTC_CNTL_XTL_FORCE_NOISO : R/W ;bitpos:[26] ;default: 1'd1 ; */ 64 /*description: */ 65 #define RTC_CNTL_XTL_FORCE_NOISO (BIT(26)) 66 #define RTC_CNTL_XTL_FORCE_NOISO_M (BIT(26)) 67 #define RTC_CNTL_XTL_FORCE_NOISO_V 0x1 68 #define RTC_CNTL_XTL_FORCE_NOISO_S 26 69 /* RTC_CNTL_ANALOG_FORCE_ISO : R/W ;bitpos:[25] ;default: 1'd0 ; */ 70 /*description: */ 71 #define RTC_CNTL_ANALOG_FORCE_ISO (BIT(25)) 72 #define RTC_CNTL_ANALOG_FORCE_ISO_M (BIT(25)) 73 #define RTC_CNTL_ANALOG_FORCE_ISO_V 0x1 74 #define RTC_CNTL_ANALOG_FORCE_ISO_S 25 75 /* RTC_CNTL_PLL_FORCE_ISO : R/W ;bitpos:[24] ;default: 1'd0 ; */ 76 /*description: */ 77 #define RTC_CNTL_PLL_FORCE_ISO (BIT(24)) 78 #define RTC_CNTL_PLL_FORCE_ISO_M (BIT(24)) 79 #define RTC_CNTL_PLL_FORCE_ISO_V 0x1 80 #define RTC_CNTL_PLL_FORCE_ISO_S 24 81 /* RTC_CNTL_XTL_FORCE_ISO : R/W ;bitpos:[23] ;default: 1'd0 ; */ 82 /*description: */ 83 #define RTC_CNTL_XTL_FORCE_ISO (BIT(23)) 84 #define RTC_CNTL_XTL_FORCE_ISO_M (BIT(23)) 85 #define RTC_CNTL_XTL_FORCE_ISO_V 0x1 86 #define RTC_CNTL_XTL_FORCE_ISO_S 23 87 /* RTC_CNTL_XTL_EXT_CTR_SEL : R/W ;bitpos:[22:20] ;default: 3'd0 ; */ 88 /*description: */ 89 #define RTC_CNTL_XTL_EXT_CTR_SEL 0x00000007 90 #define RTC_CNTL_XTL_EXT_CTR_SEL_M ((RTC_CNTL_XTL_EXT_CTR_SEL_V)<<(RTC_CNTL_XTL_EXT_CTR_SEL_S)) 91 #define RTC_CNTL_XTL_EXT_CTR_SEL_V 0x7 92 #define RTC_CNTL_XTL_EXT_CTR_SEL_S 20 93 /* RTC_CNTL_XTL_EN_WAIT : R/W ;bitpos:[17:14] ;default: 4'd2 ; */ 94 /*description: wait bias_sleep and current source wakeup*/ 95 #define RTC_CNTL_XTL_EN_WAIT 0x0000000F 96 #define RTC_CNTL_XTL_EN_WAIT_M ((RTC_CNTL_XTL_EN_WAIT_V)<<(RTC_CNTL_XTL_EN_WAIT_S)) 97 #define RTC_CNTL_XTL_EN_WAIT_V 0xF 98 #define RTC_CNTL_XTL_EN_WAIT_S 14 99 /* RTC_CNTL_XTL_FORCE_PU : R/W ;bitpos:[13] ;default: 1'd1 ; */ 100 /*description: crystall force power up*/ 101 #define RTC_CNTL_XTL_FORCE_PU (BIT(13)) 102 #define RTC_CNTL_XTL_FORCE_PU_M (BIT(13)) 103 #define RTC_CNTL_XTL_FORCE_PU_V 0x1 104 #define RTC_CNTL_XTL_FORCE_PU_S 13 105 /* RTC_CNTL_XTL_FORCE_PD : R/W ;bitpos:[12] ;default: 1'b0 ; */ 106 /*description: crystall force power down*/ 107 #define RTC_CNTL_XTL_FORCE_PD (BIT(12)) 108 #define RTC_CNTL_XTL_FORCE_PD_M (BIT(12)) 109 #define RTC_CNTL_XTL_FORCE_PD_V 0x1 110 #define RTC_CNTL_XTL_FORCE_PD_S 12 111 /* RTC_CNTL_BBPLL_FORCE_PU : R/W ;bitpos:[11] ;default: 1'd0 ; */ 112 /*description: BB_PLL force power up*/ 113 #define RTC_CNTL_BBPLL_FORCE_PU (BIT(11)) 114 #define RTC_CNTL_BBPLL_FORCE_PU_M (BIT(11)) 115 #define RTC_CNTL_BBPLL_FORCE_PU_V 0x1 116 #define RTC_CNTL_BBPLL_FORCE_PU_S 11 117 /* RTC_CNTL_BBPLL_FORCE_PD : R/W ;bitpos:[10] ;default: 1'b0 ; */ 118 /*description: BB_PLL force power down*/ 119 #define RTC_CNTL_BBPLL_FORCE_PD (BIT(10)) 120 #define RTC_CNTL_BBPLL_FORCE_PD_M (BIT(10)) 121 #define RTC_CNTL_BBPLL_FORCE_PD_V 0x1 122 #define RTC_CNTL_BBPLL_FORCE_PD_S 10 123 /* RTC_CNTL_BBPLL_I2C_FORCE_PU : R/W ;bitpos:[9] ;default: 1'd0 ; */ 124 /*description: BB_PLL_I2C force power up*/ 125 #define RTC_CNTL_BBPLL_I2C_FORCE_PU (BIT(9)) 126 #define RTC_CNTL_BBPLL_I2C_FORCE_PU_M (BIT(9)) 127 #define RTC_CNTL_BBPLL_I2C_FORCE_PU_V 0x1 128 #define RTC_CNTL_BBPLL_I2C_FORCE_PU_S 9 129 /* RTC_CNTL_BBPLL_I2C_FORCE_PD : R/W ;bitpos:[8] ;default: 1'b0 ; */ 130 /*description: BB_PLL _I2C force power down*/ 131 #define RTC_CNTL_BBPLL_I2C_FORCE_PD (BIT(8)) 132 #define RTC_CNTL_BBPLL_I2C_FORCE_PD_M (BIT(8)) 133 #define RTC_CNTL_BBPLL_I2C_FORCE_PD_V 0x1 134 #define RTC_CNTL_BBPLL_I2C_FORCE_PD_S 8 135 /* RTC_CNTL_BB_I2C_FORCE_PU : R/W ;bitpos:[7] ;default: 1'd0 ; */ 136 /*description: BB_I2C force power up*/ 137 #define RTC_CNTL_BB_I2C_FORCE_PU (BIT(7)) 138 #define RTC_CNTL_BB_I2C_FORCE_PU_M (BIT(7)) 139 #define RTC_CNTL_BB_I2C_FORCE_PU_V 0x1 140 #define RTC_CNTL_BB_I2C_FORCE_PU_S 7 141 /* RTC_CNTL_BB_I2C_FORCE_PD : R/W ;bitpos:[6] ;default: 1'b0 ; */ 142 /*description: BB_I2C force power down*/ 143 #define RTC_CNTL_BB_I2C_FORCE_PD (BIT(6)) 144 #define RTC_CNTL_BB_I2C_FORCE_PD_M (BIT(6)) 145 #define RTC_CNTL_BB_I2C_FORCE_PD_V 0x1 146 #define RTC_CNTL_BB_I2C_FORCE_PD_S 6 147 /* RTC_CNTL_SW_PROCPU_RST : WO ;bitpos:[5] ;default: 1'b0 ; */ 148 /*description: PRO CPU SW reset*/ 149 #define RTC_CNTL_SW_PROCPU_RST (BIT(5)) 150 #define RTC_CNTL_SW_PROCPU_RST_M (BIT(5)) 151 #define RTC_CNTL_SW_PROCPU_RST_V 0x1 152 #define RTC_CNTL_SW_PROCPU_RST_S 5 153 /* RTC_CNTL_SW_APPCPU_RST : WO ;bitpos:[4] ;default: 1'b0 ; */ 154 /*description: APP CPU SW reset*/ 155 #define RTC_CNTL_SW_APPCPU_RST (BIT(4)) 156 #define RTC_CNTL_SW_APPCPU_RST_M (BIT(4)) 157 #define RTC_CNTL_SW_APPCPU_RST_V 0x1 158 #define RTC_CNTL_SW_APPCPU_RST_S 4 159 /* RTC_CNTL_SW_STALL_PROCPU_C0 : R/W ;bitpos:[3:2] ;default: 2'b0 ; */ 160 /*description: {reg_sw_stall_procpu_c1[5:0] reg_sw_stall_procpu_c0[1:0]} == 161 0x86 will stall PRO CPU*/ 162 #define RTC_CNTL_SW_STALL_PROCPU_C0 0x00000003 163 #define RTC_CNTL_SW_STALL_PROCPU_C0_M ((RTC_CNTL_SW_STALL_PROCPU_C0_V)<<(RTC_CNTL_SW_STALL_PROCPU_C0_S)) 164 #define RTC_CNTL_SW_STALL_PROCPU_C0_V 0x3 165 #define RTC_CNTL_SW_STALL_PROCPU_C0_S 2 166 /* RTC_CNTL_SW_STALL_APPCPU_C0 : R/W ;bitpos:[1:0] ;default: 2'b0 ; */ 167 /*description: {reg_sw_stall_appcpu_c1[5:0] reg_sw_stall_appcpu_c0[1:0]} == 168 0x86 will stall APP CPU*/ 169 #define RTC_CNTL_SW_STALL_APPCPU_C0 0x00000003 170 #define RTC_CNTL_SW_STALL_APPCPU_C0_M ((RTC_CNTL_SW_STALL_APPCPU_C0_V)<<(RTC_CNTL_SW_STALL_APPCPU_C0_S)) 171 #define RTC_CNTL_SW_STALL_APPCPU_C0_V 0x3 172 #define RTC_CNTL_SW_STALL_APPCPU_C0_S 0 173 174 #define RTC_CNTL_SLP_TIMER0_REG (DR_REG_RTCCNTL_BASE + 0x0004) 175 /* RTC_CNTL_SLP_VAL_LO : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ 176 /*description: */ 177 #define RTC_CNTL_SLP_VAL_LO 0xFFFFFFFF 178 #define RTC_CNTL_SLP_VAL_LO_M ((RTC_CNTL_SLP_VAL_LO_V)<<(RTC_CNTL_SLP_VAL_LO_S)) 179 #define RTC_CNTL_SLP_VAL_LO_V 0xFFFFFFFF 180 #define RTC_CNTL_SLP_VAL_LO_S 0 181 182 #define RTC_CNTL_SLP_TIMER1_REG (DR_REG_RTCCNTL_BASE + 0x0008) 183 /* RTC_CNTL_MAIN_TIMER_ALARM_EN : WO ;bitpos:[16] ;default: 1'h0 ; */ 184 /*description: timer alarm enable bit*/ 185 #define RTC_CNTL_MAIN_TIMER_ALARM_EN (BIT(16)) 186 #define RTC_CNTL_MAIN_TIMER_ALARM_EN_M (BIT(16)) 187 #define RTC_CNTL_MAIN_TIMER_ALARM_EN_V 0x1 188 #define RTC_CNTL_MAIN_TIMER_ALARM_EN_S 16 189 /* RTC_CNTL_SLP_VAL_HI : R/W ;bitpos:[15:0] ;default: 16'h0 ; */ 190 /*description: RTC sleep timer high 16 bits*/ 191 #define RTC_CNTL_SLP_VAL_HI 0x0000FFFF 192 #define RTC_CNTL_SLP_VAL_HI_M ((RTC_CNTL_SLP_VAL_HI_V)<<(RTC_CNTL_SLP_VAL_HI_S)) 193 #define RTC_CNTL_SLP_VAL_HI_V 0xFFFF 194 #define RTC_CNTL_SLP_VAL_HI_S 0 195 196 #define RTC_CNTL_TIME_UPDATE_REG (DR_REG_RTCCNTL_BASE + 0x000C) 197 /* RTC_CNTL_TIME_UPDATE : WO ;bitpos:[31] ;default: 1'h0 ; */ 198 /*description: Set 1: to update register with RTC timer*/ 199 #define RTC_CNTL_TIME_UPDATE (BIT(31)) 200 #define RTC_CNTL_TIME_UPDATE_M (BIT(31)) 201 #define RTC_CNTL_TIME_UPDATE_V 0x1 202 #define RTC_CNTL_TIME_UPDATE_S 31 203 /* RTC_CNTL_TIMER_SYS_RST : R/W ;bitpos:[29] ;default: 1'b0 ; */ 204 /*description: enable to record system reset time*/ 205 #define RTC_CNTL_TIMER_SYS_RST (BIT(29)) 206 #define RTC_CNTL_TIMER_SYS_RST_M (BIT(29)) 207 #define RTC_CNTL_TIMER_SYS_RST_V 0x1 208 #define RTC_CNTL_TIMER_SYS_RST_S 29 209 /* RTC_CNTL_TIMER_XTL_OFF : R/W ;bitpos:[28] ;default: 1'b0 ; */ 210 /*description: Enable to record 40M XTAL OFF time*/ 211 #define RTC_CNTL_TIMER_XTL_OFF (BIT(28)) 212 #define RTC_CNTL_TIMER_XTL_OFF_M (BIT(28)) 213 #define RTC_CNTL_TIMER_XTL_OFF_V 0x1 214 #define RTC_CNTL_TIMER_XTL_OFF_S 28 215 /* RTC_CNTL_TIMER_SYS_STALL : R/W ;bitpos:[27] ;default: 1'b0 ; */ 216 /*description: Enable to record system stall time*/ 217 #define RTC_CNTL_TIMER_SYS_STALL (BIT(27)) 218 #define RTC_CNTL_TIMER_SYS_STALL_M (BIT(27)) 219 #define RTC_CNTL_TIMER_SYS_STALL_V 0x1 220 #define RTC_CNTL_TIMER_SYS_STALL_S 27 221 222 #define RTC_CNTL_TIME_LOW0_REG (DR_REG_RTCCNTL_BASE + 0x0010) 223 /* RTC_CNTL_TIMER_VALUE0_LOW : RO ;bitpos:[31:0] ;default: 32'h0 ; */ 224 /*description: RTC timer low 32 bits*/ 225 #define RTC_CNTL_TIMER_VALUE0_LOW 0xFFFFFFFF 226 #define RTC_CNTL_TIMER_VALUE0_LOW_M ((RTC_CNTL_TIMER_VALUE0_LOW_V)<<(RTC_CNTL_TIMER_VALUE0_LOW_S)) 227 #define RTC_CNTL_TIMER_VALUE0_LOW_V 0xFFFFFFFF 228 #define RTC_CNTL_TIMER_VALUE0_LOW_S 0 229 230 #define RTC_CNTL_TIME_HIGH0_REG (DR_REG_RTCCNTL_BASE + 0x0014) 231 /* RTC_CNTL_TIMER_VALUE0_HIGH : RO ;bitpos:[15:0] ;default: 16'h0 ; */ 232 /*description: RTC timer high 16 bits*/ 233 #define RTC_CNTL_TIMER_VALUE0_HIGH 0x0000FFFF 234 #define RTC_CNTL_TIMER_VALUE0_HIGH_M ((RTC_CNTL_TIMER_VALUE0_HIGH_V)<<(RTC_CNTL_TIMER_VALUE0_HIGH_S)) 235 #define RTC_CNTL_TIMER_VALUE0_HIGH_V 0xFFFF 236 #define RTC_CNTL_TIMER_VALUE0_HIGH_S 0 237 238 #define RTC_CNTL_STATE0_REG (DR_REG_RTCCNTL_BASE + 0x0018) 239 /* RTC_CNTL_SLEEP_EN : R/W ;bitpos:[31] ;default: 1'd0 ; */ 240 /*description: sleep enable bit*/ 241 #define RTC_CNTL_SLEEP_EN (BIT(31)) 242 #define RTC_CNTL_SLEEP_EN_M (BIT(31)) 243 #define RTC_CNTL_SLEEP_EN_V 0x1 244 #define RTC_CNTL_SLEEP_EN_S 31 245 /* RTC_CNTL_SLP_REJECT : R/W ;bitpos:[30] ;default: 1'd0 ; */ 246 /*description: leep reject bit*/ 247 #define RTC_CNTL_SLP_REJECT (BIT(30)) 248 #define RTC_CNTL_SLP_REJECT_M (BIT(30)) 249 #define RTC_CNTL_SLP_REJECT_V 0x1 250 #define RTC_CNTL_SLP_REJECT_S 30 251 /* RTC_CNTL_SLP_WAKEUP : R/W ;bitpos:[29] ;default: 1'd0 ; */ 252 /*description: leep wakeup bit*/ 253 #define RTC_CNTL_SLP_WAKEUP (BIT(29)) 254 #define RTC_CNTL_SLP_WAKEUP_M (BIT(29)) 255 #define RTC_CNTL_SLP_WAKEUP_V 0x1 256 #define RTC_CNTL_SLP_WAKEUP_S 29 257 /* RTC_CNTL_SDIO_ACTIVE_IND : RO ;bitpos:[28] ;default: 1'd0 ; */ 258 /*description: SDIO active indication*/ 259 #define RTC_CNTL_SDIO_ACTIVE_IND (BIT(28)) 260 #define RTC_CNTL_SDIO_ACTIVE_IND_M (BIT(28)) 261 #define RTC_CNTL_SDIO_ACTIVE_IND_V 0x1 262 #define RTC_CNTL_SDIO_ACTIVE_IND_S 28 263 /* RTC_CNTL_APB2RTC_BRIDGE_SEL : R/W ;bitpos:[22] ;default: 1'd0 ; */ 264 /*description: 1: APB to RTC using bridge*/ 265 #define RTC_CNTL_APB2RTC_BRIDGE_SEL (BIT(22)) 266 #define RTC_CNTL_APB2RTC_BRIDGE_SEL_M (BIT(22)) 267 #define RTC_CNTL_APB2RTC_BRIDGE_SEL_V 0x1 268 #define RTC_CNTL_APB2RTC_BRIDGE_SEL_S 22 269 /* RTC_CNTL_SLP_REJECT_CAUSE_CLR : WO ;bitpos:[1] ;default: 1'b0 ; */ 270 /*description: clear rtc sleep reject cause*/ 271 #define RTC_CNTL_SLP_REJECT_CAUSE_CLR (BIT(1)) 272 #define RTC_CNTL_SLP_REJECT_CAUSE_CLR_M (BIT(1)) 273 #define RTC_CNTL_SLP_REJECT_CAUSE_CLR_V 0x1 274 #define RTC_CNTL_SLP_REJECT_CAUSE_CLR_S 1 275 /* RTC_CNTL_SW_CPU_INT : WO ;bitpos:[0] ;default: 1'b0 ; */ 276 /*description: rtc software interrupt to main cpu*/ 277 #define RTC_CNTL_SW_CPU_INT (BIT(0)) 278 #define RTC_CNTL_SW_CPU_INT_M (BIT(0)) 279 #define RTC_CNTL_SW_CPU_INT_V 0x1 280 #define RTC_CNTL_SW_CPU_INT_S 0 281 282 #define RTC_CNTL_TIMER1_REG (DR_REG_RTCCNTL_BASE + 0x001C) 283 /* RTC_CNTL_PLL_BUF_WAIT : R/W ;bitpos:[31:24] ;default: 8'd40 ; */ 284 /*description: PLL wait cycles in slow_clk_rtc*/ 285 #define RTC_CNTL_PLL_BUF_WAIT 0x000000FF 286 #define RTC_CNTL_PLL_BUF_WAIT_M ((RTC_CNTL_PLL_BUF_WAIT_V)<<(RTC_CNTL_PLL_BUF_WAIT_S)) 287 #define RTC_CNTL_PLL_BUF_WAIT_V 0xFF 288 #define RTC_CNTL_PLL_BUF_WAIT_S 24 289 #define RTC_CNTL_PLL_BUF_WAIT_DEFAULT 20 290 /* RTC_CNTL_XTL_BUF_WAIT : R/W ;bitpos:[23:14] ;default: 10'd80 ; */ 291 /*description: XTAL wait cycles in slow_clk_rtc*/ 292 #define RTC_CNTL_XTL_BUF_WAIT 0x000003FF 293 #define RTC_CNTL_XTL_BUF_WAIT_M ((RTC_CNTL_XTL_BUF_WAIT_V)<<(RTC_CNTL_XTL_BUF_WAIT_S)) 294 #define RTC_CNTL_XTL_BUF_WAIT_V 0x3FF 295 #define RTC_CNTL_XTL_BUF_WAIT_S 14 296 #define RTC_CNTL_XTL_BUF_WAIT_DEFAULT 100 297 /* RTC_CNTL_CK8M_WAIT : R/W ;bitpos:[13:6] ;default: 8'h10 ; */ 298 /*description: CK8M wait cycles in slow_clk_rtc*/ 299 #define RTC_CNTL_CK8M_WAIT 0x000000FF 300 #define RTC_CNTL_CK8M_WAIT_M ((RTC_CNTL_CK8M_WAIT_V)<<(RTC_CNTL_CK8M_WAIT_S)) 301 #define RTC_CNTL_CK8M_WAIT_V 0xFF 302 #define RTC_CNTL_CK8M_WAIT_S 6 303 /* RTC_CNTL_CPU_STALL_WAIT : R/W ;bitpos:[5:1] ;default: 5'd1 ; */ 304 /*description: CPU stall wait cycles in fast_clk_rtc*/ 305 #define RTC_CNTL_CPU_STALL_WAIT 0x0000001F 306 #define RTC_CNTL_CPU_STALL_WAIT_M ((RTC_CNTL_CPU_STALL_WAIT_V)<<(RTC_CNTL_CPU_STALL_WAIT_S)) 307 #define RTC_CNTL_CPU_STALL_WAIT_V 0x1F 308 #define RTC_CNTL_CPU_STALL_WAIT_S 1 309 /* RTC_CNTL_CPU_STALL_EN : R/W ;bitpos:[0] ;default: 1'd1 ; */ 310 /*description: CPU stall enable bit*/ 311 #define RTC_CNTL_CPU_STALL_EN (BIT(0)) 312 #define RTC_CNTL_CPU_STALL_EN_M (BIT(0)) 313 #define RTC_CNTL_CPU_STALL_EN_V 0x1 314 #define RTC_CNTL_CPU_STALL_EN_S 0 315 316 #define RTC_CNTL_TIMER2_REG (DR_REG_RTCCNTL_BASE + 0x0020) 317 /* RTC_CNTL_MIN_TIME_CK8M_OFF : R/W ;bitpos:[31:24] ;default: 8'h1 ; */ 318 /*description: minimal cycles in slow_clk_rtc for CK8M in power down state*/ 319 #define RTC_CNTL_MIN_TIME_CK8M_OFF 0x000000FF 320 #define RTC_CNTL_MIN_TIME_CK8M_OFF_M ((RTC_CNTL_MIN_TIME_CK8M_OFF_V)<<(RTC_CNTL_MIN_TIME_CK8M_OFF_S)) 321 #define RTC_CNTL_MIN_TIME_CK8M_OFF_V 0xFF 322 #define RTC_CNTL_MIN_TIME_CK8M_OFF_S 24 323 324 #define RTC_CNTL_TIMER3_REG (DR_REG_RTCCNTL_BASE + 0x0024) 325 /* RTC_CNTL_BT_POWERUP_TIMER : R/W ;bitpos:[31:25] ;default: 7'h5 ; */ 326 /*description: */ 327 #define RTC_CNTL_BT_POWERUP_TIMER 0x0000007F 328 #define RTC_CNTL_BT_POWERUP_TIMER_M ((RTC_CNTL_BT_POWERUP_TIMER_V)<<(RTC_CNTL_BT_POWERUP_TIMER_S)) 329 #define RTC_CNTL_BT_POWERUP_TIMER_V 0x7F 330 #define RTC_CNTL_BT_POWERUP_TIMER_S 25 331 /* RTC_CNTL_BT_WAIT_TIMER : R/W ;bitpos:[24:16] ;default: 9'h8 ; */ 332 /*description: */ 333 #define RTC_CNTL_BT_WAIT_TIMER 0x000001FF 334 #define RTC_CNTL_BT_WAIT_TIMER_M ((RTC_CNTL_BT_WAIT_TIMER_V)<<(RTC_CNTL_BT_WAIT_TIMER_S)) 335 #define RTC_CNTL_BT_WAIT_TIMER_V 0x1FF 336 #define RTC_CNTL_BT_WAIT_TIMER_S 16 337 /* RTC_CNTL_WIFI_POWERUP_TIMER : R/W ;bitpos:[15:9] ;default: 7'h5 ; */ 338 /*description: */ 339 #define RTC_CNTL_WIFI_POWERUP_TIMER 0x0000007F 340 #define RTC_CNTL_WIFI_POWERUP_TIMER_M ((RTC_CNTL_WIFI_POWERUP_TIMER_V)<<(RTC_CNTL_WIFI_POWERUP_TIMER_S)) 341 #define RTC_CNTL_WIFI_POWERUP_TIMER_V 0x7F 342 #define RTC_CNTL_WIFI_POWERUP_TIMER_S 9 343 /* RTC_CNTL_WIFI_WAIT_TIMER : R/W ;bitpos:[8:0] ;default: 9'h8 ; */ 344 /*description: */ 345 #define RTC_CNTL_WIFI_WAIT_TIMER 0x000001FF 346 #define RTC_CNTL_WIFI_WAIT_TIMER_M ((RTC_CNTL_WIFI_WAIT_TIMER_V)<<(RTC_CNTL_WIFI_WAIT_TIMER_S)) 347 #define RTC_CNTL_WIFI_WAIT_TIMER_V 0x1FF 348 #define RTC_CNTL_WIFI_WAIT_TIMER_S 0 349 350 #define RTC_CNTL_TIMER4_REG (DR_REG_RTCCNTL_BASE + 0x0028) 351 /* RTC_CNTL_DG_WRAP_POWERUP_TIMER : R/W ;bitpos:[31:25] ;default: 7'h8 ; */ 352 /*description: */ 353 #define RTC_CNTL_DG_WRAP_POWERUP_TIMER 0x0000007F 354 #define RTC_CNTL_DG_WRAP_POWERUP_TIMER_M ((RTC_CNTL_DG_WRAP_POWERUP_TIMER_V)<<(RTC_CNTL_DG_WRAP_POWERUP_TIMER_S)) 355 #define RTC_CNTL_DG_WRAP_POWERUP_TIMER_V 0x7F 356 #define RTC_CNTL_DG_WRAP_POWERUP_TIMER_S 25 357 /* RTC_CNTL_DG_WRAP_WAIT_TIMER : R/W ;bitpos:[24:16] ;default: 9'h20 ; */ 358 /*description: */ 359 #define RTC_CNTL_DG_WRAP_WAIT_TIMER 0x000001FF 360 #define RTC_CNTL_DG_WRAP_WAIT_TIMER_M ((RTC_CNTL_DG_WRAP_WAIT_TIMER_V)<<(RTC_CNTL_DG_WRAP_WAIT_TIMER_S)) 361 #define RTC_CNTL_DG_WRAP_WAIT_TIMER_V 0x1FF 362 #define RTC_CNTL_DG_WRAP_WAIT_TIMER_S 16 363 /* RTC_CNTL_CPU_TOP_POWERUP_TIMER : R/W ;bitpos:[15:9] ;default: 7'h5 ; */ 364 /*description: */ 365 #define RTC_CNTL_CPU_TOP_POWERUP_TIMER 0x0000007F 366 #define RTC_CNTL_CPU_TOP_POWERUP_TIMER_M ((RTC_CNTL_CPU_TOP_POWERUP_TIMER_V)<<(RTC_CNTL_CPU_TOP_POWERUP_TIMER_S)) 367 #define RTC_CNTL_CPU_TOP_POWERUP_TIMER_V 0x7F 368 #define RTC_CNTL_CPU_TOP_POWERUP_TIMER_S 9 369 /* RTC_CNTL_CPU_TOP_WAIT_TIMER : R/W ;bitpos:[8:0] ;default: 9'h8 ; */ 370 /*description: */ 371 #define RTC_CNTL_CPU_TOP_WAIT_TIMER 0x000001FF 372 #define RTC_CNTL_CPU_TOP_WAIT_TIMER_M ((RTC_CNTL_CPU_TOP_WAIT_TIMER_V)<<(RTC_CNTL_CPU_TOP_WAIT_TIMER_S)) 373 #define RTC_CNTL_CPU_TOP_WAIT_TIMER_V 0x1FF 374 #define RTC_CNTL_CPU_TOP_WAIT_TIMER_S 0 375 376 #define RTC_CNTL_TIMER5_REG (DR_REG_RTCCNTL_BASE + 0x002C) 377 /* RTC_CNTL_MIN_SLP_VAL : R/W ;bitpos:[15:8] ;default: 8'h80 ; */ 378 /*description: minimal sleep cycles in slow_clk_rtc*/ 379 #define RTC_CNTL_MIN_SLP_VAL 0x000000FF 380 #define RTC_CNTL_MIN_SLP_VAL_M ((RTC_CNTL_MIN_SLP_VAL_V)<<(RTC_CNTL_MIN_SLP_VAL_S)) 381 #define RTC_CNTL_MIN_SLP_VAL_V 0xFF 382 #define RTC_CNTL_MIN_SLP_VAL_S 8 383 384 #define RTC_CNTL_TIMER6_REG (DR_REG_RTCCNTL_BASE + 0x0030) 385 /* RTC_CNTL_DG_PERI_POWERUP_TIMER : R/W ;bitpos:[31:25] ;default: 7'h5 ; */ 386 /*description: */ 387 #define RTC_CNTL_DG_PERI_POWERUP_TIMER 0x0000007F 388 #define RTC_CNTL_DG_PERI_POWERUP_TIMER_M ((RTC_CNTL_DG_PERI_POWERUP_TIMER_V)<<(RTC_CNTL_DG_PERI_POWERUP_TIMER_S)) 389 #define RTC_CNTL_DG_PERI_POWERUP_TIMER_V 0x7F 390 #define RTC_CNTL_DG_PERI_POWERUP_TIMER_S 25 391 /* RTC_CNTL_DG_PERI_WAIT_TIMER : R/W ;bitpos:[24:16] ;default: 9'h8 ; */ 392 /*description: */ 393 #define RTC_CNTL_DG_PERI_WAIT_TIMER 0x000001FF 394 #define RTC_CNTL_DG_PERI_WAIT_TIMER_M ((RTC_CNTL_DG_PERI_WAIT_TIMER_V)<<(RTC_CNTL_DG_PERI_WAIT_TIMER_S)) 395 #define RTC_CNTL_DG_PERI_WAIT_TIMER_V 0x1FF 396 #define RTC_CNTL_DG_PERI_WAIT_TIMER_S 16 397 398 #define RTC_CNTL_ANA_CONF_REG (DR_REG_RTCCNTL_BASE + 0x0034) 399 /* RTC_CNTL_PLL_I2C_PU : R/W ;bitpos:[31] ;default: 1'd0 ; */ 400 /*description: */ 401 #define RTC_CNTL_PLL_I2C_PU (BIT(31)) 402 #define RTC_CNTL_PLL_I2C_PU_M (BIT(31)) 403 #define RTC_CNTL_PLL_I2C_PU_V 0x1 404 #define RTC_CNTL_PLL_I2C_PU_S 31 405 /* RTC_CNTL_CKGEN_I2C_PU : R/W ;bitpos:[30] ;default: 1'd0 ; */ 406 /*description: 1: CKGEN_I2C power up*/ 407 #define RTC_CNTL_CKGEN_I2C_PU (BIT(30)) 408 #define RTC_CNTL_CKGEN_I2C_PU_M (BIT(30)) 409 #define RTC_CNTL_CKGEN_I2C_PU_V 0x1 410 #define RTC_CNTL_CKGEN_I2C_PU_S 30 411 /* RTC_CNTL_RFRX_PBUS_PU : R/W ;bitpos:[28] ;default: 1'd0 ; */ 412 /*description: 1: RFRX_PBUS power up*/ 413 #define RTC_CNTL_RFRX_PBUS_PU (BIT(28)) 414 #define RTC_CNTL_RFRX_PBUS_PU_M (BIT(28)) 415 #define RTC_CNTL_RFRX_PBUS_PU_V 0x1 416 #define RTC_CNTL_RFRX_PBUS_PU_S 28 417 /* RTC_CNTL_TXRF_I2C_PU : R/W ;bitpos:[27] ;default: 1'd0 ; */ 418 /*description: 1: TXRF_I2C power up*/ 419 #define RTC_CNTL_TXRF_I2C_PU (BIT(27)) 420 #define RTC_CNTL_TXRF_I2C_PU_M (BIT(27)) 421 #define RTC_CNTL_TXRF_I2C_PU_V 0x1 422 #define RTC_CNTL_TXRF_I2C_PU_S 27 423 /* RTC_CNTL_PVTMON_PU : R/W ;bitpos:[26] ;default: 1'b0 ; */ 424 /*description: 1: PVTMON power up*/ 425 #define RTC_CNTL_PVTMON_PU (BIT(26)) 426 #define RTC_CNTL_PVTMON_PU_M (BIT(26)) 427 #define RTC_CNTL_PVTMON_PU_V 0x1 428 #define RTC_CNTL_PVTMON_PU_S 26 429 /* RTC_CNTL_BBPLL_CAL_SLP_START : R/W ;bitpos:[25] ;default: 1'b0 ; */ 430 /*description: start BBPLL calibration during sleep*/ 431 #define RTC_CNTL_BBPLL_CAL_SLP_START (BIT(25)) 432 #define RTC_CNTL_BBPLL_CAL_SLP_START_M (BIT(25)) 433 #define RTC_CNTL_BBPLL_CAL_SLP_START_V 0x1 434 #define RTC_CNTL_BBPLL_CAL_SLP_START_S 25 435 /* RTC_CNTL_PLLA_FORCE_PU : R/W ;bitpos:[24] ;default: 1'b0 ; */ 436 /*description: PLLA force power up*/ 437 #define RTC_CNTL_PLLA_FORCE_PU (BIT(24)) 438 #define RTC_CNTL_PLLA_FORCE_PU_M (BIT(24)) 439 #define RTC_CNTL_PLLA_FORCE_PU_V 0x1 440 #define RTC_CNTL_PLLA_FORCE_PU_S 24 441 /* RTC_CNTL_PLLA_FORCE_PD : R/W ;bitpos:[23] ;default: 1'b1 ; */ 442 /*description: PLLA force power down*/ 443 #define RTC_CNTL_PLLA_FORCE_PD (BIT(23)) 444 #define RTC_CNTL_PLLA_FORCE_PD_M (BIT(23)) 445 #define RTC_CNTL_PLLA_FORCE_PD_V 0x1 446 #define RTC_CNTL_PLLA_FORCE_PD_S 23 447 /* RTC_CNTL_SAR_I2C_PU : R/W ;bitpos:[22] ;default: 1'b1 ; */ 448 /*description: PLLA force power up*/ 449 #define RTC_CNTL_SAR_I2C_PU (BIT(22)) 450 #define RTC_CNTL_SAR_I2C_PU_M (BIT(22)) 451 #define RTC_CNTL_SAR_I2C_PU_V 0x1 452 #define RTC_CNTL_SAR_I2C_PU_S 22 453 /* RTC_CNTL_GLITCH_RST_EN : R/W ;bitpos:[20] ;default: 1'b0 ; */ 454 /*description: */ 455 #define RTC_CNTL_GLITCH_RST_EN (BIT(20)) 456 #define RTC_CNTL_GLITCH_RST_EN_M (BIT(20)) 457 #define RTC_CNTL_GLITCH_RST_EN_V 0x1 458 #define RTC_CNTL_GLITCH_RST_EN_S 20 459 /* RTC_CNTL_I2C_RESET_POR_FORCE_PU : R/W ;bitpos:[19] ;default: 1'b0 ; */ 460 /*description: */ 461 #define RTC_CNTL_I2C_RESET_POR_FORCE_PU (BIT(19)) 462 #define RTC_CNTL_I2C_RESET_POR_FORCE_PU_M (BIT(19)) 463 #define RTC_CNTL_I2C_RESET_POR_FORCE_PU_V 0x1 464 #define RTC_CNTL_I2C_RESET_POR_FORCE_PU_S 19 465 /* RTC_CNTL_I2C_RESET_POR_FORCE_PD : R/W ;bitpos:[18] ;default: 1'b1 ; */ 466 /*description: */ 467 #define RTC_CNTL_I2C_RESET_POR_FORCE_PD (BIT(18)) 468 #define RTC_CNTL_I2C_RESET_POR_FORCE_PD_M (BIT(18)) 469 #define RTC_CNTL_I2C_RESET_POR_FORCE_PD_V 0x1 470 #define RTC_CNTL_I2C_RESET_POR_FORCE_PD_S 18 471 472 #define RTC_CNTL_RESET_STATE_REG (DR_REG_RTCCNTL_BASE + 0x0038) 473 /* RTC_CNTL_DRESET_MASK_PROCPU : R/W ;bitpos:[25] ;default: 1'b0 ; */ 474 /*description: */ 475 #define RTC_CNTL_DRESET_MASK_PROCPU (BIT(25)) 476 #define RTC_CNTL_DRESET_MASK_PROCPU_M (BIT(25)) 477 #define RTC_CNTL_DRESET_MASK_PROCPU_V 0x1 478 #define RTC_CNTL_DRESET_MASK_PROCPU_S 25 479 /* RTC_CNTL_DRESET_MASK_APPCPU : R/W ;bitpos:[24] ;default: 1'b0 ; */ 480 /*description: */ 481 #define RTC_CNTL_DRESET_MASK_APPCPU (BIT(24)) 482 #define RTC_CNTL_DRESET_MASK_APPCPU_M (BIT(24)) 483 #define RTC_CNTL_DRESET_MASK_APPCPU_V 0x1 484 #define RTC_CNTL_DRESET_MASK_APPCPU_S 24 485 /* RTC_CNTL_JTAG_RESET_FLAG_CLR_APPCPU : WO ;bitpos:[23] ;default: 1'b0 ; */ 486 /*description: */ 487 #define RTC_CNTL_JTAG_RESET_FLAG_CLR_APPCPU (BIT(23)) 488 #define RTC_CNTL_JTAG_RESET_FLAG_CLR_APPCPU_M (BIT(23)) 489 #define RTC_CNTL_JTAG_RESET_FLAG_CLR_APPCPU_V 0x1 490 #define RTC_CNTL_JTAG_RESET_FLAG_CLR_APPCPU_S 23 491 /* RTC_CNTL_JTAG_RESET_FLAG_CLR_PROCPU : WO ;bitpos:[22] ;default: 1'b0 ; */ 492 /*description: */ 493 #define RTC_CNTL_JTAG_RESET_FLAG_CLR_PROCPU (BIT(22)) 494 #define RTC_CNTL_JTAG_RESET_FLAG_CLR_PROCPU_M (BIT(22)) 495 #define RTC_CNTL_JTAG_RESET_FLAG_CLR_PROCPU_V 0x1 496 #define RTC_CNTL_JTAG_RESET_FLAG_CLR_PROCPU_S 22 497 /* RTC_CNTL_JTAG_RESET_FLAG_APPCPU : RO ;bitpos:[21] ;default: 1'b0 ; */ 498 /*description: */ 499 #define RTC_CNTL_JTAG_RESET_FLAG_APPCPU (BIT(21)) 500 #define RTC_CNTL_JTAG_RESET_FLAG_APPCPU_M (BIT(21)) 501 #define RTC_CNTL_JTAG_RESET_FLAG_APPCPU_V 0x1 502 #define RTC_CNTL_JTAG_RESET_FLAG_APPCPU_S 21 503 /* RTC_CNTL_JTAG_RESET_FLAG_PROCPU : RO ;bitpos:[20] ;default: 1'b0 ; */ 504 /*description: */ 505 #define RTC_CNTL_JTAG_RESET_FLAG_PROCPU (BIT(20)) 506 #define RTC_CNTL_JTAG_RESET_FLAG_PROCPU_M (BIT(20)) 507 #define RTC_CNTL_JTAG_RESET_FLAG_PROCPU_V 0x1 508 #define RTC_CNTL_JTAG_RESET_FLAG_PROCPU_S 20 509 /* RTC_CNTL_OCD_HALT_ON_RESET_PROCPU : R/W ;bitpos:[19] ;default: 1'b0 ; */ 510 /*description: PROCPU OcdHaltOnReset*/ 511 #define RTC_CNTL_OCD_HALT_ON_RESET_PROCPU (BIT(19)) 512 #define RTC_CNTL_OCD_HALT_ON_RESET_PROCPU_M (BIT(19)) 513 #define RTC_CNTL_OCD_HALT_ON_RESET_PROCPU_V 0x1 514 #define RTC_CNTL_OCD_HALT_ON_RESET_PROCPU_S 19 515 /* RTC_CNTL_OCD_HALT_ON_RESET_APPCPU : R/W ;bitpos:[18] ;default: 1'b0 ; */ 516 /*description: APPCPU OcdHaltOnReset*/ 517 #define RTC_CNTL_OCD_HALT_ON_RESET_APPCPU (BIT(18)) 518 #define RTC_CNTL_OCD_HALT_ON_RESET_APPCPU_M (BIT(18)) 519 #define RTC_CNTL_OCD_HALT_ON_RESET_APPCPU_V 0x1 520 #define RTC_CNTL_OCD_HALT_ON_RESET_APPCPU_S 18 521 /* RTC_CNTL_ALL_RESET_FLAG_CLR_APPCPU : WO ;bitpos:[17] ;default: 1'b0 ; */ 522 /*description: clear APP CPU reset flag*/ 523 #define RTC_CNTL_ALL_RESET_FLAG_CLR_APPCPU (BIT(17)) 524 #define RTC_CNTL_ALL_RESET_FLAG_CLR_APPCPU_M (BIT(17)) 525 #define RTC_CNTL_ALL_RESET_FLAG_CLR_APPCPU_V 0x1 526 #define RTC_CNTL_ALL_RESET_FLAG_CLR_APPCPU_S 17 527 /* RTC_CNTL_ALL_RESET_FLAG_CLR_PROCPU : WO ;bitpos:[16] ;default: 1'b0 ; */ 528 /*description: clear PRO CPU reset_flag*/ 529 #define RTC_CNTL_ALL_RESET_FLAG_CLR_PROCPU (BIT(16)) 530 #define RTC_CNTL_ALL_RESET_FLAG_CLR_PROCPU_M (BIT(16)) 531 #define RTC_CNTL_ALL_RESET_FLAG_CLR_PROCPU_V 0x1 532 #define RTC_CNTL_ALL_RESET_FLAG_CLR_PROCPU_S 16 533 /* RTC_CNTL_ALL_RESET_FLAG_APPCPU : RO ;bitpos:[15] ;default: 1'b0 ; */ 534 /*description: APP CPU reset flag*/ 535 #define RTC_CNTL_ALL_RESET_FLAG_APPCPU (BIT(15)) 536 #define RTC_CNTL_ALL_RESET_FLAG_APPCPU_M (BIT(15)) 537 #define RTC_CNTL_ALL_RESET_FLAG_APPCPU_V 0x1 538 #define RTC_CNTL_ALL_RESET_FLAG_APPCPU_S 15 539 /* RTC_CNTL_ALL_RESET_FLAG_PROCPU : RO ;bitpos:[14] ;default: 1'b0 ; */ 540 /*description: PRO CPU reset_flag*/ 541 #define RTC_CNTL_ALL_RESET_FLAG_PROCPU (BIT(14)) 542 #define RTC_CNTL_ALL_RESET_FLAG_PROCPU_M (BIT(14)) 543 #define RTC_CNTL_ALL_RESET_FLAG_PROCPU_V 0x1 544 #define RTC_CNTL_ALL_RESET_FLAG_PROCPU_S 14 545 /* RTC_CNTL_STAT_VECTOR_SEL_PROCPU : R/W ;bitpos:[13] ;default: 1'b1 ; */ 546 /*description: PRO CPU state vector sel*/ 547 #define RTC_CNTL_STAT_VECTOR_SEL_PROCPU (BIT(13)) 548 #define RTC_CNTL_STAT_VECTOR_SEL_PROCPU_M (BIT(13)) 549 #define RTC_CNTL_STAT_VECTOR_SEL_PROCPU_V 0x1 550 #define RTC_CNTL_STAT_VECTOR_SEL_PROCPU_S 13 551 /* RTC_CNTL_STAT_VECTOR_SEL_APPCPU : R/W ;bitpos:[12] ;default: 1'b1 ; */ 552 /*description: APP CPU state vector sel*/ 553 #define RTC_CNTL_STAT_VECTOR_SEL_APPCPU (BIT(12)) 554 #define RTC_CNTL_STAT_VECTOR_SEL_APPCPU_M (BIT(12)) 555 #define RTC_CNTL_STAT_VECTOR_SEL_APPCPU_V 0x1 556 #define RTC_CNTL_STAT_VECTOR_SEL_APPCPU_S 12 557 /* RTC_CNTL_RESET_CAUSE_APPCPU : RO ;bitpos:[11:6] ;default: 0 ; */ 558 /*description: reset cause of APP CPU*/ 559 #define RTC_CNTL_RESET_CAUSE_APPCPU 0x0000003F 560 #define RTC_CNTL_RESET_CAUSE_APPCPU_M ((RTC_CNTL_RESET_CAUSE_APPCPU_V)<<(RTC_CNTL_RESET_CAUSE_APPCPU_S)) 561 #define RTC_CNTL_RESET_CAUSE_APPCPU_V 0x3F 562 #define RTC_CNTL_RESET_CAUSE_APPCPU_S 6 563 /* RTC_CNTL_RESET_CAUSE_PROCPU : RO ;bitpos:[5:0] ;default: 0 ; */ 564 /*description: reset cause of PRO CPU*/ 565 #define RTC_CNTL_RESET_CAUSE_PROCPU 0x0000003F 566 #define RTC_CNTL_RESET_CAUSE_PROCPU_M ((RTC_CNTL_RESET_CAUSE_PROCPU_V)<<(RTC_CNTL_RESET_CAUSE_PROCPU_S)) 567 #define RTC_CNTL_RESET_CAUSE_PROCPU_V 0x3F 568 #define RTC_CNTL_RESET_CAUSE_PROCPU_S 0 569 570 #define RTC_CNTL_WAKEUP_STATE_REG (DR_REG_RTCCNTL_BASE + 0x003C) 571 /* RTC_CNTL_WAKEUP_ENA : R/W ;bitpos:[31:15] ;default: 17'b1100 ; */ 572 /*description: wakeup enable bitmap*/ 573 #define RTC_CNTL_WAKEUP_ENA 0x0001FFFF 574 #define RTC_CNTL_WAKEUP_ENA_M ((RTC_CNTL_WAKEUP_ENA_V)<<(RTC_CNTL_WAKEUP_ENA_S)) 575 #define RTC_CNTL_WAKEUP_ENA_V 0x1FFFF 576 #define RTC_CNTL_WAKEUP_ENA_S 15 577 578 #define RTC_CNTL_INT_ENA_REG (DR_REG_RTCCNTL_BASE + 0x0040) 579 /* RTC_CNTL_BBPLL_CAL_INT_ENA : R/W ;bitpos:[20] ;default: 1'b0 ; */ 580 /*description: */ 581 #define RTC_CNTL_BBPLL_CAL_INT_ENA (BIT(20)) 582 #define RTC_CNTL_BBPLL_CAL_INT_ENA_M (BIT(20)) 583 #define RTC_CNTL_BBPLL_CAL_INT_ENA_V 0x1 584 #define RTC_CNTL_BBPLL_CAL_INT_ENA_S 20 585 /* RTC_CNTL_GLITCH_DET_INT_ENA : R/W ;bitpos:[19] ;default: 1'b0 ; */ 586 /*description: enbale gitch det interrupt*/ 587 #define RTC_CNTL_GLITCH_DET_INT_ENA (BIT(19)) 588 #define RTC_CNTL_GLITCH_DET_INT_ENA_M (BIT(19)) 589 #define RTC_CNTL_GLITCH_DET_INT_ENA_V 0x1 590 #define RTC_CNTL_GLITCH_DET_INT_ENA_S 19 591 /* RTC_CNTL_XTAL32K_DEAD_INT_ENA : R/W ;bitpos:[16] ;default: 1'b0 ; */ 592 /*description: enable xtal32k_dead interrupt*/ 593 #define RTC_CNTL_XTAL32K_DEAD_INT_ENA (BIT(16)) 594 #define RTC_CNTL_XTAL32K_DEAD_INT_ENA_M (BIT(16)) 595 #define RTC_CNTL_XTAL32K_DEAD_INT_ENA_V 0x1 596 #define RTC_CNTL_XTAL32K_DEAD_INT_ENA_S 16 597 /* RTC_CNTL_SWD_INT_ENA : R/W ;bitpos:[15] ;default: 1'b0 ; */ 598 /*description: enable super watch dog interrupt*/ 599 #define RTC_CNTL_SWD_INT_ENA (BIT(15)) 600 #define RTC_CNTL_SWD_INT_ENA_M (BIT(15)) 601 #define RTC_CNTL_SWD_INT_ENA_V 0x1 602 #define RTC_CNTL_SWD_INT_ENA_S 15 603 /* RTC_CNTL_MAIN_TIMER_INT_ENA : R/W ;bitpos:[10] ;default: 1'b0 ; */ 604 /*description: enable RTC main timer interrupt*/ 605 #define RTC_CNTL_MAIN_TIMER_INT_ENA (BIT(10)) 606 #define RTC_CNTL_MAIN_TIMER_INT_ENA_M (BIT(10)) 607 #define RTC_CNTL_MAIN_TIMER_INT_ENA_V 0x1 608 #define RTC_CNTL_MAIN_TIMER_INT_ENA_S 10 609 /* RTC_CNTL_BROWN_OUT_INT_ENA : R/W ;bitpos:[9] ;default: 1'b0 ; */ 610 /*description: enable brown out interrupt*/ 611 #define RTC_CNTL_BROWN_OUT_INT_ENA (BIT(9)) 612 #define RTC_CNTL_BROWN_OUT_INT_ENA_M (BIT(9)) 613 #define RTC_CNTL_BROWN_OUT_INT_ENA_V 0x1 614 #define RTC_CNTL_BROWN_OUT_INT_ENA_S 9 615 /* RTC_CNTL_WDT_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */ 616 /*description: enable RTC WDT interrupt*/ 617 #define RTC_CNTL_WDT_INT_ENA (BIT(3)) 618 #define RTC_CNTL_WDT_INT_ENA_M (BIT(3)) 619 #define RTC_CNTL_WDT_INT_ENA_V 0x1 620 #define RTC_CNTL_WDT_INT_ENA_S 3 621 /* RTC_CNTL_SLP_REJECT_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */ 622 /*description: enable sleep reject interrupt*/ 623 #define RTC_CNTL_SLP_REJECT_INT_ENA (BIT(1)) 624 #define RTC_CNTL_SLP_REJECT_INT_ENA_M (BIT(1)) 625 #define RTC_CNTL_SLP_REJECT_INT_ENA_V 0x1 626 #define RTC_CNTL_SLP_REJECT_INT_ENA_S 1 627 /* RTC_CNTL_SLP_WAKEUP_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ 628 /*description: enable sleep wakeup interrupt*/ 629 #define RTC_CNTL_SLP_WAKEUP_INT_ENA (BIT(0)) 630 #define RTC_CNTL_SLP_WAKEUP_INT_ENA_M (BIT(0)) 631 #define RTC_CNTL_SLP_WAKEUP_INT_ENA_V 0x1 632 #define RTC_CNTL_SLP_WAKEUP_INT_ENA_S 0 633 634 #define RTC_CNTL_INT_RAW_REG (DR_REG_RTCCNTL_BASE + 0x0044) 635 /* RTC_CNTL_BBPLL_CAL_INT_RAW : RO ;bitpos:[20] ;default: 1'b0 ; */ 636 /*description: */ 637 #define RTC_CNTL_BBPLL_CAL_INT_RAW (BIT(20)) 638 #define RTC_CNTL_BBPLL_CAL_INT_RAW_M (BIT(20)) 639 #define RTC_CNTL_BBPLL_CAL_INT_RAW_V 0x1 640 #define RTC_CNTL_BBPLL_CAL_INT_RAW_S 20 641 /* RTC_CNTL_GLITCH_DET_INT_RAW : RO ;bitpos:[19] ;default: 1'b0 ; */ 642 /*description: glitch_det_interrupt_raw*/ 643 #define RTC_CNTL_GLITCH_DET_INT_RAW (BIT(19)) 644 #define RTC_CNTL_GLITCH_DET_INT_RAW_M (BIT(19)) 645 #define RTC_CNTL_GLITCH_DET_INT_RAW_V 0x1 646 #define RTC_CNTL_GLITCH_DET_INT_RAW_S 19 647 /* RTC_CNTL_XTAL32K_DEAD_INT_RAW : RO ;bitpos:[16] ;default: 1'b0 ; */ 648 /*description: xtal32k dead detection interrupt raw*/ 649 #define RTC_CNTL_XTAL32K_DEAD_INT_RAW (BIT(16)) 650 #define RTC_CNTL_XTAL32K_DEAD_INT_RAW_M (BIT(16)) 651 #define RTC_CNTL_XTAL32K_DEAD_INT_RAW_V 0x1 652 #define RTC_CNTL_XTAL32K_DEAD_INT_RAW_S 16 653 /* RTC_CNTL_SWD_INT_RAW : RO ;bitpos:[15] ;default: 1'b0 ; */ 654 /*description: super watch dog interrupt raw*/ 655 #define RTC_CNTL_SWD_INT_RAW (BIT(15)) 656 #define RTC_CNTL_SWD_INT_RAW_M (BIT(15)) 657 #define RTC_CNTL_SWD_INT_RAW_V 0x1 658 #define RTC_CNTL_SWD_INT_RAW_S 15 659 /* RTC_CNTL_MAIN_TIMER_INT_RAW : RO ;bitpos:[10] ;default: 1'b0 ; */ 660 /*description: RTC main timer interrupt raw*/ 661 #define RTC_CNTL_MAIN_TIMER_INT_RAW (BIT(10)) 662 #define RTC_CNTL_MAIN_TIMER_INT_RAW_M (BIT(10)) 663 #define RTC_CNTL_MAIN_TIMER_INT_RAW_V 0x1 664 #define RTC_CNTL_MAIN_TIMER_INT_RAW_S 10 665 /* RTC_CNTL_BROWN_OUT_INT_RAW : RO ;bitpos:[9] ;default: 1'b0 ; */ 666 /*description: brown out interrupt raw*/ 667 #define RTC_CNTL_BROWN_OUT_INT_RAW (BIT(9)) 668 #define RTC_CNTL_BROWN_OUT_INT_RAW_M (BIT(9)) 669 #define RTC_CNTL_BROWN_OUT_INT_RAW_V 0x1 670 #define RTC_CNTL_BROWN_OUT_INT_RAW_S 9 671 /* RTC_CNTL_WDT_INT_RAW : RO ;bitpos:[3] ;default: 1'b0 ; */ 672 /*description: RTC WDT interrupt raw*/ 673 #define RTC_CNTL_WDT_INT_RAW (BIT(3)) 674 #define RTC_CNTL_WDT_INT_RAW_M (BIT(3)) 675 #define RTC_CNTL_WDT_INT_RAW_V 0x1 676 #define RTC_CNTL_WDT_INT_RAW_S 3 677 /* RTC_CNTL_SLP_REJECT_INT_RAW : RO ;bitpos:[1] ;default: 1'b0 ; */ 678 /*description: sleep reject interrupt raw*/ 679 #define RTC_CNTL_SLP_REJECT_INT_RAW (BIT(1)) 680 #define RTC_CNTL_SLP_REJECT_INT_RAW_M (BIT(1)) 681 #define RTC_CNTL_SLP_REJECT_INT_RAW_V 0x1 682 #define RTC_CNTL_SLP_REJECT_INT_RAW_S 1 683 /* RTC_CNTL_SLP_WAKEUP_INT_RAW : RO ;bitpos:[0] ;default: 1'b0 ; */ 684 /*description: sleep wakeup interrupt raw*/ 685 #define RTC_CNTL_SLP_WAKEUP_INT_RAW (BIT(0)) 686 #define RTC_CNTL_SLP_WAKEUP_INT_RAW_M (BIT(0)) 687 #define RTC_CNTL_SLP_WAKEUP_INT_RAW_V 0x1 688 #define RTC_CNTL_SLP_WAKEUP_INT_RAW_S 0 689 690 #define RTC_CNTL_INT_ST_REG (DR_REG_RTCCNTL_BASE + 0x0048) 691 /* RTC_CNTL_BBPLL_CAL_INT_ST : RO ;bitpos:[20] ;default: 1'b0 ; */ 692 /*description: */ 693 #define RTC_CNTL_BBPLL_CAL_INT_ST (BIT(20)) 694 #define RTC_CNTL_BBPLL_CAL_INT_ST_M (BIT(20)) 695 #define RTC_CNTL_BBPLL_CAL_INT_ST_V 0x1 696 #define RTC_CNTL_BBPLL_CAL_INT_ST_S 20 697 /* RTC_CNTL_GLITCH_DET_INT_ST : RO ;bitpos:[19] ;default: 1'b0 ; */ 698 /*description: glitch_det_interrupt state*/ 699 #define RTC_CNTL_GLITCH_DET_INT_ST (BIT(19)) 700 #define RTC_CNTL_GLITCH_DET_INT_ST_M (BIT(19)) 701 #define RTC_CNTL_GLITCH_DET_INT_ST_V 0x1 702 #define RTC_CNTL_GLITCH_DET_INT_ST_S 19 703 /* RTC_CNTL_XTAL32K_DEAD_INT_ST : RO ;bitpos:[16] ;default: 1'b0 ; */ 704 /*description: xtal32k dead detection interrupt state*/ 705 #define RTC_CNTL_XTAL32K_DEAD_INT_ST (BIT(16)) 706 #define RTC_CNTL_XTAL32K_DEAD_INT_ST_M (BIT(16)) 707 #define RTC_CNTL_XTAL32K_DEAD_INT_ST_V 0x1 708 #define RTC_CNTL_XTAL32K_DEAD_INT_ST_S 16 709 /* RTC_CNTL_SWD_INT_ST : RO ;bitpos:[15] ;default: 1'b0 ; */ 710 /*description: super watch dog interrupt state*/ 711 #define RTC_CNTL_SWD_INT_ST (BIT(15)) 712 #define RTC_CNTL_SWD_INT_ST_M (BIT(15)) 713 #define RTC_CNTL_SWD_INT_ST_V 0x1 714 #define RTC_CNTL_SWD_INT_ST_S 15 715 /* RTC_CNTL_MAIN_TIMER_INT_ST : RO ;bitpos:[10] ;default: 1'b0 ; */ 716 /*description: RTC main timer interrupt state*/ 717 #define RTC_CNTL_MAIN_TIMER_INT_ST (BIT(10)) 718 #define RTC_CNTL_MAIN_TIMER_INT_ST_M (BIT(10)) 719 #define RTC_CNTL_MAIN_TIMER_INT_ST_V 0x1 720 #define RTC_CNTL_MAIN_TIMER_INT_ST_S 10 721 /* RTC_CNTL_BROWN_OUT_INT_ST : RO ;bitpos:[9] ;default: 1'b0 ; */ 722 /*description: brown out interrupt state*/ 723 #define RTC_CNTL_BROWN_OUT_INT_ST (BIT(9)) 724 #define RTC_CNTL_BROWN_OUT_INT_ST_M (BIT(9)) 725 #define RTC_CNTL_BROWN_OUT_INT_ST_V 0x1 726 #define RTC_CNTL_BROWN_OUT_INT_ST_S 9 727 /* RTC_CNTL_WDT_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */ 728 /*description: RTC WDT interrupt state*/ 729 #define RTC_CNTL_WDT_INT_ST (BIT(3)) 730 #define RTC_CNTL_WDT_INT_ST_M (BIT(3)) 731 #define RTC_CNTL_WDT_INT_ST_V 0x1 732 #define RTC_CNTL_WDT_INT_ST_S 3 733 /* RTC_CNTL_SLP_REJECT_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */ 734 /*description: sleep reject interrupt state*/ 735 #define RTC_CNTL_SLP_REJECT_INT_ST (BIT(1)) 736 #define RTC_CNTL_SLP_REJECT_INT_ST_M (BIT(1)) 737 #define RTC_CNTL_SLP_REJECT_INT_ST_V 0x1 738 #define RTC_CNTL_SLP_REJECT_INT_ST_S 1 739 /* RTC_CNTL_SLP_WAKEUP_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */ 740 /*description: sleep wakeup interrupt state*/ 741 #define RTC_CNTL_SLP_WAKEUP_INT_ST (BIT(0)) 742 #define RTC_CNTL_SLP_WAKEUP_INT_ST_M (BIT(0)) 743 #define RTC_CNTL_SLP_WAKEUP_INT_ST_V 0x1 744 #define RTC_CNTL_SLP_WAKEUP_INT_ST_S 0 745 746 #define RTC_CNTL_INT_CLR_REG (DR_REG_RTCCNTL_BASE + 0x004C) 747 /* RTC_CNTL_BBPLL_CAL_INT_CLR : WO ;bitpos:[20] ;default: 1'b0 ; */ 748 /*description: */ 749 #define RTC_CNTL_BBPLL_CAL_INT_CLR (BIT(20)) 750 #define RTC_CNTL_BBPLL_CAL_INT_CLR_M (BIT(20)) 751 #define RTC_CNTL_BBPLL_CAL_INT_CLR_V 0x1 752 #define RTC_CNTL_BBPLL_CAL_INT_CLR_S 20 753 /* RTC_CNTL_GLITCH_DET_INT_CLR : WO ;bitpos:[19] ;default: 1'b0 ; */ 754 /*description: Clear glitch det interrupt state*/ 755 #define RTC_CNTL_GLITCH_DET_INT_CLR (BIT(19)) 756 #define RTC_CNTL_GLITCH_DET_INT_CLR_M (BIT(19)) 757 #define RTC_CNTL_GLITCH_DET_INT_CLR_V 0x1 758 #define RTC_CNTL_GLITCH_DET_INT_CLR_S 19 759 /* RTC_CNTL_XTAL32K_DEAD_INT_CLR : WO ;bitpos:[16] ;default: 1'b0 ; */ 760 /*description: Clear RTC WDT interrupt state*/ 761 #define RTC_CNTL_XTAL32K_DEAD_INT_CLR (BIT(16)) 762 #define RTC_CNTL_XTAL32K_DEAD_INT_CLR_M (BIT(16)) 763 #define RTC_CNTL_XTAL32K_DEAD_INT_CLR_V 0x1 764 #define RTC_CNTL_XTAL32K_DEAD_INT_CLR_S 16 765 /* RTC_CNTL_SWD_INT_CLR : WO ;bitpos:[15] ;default: 1'b0 ; */ 766 /*description: Clear super watch dog interrupt state*/ 767 #define RTC_CNTL_SWD_INT_CLR (BIT(15)) 768 #define RTC_CNTL_SWD_INT_CLR_M (BIT(15)) 769 #define RTC_CNTL_SWD_INT_CLR_V 0x1 770 #define RTC_CNTL_SWD_INT_CLR_S 15 771 /* RTC_CNTL_MAIN_TIMER_INT_CLR : WO ;bitpos:[10] ;default: 1'b0 ; */ 772 /*description: Clear RTC main timer interrupt state*/ 773 #define RTC_CNTL_MAIN_TIMER_INT_CLR (BIT(10)) 774 #define RTC_CNTL_MAIN_TIMER_INT_CLR_M (BIT(10)) 775 #define RTC_CNTL_MAIN_TIMER_INT_CLR_V 0x1 776 #define RTC_CNTL_MAIN_TIMER_INT_CLR_S 10 777 /* RTC_CNTL_BROWN_OUT_INT_CLR : WO ;bitpos:[9] ;default: 1'b0 ; */ 778 /*description: Clear brown out interrupt state*/ 779 #define RTC_CNTL_BROWN_OUT_INT_CLR (BIT(9)) 780 #define RTC_CNTL_BROWN_OUT_INT_CLR_M (BIT(9)) 781 #define RTC_CNTL_BROWN_OUT_INT_CLR_V 0x1 782 #define RTC_CNTL_BROWN_OUT_INT_CLR_S 9 783 /* RTC_CNTL_WDT_INT_CLR : WO ;bitpos:[3] ;default: 1'b0 ; */ 784 /*description: Clear RTC WDT interrupt state*/ 785 #define RTC_CNTL_WDT_INT_CLR (BIT(3)) 786 #define RTC_CNTL_WDT_INT_CLR_M (BIT(3)) 787 #define RTC_CNTL_WDT_INT_CLR_V 0x1 788 #define RTC_CNTL_WDT_INT_CLR_S 3 789 /* RTC_CNTL_SLP_REJECT_INT_CLR : WO ;bitpos:[1] ;default: 1'b0 ; */ 790 /*description: Clear sleep reject interrupt state*/ 791 #define RTC_CNTL_SLP_REJECT_INT_CLR (BIT(1)) 792 #define RTC_CNTL_SLP_REJECT_INT_CLR_M (BIT(1)) 793 #define RTC_CNTL_SLP_REJECT_INT_CLR_V 0x1 794 #define RTC_CNTL_SLP_REJECT_INT_CLR_S 1 795 /* RTC_CNTL_SLP_WAKEUP_INT_CLR : WO ;bitpos:[0] ;default: 1'b0 ; */ 796 /*description: Clear sleep wakeup interrupt state*/ 797 #define RTC_CNTL_SLP_WAKEUP_INT_CLR (BIT(0)) 798 #define RTC_CNTL_SLP_WAKEUP_INT_CLR_M (BIT(0)) 799 #define RTC_CNTL_SLP_WAKEUP_INT_CLR_V 0x1 800 #define RTC_CNTL_SLP_WAKEUP_INT_CLR_S 0 801 802 #define RTC_CNTL_STORE0_REG (DR_REG_RTCCNTL_BASE + 0x0050) 803 /* RTC_CNTL_SCRATCH0 : R/W ;bitpos:[31:0] ;default: 0 ; */ 804 /*description: */ 805 #define RTC_CNTL_SCRATCH0 0xFFFFFFFF 806 #define RTC_CNTL_SCRATCH0_M ((RTC_CNTL_SCRATCH0_V)<<(RTC_CNTL_SCRATCH0_S)) 807 #define RTC_CNTL_SCRATCH0_V 0xFFFFFFFF 808 #define RTC_CNTL_SCRATCH0_S 0 809 810 #define RTC_CNTL_STORE1_REG (DR_REG_RTCCNTL_BASE + 0x0054) 811 /* RTC_CNTL_SCRATCH1 : R/W ;bitpos:[31:0] ;default: 0 ; */ 812 /*description: */ 813 #define RTC_CNTL_SCRATCH1 0xFFFFFFFF 814 #define RTC_CNTL_SCRATCH1_M ((RTC_CNTL_SCRATCH1_V)<<(RTC_CNTL_SCRATCH1_S)) 815 #define RTC_CNTL_SCRATCH1_V 0xFFFFFFFF 816 #define RTC_CNTL_SCRATCH1_S 0 817 818 #define RTC_CNTL_STORE2_REG (DR_REG_RTCCNTL_BASE + 0x0058) 819 /* RTC_CNTL_SCRATCH2 : R/W ;bitpos:[31:0] ;default: 0 ; */ 820 /*description: */ 821 #define RTC_CNTL_SCRATCH2 0xFFFFFFFF 822 #define RTC_CNTL_SCRATCH2_M ((RTC_CNTL_SCRATCH2_V)<<(RTC_CNTL_SCRATCH2_S)) 823 #define RTC_CNTL_SCRATCH2_V 0xFFFFFFFF 824 #define RTC_CNTL_SCRATCH2_S 0 825 826 #define RTC_CNTL_STORE3_REG (DR_REG_RTCCNTL_BASE + 0x005C) 827 /* RTC_CNTL_SCRATCH3 : R/W ;bitpos:[31:0] ;default: 0 ; */ 828 /*description: */ 829 #define RTC_CNTL_SCRATCH3 0xFFFFFFFF 830 #define RTC_CNTL_SCRATCH3_M ((RTC_CNTL_SCRATCH3_V)<<(RTC_CNTL_SCRATCH3_S)) 831 #define RTC_CNTL_SCRATCH3_V 0xFFFFFFFF 832 #define RTC_CNTL_SCRATCH3_S 0 833 834 #define RTC_CNTL_EXT_XTL_CONF_REG (DR_REG_RTCCNTL_BASE + 0x0060) 835 /* RTC_CNTL_XTL_EXT_CTR_EN : R/W ;bitpos:[31] ;default: 1'b0 ; */ 836 /*description: */ 837 #define RTC_CNTL_XTL_EXT_CTR_EN (BIT(31)) 838 #define RTC_CNTL_XTL_EXT_CTR_EN_M (BIT(31)) 839 #define RTC_CNTL_XTL_EXT_CTR_EN_V 0x1 840 #define RTC_CNTL_XTL_EXT_CTR_EN_S 31 841 /* RTC_CNTL_XTL_EXT_CTR_LV : R/W ;bitpos:[30] ;default: 1'b0 ; */ 842 /*description: 0: power down XTAL at high level*/ 843 #define RTC_CNTL_XTL_EXT_CTR_LV (BIT(30)) 844 #define RTC_CNTL_XTL_EXT_CTR_LV_M (BIT(30)) 845 #define RTC_CNTL_XTL_EXT_CTR_LV_V 0x1 846 #define RTC_CNTL_XTL_EXT_CTR_LV_S 30 847 /* RTC_CNTL_XTAL32K_GPIO_SEL : R/W ;bitpos:[23] ;default: 1'b0 ; */ 848 /*description: XTAL_32K sel. 0: external XTAL_32K*/ 849 #define RTC_CNTL_XTAL32K_GPIO_SEL (BIT(23)) 850 #define RTC_CNTL_XTAL32K_GPIO_SEL_M (BIT(23)) 851 #define RTC_CNTL_XTAL32K_GPIO_SEL_V 0x1 852 #define RTC_CNTL_XTAL32K_GPIO_SEL_S 23 853 /* RTC_CNTL_WDT_STATE : RO ;bitpos:[22:20] ;default: 3'h0 ; */ 854 /*description: state of 32k_wdt*/ 855 #define RTC_CNTL_WDT_STATE 0x00000007 856 #define RTC_CNTL_WDT_STATE_M ((RTC_CNTL_WDT_STATE_V)<<(RTC_CNTL_WDT_STATE_S)) 857 #define RTC_CNTL_WDT_STATE_V 0x7 858 #define RTC_CNTL_WDT_STATE_S 20 859 /* RTC_CNTL_DAC_XTAL_32K : R/W ;bitpos:[19:17] ;default: 3'd3 ; */ 860 /*description: DAC_XTAL_32K*/ 861 #define RTC_CNTL_DAC_XTAL_32K 0x00000007 862 #define RTC_CNTL_DAC_XTAL_32K_M ((RTC_CNTL_DAC_XTAL_32K_V)<<(RTC_CNTL_DAC_XTAL_32K_S)) 863 #define RTC_CNTL_DAC_XTAL_32K_V 0x7 864 #define RTC_CNTL_DAC_XTAL_32K_S 17 865 /* RTC_CNTL_XPD_XTAL_32K : R/W ;bitpos:[16] ;default: 1'd0 ; */ 866 /*description: XPD_XTAL_32K*/ 867 #define RTC_CNTL_XPD_XTAL_32K (BIT(16)) 868 #define RTC_CNTL_XPD_XTAL_32K_M (BIT(16)) 869 #define RTC_CNTL_XPD_XTAL_32K_V 0x1 870 #define RTC_CNTL_XPD_XTAL_32K_S 16 871 /* RTC_CNTL_DRES_XTAL_32K : R/W ;bitpos:[15:13] ;default: 3'd3 ; */ 872 /*description: DRES_XTAL_32K*/ 873 #define RTC_CNTL_DRES_XTAL_32K 0x00000007 874 #define RTC_CNTL_DRES_XTAL_32K_M ((RTC_CNTL_DRES_XTAL_32K_V)<<(RTC_CNTL_DRES_XTAL_32K_S)) 875 #define RTC_CNTL_DRES_XTAL_32K_V 0x7 876 #define RTC_CNTL_DRES_XTAL_32K_S 13 877 /* RTC_CNTL_DGM_XTAL_32K : R/W ;bitpos:[12:10] ;default: 3'd3 ; */ 878 /*description: xtal_32k gm control*/ 879 #define RTC_CNTL_DGM_XTAL_32K 0x00000007 880 #define RTC_CNTL_DGM_XTAL_32K_M ((RTC_CNTL_DGM_XTAL_32K_V)<<(RTC_CNTL_DGM_XTAL_32K_S)) 881 #define RTC_CNTL_DGM_XTAL_32K_V 0x7 882 #define RTC_CNTL_DGM_XTAL_32K_S 10 883 /* RTC_CNTL_DBUF_XTAL_32K : R/W ;bitpos:[9] ;default: 1'b0 ; */ 884 /*description: 0: single-end buffer 1: differential buffer*/ 885 #define RTC_CNTL_DBUF_XTAL_32K (BIT(9)) 886 #define RTC_CNTL_DBUF_XTAL_32K_M (BIT(9)) 887 #define RTC_CNTL_DBUF_XTAL_32K_V 0x1 888 #define RTC_CNTL_DBUF_XTAL_32K_S 9 889 /* RTC_CNTL_ENCKINIT_XTAL_32K : R/W ;bitpos:[8] ;default: 1'b0 ; */ 890 /*description: apply an internal clock to help xtal 32k to start*/ 891 #define RTC_CNTL_ENCKINIT_XTAL_32K (BIT(8)) 892 #define RTC_CNTL_ENCKINIT_XTAL_32K_M (BIT(8)) 893 #define RTC_CNTL_ENCKINIT_XTAL_32K_V 0x1 894 #define RTC_CNTL_ENCKINIT_XTAL_32K_S 8 895 /* RTC_CNTL_XTAL32K_XPD_FORCE : R/W ;bitpos:[7] ;default: 1'b1 ; */ 896 /*description: Xtal 32k xpd control by sw or fsm*/ 897 #define RTC_CNTL_XTAL32K_XPD_FORCE (BIT(7)) 898 #define RTC_CNTL_XTAL32K_XPD_FORCE_M (BIT(7)) 899 #define RTC_CNTL_XTAL32K_XPD_FORCE_V 0x1 900 #define RTC_CNTL_XTAL32K_XPD_FORCE_S 7 901 /* RTC_CNTL_XTAL32K_AUTO_RETURN : R/W ;bitpos:[6] ;default: 1'b0 ; */ 902 /*description: xtal 32k switch back xtal when xtal is restarted*/ 903 #define RTC_CNTL_XTAL32K_AUTO_RETURN (BIT(6)) 904 #define RTC_CNTL_XTAL32K_AUTO_RETURN_M (BIT(6)) 905 #define RTC_CNTL_XTAL32K_AUTO_RETURN_V 0x1 906 #define RTC_CNTL_XTAL32K_AUTO_RETURN_S 6 907 /* RTC_CNTL_XTAL32K_AUTO_RESTART : R/W ;bitpos:[5] ;default: 1'b0 ; */ 908 /*description: xtal 32k restart xtal when xtal is dead*/ 909 #define RTC_CNTL_XTAL32K_AUTO_RESTART (BIT(5)) 910 #define RTC_CNTL_XTAL32K_AUTO_RESTART_M (BIT(5)) 911 #define RTC_CNTL_XTAL32K_AUTO_RESTART_V 0x1 912 #define RTC_CNTL_XTAL32K_AUTO_RESTART_S 5 913 /* RTC_CNTL_XTAL32K_AUTO_BACKUP : R/W ;bitpos:[4] ;default: 1'b0 ; */ 914 /*description: xtal 32k switch to back up clock when xtal is dead*/ 915 #define RTC_CNTL_XTAL32K_AUTO_BACKUP (BIT(4)) 916 #define RTC_CNTL_XTAL32K_AUTO_BACKUP_M (BIT(4)) 917 #define RTC_CNTL_XTAL32K_AUTO_BACKUP_V 0x1 918 #define RTC_CNTL_XTAL32K_AUTO_BACKUP_S 4 919 /* RTC_CNTL_XTAL32K_EXT_CLK_FO : R/W ;bitpos:[3] ;default: 1'b0 ; */ 920 /*description: xtal 32k external xtal clock force on*/ 921 #define RTC_CNTL_XTAL32K_EXT_CLK_FO (BIT(3)) 922 #define RTC_CNTL_XTAL32K_EXT_CLK_FO_M (BIT(3)) 923 #define RTC_CNTL_XTAL32K_EXT_CLK_FO_V 0x1 924 #define RTC_CNTL_XTAL32K_EXT_CLK_FO_S 3 925 /* RTC_CNTL_XTAL32K_WDT_RESET : R/W ;bitpos:[2] ;default: 1'b0 ; */ 926 /*description: xtal 32k watch dog sw reset*/ 927 #define RTC_CNTL_XTAL32K_WDT_RESET (BIT(2)) 928 #define RTC_CNTL_XTAL32K_WDT_RESET_M (BIT(2)) 929 #define RTC_CNTL_XTAL32K_WDT_RESET_V 0x1 930 #define RTC_CNTL_XTAL32K_WDT_RESET_S 2 931 /* RTC_CNTL_XTAL32K_WDT_CLK_FO : R/W ;bitpos:[1] ;default: 1'b0 ; */ 932 /*description: xtal 32k watch dog clock force on*/ 933 #define RTC_CNTL_XTAL32K_WDT_CLK_FO (BIT(1)) 934 #define RTC_CNTL_XTAL32K_WDT_CLK_FO_M (BIT(1)) 935 #define RTC_CNTL_XTAL32K_WDT_CLK_FO_V 0x1 936 #define RTC_CNTL_XTAL32K_WDT_CLK_FO_S 1 937 /* RTC_CNTL_XTAL32K_WDT_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */ 938 /*description: xtal 32k watch dog enable*/ 939 #define RTC_CNTL_XTAL32K_WDT_EN (BIT(0)) 940 #define RTC_CNTL_XTAL32K_WDT_EN_M (BIT(0)) 941 #define RTC_CNTL_XTAL32K_WDT_EN_V 0x1 942 #define RTC_CNTL_XTAL32K_WDT_EN_S 0 943 944 #define RTC_CNTL_EXT_WAKEUP_CONF_REG (DR_REG_RTCCNTL_BASE + 0x0064) 945 /* RTC_CNTL_GPIO_WAKEUP_FILTER : R/W ;bitpos:[31] ;default: 1'b0 ; */ 946 /*description: enable filter for gpio wakeup event*/ 947 #define RTC_CNTL_GPIO_WAKEUP_FILTER (BIT(31)) 948 #define RTC_CNTL_GPIO_WAKEUP_FILTER_M (BIT(31)) 949 #define RTC_CNTL_GPIO_WAKEUP_FILTER_V 0x1 950 #define RTC_CNTL_GPIO_WAKEUP_FILTER_S 31 951 952 #define RTC_CNTL_SLP_REJECT_CONF_REG (DR_REG_RTCCNTL_BASE + 0x0068) 953 /* RTC_CNTL_DEEP_SLP_REJECT_EN : R/W ;bitpos:[31] ;default: 1'b0 ; */ 954 /*description: enable reject for deep sleep*/ 955 #define RTC_CNTL_DEEP_SLP_REJECT_EN (BIT(31)) 956 #define RTC_CNTL_DEEP_SLP_REJECT_EN_M (BIT(31)) 957 #define RTC_CNTL_DEEP_SLP_REJECT_EN_V 0x1 958 #define RTC_CNTL_DEEP_SLP_REJECT_EN_S 31 959 /* RTC_CNTL_LIGHT_SLP_REJECT_EN : R/W ;bitpos:[30] ;default: 1'b0 ; */ 960 /*description: enable reject for light sleep*/ 961 #define RTC_CNTL_LIGHT_SLP_REJECT_EN (BIT(30)) 962 #define RTC_CNTL_LIGHT_SLP_REJECT_EN_M (BIT(30)) 963 #define RTC_CNTL_LIGHT_SLP_REJECT_EN_V 0x1 964 #define RTC_CNTL_LIGHT_SLP_REJECT_EN_S 30 965 /* RTC_CNTL_SLEEP_REJECT_ENA : R/W ;bitpos:[29:12] ;default: 17'd0 ; */ 966 /*description: sleep reject enable*/ 967 #define RTC_CNTL_SLEEP_REJECT_ENA 0x0003FFFF 968 #define RTC_CNTL_SLEEP_REJECT_ENA_M ((RTC_CNTL_SLEEP_REJECT_ENA_V)<<(RTC_CNTL_SLEEP_REJECT_ENA_S)) 969 #define RTC_CNTL_SLEEP_REJECT_ENA_V 0x3FFFF 970 #define RTC_CNTL_SLEEP_REJECT_ENA_S 12 971 972 #define RTC_CNTL_CPU_PERIOD_CONF_REG (DR_REG_RTCCNTL_BASE + 0x006C) 973 /* RTC_CNTL_CPUPERIOD_SEL : R/W ;bitpos:[31:30] ;default: 2'b00 ; */ 974 /*description: */ 975 #define RTC_CNTL_CPUPERIOD_SEL 0x00000003 976 #define RTC_CNTL_CPUPERIOD_SEL_M ((RTC_CNTL_CPUPERIOD_SEL_V)<<(RTC_CNTL_CPUPERIOD_SEL_S)) 977 #define RTC_CNTL_CPUPERIOD_SEL_V 0x3 978 #define RTC_CNTL_CPUPERIOD_SEL_S 30 979 /* RTC_CNTL_CPUSEL_CONF : R/W ;bitpos:[29] ;default: 1'b0 ; */ 980 /*description: CPU sel option*/ 981 #define RTC_CNTL_CPUSEL_CONF (BIT(29)) 982 #define RTC_CNTL_CPUSEL_CONF_M (BIT(29)) 983 #define RTC_CNTL_CPUSEL_CONF_V 0x1 984 #define RTC_CNTL_CPUSEL_CONF_S 29 985 986 #define RTC_CNTL_CLK_CONF_REG (DR_REG_RTCCNTL_BASE + 0x0070) 987 /* RTC_CNTL_ANA_CLK_RTC_SEL : R/W ;bitpos:[31:30] ;default: 2'd0 ; */ 988 /*description: */ 989 #define RTC_CNTL_ANA_CLK_RTC_SEL 0x00000003 990 #define RTC_CNTL_ANA_CLK_RTC_SEL_M ((RTC_CNTL_ANA_CLK_RTC_SEL_V)<<(RTC_CNTL_ANA_CLK_RTC_SEL_S)) 991 #define RTC_CNTL_ANA_CLK_RTC_SEL_V 0x3 992 #define RTC_CNTL_ANA_CLK_RTC_SEL_S 30 993 /* RTC_CNTL_FAST_CLK_RTC_SEL : R/W ;bitpos:[29] ;default: 1'b0 ; */ 994 /*description: fast_clk_rtc sel. 0: XTAL div 2*/ 995 #define RTC_CNTL_FAST_CLK_RTC_SEL (BIT(29)) 996 #define RTC_CNTL_FAST_CLK_RTC_SEL_M (BIT(29)) 997 #define RTC_CNTL_FAST_CLK_RTC_SEL_V 0x1 998 #define RTC_CNTL_FAST_CLK_RTC_SEL_S 29 999 /* RTC_CNTL_XTAL_GLOBAL_FORCE_NOGATING : R/W ;bitpos:[28] ;default: 1'b1 ; */ 1000 /*description: */ 1001 #define RTC_CNTL_XTAL_GLOBAL_FORCE_NOGATING (BIT(28)) 1002 #define RTC_CNTL_XTAL_GLOBAL_FORCE_NOGATING_M (BIT(28)) 1003 #define RTC_CNTL_XTAL_GLOBAL_FORCE_NOGATING_V 0x1 1004 #define RTC_CNTL_XTAL_GLOBAL_FORCE_NOGATING_S 28 1005 /* RTC_CNTL_XTAL_GLOBAL_FORCE_GATING : R/W ;bitpos:[27] ;default: 1'b0 ; */ 1006 /*description: */ 1007 #define RTC_CNTL_XTAL_GLOBAL_FORCE_GATING (BIT(27)) 1008 #define RTC_CNTL_XTAL_GLOBAL_FORCE_GATING_M (BIT(27)) 1009 #define RTC_CNTL_XTAL_GLOBAL_FORCE_GATING_V 0x1 1010 #define RTC_CNTL_XTAL_GLOBAL_FORCE_GATING_S 27 1011 /* RTC_CNTL_CK8M_FORCE_PU : R/W ;bitpos:[26] ;default: 1'd0 ; */ 1012 /*description: CK8M force power up*/ 1013 #define RTC_CNTL_CK8M_FORCE_PU (BIT(26)) 1014 #define RTC_CNTL_CK8M_FORCE_PU_M (BIT(26)) 1015 #define RTC_CNTL_CK8M_FORCE_PU_V 0x1 1016 #define RTC_CNTL_CK8M_FORCE_PU_S 26 1017 /* RTC_CNTL_CK8M_FORCE_PD : R/W ;bitpos:[25] ;default: 1'd0 ; */ 1018 /*description: CK8M force power down*/ 1019 #define RTC_CNTL_CK8M_FORCE_PD (BIT(25)) 1020 #define RTC_CNTL_CK8M_FORCE_PD_M (BIT(25)) 1021 #define RTC_CNTL_CK8M_FORCE_PD_V 0x1 1022 #define RTC_CNTL_CK8M_FORCE_PD_S 25 1023 /* RTC_CNTL_CK8M_DFREQ : R/W ;bitpos:[24:17] ;default: 8'd172 ; */ 1024 /*description: CK8M_DFREQ*/ 1025 #define RTC_CNTL_CK8M_DFREQ 0x000000FF 1026 #define RTC_CNTL_CK8M_DFREQ_M ((RTC_CNTL_CK8M_DFREQ_V)<<(RTC_CNTL_CK8M_DFREQ_S)) 1027 #define RTC_CNTL_CK8M_DFREQ_V 0xFF 1028 #define RTC_CNTL_CK8M_DFREQ_S 17 1029 /* RTC_CNTL_CK8M_FORCE_NOGATING : R/W ;bitpos:[16] ;default: 1'd0 ; */ 1030 /*description: CK8M force no gating during sleep*/ 1031 #define RTC_CNTL_CK8M_FORCE_NOGATING (BIT(16)) 1032 #define RTC_CNTL_CK8M_FORCE_NOGATING_M (BIT(16)) 1033 #define RTC_CNTL_CK8M_FORCE_NOGATING_V 0x1 1034 #define RTC_CNTL_CK8M_FORCE_NOGATING_S 16 1035 /* RTC_CNTL_XTAL_FORCE_NOGATING : R/W ;bitpos:[15] ;default: 1'd0 ; */ 1036 /*description: XTAL force no gating during sleep*/ 1037 #define RTC_CNTL_XTAL_FORCE_NOGATING (BIT(15)) 1038 #define RTC_CNTL_XTAL_FORCE_NOGATING_M (BIT(15)) 1039 #define RTC_CNTL_XTAL_FORCE_NOGATING_V 0x1 1040 #define RTC_CNTL_XTAL_FORCE_NOGATING_S 15 1041 /* RTC_CNTL_CK8M_DIV_SEL : R/W ;bitpos:[14:12] ;default: 3'd3 ; */ 1042 /*description: divider = reg_ck8m_div_sel + 1*/ 1043 #define RTC_CNTL_CK8M_DIV_SEL 0x00000007 1044 #define RTC_CNTL_CK8M_DIV_SEL_M ((RTC_CNTL_CK8M_DIV_SEL_V)<<(RTC_CNTL_CK8M_DIV_SEL_S)) 1045 #define RTC_CNTL_CK8M_DIV_SEL_V 0x7 1046 #define RTC_CNTL_CK8M_DIV_SEL_S 12 1047 /* RTC_CNTL_DIG_CLK8M_EN : R/W ;bitpos:[10] ;default: 1'd0 ; */ 1048 /*description: enable CK8M for digital core (no relationship with RTC core)*/ 1049 #define RTC_CNTL_DIG_CLK8M_EN (BIT(10)) 1050 #define RTC_CNTL_DIG_CLK8M_EN_M (BIT(10)) 1051 #define RTC_CNTL_DIG_CLK8M_EN_V 0x1 1052 #define RTC_CNTL_DIG_CLK8M_EN_S 10 1053 /* RTC_CNTL_DIG_CLK8M_D256_EN : R/W ;bitpos:[9] ;default: 1'd1 ; */ 1054 /*description: enable CK8M_D256_OUT for digital core (no relationship with RTC core)*/ 1055 #define RTC_CNTL_DIG_CLK8M_D256_EN (BIT(9)) 1056 #define RTC_CNTL_DIG_CLK8M_D256_EN_M (BIT(9)) 1057 #define RTC_CNTL_DIG_CLK8M_D256_EN_V 0x1 1058 #define RTC_CNTL_DIG_CLK8M_D256_EN_S 9 1059 /* RTC_CNTL_DIG_XTAL32K_EN : R/W ;bitpos:[8] ;default: 1'd0 ; */ 1060 /*description: enable CK_XTAL_32K for digital core (no relationship with RTC core)*/ 1061 #define RTC_CNTL_DIG_XTAL32K_EN (BIT(8)) 1062 #define RTC_CNTL_DIG_XTAL32K_EN_M (BIT(8)) 1063 #define RTC_CNTL_DIG_XTAL32K_EN_V 0x1 1064 #define RTC_CNTL_DIG_XTAL32K_EN_S 8 1065 /* RTC_CNTL_ENB_CK8M_DIV : R/W ;bitpos:[7] ;default: 1'd0 ; */ 1066 /*description: 1: CK8M_D256_OUT is actually CK8M*/ 1067 #define RTC_CNTL_ENB_CK8M_DIV (BIT(7)) 1068 #define RTC_CNTL_ENB_CK8M_DIV_M (BIT(7)) 1069 #define RTC_CNTL_ENB_CK8M_DIV_V 0x1 1070 #define RTC_CNTL_ENB_CK8M_DIV_S 7 1071 /* RTC_CNTL_ENB_CK8M : R/W ;bitpos:[6] ;default: 1'd0 ; */ 1072 /*description: disable CK8M and CK8M_D256_OUT*/ 1073 #define RTC_CNTL_ENB_CK8M (BIT(6)) 1074 #define RTC_CNTL_ENB_CK8M_M (BIT(6)) 1075 #define RTC_CNTL_ENB_CK8M_V 0x1 1076 #define RTC_CNTL_ENB_CK8M_S 6 1077 /* RTC_CNTL_CK8M_DIV : R/W ;bitpos:[5:4] ;default: 2'b01 ; */ 1078 /*description: CK8M_D256_OUT divider. 00: div128*/ 1079 #define RTC_CNTL_CK8M_DIV 0x00000003 1080 #define RTC_CNTL_CK8M_DIV_M ((RTC_CNTL_CK8M_DIV_V)<<(RTC_CNTL_CK8M_DIV_S)) 1081 #define RTC_CNTL_CK8M_DIV_V 0x3 1082 #define RTC_CNTL_CK8M_DIV_S 4 1083 /* RTC_CNTL_CK8M_DIV_SEL_VLD : R/W ;bitpos:[3] ;default: 1'b1 ; */ 1084 /*description: used to sync reg_ck8m_div_sel bus. Clear vld before set reg_ck8m_div_sel*/ 1085 #define RTC_CNTL_CK8M_DIV_SEL_VLD (BIT(3)) 1086 #define RTC_CNTL_CK8M_DIV_SEL_VLD_M (BIT(3)) 1087 #define RTC_CNTL_CK8M_DIV_SEL_VLD_V 0x1 1088 #define RTC_CNTL_CK8M_DIV_SEL_VLD_S 3 1089 /* RTC_CNTL_EFUSE_CLK_FORCE_NOGATING : R/W ;bitpos:[2] ;default: 1'b0 ; */ 1090 /*description: */ 1091 #define RTC_CNTL_EFUSE_CLK_FORCE_NOGATING (BIT(2)) 1092 #define RTC_CNTL_EFUSE_CLK_FORCE_NOGATING_M (BIT(2)) 1093 #define RTC_CNTL_EFUSE_CLK_FORCE_NOGATING_V 0x1 1094 #define RTC_CNTL_EFUSE_CLK_FORCE_NOGATING_S 2 1095 /* RTC_CNTL_EFUSE_CLK_FORCE_GATING : R/W ;bitpos:[1] ;default: 1'b0 ; */ 1096 /*description: */ 1097 #define RTC_CNTL_EFUSE_CLK_FORCE_GATING (BIT(1)) 1098 #define RTC_CNTL_EFUSE_CLK_FORCE_GATING_M (BIT(1)) 1099 #define RTC_CNTL_EFUSE_CLK_FORCE_GATING_V 0x1 1100 #define RTC_CNTL_EFUSE_CLK_FORCE_GATING_S 1 1101 1102 #define RTC_CNTL_SLOW_CLK_CONF_REG (DR_REG_RTCCNTL_BASE + 0x0074) 1103 /* RTC_CNTL_SLOW_CLK_NEXT_EDGE : R/W ;bitpos:[31] ;default: 1'b0 ; */ 1104 /*description: */ 1105 #define RTC_CNTL_SLOW_CLK_NEXT_EDGE (BIT(31)) 1106 #define RTC_CNTL_SLOW_CLK_NEXT_EDGE_M (BIT(31)) 1107 #define RTC_CNTL_SLOW_CLK_NEXT_EDGE_V 0x1 1108 #define RTC_CNTL_SLOW_CLK_NEXT_EDGE_S 31 1109 /* RTC_CNTL_ANA_CLK_DIV : R/W ;bitpos:[30:23] ;default: 8'd0 ; */ 1110 /*description: */ 1111 #define RTC_CNTL_ANA_CLK_DIV 0x000000FF 1112 #define RTC_CNTL_ANA_CLK_DIV_M ((RTC_CNTL_ANA_CLK_DIV_V)<<(RTC_CNTL_ANA_CLK_DIV_S)) 1113 #define RTC_CNTL_ANA_CLK_DIV_V 0xFF 1114 #define RTC_CNTL_ANA_CLK_DIV_S 23 1115 /* RTC_CNTL_ANA_CLK_DIV_VLD : R/W ;bitpos:[22] ;default: 1'b1 ; */ 1116 /*description: used to sync div bus. clear vld before set reg_rtc_ana_clk_div*/ 1117 #define RTC_CNTL_ANA_CLK_DIV_VLD (BIT(22)) 1118 #define RTC_CNTL_ANA_CLK_DIV_VLD_M (BIT(22)) 1119 #define RTC_CNTL_ANA_CLK_DIV_VLD_V 0x1 1120 #define RTC_CNTL_ANA_CLK_DIV_VLD_S 22 1121 1122 #define RTC_CNTL_SDIO_CONF_REG (DR_REG_RTCCNTL_BASE + 0x0078) 1123 /* RTC_CNTL_XPD_SDIO_REG : R/W ;bitpos:[31] ;default: 1'd0 ; */ 1124 /*description: */ 1125 #define RTC_CNTL_XPD_SDIO_REG (BIT(31)) 1126 #define RTC_CNTL_XPD_SDIO_REG_M (BIT(31)) 1127 #define RTC_CNTL_XPD_SDIO_REG_V 0x1 1128 #define RTC_CNTL_XPD_SDIO_REG_S 31 1129 /* RTC_CNTL_DREFH_SDIO : R/W ;bitpos:[30:29] ;default: 2'b00 ; */ 1130 /*description: SW option for DREFH_SDIO. Only active when reg_sdio_force = 1*/ 1131 #define RTC_CNTL_DREFH_SDIO 0x00000003 1132 #define RTC_CNTL_DREFH_SDIO_M ((RTC_CNTL_DREFH_SDIO_V)<<(RTC_CNTL_DREFH_SDIO_S)) 1133 #define RTC_CNTL_DREFH_SDIO_V 0x3 1134 #define RTC_CNTL_DREFH_SDIO_S 29 1135 /* RTC_CNTL_DREFM_SDIO : R/W ;bitpos:[28:27] ;default: 2'b01 ; */ 1136 /*description: SW option for DREFM_SDIO. Only active when reg_sdio_force = 1*/ 1137 #define RTC_CNTL_DREFM_SDIO 0x00000003 1138 #define RTC_CNTL_DREFM_SDIO_M ((RTC_CNTL_DREFM_SDIO_V)<<(RTC_CNTL_DREFM_SDIO_S)) 1139 #define RTC_CNTL_DREFM_SDIO_V 0x3 1140 #define RTC_CNTL_DREFM_SDIO_S 27 1141 /* RTC_CNTL_DREFL_SDIO : R/W ;bitpos:[26:25] ;default: 2'b01 ; */ 1142 /*description: SW option for DREFL_SDIO. Only active when reg_sdio_force = 1*/ 1143 #define RTC_CNTL_DREFL_SDIO 0x00000003 1144 #define RTC_CNTL_DREFL_SDIO_M ((RTC_CNTL_DREFL_SDIO_V)<<(RTC_CNTL_DREFL_SDIO_S)) 1145 #define RTC_CNTL_DREFL_SDIO_V 0x3 1146 #define RTC_CNTL_DREFL_SDIO_S 25 1147 /* RTC_CNTL_REG1P8_READY : RO ;bitpos:[24] ;default: 1'd0 ; */ 1148 /*description: read only register for REG1P8_READY*/ 1149 #define RTC_CNTL_REG1P8_READY (BIT(24)) 1150 #define RTC_CNTL_REG1P8_READY_M (BIT(24)) 1151 #define RTC_CNTL_REG1P8_READY_V 0x1 1152 #define RTC_CNTL_REG1P8_READY_S 24 1153 /* RTC_CNTL_SDIO_TIEH : R/W ;bitpos:[23] ;default: 1'd1 ; */ 1154 /*description: SW option for SDIO_TIEH. Only active when reg_sdio_force = 1*/ 1155 #define RTC_CNTL_SDIO_TIEH (BIT(23)) 1156 #define RTC_CNTL_SDIO_TIEH_M (BIT(23)) 1157 #define RTC_CNTL_SDIO_TIEH_V 0x1 1158 #define RTC_CNTL_SDIO_TIEH_S 23 1159 /* RTC_CNTL_SDIO_FORCE : R/W ;bitpos:[22] ;default: 1'd0 ; */ 1160 /*description: 1: use SW option to control SDIO_REG*/ 1161 #define RTC_CNTL_SDIO_FORCE (BIT(22)) 1162 #define RTC_CNTL_SDIO_FORCE_M (BIT(22)) 1163 #define RTC_CNTL_SDIO_FORCE_V 0x1 1164 #define RTC_CNTL_SDIO_FORCE_S 22 1165 /* RTC_CNTL_SDIO_PD_EN : R/W ;bitpos:[21] ;default: 1'd1 ; */ 1166 /*description: power down SDIO_REG in sleep. Only active when reg_sdio_force = 0*/ 1167 #define RTC_CNTL_SDIO_PD_EN (BIT(21)) 1168 #define RTC_CNTL_SDIO_PD_EN_M (BIT(21)) 1169 #define RTC_CNTL_SDIO_PD_EN_V 0x1 1170 #define RTC_CNTL_SDIO_PD_EN_S 21 1171 /* RTC_CNTL_SDIO_ENCURLIM : R/W ;bitpos:[20] ;default: 1'd1 ; */ 1172 /*description: enable current limit*/ 1173 #define RTC_CNTL_SDIO_ENCURLIM (BIT(20)) 1174 #define RTC_CNTL_SDIO_ENCURLIM_M (BIT(20)) 1175 #define RTC_CNTL_SDIO_ENCURLIM_V 0x1 1176 #define RTC_CNTL_SDIO_ENCURLIM_S 20 1177 /* RTC_CNTL_SDIO_MODECURLIM : R/W ;bitpos:[19] ;default: 1'd0 ; */ 1178 /*description: select current limit mode*/ 1179 #define RTC_CNTL_SDIO_MODECURLIM (BIT(19)) 1180 #define RTC_CNTL_SDIO_MODECURLIM_M (BIT(19)) 1181 #define RTC_CNTL_SDIO_MODECURLIM_V 0x1 1182 #define RTC_CNTL_SDIO_MODECURLIM_S 19 1183 /* RTC_CNTL_SDIO_DCURLIM : R/W ;bitpos:[18:16] ;default: 3'd0 ; */ 1184 /*description: tune current limit threshold when tieh = 0. About 800mA/(8+d)*/ 1185 #define RTC_CNTL_SDIO_DCURLIM 0x00000007 1186 #define RTC_CNTL_SDIO_DCURLIM_M ((RTC_CNTL_SDIO_DCURLIM_V)<<(RTC_CNTL_SDIO_DCURLIM_S)) 1187 #define RTC_CNTL_SDIO_DCURLIM_V 0x7 1188 #define RTC_CNTL_SDIO_DCURLIM_S 16 1189 /* RTC_CNTL_SDIO_EN_INITI : R/W ;bitpos:[15] ;default: 1'd1 ; */ 1190 /*description: 0 to set init[1:0]=0*/ 1191 #define RTC_CNTL_SDIO_EN_INITI (BIT(15)) 1192 #define RTC_CNTL_SDIO_EN_INITI_M (BIT(15)) 1193 #define RTC_CNTL_SDIO_EN_INITI_V 0x1 1194 #define RTC_CNTL_SDIO_EN_INITI_S 15 1195 /* RTC_CNTL_SDIO_INITI : R/W ;bitpos:[14:13] ;default: 2'd1 ; */ 1196 /*description: add resistor from ldo output to ground. 0: no res*/ 1197 #define RTC_CNTL_SDIO_INITI 0x00000003 1198 #define RTC_CNTL_SDIO_INITI_M ((RTC_CNTL_SDIO_INITI_V)<<(RTC_CNTL_SDIO_INITI_S)) 1199 #define RTC_CNTL_SDIO_INITI_V 0x3 1200 #define RTC_CNTL_SDIO_INITI_S 13 1201 /* RTC_CNTL_SDIO_DCAP : R/W ;bitpos:[12:11] ;default: 2'b11 ; */ 1202 /*description: ability to prevent LDO from overshoot*/ 1203 #define RTC_CNTL_SDIO_DCAP 0x00000003 1204 #define RTC_CNTL_SDIO_DCAP_M ((RTC_CNTL_SDIO_DCAP_V)<<(RTC_CNTL_SDIO_DCAP_S)) 1205 #define RTC_CNTL_SDIO_DCAP_V 0x3 1206 #define RTC_CNTL_SDIO_DCAP_S 11 1207 /* RTC_CNTL_SDIO_DTHDRV : R/W ;bitpos:[10:9] ;default: 2'b11 ; */ 1208 /*description: Tieh = 1 mode drive ability. Initially set to 0 to limit charge current*/ 1209 #define RTC_CNTL_SDIO_DTHDRV 0x00000003 1210 #define RTC_CNTL_SDIO_DTHDRV_M ((RTC_CNTL_SDIO_DTHDRV_V)<<(RTC_CNTL_SDIO_DTHDRV_S)) 1211 #define RTC_CNTL_SDIO_DTHDRV_V 0x3 1212 #define RTC_CNTL_SDIO_DTHDRV_S 9 1213 /* RTC_CNTL_SDIO_TIMER_TARGET : R/W ;bitpos:[7:0] ;default: 8'd10 ; */ 1214 /*description: timer count to apply reg_sdio_dcap after sdio power on*/ 1215 #define RTC_CNTL_SDIO_TIMER_TARGET 0x000000FF 1216 #define RTC_CNTL_SDIO_TIMER_TARGET_M ((RTC_CNTL_SDIO_TIMER_TARGET_V)<<(RTC_CNTL_SDIO_TIMER_TARGET_S)) 1217 #define RTC_CNTL_SDIO_TIMER_TARGET_V 0xFF 1218 #define RTC_CNTL_SDIO_TIMER_TARGET_S 0 1219 1220 #define RTC_CNTL_BIAS_CONF_REG (DR_REG_RTCCNTL_BASE + 0x007C) 1221 /* RTC_CNTL_DBG_ATTEN_MONITOR : R/W ;bitpos:[25:22] ;default: 4'd0 ; */ 1222 /*description: DBG_ATTEN when rtc in monitor state*/ 1223 #define RTC_CNTL_DBG_ATTEN_MONITOR 0x0000000F 1224 #define RTC_CNTL_DBG_ATTEN_MONITOR_M ((RTC_CNTL_DBG_ATTEN_MONITOR_V)<<(RTC_CNTL_DBG_ATTEN_MONITOR_S)) 1225 #define RTC_CNTL_DBG_ATTEN_MONITOR_V 0xF 1226 #define RTC_CNTL_DBG_ATTEN_MONITOR_S 22 1227 /* RTC_CNTL_DBG_ATTEN_DEEP_SLP : R/W ;bitpos:[21:18] ;default: 4'd0 ; */ 1228 /*description: DBG_ATTEN when rtc in sleep state*/ 1229 #define RTC_CNTL_DBG_ATTEN_DEEP_SLP 0x0000000F 1230 #define RTC_CNTL_DBG_ATTEN_DEEP_SLP_M ((RTC_CNTL_DBG_ATTEN_DEEP_SLP_V)<<(RTC_CNTL_DBG_ATTEN_DEEP_SLP_S)) 1231 #define RTC_CNTL_DBG_ATTEN_DEEP_SLP_V 0xF 1232 #define RTC_CNTL_DBG_ATTEN_DEEP_SLP_S 18 1233 /* RTC_CNTL_BIAS_SLEEP_MONITOR : R/W ;bitpos:[17] ;default: 1'b0 ; */ 1234 /*description: bias_sleep when rtc in monitor state*/ 1235 #define RTC_CNTL_BIAS_SLEEP_MONITOR (BIT(17)) 1236 #define RTC_CNTL_BIAS_SLEEP_MONITOR_M (BIT(17)) 1237 #define RTC_CNTL_BIAS_SLEEP_MONITOR_V 0x1 1238 #define RTC_CNTL_BIAS_SLEEP_MONITOR_S 17 1239 /* RTC_CNTL_BIAS_SLEEP_DEEP_SLP : R/W ;bitpos:[16] ;default: 1'b1 ; */ 1240 /*description: bias_sleep when rtc in sleep_state*/ 1241 #define RTC_CNTL_BIAS_SLEEP_DEEP_SLP (BIT(16)) 1242 #define RTC_CNTL_BIAS_SLEEP_DEEP_SLP_M (BIT(16)) 1243 #define RTC_CNTL_BIAS_SLEEP_DEEP_SLP_V 0x1 1244 #define RTC_CNTL_BIAS_SLEEP_DEEP_SLP_S 16 1245 /* RTC_CNTL_PD_CUR_MONITOR : R/W ;bitpos:[15] ;default: 1'b0 ; */ 1246 /*description: xpd cur when rtc in monitor state*/ 1247 #define RTC_CNTL_PD_CUR_MONITOR (BIT(15)) 1248 #define RTC_CNTL_PD_CUR_MONITOR_M (BIT(15)) 1249 #define RTC_CNTL_PD_CUR_MONITOR_V 0x1 1250 #define RTC_CNTL_PD_CUR_MONITOR_S 15 1251 /* RTC_CNTL_PD_CUR_DEEP_SLP : R/W ;bitpos:[14] ;default: 1'b0 ; */ 1252 /*description: xpd cur when rtc in sleep_state*/ 1253 #define RTC_CNTL_PD_CUR_DEEP_SLP (BIT(14)) 1254 #define RTC_CNTL_PD_CUR_DEEP_SLP_M (BIT(14)) 1255 #define RTC_CNTL_PD_CUR_DEEP_SLP_V 0x1 1256 #define RTC_CNTL_PD_CUR_DEEP_SLP_S 14 1257 /* RTC_CNTL_BIAS_BUF_MONITOR : R/W ;bitpos:[13] ;default: 1'b0 ; */ 1258 /*description: */ 1259 #define RTC_CNTL_BIAS_BUF_MONITOR (BIT(13)) 1260 #define RTC_CNTL_BIAS_BUF_MONITOR_M (BIT(13)) 1261 #define RTC_CNTL_BIAS_BUF_MONITOR_V 0x1 1262 #define RTC_CNTL_BIAS_BUF_MONITOR_S 13 1263 /* RTC_CNTL_BIAS_BUF_DEEP_SLP : R/W ;bitpos:[12] ;default: 1'b0 ; */ 1264 /*description: */ 1265 #define RTC_CNTL_BIAS_BUF_DEEP_SLP (BIT(12)) 1266 #define RTC_CNTL_BIAS_BUF_DEEP_SLP_M (BIT(12)) 1267 #define RTC_CNTL_BIAS_BUF_DEEP_SLP_V 0x1 1268 #define RTC_CNTL_BIAS_BUF_DEEP_SLP_S 12 1269 /* RTC_CNTL_BIAS_BUF_WAKE : R/W ;bitpos:[11] ;default: 1'b1 ; */ 1270 /*description: */ 1271 #define RTC_CNTL_BIAS_BUF_WAKE (BIT(11)) 1272 #define RTC_CNTL_BIAS_BUF_WAKE_M (BIT(11)) 1273 #define RTC_CNTL_BIAS_BUF_WAKE_V 0x1 1274 #define RTC_CNTL_BIAS_BUF_WAKE_S 11 1275 /* RTC_CNTL_BIAS_BUF_IDLE : R/W ;bitpos:[10] ;default: 1'b0 ; */ 1276 /*description: */ 1277 #define RTC_CNTL_BIAS_BUF_IDLE (BIT(10)) 1278 #define RTC_CNTL_BIAS_BUF_IDLE_M (BIT(10)) 1279 #define RTC_CNTL_BIAS_BUF_IDLE_V 0x1 1280 #define RTC_CNTL_BIAS_BUF_IDLE_S 10 1281 /* RTC_CNTL_DG_VDD_DRV_B_SLP_EN : R/W ;bitpos:[8] ;default: 1'b0 ; */ 1282 /*description: */ 1283 #define RTC_CNTL_DG_VDD_DRV_B_SLP_EN (BIT(8)) 1284 #define RTC_CNTL_DG_VDD_DRV_B_SLP_EN_M (BIT(8)) 1285 #define RTC_CNTL_DG_VDD_DRV_B_SLP_EN_V 0x1 1286 #define RTC_CNTL_DG_VDD_DRV_B_SLP_EN_S 8 1287 /* RTC_CNTL_DG_VDD_DRV_B_SLP : R/W ;bitpos:[7:0] ;default: 8'h0 ; */ 1288 /*description: */ 1289 #define RTC_CNTL_DG_VDD_DRV_B_SLP 0x000000FF 1290 #define RTC_CNTL_DG_VDD_DRV_B_SLP_M ((RTC_CNTL_DG_VDD_DRV_B_SLP_V)<<(RTC_CNTL_DG_VDD_DRV_B_SLP_S)) 1291 #define RTC_CNTL_DG_VDD_DRV_B_SLP_V 0xFF 1292 #define RTC_CNTL_DG_VDD_DRV_B_SLP_S 0 1293 1294 #define RTC_CNTL_REG (DR_REG_RTCCNTL_BASE + 0x0080) 1295 /* RTC_CNTL_REGULATOR_FORCE_PU : R/W ;bitpos:[31] ;default: 1'd1 ; */ 1296 /*description: */ 1297 #define RTC_CNTL_REGULATOR_FORCE_PU (BIT(31)) 1298 #define RTC_CNTL_REGULATOR_FORCE_PU_M (BIT(31)) 1299 #define RTC_CNTL_REGULATOR_FORCE_PU_V 0x1 1300 #define RTC_CNTL_REGULATOR_FORCE_PU_S 31 1301 /* RTC_CNTL_REGULATOR_FORCE_PD : R/W ;bitpos:[30] ;default: 1'd0 ; */ 1302 /*description: RTC_REG force power down (for RTC_REG power down means decrease 1303 the voltage to 0.8v or lower )*/ 1304 #define RTC_CNTL_REGULATOR_FORCE_PD (BIT(30)) 1305 #define RTC_CNTL_REGULATOR_FORCE_PD_M (BIT(30)) 1306 #define RTC_CNTL_REGULATOR_FORCE_PD_V 0x1 1307 #define RTC_CNTL_REGULATOR_FORCE_PD_S 30 1308 /* RTC_CNTL_DBOOST_FORCE_PU : R/W ;bitpos:[29] ;default: 1'd1 ; */ 1309 /*description: RTC_DBOOST force power up*/ 1310 #define RTC_CNTL_DBOOST_FORCE_PU (BIT(29)) 1311 #define RTC_CNTL_DBOOST_FORCE_PU_M (BIT(29)) 1312 #define RTC_CNTL_DBOOST_FORCE_PU_V 0x1 1313 #define RTC_CNTL_DBOOST_FORCE_PU_S 29 1314 /* RTC_CNTL_DBOOST_FORCE_PD : R/W ;bitpos:[28] ;default: 1'd0 ; */ 1315 /*description: RTC_DBOOST force power down*/ 1316 #define RTC_CNTL_DBOOST_FORCE_PD (BIT(28)) 1317 #define RTC_CNTL_DBOOST_FORCE_PD_M (BIT(28)) 1318 #define RTC_CNTL_DBOOST_FORCE_PD_V 0x1 1319 #define RTC_CNTL_DBOOST_FORCE_PD_S 28 1320 1321 /* RTC_CNTL_SCK_DCAP : R/W ;bitpos:[21:14] ;default: 8'd0 ; */ 1322 /*description: SCK_DCAP*/ 1323 #define RTC_CNTL_SCK_DCAP 0x000000FF 1324 #define RTC_CNTL_SCK_DCAP_M ((RTC_CNTL_SCK_DCAP_V)<<(RTC_CNTL_SCK_DCAP_S)) 1325 #define RTC_CNTL_SCK_DCAP_V 0xFF 1326 #define RTC_CNTL_SCK_DCAP_S 14 1327 #define RTC_CNTL_SCK_DCAP_DEFAULT 255 1328 /* RTC_CNTL_DIG_CAL_EN : R/W ;bitpos:[7] ;default: 1'b0 ; */ 1329 /*description: */ 1330 #define RTC_CNTL_DIG_CAL_EN (BIT(7)) 1331 #define RTC_CNTL_DIG_CAL_EN_M (BIT(7)) 1332 #define RTC_CNTL_DIG_CAL_EN_V 0x1 1333 #define RTC_CNTL_DIG_CAL_EN_S 7 1334 1335 #define RTC_CNTL_PWC_REG (DR_REG_RTCCNTL_BASE + 0x0084) 1336 /* RTC_CNTL_PAD_FORCE_HOLD : R/W ;bitpos:[21] ;default: 1'd0 ; */ 1337 /*description: rtc pad force hold*/ 1338 #define RTC_CNTL_PAD_FORCE_HOLD (BIT(21)) 1339 #define RTC_CNTL_PAD_FORCE_HOLD_M (BIT(21)) 1340 #define RTC_CNTL_PAD_FORCE_HOLD_V 0x1 1341 #define RTC_CNTL_PAD_FORCE_HOLD_S 21 1342 1343 #define RTC_CNTL_DIG_PWC_REG (DR_REG_RTCCNTL_BASE + 0x0088) 1344 /* RTC_CNTL_DG_WRAP_PD_EN : R/W ;bitpos:[31] ;default: 1'b0 ; */ 1345 /*description: */ 1346 #define RTC_CNTL_DG_WRAP_PD_EN (BIT(31)) 1347 #define RTC_CNTL_DG_WRAP_PD_EN_M (BIT(31)) 1348 #define RTC_CNTL_DG_WRAP_PD_EN_V 0x1 1349 #define RTC_CNTL_DG_WRAP_PD_EN_S 31 1350 /* RTC_CNTL_WIFI_PD_EN : R/W ;bitpos:[30] ;default: 1'b0 ; */ 1351 /*description: enable power down wifi in sleep*/ 1352 #define RTC_CNTL_WIFI_PD_EN (BIT(30)) 1353 #define RTC_CNTL_WIFI_PD_EN_M (BIT(30)) 1354 #define RTC_CNTL_WIFI_PD_EN_V 0x1 1355 #define RTC_CNTL_WIFI_PD_EN_S 30 1356 /* RTC_CNTL_CPU_TOP_PD_EN : R/W ;bitpos:[29] ;default: 1'b0 ; */ 1357 /*description: */ 1358 #define RTC_CNTL_CPU_TOP_PD_EN (BIT(29)) 1359 #define RTC_CNTL_CPU_TOP_PD_EN_M (BIT(29)) 1360 #define RTC_CNTL_CPU_TOP_PD_EN_V 0x1 1361 #define RTC_CNTL_CPU_TOP_PD_EN_S 29 1362 /* RTC_CNTL_DG_PERI_PD_EN : R/W ;bitpos:[28] ;default: 1'b0 ; */ 1363 /*description: */ 1364 #define RTC_CNTL_DG_PERI_PD_EN (BIT(28)) 1365 #define RTC_CNTL_DG_PERI_PD_EN_M (BIT(28)) 1366 #define RTC_CNTL_DG_PERI_PD_EN_V 0x1 1367 #define RTC_CNTL_DG_PERI_PD_EN_S 28 1368 /* RTC_CNTL_BT_PD_EN : R/W ;bitpos:[27] ;default: 1'b0 ; */ 1369 /*description: */ 1370 #define RTC_CNTL_BT_PD_EN (BIT(27)) 1371 #define RTC_CNTL_BT_PD_EN_M (BIT(27)) 1372 #define RTC_CNTL_BT_PD_EN_V 0x1 1373 #define RTC_CNTL_BT_PD_EN_S 27 1374 /* RTC_CNTL_CPU_TOP_FORCE_PU : R/W ;bitpos:[22] ;default: 1'b1 ; */ 1375 /*description: */ 1376 #define RTC_CNTL_CPU_TOP_FORCE_PU (BIT(22)) 1377 #define RTC_CNTL_CPU_TOP_FORCE_PU_M (BIT(22)) 1378 #define RTC_CNTL_CPU_TOP_FORCE_PU_V 0x1 1379 #define RTC_CNTL_CPU_TOP_FORCE_PU_S 22 1380 /* RTC_CNTL_CPU_TOP_FORCE_PD : R/W ;bitpos:[21] ;default: 1'b0 ; */ 1381 /*description: */ 1382 #define RTC_CNTL_CPU_TOP_FORCE_PD (BIT(21)) 1383 #define RTC_CNTL_CPU_TOP_FORCE_PD_M (BIT(21)) 1384 #define RTC_CNTL_CPU_TOP_FORCE_PD_V 0x1 1385 #define RTC_CNTL_CPU_TOP_FORCE_PD_S 21 1386 /* RTC_CNTL_DG_WRAP_FORCE_PU : R/W ;bitpos:[20] ;default: 1'd1 ; */ 1387 /*description: digital core force power up*/ 1388 #define RTC_CNTL_DG_WRAP_FORCE_PU (BIT(20)) 1389 #define RTC_CNTL_DG_WRAP_FORCE_PU_M (BIT(20)) 1390 #define RTC_CNTL_DG_WRAP_FORCE_PU_V 0x1 1391 #define RTC_CNTL_DG_WRAP_FORCE_PU_S 20 1392 /* RTC_CNTL_DG_WRAP_FORCE_PD : R/W ;bitpos:[19] ;default: 1'b0 ; */ 1393 /*description: digital core force power down*/ 1394 #define RTC_CNTL_DG_WRAP_FORCE_PD (BIT(19)) 1395 #define RTC_CNTL_DG_WRAP_FORCE_PD_M (BIT(19)) 1396 #define RTC_CNTL_DG_WRAP_FORCE_PD_V 0x1 1397 #define RTC_CNTL_DG_WRAP_FORCE_PD_S 19 1398 /* RTC_CNTL_WIFI_FORCE_PU : R/W ;bitpos:[18] ;default: 1'd1 ; */ 1399 /*description: wifi force power up*/ 1400 #define RTC_CNTL_WIFI_FORCE_PU (BIT(18)) 1401 #define RTC_CNTL_WIFI_FORCE_PU_M (BIT(18)) 1402 #define RTC_CNTL_WIFI_FORCE_PU_V 0x1 1403 #define RTC_CNTL_WIFI_FORCE_PU_S 18 1404 /* RTC_CNTL_WIFI_FORCE_PD : R/W ;bitpos:[17] ;default: 1'b0 ; */ 1405 /*description: wifi force power down*/ 1406 #define RTC_CNTL_WIFI_FORCE_PD (BIT(17)) 1407 #define RTC_CNTL_WIFI_FORCE_PD_M (BIT(17)) 1408 #define RTC_CNTL_WIFI_FORCE_PD_V 0x1 1409 #define RTC_CNTL_WIFI_FORCE_PD_S 17 1410 /* RTC_CNTL_FASTMEM_FORCE_LPU : R/W ;bitpos:[16] ;default: 1'b1 ; */ 1411 /*description: */ 1412 #define RTC_CNTL_FASTMEM_FORCE_LPU (BIT(16)) 1413 #define RTC_CNTL_FASTMEM_FORCE_LPU_M (BIT(16)) 1414 #define RTC_CNTL_FASTMEM_FORCE_LPU_V 0x1 1415 #define RTC_CNTL_FASTMEM_FORCE_LPU_S 16 1416 /* RTC_CNTL_FASTMEM_FORCE_LPD : R/W ;bitpos:[15] ;default: 1'b0 ; */ 1417 /*description: */ 1418 #define RTC_CNTL_FASTMEM_FORCE_LPD (BIT(15)) 1419 #define RTC_CNTL_FASTMEM_FORCE_LPD_M (BIT(15)) 1420 #define RTC_CNTL_FASTMEM_FORCE_LPD_V 0x1 1421 #define RTC_CNTL_FASTMEM_FORCE_LPD_S 15 1422 /* RTC_CNTL_DG_PERI_FORCE_PU : R/W ;bitpos:[14] ;default: 1'b1 ; */ 1423 /*description: */ 1424 #define RTC_CNTL_DG_PERI_FORCE_PU (BIT(14)) 1425 #define RTC_CNTL_DG_PERI_FORCE_PU_M (BIT(14)) 1426 #define RTC_CNTL_DG_PERI_FORCE_PU_V 0x1 1427 #define RTC_CNTL_DG_PERI_FORCE_PU_S 14 1428 /* RTC_CNTL_DG_PERI_FORCE_PD : R/W ;bitpos:[13] ;default: 1'b0 ; */ 1429 /*description: */ 1430 #define RTC_CNTL_DG_PERI_FORCE_PD (BIT(13)) 1431 #define RTC_CNTL_DG_PERI_FORCE_PD_M (BIT(13)) 1432 #define RTC_CNTL_DG_PERI_FORCE_PD_V 0x1 1433 #define RTC_CNTL_DG_PERI_FORCE_PD_S 13 1434 /* RTC_CNTL_BT_FORCE_PU : R/W ;bitpos:[12] ;default: 1'd1 ; */ 1435 /*description: */ 1436 #define RTC_CNTL_BT_FORCE_PU (BIT(12)) 1437 #define RTC_CNTL_BT_FORCE_PU_M (BIT(12)) 1438 #define RTC_CNTL_BT_FORCE_PU_V 0x1 1439 #define RTC_CNTL_BT_FORCE_PU_S 12 1440 /* RTC_CNTL_BT_FORCE_PD : R/W ;bitpos:[11] ;default: 1'b0 ; */ 1441 /*description: */ 1442 #define RTC_CNTL_BT_FORCE_PD (BIT(11)) 1443 #define RTC_CNTL_BT_FORCE_PD_M (BIT(11)) 1444 #define RTC_CNTL_BT_FORCE_PD_V 0x1 1445 #define RTC_CNTL_BT_FORCE_PD_S 11 1446 /* RTC_CNTL_LSLP_MEM_FORCE_PU : R/W ;bitpos:[4] ;default: 1'b1 ; */ 1447 /*description: memories in digital core force no PD in sleep*/ 1448 #define RTC_CNTL_LSLP_MEM_FORCE_PU (BIT(4)) 1449 #define RTC_CNTL_LSLP_MEM_FORCE_PU_M (BIT(4)) 1450 #define RTC_CNTL_LSLP_MEM_FORCE_PU_V 0x1 1451 #define RTC_CNTL_LSLP_MEM_FORCE_PU_S 4 1452 /* RTC_CNTL_LSLP_MEM_FORCE_PD : R/W ;bitpos:[3] ;default: 1'b0 ; */ 1453 /*description: memories in digital core force PD in sleep*/ 1454 #define RTC_CNTL_LSLP_MEM_FORCE_PD (BIT(3)) 1455 #define RTC_CNTL_LSLP_MEM_FORCE_PD_M (BIT(3)) 1456 #define RTC_CNTL_LSLP_MEM_FORCE_PD_V 0x1 1457 #define RTC_CNTL_LSLP_MEM_FORCE_PD_S 3 1458 /* RTC_CNTL_VDD_SPI_PWR_FORCE : R/W ;bitpos:[2] ;default: 1'b0 ; */ 1459 /*description: */ 1460 #define RTC_CNTL_VDD_SPI_PWR_FORCE (BIT(2)) 1461 #define RTC_CNTL_VDD_SPI_PWR_FORCE_M (BIT(2)) 1462 #define RTC_CNTL_VDD_SPI_PWR_FORCE_V 0x1 1463 #define RTC_CNTL_VDD_SPI_PWR_FORCE_S 2 1464 /* RTC_CNTL_VDD_SPI_PWR_DRV : R/W ;bitpos:[1:0] ;default: 2'b0 ; */ 1465 /*description: */ 1466 #define RTC_CNTL_VDD_SPI_PWR_DRV 0x00000003 1467 #define RTC_CNTL_VDD_SPI_PWR_DRV_M ((RTC_CNTL_VDD_SPI_PWR_DRV_V)<<(RTC_CNTL_VDD_SPI_PWR_DRV_S)) 1468 #define RTC_CNTL_VDD_SPI_PWR_DRV_V 0x3 1469 #define RTC_CNTL_VDD_SPI_PWR_DRV_S 0 1470 1471 #define RTC_CNTL_DIG_ISO_REG (DR_REG_RTCCNTL_BASE + 0x008C) 1472 /* RTC_CNTL_DG_WRAP_FORCE_NOISO : R/W ;bitpos:[31] ;default: 1'd1 ; */ 1473 /*description: */ 1474 #define RTC_CNTL_DG_WRAP_FORCE_NOISO (BIT(31)) 1475 #define RTC_CNTL_DG_WRAP_FORCE_NOISO_M (BIT(31)) 1476 #define RTC_CNTL_DG_WRAP_FORCE_NOISO_V 0x1 1477 #define RTC_CNTL_DG_WRAP_FORCE_NOISO_S 31 1478 /* RTC_CNTL_DG_WRAP_FORCE_ISO : R/W ;bitpos:[30] ;default: 1'd0 ; */ 1479 /*description: digital core force ISO*/ 1480 #define RTC_CNTL_DG_WRAP_FORCE_ISO (BIT(30)) 1481 #define RTC_CNTL_DG_WRAP_FORCE_ISO_M (BIT(30)) 1482 #define RTC_CNTL_DG_WRAP_FORCE_ISO_V 0x1 1483 #define RTC_CNTL_DG_WRAP_FORCE_ISO_S 30 1484 /* RTC_CNTL_WIFI_FORCE_NOISO : R/W ;bitpos:[29] ;default: 1'd1 ; */ 1485 /*description: wifi force no ISO*/ 1486 #define RTC_CNTL_WIFI_FORCE_NOISO (BIT(29)) 1487 #define RTC_CNTL_WIFI_FORCE_NOISO_M (BIT(29)) 1488 #define RTC_CNTL_WIFI_FORCE_NOISO_V 0x1 1489 #define RTC_CNTL_WIFI_FORCE_NOISO_S 29 1490 /* RTC_CNTL_WIFI_FORCE_ISO : R/W ;bitpos:[28] ;default: 1'd0 ; */ 1491 /*description: wifi force ISO*/ 1492 #define RTC_CNTL_WIFI_FORCE_ISO (BIT(28)) 1493 #define RTC_CNTL_WIFI_FORCE_ISO_M (BIT(28)) 1494 #define RTC_CNTL_WIFI_FORCE_ISO_V 0x1 1495 #define RTC_CNTL_WIFI_FORCE_ISO_S 28 1496 /* RTC_CNTL_CPU_TOP_FORCE_NOISO : R/W ;bitpos:[27] ;default: 1'd1 ; */ 1497 /*description: cpu force no ISO*/ 1498 #define RTC_CNTL_CPU_TOP_FORCE_NOISO (BIT(27)) 1499 #define RTC_CNTL_CPU_TOP_FORCE_NOISO_M (BIT(27)) 1500 #define RTC_CNTL_CPU_TOP_FORCE_NOISO_V 0x1 1501 #define RTC_CNTL_CPU_TOP_FORCE_NOISO_S 27 1502 /* RTC_CNTL_CPU_TOP_FORCE_ISO : R/W ;bitpos:[26] ;default: 1'd0 ; */ 1503 /*description: cpu force ISO*/ 1504 #define RTC_CNTL_CPU_TOP_FORCE_ISO (BIT(26)) 1505 #define RTC_CNTL_CPU_TOP_FORCE_ISO_M (BIT(26)) 1506 #define RTC_CNTL_CPU_TOP_FORCE_ISO_V 0x1 1507 #define RTC_CNTL_CPU_TOP_FORCE_ISO_S 26 1508 /* RTC_CNTL_DG_PERI_FORCE_NOISO : R/W ;bitpos:[25] ;default: 1'd1 ; */ 1509 /*description: */ 1510 #define RTC_CNTL_DG_PERI_FORCE_NOISO (BIT(25)) 1511 #define RTC_CNTL_DG_PERI_FORCE_NOISO_M (BIT(25)) 1512 #define RTC_CNTL_DG_PERI_FORCE_NOISO_V 0x1 1513 #define RTC_CNTL_DG_PERI_FORCE_NOISO_S 25 1514 /* RTC_CNTL_DG_PERI_FORCE_ISO : R/W ;bitpos:[24] ;default: 1'd0 ; */ 1515 /*description: */ 1516 #define RTC_CNTL_DG_PERI_FORCE_ISO (BIT(24)) 1517 #define RTC_CNTL_DG_PERI_FORCE_ISO_M (BIT(24)) 1518 #define RTC_CNTL_DG_PERI_FORCE_ISO_V 0x1 1519 #define RTC_CNTL_DG_PERI_FORCE_ISO_S 24 1520 /* RTC_CNTL_BT_FORCE_NOISO : R/W ;bitpos:[23] ;default: 1'd1 ; */ 1521 /*description: */ 1522 #define RTC_CNTL_BT_FORCE_NOISO (BIT(23)) 1523 #define RTC_CNTL_BT_FORCE_NOISO_M (BIT(23)) 1524 #define RTC_CNTL_BT_FORCE_NOISO_V 0x1 1525 #define RTC_CNTL_BT_FORCE_NOISO_S 23 1526 /* RTC_CNTL_BT_FORCE_ISO : R/W ;bitpos:[22] ;default: 1'd0 ; */ 1527 /*description: */ 1528 #define RTC_CNTL_BT_FORCE_ISO (BIT(22)) 1529 #define RTC_CNTL_BT_FORCE_ISO_M (BIT(22)) 1530 #define RTC_CNTL_BT_FORCE_ISO_V 0x1 1531 #define RTC_CNTL_BT_FORCE_ISO_S 22 1532 /* RTC_CNTL_DG_PAD_FORCE_HOLD : R/W ;bitpos:[15] ;default: 1'd0 ; */ 1533 /*description: digital pad force hold*/ 1534 #define RTC_CNTL_DG_PAD_FORCE_HOLD (BIT(15)) 1535 #define RTC_CNTL_DG_PAD_FORCE_HOLD_M (BIT(15)) 1536 #define RTC_CNTL_DG_PAD_FORCE_HOLD_V 0x1 1537 #define RTC_CNTL_DG_PAD_FORCE_HOLD_S 15 1538 /* RTC_CNTL_DG_PAD_FORCE_UNHOLD : R/W ;bitpos:[14] ;default: 1'd1 ; */ 1539 /*description: digital pad force un-hold*/ 1540 #define RTC_CNTL_DG_PAD_FORCE_UNHOLD (BIT(14)) 1541 #define RTC_CNTL_DG_PAD_FORCE_UNHOLD_M (BIT(14)) 1542 #define RTC_CNTL_DG_PAD_FORCE_UNHOLD_V 0x1 1543 #define RTC_CNTL_DG_PAD_FORCE_UNHOLD_S 14 1544 /* RTC_CNTL_DG_PAD_FORCE_ISO : R/W ;bitpos:[13] ;default: 1'd0 ; */ 1545 /*description: digital pad force ISO*/ 1546 #define RTC_CNTL_DG_PAD_FORCE_ISO (BIT(13)) 1547 #define RTC_CNTL_DG_PAD_FORCE_ISO_M (BIT(13)) 1548 #define RTC_CNTL_DG_PAD_FORCE_ISO_V 0x1 1549 #define RTC_CNTL_DG_PAD_FORCE_ISO_S 13 1550 /* RTC_CNTL_DG_PAD_FORCE_NOISO : R/W ;bitpos:[12] ;default: 1'd1 ; */ 1551 /*description: digital pad force no ISO*/ 1552 #define RTC_CNTL_DG_PAD_FORCE_NOISO (BIT(12)) 1553 #define RTC_CNTL_DG_PAD_FORCE_NOISO_M (BIT(12)) 1554 #define RTC_CNTL_DG_PAD_FORCE_NOISO_V 0x1 1555 #define RTC_CNTL_DG_PAD_FORCE_NOISO_S 12 1556 /* RTC_CNTL_DG_PAD_AUTOHOLD_EN : R/W ;bitpos:[11] ;default: 1'd0 ; */ 1557 /*description: digital pad enable auto-hold*/ 1558 #define RTC_CNTL_DG_PAD_AUTOHOLD_EN (BIT(11)) 1559 #define RTC_CNTL_DG_PAD_AUTOHOLD_EN_M (BIT(11)) 1560 #define RTC_CNTL_DG_PAD_AUTOHOLD_EN_V 0x1 1561 #define RTC_CNTL_DG_PAD_AUTOHOLD_EN_S 11 1562 /* RTC_CNTL_CLR_DG_PAD_AUTOHOLD : WO ;bitpos:[10] ;default: 1'd0 ; */ 1563 /*description: wtite only register to clear digital pad auto-hold*/ 1564 #define RTC_CNTL_CLR_DG_PAD_AUTOHOLD (BIT(10)) 1565 #define RTC_CNTL_CLR_DG_PAD_AUTOHOLD_M (BIT(10)) 1566 #define RTC_CNTL_CLR_DG_PAD_AUTOHOLD_V 0x1 1567 #define RTC_CNTL_CLR_DG_PAD_AUTOHOLD_S 10 1568 /* RTC_CNTL_DG_PAD_AUTOHOLD : RO ;bitpos:[9] ;default: 1'd0 ; */ 1569 /*description: read only register to indicate digital pad auto-hold status*/ 1570 #define RTC_CNTL_DG_PAD_AUTOHOLD (BIT(9)) 1571 #define RTC_CNTL_DG_PAD_AUTOHOLD_M (BIT(9)) 1572 #define RTC_CNTL_DG_PAD_AUTOHOLD_V 0x1 1573 #define RTC_CNTL_DG_PAD_AUTOHOLD_S 9 1574 /* RTC_CNTL_DIG_ISO_FORCE_ON : R/W ;bitpos:[8] ;default: 1'd0 ; */ 1575 /*description: */ 1576 #define RTC_CNTL_DIG_ISO_FORCE_ON (BIT(8)) 1577 #define RTC_CNTL_DIG_ISO_FORCE_ON_M (BIT(8)) 1578 #define RTC_CNTL_DIG_ISO_FORCE_ON_V 0x1 1579 #define RTC_CNTL_DIG_ISO_FORCE_ON_S 8 1580 /* RTC_CNTL_DIG_ISO_FORCE_OFF : R/W ;bitpos:[7] ;default: 1'd1 ; */ 1581 /*description: */ 1582 #define RTC_CNTL_DIG_ISO_FORCE_OFF (BIT(7)) 1583 #define RTC_CNTL_DIG_ISO_FORCE_OFF_M (BIT(7)) 1584 #define RTC_CNTL_DIG_ISO_FORCE_OFF_V 0x1 1585 #define RTC_CNTL_DIG_ISO_FORCE_OFF_S 7 1586 1587 #define RTC_CNTL_WDTCONFIG0_REG (DR_REG_RTCCNTL_BASE + 0x0090) 1588 /* RTC_CNTL_WDT_EN : R/W ;bitpos:[31] ;default: 1'h0 ; */ 1589 /*description: */ 1590 #define RTC_CNTL_WDT_EN (BIT(31)) 1591 #define RTC_CNTL_WDT_EN_M (BIT(31)) 1592 #define RTC_CNTL_WDT_EN_V 0x1 1593 #define RTC_CNTL_WDT_EN_S 31 1594 /* RTC_CNTL_WDT_STG0 : R/W ;bitpos:[30:28] ;default: 3'h0 ; */ 1595 /*description: 1: interrupt stage en*/ 1596 #define RTC_CNTL_WDT_STG0 0x00000007 1597 #define RTC_CNTL_WDT_STG0_M ((RTC_CNTL_WDT_STG0_V)<<(RTC_CNTL_WDT_STG0_S)) 1598 #define RTC_CNTL_WDT_STG0_V 0x7 1599 #define RTC_CNTL_WDT_STG0_S 28 1600 /* RTC_CNTL_WDT_STG1 : R/W ;bitpos:[27:25] ;default: 3'h0 ; */ 1601 /*description: 1: interrupt stage en*/ 1602 #define RTC_CNTL_WDT_STG1 0x00000007 1603 #define RTC_CNTL_WDT_STG1_M ((RTC_CNTL_WDT_STG1_V)<<(RTC_CNTL_WDT_STG1_S)) 1604 #define RTC_CNTL_WDT_STG1_V 0x7 1605 #define RTC_CNTL_WDT_STG1_S 25 1606 /* RTC_CNTL_WDT_STG2 : R/W ;bitpos:[24:22] ;default: 3'h0 ; */ 1607 /*description: 1: interrupt stage en*/ 1608 #define RTC_CNTL_WDT_STG2 0x00000007 1609 #define RTC_CNTL_WDT_STG2_M ((RTC_CNTL_WDT_STG2_V)<<(RTC_CNTL_WDT_STG2_S)) 1610 #define RTC_CNTL_WDT_STG2_V 0x7 1611 #define RTC_CNTL_WDT_STG2_S 22 1612 /* RTC_CNTL_WDT_STG3 : R/W ;bitpos:[21:19] ;default: 3'h0 ; */ 1613 /*description: 1: interrupt stage en*/ 1614 #define RTC_CNTL_WDT_STG3 0x00000007 1615 #define RTC_CNTL_WDT_STG3_M ((RTC_CNTL_WDT_STG3_V)<<(RTC_CNTL_WDT_STG3_S)) 1616 #define RTC_CNTL_WDT_STG3_V 0x7 1617 #define RTC_CNTL_WDT_STG3_S 19 1618 /* RTC_CNTL_WDT_STGX : */ 1619 /*description: stage action selection values */ 1620 #define RTC_WDT_STG_SEL_OFF 0 1621 #define RTC_WDT_STG_SEL_INT 1 1622 #define RTC_WDT_STG_SEL_RESET_CPU 2 1623 #define RTC_WDT_STG_SEL_RESET_SYSTEM 3 1624 #define RTC_WDT_STG_SEL_RESET_RTC 4 1625 1626 /* RTC_CNTL_WDT_CPU_RESET_LENGTH : R/W ;bitpos:[18:16] ;default: 3'h1 ; */ 1627 /*description: CPU reset counter length*/ 1628 #define RTC_CNTL_WDT_CPU_RESET_LENGTH 0x00000007 1629 #define RTC_CNTL_WDT_CPU_RESET_LENGTH_M ((RTC_CNTL_WDT_CPU_RESET_LENGTH_V)<<(RTC_CNTL_WDT_CPU_RESET_LENGTH_S)) 1630 #define RTC_CNTL_WDT_CPU_RESET_LENGTH_V 0x7 1631 #define RTC_CNTL_WDT_CPU_RESET_LENGTH_S 16 1632 /* RTC_CNTL_WDT_SYS_RESET_LENGTH : R/W ;bitpos:[15:13] ;default: 3'h1 ; */ 1633 /*description: system reset counter length*/ 1634 #define RTC_CNTL_WDT_SYS_RESET_LENGTH 0x00000007 1635 #define RTC_CNTL_WDT_SYS_RESET_LENGTH_M ((RTC_CNTL_WDT_SYS_RESET_LENGTH_V)<<(RTC_CNTL_WDT_SYS_RESET_LENGTH_S)) 1636 #define RTC_CNTL_WDT_SYS_RESET_LENGTH_V 0x7 1637 #define RTC_CNTL_WDT_SYS_RESET_LENGTH_S 13 1638 /* RTC_CNTL_WDT_FLASHBOOT_MOD_EN : R/W ;bitpos:[12] ;default: 1'h1 ; */ 1639 /*description: enable WDT in flash boot*/ 1640 #define RTC_CNTL_WDT_FLASHBOOT_MOD_EN (BIT(12)) 1641 #define RTC_CNTL_WDT_FLASHBOOT_MOD_EN_M (BIT(12)) 1642 #define RTC_CNTL_WDT_FLASHBOOT_MOD_EN_V 0x1 1643 #define RTC_CNTL_WDT_FLASHBOOT_MOD_EN_S 12 1644 /* RTC_CNTL_WDT_PROCPU_RESET_EN : R/W ;bitpos:[11] ;default: 1'd0 ; */ 1645 /*description: enable WDT reset PRO CPU*/ 1646 #define RTC_CNTL_WDT_PROCPU_RESET_EN (BIT(11)) 1647 #define RTC_CNTL_WDT_PROCPU_RESET_EN_M (BIT(11)) 1648 #define RTC_CNTL_WDT_PROCPU_RESET_EN_V 0x1 1649 #define RTC_CNTL_WDT_PROCPU_RESET_EN_S 11 1650 /* RTC_CNTL_WDT_APPCPU_RESET_EN : R/W ;bitpos:[10] ;default: 1'd0 ; */ 1651 /*description: enable WDT reset APP CPU*/ 1652 #define RTC_CNTL_WDT_APPCPU_RESET_EN (BIT(10)) 1653 #define RTC_CNTL_WDT_APPCPU_RESET_EN_M (BIT(10)) 1654 #define RTC_CNTL_WDT_APPCPU_RESET_EN_V 0x1 1655 #define RTC_CNTL_WDT_APPCPU_RESET_EN_S 10 1656 /* RTC_CNTL_WDT_PAUSE_IN_SLP : R/W ;bitpos:[9] ;default: 1'd1 ; */ 1657 /*description: pause WDT in sleep*/ 1658 #define RTC_CNTL_WDT_PAUSE_IN_SLP (BIT(9)) 1659 #define RTC_CNTL_WDT_PAUSE_IN_SLP_M (BIT(9)) 1660 #define RTC_CNTL_WDT_PAUSE_IN_SLP_V 0x1 1661 #define RTC_CNTL_WDT_PAUSE_IN_SLP_S 9 1662 /* RTC_CNTL_WDT_CHIP_RESET_EN : R/W ;bitpos:[8] ;default: 1'b0 ; */ 1663 /*description: wdt reset whole chip enable*/ 1664 #define RTC_CNTL_WDT_CHIP_RESET_EN (BIT(8)) 1665 #define RTC_CNTL_WDT_CHIP_RESET_EN_M (BIT(8)) 1666 #define RTC_CNTL_WDT_CHIP_RESET_EN_V 0x1 1667 #define RTC_CNTL_WDT_CHIP_RESET_EN_S 8 1668 /* RTC_CNTL_WDT_CHIP_RESET_WIDTH : R/W ;bitpos:[7:0] ;default: 8'd20 ; */ 1669 /*description: chip reset siginal pulse width*/ 1670 #define RTC_CNTL_WDT_CHIP_RESET_WIDTH 0x000000FF 1671 #define RTC_CNTL_WDT_CHIP_RESET_WIDTH_M ((RTC_CNTL_WDT_CHIP_RESET_WIDTH_V)<<(RTC_CNTL_WDT_CHIP_RESET_WIDTH_S)) 1672 #define RTC_CNTL_WDT_CHIP_RESET_WIDTH_V 0xFF 1673 #define RTC_CNTL_WDT_CHIP_RESET_WIDTH_S 0 1674 1675 #define RTC_CNTL_WDTCONFIG1_REG (DR_REG_RTCCNTL_BASE + 0x0094) 1676 /* RTC_CNTL_WDT_STG0_HOLD : R/W ;bitpos:[31:0] ;default: 32'd200000 ; */ 1677 /*description: */ 1678 #define RTC_CNTL_WDT_STG0_HOLD 0xFFFFFFFF 1679 #define RTC_CNTL_WDT_STG0_HOLD_M ((RTC_CNTL_WDT_STG0_HOLD_V)<<(RTC_CNTL_WDT_STG0_HOLD_S)) 1680 #define RTC_CNTL_WDT_STG0_HOLD_V 0xFFFFFFFF 1681 #define RTC_CNTL_WDT_STG0_HOLD_S 0 1682 1683 #define RTC_CNTL_WDTCONFIG2_REG (DR_REG_RTCCNTL_BASE + 0x0098) 1684 /* RTC_CNTL_WDT_STG1_HOLD : R/W ;bitpos:[31:0] ;default: 32'd80000 ; */ 1685 /*description: */ 1686 #define RTC_CNTL_WDT_STG1_HOLD 0xFFFFFFFF 1687 #define RTC_CNTL_WDT_STG1_HOLD_M ((RTC_CNTL_WDT_STG1_HOLD_V)<<(RTC_CNTL_WDT_STG1_HOLD_S)) 1688 #define RTC_CNTL_WDT_STG1_HOLD_V 0xFFFFFFFF 1689 #define RTC_CNTL_WDT_STG1_HOLD_S 0 1690 1691 #define RTC_CNTL_WDTCONFIG3_REG (DR_REG_RTCCNTL_BASE + 0x009C) 1692 /* RTC_CNTL_WDT_STG2_HOLD : R/W ;bitpos:[31:0] ;default: 32'hfff ; */ 1693 /*description: */ 1694 #define RTC_CNTL_WDT_STG2_HOLD 0xFFFFFFFF 1695 #define RTC_CNTL_WDT_STG2_HOLD_M ((RTC_CNTL_WDT_STG2_HOLD_V)<<(RTC_CNTL_WDT_STG2_HOLD_S)) 1696 #define RTC_CNTL_WDT_STG2_HOLD_V 0xFFFFFFFF 1697 #define RTC_CNTL_WDT_STG2_HOLD_S 0 1698 1699 #define RTC_CNTL_WDTCONFIG4_REG (DR_REG_RTCCNTL_BASE + 0x00A0) 1700 /* RTC_CNTL_WDT_STG3_HOLD : R/W ;bitpos:[31:0] ;default: 32'hfff ; */ 1701 /*description: */ 1702 #define RTC_CNTL_WDT_STG3_HOLD 0xFFFFFFFF 1703 #define RTC_CNTL_WDT_STG3_HOLD_M ((RTC_CNTL_WDT_STG3_HOLD_V)<<(RTC_CNTL_WDT_STG3_HOLD_S)) 1704 #define RTC_CNTL_WDT_STG3_HOLD_V 0xFFFFFFFF 1705 #define RTC_CNTL_WDT_STG3_HOLD_S 0 1706 1707 #define RTC_CNTL_WDTFEED_REG (DR_REG_RTCCNTL_BASE + 0x00A4) 1708 /* RTC_CNTL_WDT_FEED : WO ;bitpos:[31] ;default: 1'd0 ; */ 1709 /*description: */ 1710 #define RTC_CNTL_WDT_FEED (BIT(31)) 1711 #define RTC_CNTL_WDT_FEED_M (BIT(31)) 1712 #define RTC_CNTL_WDT_FEED_V 0x1 1713 #define RTC_CNTL_WDT_FEED_S 31 1714 1715 #define RTC_CNTL_WDTWPROTECT_REG (DR_REG_RTCCNTL_BASE + 0x00A8) 1716 /* RTC_CNTL_WDT_WKEY : R/W ;bitpos:[31:0] ;default: 32'h50d83aa1 ; */ 1717 /*description: */ 1718 #define RTC_CNTL_WDT_WKEY 0xFFFFFFFF 1719 #define RTC_CNTL_WDT_WKEY_M ((RTC_CNTL_WDT_WKEY_V)<<(RTC_CNTL_WDT_WKEY_S)) 1720 #define RTC_CNTL_WDT_WKEY_V 0xFFFFFFFF 1721 #define RTC_CNTL_WDT_WKEY_S 0 1722 1723 #define RTC_CNTL_SWD_CONF_REG (DR_REG_RTCCNTL_BASE + 0x00AC) 1724 /* RTC_CNTL_SWD_AUTO_FEED_EN : R/W ;bitpos:[31] ;default: 1'b0 ; */ 1725 /*description: automatically feed swd when int comes*/ 1726 #define RTC_CNTL_SWD_AUTO_FEED_EN (BIT(31)) 1727 #define RTC_CNTL_SWD_AUTO_FEED_EN_M (BIT(31)) 1728 #define RTC_CNTL_SWD_AUTO_FEED_EN_V 0x1 1729 #define RTC_CNTL_SWD_AUTO_FEED_EN_S 31 1730 /* RTC_CNTL_SWD_DISABLE : R/W ;bitpos:[30] ;default: 1'b0 ; */ 1731 /*description: disabel SWD*/ 1732 #define RTC_CNTL_SWD_DISABLE (BIT(30)) 1733 #define RTC_CNTL_SWD_DISABLE_M (BIT(30)) 1734 #define RTC_CNTL_SWD_DISABLE_V 0x1 1735 #define RTC_CNTL_SWD_DISABLE_S 30 1736 /* RTC_CNTL_SWD_FEED : WO ;bitpos:[29] ;default: 1'b0 ; */ 1737 /*description: Sw feed swd*/ 1738 #define RTC_CNTL_SWD_FEED (BIT(29)) 1739 #define RTC_CNTL_SWD_FEED_M (BIT(29)) 1740 #define RTC_CNTL_SWD_FEED_V 0x1 1741 #define RTC_CNTL_SWD_FEED_S 29 1742 /* RTC_CNTL_SWD_RST_FLAG_CLR : WO ;bitpos:[28] ;default: 1'b0 ; */ 1743 /*description: reset swd reset flag*/ 1744 #define RTC_CNTL_SWD_RST_FLAG_CLR (BIT(28)) 1745 #define RTC_CNTL_SWD_RST_FLAG_CLR_M (BIT(28)) 1746 #define RTC_CNTL_SWD_RST_FLAG_CLR_V 0x1 1747 #define RTC_CNTL_SWD_RST_FLAG_CLR_S 28 1748 /* RTC_CNTL_SWD_SIGNAL_WIDTH : R/W ;bitpos:[27:18] ;default: 10'd300 ; */ 1749 /*description: adjust signal width send to swd*/ 1750 #define RTC_CNTL_SWD_SIGNAL_WIDTH 0x000003FF 1751 #define RTC_CNTL_SWD_SIGNAL_WIDTH_M ((RTC_CNTL_SWD_SIGNAL_WIDTH_V)<<(RTC_CNTL_SWD_SIGNAL_WIDTH_S)) 1752 #define RTC_CNTL_SWD_SIGNAL_WIDTH_V 0x3FF 1753 #define RTC_CNTL_SWD_SIGNAL_WIDTH_S 18 1754 /* RTC_CNTL_SWD_BYPASS_RST : R/W ;bitpos:[17] ;default: 1'b0 ; */ 1755 /*description: */ 1756 #define RTC_CNTL_SWD_BYPASS_RST (BIT(17)) 1757 #define RTC_CNTL_SWD_BYPASS_RST_M (BIT(17)) 1758 #define RTC_CNTL_SWD_BYPASS_RST_V 0x1 1759 #define RTC_CNTL_SWD_BYPASS_RST_S 17 1760 /* RTC_CNTL_SWD_FEED_INT : RO ;bitpos:[1] ;default: 1'b0 ; */ 1761 /*description: swd interrupt for feeding*/ 1762 #define RTC_CNTL_SWD_FEED_INT (BIT(1)) 1763 #define RTC_CNTL_SWD_FEED_INT_M (BIT(1)) 1764 #define RTC_CNTL_SWD_FEED_INT_V 0x1 1765 #define RTC_CNTL_SWD_FEED_INT_S 1 1766 /* RTC_CNTL_SWD_RESET_FLAG : RO ;bitpos:[0] ;default: 1'b0 ; */ 1767 /*description: swd reset flag*/ 1768 #define RTC_CNTL_SWD_RESET_FLAG (BIT(0)) 1769 #define RTC_CNTL_SWD_RESET_FLAG_M (BIT(0)) 1770 #define RTC_CNTL_SWD_RESET_FLAG_V 0x1 1771 #define RTC_CNTL_SWD_RESET_FLAG_S 0 1772 1773 #define RTC_CNTL_SWD_WPROTECT_REG (DR_REG_RTCCNTL_BASE + 0x00B0) 1774 /* RTC_CNTL_SWD_WKEY : R/W ;bitpos:[31:0] ;default: 32'h8f1d312a ; */ 1775 /*description: */ 1776 #define RTC_CNTL_SWD_WKEY 0xFFFFFFFF 1777 #define RTC_CNTL_SWD_WKEY_M ((RTC_CNTL_SWD_WKEY_V)<<(RTC_CNTL_SWD_WKEY_S)) 1778 #define RTC_CNTL_SWD_WKEY_V 0xFFFFFFFF 1779 #define RTC_CNTL_SWD_WKEY_S 0 1780 1781 #define RTC_CNTL_SW_CPU_STALL_REG (DR_REG_RTCCNTL_BASE + 0x00B4) 1782 /* RTC_CNTL_SW_STALL_PROCPU_C1 : R/W ;bitpos:[31:26] ;default: 6'b0 ; */ 1783 /*description: */ 1784 #define RTC_CNTL_SW_STALL_PROCPU_C1 0x0000003F 1785 #define RTC_CNTL_SW_STALL_PROCPU_C1_M ((RTC_CNTL_SW_STALL_PROCPU_C1_V)<<(RTC_CNTL_SW_STALL_PROCPU_C1_S)) 1786 #define RTC_CNTL_SW_STALL_PROCPU_C1_V 0x3F 1787 #define RTC_CNTL_SW_STALL_PROCPU_C1_S 26 1788 /* RTC_CNTL_SW_STALL_APPCPU_C1 : R/W ;bitpos:[25:20] ;default: 6'b0 ; */ 1789 /*description: {reg_sw_stall_appcpu_c1[5:0]*/ 1790 #define RTC_CNTL_SW_STALL_APPCPU_C1 0x0000003F 1791 #define RTC_CNTL_SW_STALL_APPCPU_C1_M ((RTC_CNTL_SW_STALL_APPCPU_C1_V)<<(RTC_CNTL_SW_STALL_APPCPU_C1_S)) 1792 #define RTC_CNTL_SW_STALL_APPCPU_C1_V 0x3F 1793 #define RTC_CNTL_SW_STALL_APPCPU_C1_S 20 1794 1795 #define RTC_CNTL_STORE4_REG (DR_REG_RTCCNTL_BASE + 0x00B8) 1796 /* RTC_CNTL_SCRATCH4 : R/W ;bitpos:[31:0] ;default: 0 ; */ 1797 /*description: */ 1798 #define RTC_CNTL_SCRATCH4 0xFFFFFFFF 1799 #define RTC_CNTL_SCRATCH4_M ((RTC_CNTL_SCRATCH4_V)<<(RTC_CNTL_SCRATCH4_S)) 1800 #define RTC_CNTL_SCRATCH4_V 0xFFFFFFFF 1801 #define RTC_CNTL_SCRATCH4_S 0 1802 1803 #define RTC_CNTL_STORE5_REG (DR_REG_RTCCNTL_BASE + 0x00BC) 1804 /* RTC_CNTL_SCRATCH5 : R/W ;bitpos:[31:0] ;default: 0 ; */ 1805 /*description: */ 1806 #define RTC_CNTL_SCRATCH5 0xFFFFFFFF 1807 #define RTC_CNTL_SCRATCH5_M ((RTC_CNTL_SCRATCH5_V)<<(RTC_CNTL_SCRATCH5_S)) 1808 #define RTC_CNTL_SCRATCH5_V 0xFFFFFFFF 1809 #define RTC_CNTL_SCRATCH5_S 0 1810 1811 #define RTC_CNTL_STORE6_REG (DR_REG_RTCCNTL_BASE + 0x00C0) 1812 /* RTC_CNTL_SCRATCH6 : R/W ;bitpos:[31:0] ;default: 0 ; */ 1813 /*description: */ 1814 #define RTC_CNTL_SCRATCH6 0xFFFFFFFF 1815 #define RTC_CNTL_SCRATCH6_M ((RTC_CNTL_SCRATCH6_V)<<(RTC_CNTL_SCRATCH6_S)) 1816 #define RTC_CNTL_SCRATCH6_V 0xFFFFFFFF 1817 #define RTC_CNTL_SCRATCH6_S 0 1818 1819 #define RTC_CNTL_STORE7_REG (DR_REG_RTCCNTL_BASE + 0x00C4) 1820 /* RTC_CNTL_SCRATCH7 : R/W ;bitpos:[31:0] ;default: 0 ; */ 1821 /*description: */ 1822 #define RTC_CNTL_SCRATCH7 0xFFFFFFFF 1823 #define RTC_CNTL_SCRATCH7_M ((RTC_CNTL_SCRATCH7_V)<<(RTC_CNTL_SCRATCH7_S)) 1824 #define RTC_CNTL_SCRATCH7_V 0xFFFFFFFF 1825 #define RTC_CNTL_SCRATCH7_S 0 1826 1827 #define RTC_CNTL_LOW_POWER_ST_REG (DR_REG_RTCCNTL_BASE + 0x00C8) 1828 /* RTC_CNTL_MAIN_STATE : RO ;bitpos:[31:28] ;default: 4'd0 ; */ 1829 /*description: rtc main state machine status*/ 1830 #define RTC_CNTL_MAIN_STATE 0x0000000F 1831 #define RTC_CNTL_MAIN_STATE_M ((RTC_CNTL_MAIN_STATE_V)<<(RTC_CNTL_MAIN_STATE_S)) 1832 #define RTC_CNTL_MAIN_STATE_V 0xF 1833 #define RTC_CNTL_MAIN_STATE_S 28 1834 /* RTC_CNTL_MAIN_STATE_IN_IDLE : RO ;bitpos:[27] ;default: 1'b0 ; */ 1835 /*description: rtc main state machine is in idle state*/ 1836 #define RTC_CNTL_MAIN_STATE_IN_IDLE (BIT(27)) 1837 #define RTC_CNTL_MAIN_STATE_IN_IDLE_M (BIT(27)) 1838 #define RTC_CNTL_MAIN_STATE_IN_IDLE_V 0x1 1839 #define RTC_CNTL_MAIN_STATE_IN_IDLE_S 27 1840 /* RTC_CNTL_MAIN_STATE_IN_SLP : RO ;bitpos:[26] ;default: 1'b0 ; */ 1841 /*description: rtc main state machine is in sleep state*/ 1842 #define RTC_CNTL_MAIN_STATE_IN_SLP (BIT(26)) 1843 #define RTC_CNTL_MAIN_STATE_IN_SLP_M (BIT(26)) 1844 #define RTC_CNTL_MAIN_STATE_IN_SLP_V 0x1 1845 #define RTC_CNTL_MAIN_STATE_IN_SLP_S 26 1846 /* RTC_CNTL_MAIN_STATE_IN_WAIT_XTL : RO ;bitpos:[25] ;default: 1'b0 ; */ 1847 /*description: rtc main state machine is in wait xtal state*/ 1848 #define RTC_CNTL_MAIN_STATE_IN_WAIT_XTL (BIT(25)) 1849 #define RTC_CNTL_MAIN_STATE_IN_WAIT_XTL_M (BIT(25)) 1850 #define RTC_CNTL_MAIN_STATE_IN_WAIT_XTL_V 0x1 1851 #define RTC_CNTL_MAIN_STATE_IN_WAIT_XTL_S 25 1852 /* RTC_CNTL_MAIN_STATE_IN_WAIT_PLL : RO ;bitpos:[24] ;default: 1'b0 ; */ 1853 /*description: rtc main state machine is in wait pll state*/ 1854 #define RTC_CNTL_MAIN_STATE_IN_WAIT_PLL (BIT(24)) 1855 #define RTC_CNTL_MAIN_STATE_IN_WAIT_PLL_M (BIT(24)) 1856 #define RTC_CNTL_MAIN_STATE_IN_WAIT_PLL_V 0x1 1857 #define RTC_CNTL_MAIN_STATE_IN_WAIT_PLL_S 24 1858 /* RTC_CNTL_MAIN_STATE_IN_WAIT_8M : RO ;bitpos:[23] ;default: 1'b0 ; */ 1859 /*description: rtc main state machine is in wait 8m state*/ 1860 #define RTC_CNTL_MAIN_STATE_IN_WAIT_8M (BIT(23)) 1861 #define RTC_CNTL_MAIN_STATE_IN_WAIT_8M_M (BIT(23)) 1862 #define RTC_CNTL_MAIN_STATE_IN_WAIT_8M_V 0x1 1863 #define RTC_CNTL_MAIN_STATE_IN_WAIT_8M_S 23 1864 /* RTC_CNTL_IN_LOW_POWER_STATE : RO ;bitpos:[22] ;default: 1'b0 ; */ 1865 /*description: rtc main state machine is in the states of low power*/ 1866 #define RTC_CNTL_IN_LOW_POWER_STATE (BIT(22)) 1867 #define RTC_CNTL_IN_LOW_POWER_STATE_M (BIT(22)) 1868 #define RTC_CNTL_IN_LOW_POWER_STATE_V 0x1 1869 #define RTC_CNTL_IN_LOW_POWER_STATE_S 22 1870 /* RTC_CNTL_IN_WAKEUP_STATE : RO ;bitpos:[21] ;default: 1'b0 ; */ 1871 /*description: rtc main state machine is in the states of wakeup process*/ 1872 #define RTC_CNTL_IN_WAKEUP_STATE (BIT(21)) 1873 #define RTC_CNTL_IN_WAKEUP_STATE_M (BIT(21)) 1874 #define RTC_CNTL_IN_WAKEUP_STATE_V 0x1 1875 #define RTC_CNTL_IN_WAKEUP_STATE_S 21 1876 /* RTC_CNTL_MAIN_STATE_WAIT_END : RO ;bitpos:[20] ;default: 1'b0 ; */ 1877 /*description: rtc main state machine has been waited for some cycles*/ 1878 #define RTC_CNTL_MAIN_STATE_WAIT_END (BIT(20)) 1879 #define RTC_CNTL_MAIN_STATE_WAIT_END_M (BIT(20)) 1880 #define RTC_CNTL_MAIN_STATE_WAIT_END_V 0x1 1881 #define RTC_CNTL_MAIN_STATE_WAIT_END_S 20 1882 /* RTC_CNTL_RDY_FOR_WAKEUP : RO ;bitpos:[19] ;default: 1'b0 ; */ 1883 /*description: rtc is ready to receive wake up trigger from wake up source*/ 1884 #define RTC_CNTL_RDY_FOR_WAKEUP (BIT(19)) 1885 #define RTC_CNTL_RDY_FOR_WAKEUP_M (BIT(19)) 1886 #define RTC_CNTL_RDY_FOR_WAKEUP_V 0x1 1887 #define RTC_CNTL_RDY_FOR_WAKEUP_S 19 1888 /* RTC_CNTL_MAIN_STATE_PLL_ON : RO ;bitpos:[18] ;default: 1'b0 ; */ 1889 /*description: rtc main state machine is in states that pll should be running*/ 1890 #define RTC_CNTL_MAIN_STATE_PLL_ON (BIT(18)) 1891 #define RTC_CNTL_MAIN_STATE_PLL_ON_M (BIT(18)) 1892 #define RTC_CNTL_MAIN_STATE_PLL_ON_V 0x1 1893 #define RTC_CNTL_MAIN_STATE_PLL_ON_S 18 1894 /* RTC_CNTL_MAIN_STATE_XTAL_ISO : RO ;bitpos:[17] ;default: 1'b0 ; */ 1895 /*description: no use any more*/ 1896 #define RTC_CNTL_MAIN_STATE_XTAL_ISO (BIT(17)) 1897 #define RTC_CNTL_MAIN_STATE_XTAL_ISO_M (BIT(17)) 1898 #define RTC_CNTL_MAIN_STATE_XTAL_ISO_V 0x1 1899 #define RTC_CNTL_MAIN_STATE_XTAL_ISO_S 17 1900 /* RTC_CNTL_COCPU_STATE_DONE : RO ;bitpos:[16] ;default: 1'b0 ; */ 1901 /*description: ulp/cocpu is done*/ 1902 #define RTC_CNTL_COCPU_STATE_DONE (BIT(16)) 1903 #define RTC_CNTL_COCPU_STATE_DONE_M (BIT(16)) 1904 #define RTC_CNTL_COCPU_STATE_DONE_V 0x1 1905 #define RTC_CNTL_COCPU_STATE_DONE_S 16 1906 /* RTC_CNTL_COCPU_STATE_SLP : RO ;bitpos:[15] ;default: 1'b0 ; */ 1907 /*description: ulp/cocpu is in sleep state*/ 1908 #define RTC_CNTL_COCPU_STATE_SLP (BIT(15)) 1909 #define RTC_CNTL_COCPU_STATE_SLP_M (BIT(15)) 1910 #define RTC_CNTL_COCPU_STATE_SLP_V 0x1 1911 #define RTC_CNTL_COCPU_STATE_SLP_S 15 1912 /* RTC_CNTL_COCPU_STATE_SWITCH : RO ;bitpos:[14] ;default: 1'b0 ; */ 1913 /*description: ulp/cocpu is about to working. Switch rtc main state*/ 1914 #define RTC_CNTL_COCPU_STATE_SWITCH (BIT(14)) 1915 #define RTC_CNTL_COCPU_STATE_SWITCH_M (BIT(14)) 1916 #define RTC_CNTL_COCPU_STATE_SWITCH_V 0x1 1917 #define RTC_CNTL_COCPU_STATE_SWITCH_S 14 1918 /* RTC_CNTL_COCPU_STATE_START : RO ;bitpos:[13] ;default: 1'b0 ; */ 1919 /*description: ulp/cocpu should start to work*/ 1920 #define RTC_CNTL_COCPU_STATE_START (BIT(13)) 1921 #define RTC_CNTL_COCPU_STATE_START_M (BIT(13)) 1922 #define RTC_CNTL_COCPU_STATE_START_V 0x1 1923 #define RTC_CNTL_COCPU_STATE_START_S 13 1924 /* RTC_CNTL_TOUCH_STATE_DONE : RO ;bitpos:[12] ;default: 1'b0 ; */ 1925 /*description: touch is done*/ 1926 #define RTC_CNTL_TOUCH_STATE_DONE (BIT(12)) 1927 #define RTC_CNTL_TOUCH_STATE_DONE_M (BIT(12)) 1928 #define RTC_CNTL_TOUCH_STATE_DONE_V 0x1 1929 #define RTC_CNTL_TOUCH_STATE_DONE_S 12 1930 /* RTC_CNTL_TOUCH_STATE_SLP : RO ;bitpos:[11] ;default: 1'b0 ; */ 1931 /*description: touch is in sleep state*/ 1932 #define RTC_CNTL_TOUCH_STATE_SLP (BIT(11)) 1933 #define RTC_CNTL_TOUCH_STATE_SLP_M (BIT(11)) 1934 #define RTC_CNTL_TOUCH_STATE_SLP_V 0x1 1935 #define RTC_CNTL_TOUCH_STATE_SLP_S 11 1936 /* RTC_CNTL_TOUCH_STATE_SWITCH : RO ;bitpos:[10] ;default: 1'b0 ; */ 1937 /*description: touch is about to working. Switch rtc main state*/ 1938 #define RTC_CNTL_TOUCH_STATE_SWITCH (BIT(10)) 1939 #define RTC_CNTL_TOUCH_STATE_SWITCH_M (BIT(10)) 1940 #define RTC_CNTL_TOUCH_STATE_SWITCH_V 0x1 1941 #define RTC_CNTL_TOUCH_STATE_SWITCH_S 10 1942 /* RTC_CNTL_TOUCH_STATE_START : RO ;bitpos:[9] ;default: 1'b0 ; */ 1943 /*description: touch should start to work*/ 1944 #define RTC_CNTL_TOUCH_STATE_START (BIT(9)) 1945 #define RTC_CNTL_TOUCH_STATE_START_M (BIT(9)) 1946 #define RTC_CNTL_TOUCH_STATE_START_V 0x1 1947 #define RTC_CNTL_TOUCH_STATE_START_S 9 1948 /* RTC_CNTL_XPD_DIG : RO ;bitpos:[8] ;default: 1'b0 ; */ 1949 /*description: digital wrap power down*/ 1950 #define RTC_CNTL_XPD_DIG (BIT(8)) 1951 #define RTC_CNTL_XPD_DIG_M (BIT(8)) 1952 #define RTC_CNTL_XPD_DIG_V 0x1 1953 #define RTC_CNTL_XPD_DIG_S 8 1954 /* RTC_CNTL_DIG_ISO : RO ;bitpos:[7] ;default: 1'b0 ; */ 1955 /*description: digital wrap iso*/ 1956 #define RTC_CNTL_DIG_ISO (BIT(7)) 1957 #define RTC_CNTL_DIG_ISO_M (BIT(7)) 1958 #define RTC_CNTL_DIG_ISO_V 0x1 1959 #define RTC_CNTL_DIG_ISO_S 7 1960 /* RTC_CNTL_XPD_WIFI : RO ;bitpos:[6] ;default: 1'b0 ; */ 1961 /*description: wifi wrap power down*/ 1962 #define RTC_CNTL_XPD_WIFI (BIT(6)) 1963 #define RTC_CNTL_XPD_WIFI_M (BIT(6)) 1964 #define RTC_CNTL_XPD_WIFI_V 0x1 1965 #define RTC_CNTL_XPD_WIFI_S 6 1966 /* RTC_CNTL_WIFI_ISO : RO ;bitpos:[5] ;default: 1'b0 ; */ 1967 /*description: wifi iso*/ 1968 #define RTC_CNTL_WIFI_ISO (BIT(5)) 1969 #define RTC_CNTL_WIFI_ISO_M (BIT(5)) 1970 #define RTC_CNTL_WIFI_ISO_V 0x1 1971 #define RTC_CNTL_WIFI_ISO_S 5 1972 /* RTC_CNTL_XPD_RTC_PERI : RO ;bitpos:[4] ;default: 1'b0 ; */ 1973 /*description: rtc peripheral power down*/ 1974 #define RTC_CNTL_XPD_RTC_PERI (BIT(4)) 1975 #define RTC_CNTL_XPD_RTC_PERI_M (BIT(4)) 1976 #define RTC_CNTL_XPD_RTC_PERI_V 0x1 1977 #define RTC_CNTL_XPD_RTC_PERI_S 4 1978 /* RTC_CNTL_PERI_ISO : RO ;bitpos:[3] ;default: 1'b0 ; */ 1979 /*description: rtc peripheral iso*/ 1980 #define RTC_CNTL_PERI_ISO (BIT(3)) 1981 #define RTC_CNTL_PERI_ISO_M (BIT(3)) 1982 #define RTC_CNTL_PERI_ISO_V 0x1 1983 #define RTC_CNTL_PERI_ISO_S 3 1984 /* RTC_CNTL_XPD_DIG_DCDC : RO ;bitpos:[2] ;default: 1'b0 ; */ 1985 /*description: External DCDC power down*/ 1986 #define RTC_CNTL_XPD_DIG_DCDC (BIT(2)) 1987 #define RTC_CNTL_XPD_DIG_DCDC_M (BIT(2)) 1988 #define RTC_CNTL_XPD_DIG_DCDC_V 0x1 1989 #define RTC_CNTL_XPD_DIG_DCDC_S 2 1990 /* RTC_CNTL_XPD_ROM0 : RO ;bitpos:[0] ;default: 1'b0 ; */ 1991 /*description: rom0 power down*/ 1992 #define RTC_CNTL_XPD_ROM0 (BIT(0)) 1993 #define RTC_CNTL_XPD_ROM0_M (BIT(0)) 1994 #define RTC_CNTL_XPD_ROM0_V 0x1 1995 #define RTC_CNTL_XPD_ROM0_S 0 1996 1997 #define RTC_CNTL_DIAG0_REG (DR_REG_RTCCNTL_BASE + 0x00CC) 1998 /* RTC_CNTL_LOW_POWER_DIAG1 : RO ;bitpos:[31:0] ;default: 0 ; */ 1999 /*description: */ 2000 #define RTC_CNTL_LOW_POWER_DIAG1 0xFFFFFFFF 2001 #define RTC_CNTL_LOW_POWER_DIAG1_M ((RTC_CNTL_LOW_POWER_DIAG1_V)<<(RTC_CNTL_LOW_POWER_DIAG1_S)) 2002 #define RTC_CNTL_LOW_POWER_DIAG1_V 0xFFFFFFFF 2003 #define RTC_CNTL_LOW_POWER_DIAG1_S 0 2004 2005 #define RTC_CNTL_PAD_HOLD_REG (DR_REG_RTCCNTL_BASE + 0x00D0) 2006 /* RTC_CNTL_GPIO_PIN5_HOLD : R/W ;bitpos:[5] ;default: 1'b0 ; */ 2007 /*description: */ 2008 #define RTC_CNTL_GPIO_PIN5_HOLD (BIT(5)) 2009 #define RTC_CNTL_GPIO_PIN5_HOLD_M (BIT(5)) 2010 #define RTC_CNTL_GPIO_PIN5_HOLD_V 0x1 2011 #define RTC_CNTL_GPIO_PIN5_HOLD_S 5 2012 /* RTC_CNTL_GPIO_PIN4_HOLD : R/W ;bitpos:[4] ;default: 1'b0 ; */ 2013 /*description: */ 2014 #define RTC_CNTL_GPIO_PIN4_HOLD (BIT(4)) 2015 #define RTC_CNTL_GPIO_PIN4_HOLD_M (BIT(4)) 2016 #define RTC_CNTL_GPIO_PIN4_HOLD_V 0x1 2017 #define RTC_CNTL_GPIO_PIN4_HOLD_S 4 2018 /* RTC_CNTL_GPIO_PIN3_HOLD : R/W ;bitpos:[3] ;default: 1'b0 ; */ 2019 /*description: */ 2020 #define RTC_CNTL_GPIO_PIN3_HOLD (BIT(3)) 2021 #define RTC_CNTL_GPIO_PIN3_HOLD_M (BIT(3)) 2022 #define RTC_CNTL_GPIO_PIN3_HOLD_V 0x1 2023 #define RTC_CNTL_GPIO_PIN3_HOLD_S 3 2024 /* RTC_CNTL_GPIO_PIN2_HOLD : R/W ;bitpos:[2] ;default: 1'b0 ; */ 2025 /*description: */ 2026 #define RTC_CNTL_GPIO_PIN2_HOLD (BIT(2)) 2027 #define RTC_CNTL_GPIO_PIN2_HOLD_M (BIT(2)) 2028 #define RTC_CNTL_GPIO_PIN2_HOLD_V 0x1 2029 #define RTC_CNTL_GPIO_PIN2_HOLD_S 2 2030 /* RTC_CNTL_GPIO_PIN1_HOLD : R/W ;bitpos:[1] ;default: 1'b0 ; */ 2031 /*description: */ 2032 #define RTC_CNTL_GPIO_PIN1_HOLD (BIT(1)) 2033 #define RTC_CNTL_GPIO_PIN1_HOLD_M (BIT(1)) 2034 #define RTC_CNTL_GPIO_PIN1_HOLD_V 0x1 2035 #define RTC_CNTL_GPIO_PIN1_HOLD_S 1 2036 /* RTC_CNTL_GPIO_PIN0_HOLD : R/W ;bitpos:[0] ;default: 1'b0 ; */ 2037 /*description: */ 2038 #define RTC_CNTL_GPIO_PIN0_HOLD (BIT(0)) 2039 #define RTC_CNTL_GPIO_PIN0_HOLD_M (BIT(0)) 2040 #define RTC_CNTL_GPIO_PIN0_HOLD_V 0x1 2041 #define RTC_CNTL_GPIO_PIN0_HOLD_S 0 2042 2043 #define RTC_CNTL_DIG_PAD_HOLD_REG (DR_REG_RTCCNTL_BASE + 0x00D4) 2044 /* RTC_CNTL_DIG_PAD_HOLD : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ 2045 /*description: */ 2046 #define RTC_CNTL_DIG_PAD_HOLD 0xFFFFFFFF 2047 #define RTC_CNTL_DIG_PAD_HOLD_M ((RTC_CNTL_DIG_PAD_HOLD_V)<<(RTC_CNTL_DIG_PAD_HOLD_S)) 2048 #define RTC_CNTL_DIG_PAD_HOLD_V 0xFFFFFFFF 2049 #define RTC_CNTL_DIG_PAD_HOLD_S 0 2050 2051 #define RTC_CNTL_BROWN_OUT_REG (DR_REG_RTCCNTL_BASE + 0x00D8) 2052 /* RTC_CNTL_BROWN_OUT_DET : RO ;bitpos:[31] ;default: 1'b0 ; */ 2053 /*description: */ 2054 #define RTC_CNTL_BROWN_OUT_DET (BIT(31)) 2055 #define RTC_CNTL_BROWN_OUT_DET_M (BIT(31)) 2056 #define RTC_CNTL_BROWN_OUT_DET_V 0x1 2057 #define RTC_CNTL_BROWN_OUT_DET_S 31 2058 /* RTC_CNTL_BROWN_OUT_ENA : R/W ;bitpos:[30] ;default: 1'b1 ; */ 2059 /*description: enable brown out*/ 2060 #define RTC_CNTL_BROWN_OUT_ENA (BIT(30)) 2061 #define RTC_CNTL_BROWN_OUT_ENA_M (BIT(30)) 2062 #define RTC_CNTL_BROWN_OUT_ENA_V 0x1 2063 #define RTC_CNTL_BROWN_OUT_ENA_S 30 2064 /* RTC_CNTL_BROWN_OUT_CNT_CLR : WO ;bitpos:[29] ;default: 1'b0 ; */ 2065 /*description: clear brown out counter*/ 2066 #define RTC_CNTL_BROWN_OUT_CNT_CLR (BIT(29)) 2067 #define RTC_CNTL_BROWN_OUT_CNT_CLR_M (BIT(29)) 2068 #define RTC_CNTL_BROWN_OUT_CNT_CLR_V 0x1 2069 #define RTC_CNTL_BROWN_OUT_CNT_CLR_S 29 2070 /* RTC_CNTL_BROWN_OUT_ANA_RST_EN : R/W ;bitpos:[28] ;default: 1'b0 ; */ 2071 /*description: */ 2072 #define RTC_CNTL_BROWN_OUT_ANA_RST_EN (BIT(28)) 2073 #define RTC_CNTL_BROWN_OUT_ANA_RST_EN_M (BIT(28)) 2074 #define RTC_CNTL_BROWN_OUT_ANA_RST_EN_V 0x1 2075 #define RTC_CNTL_BROWN_OUT_ANA_RST_EN_S 28 2076 /* RTC_CNTL_BROWN_OUT_RST_SEL : R/W ;bitpos:[27] ;default: 1'b0 ; */ 2077 /*description: 1: 4-pos reset*/ 2078 #define RTC_CNTL_BROWN_OUT_RST_SEL (BIT(27)) 2079 #define RTC_CNTL_BROWN_OUT_RST_SEL_M (BIT(27)) 2080 #define RTC_CNTL_BROWN_OUT_RST_SEL_V 0x1 2081 #define RTC_CNTL_BROWN_OUT_RST_SEL_S 27 2082 /* RTC_CNTL_BROWN_OUT_RST_ENA : R/W ;bitpos:[26] ;default: 1'b0 ; */ 2083 /*description: enable brown out reset*/ 2084 #define RTC_CNTL_BROWN_OUT_RST_ENA (BIT(26)) 2085 #define RTC_CNTL_BROWN_OUT_RST_ENA_M (BIT(26)) 2086 #define RTC_CNTL_BROWN_OUT_RST_ENA_V 0x1 2087 #define RTC_CNTL_BROWN_OUT_RST_ENA_S 26 2088 /* RTC_CNTL_BROWN_OUT_RST_WAIT : R/W ;bitpos:[25:16] ;default: 10'h3ff ; */ 2089 /*description: brown out reset wait cycles*/ 2090 #define RTC_CNTL_BROWN_OUT_RST_WAIT 0x000003FF 2091 #define RTC_CNTL_BROWN_OUT_RST_WAIT_M ((RTC_CNTL_BROWN_OUT_RST_WAIT_V)<<(RTC_CNTL_BROWN_OUT_RST_WAIT_S)) 2092 #define RTC_CNTL_BROWN_OUT_RST_WAIT_V 0x3FF 2093 #define RTC_CNTL_BROWN_OUT_RST_WAIT_S 16 2094 /* RTC_CNTL_BROWN_OUT_PD_RF_ENA : R/W ;bitpos:[15] ;default: 1'b0 ; */ 2095 /*description: enable power down RF when brown out happens*/ 2096 #define RTC_CNTL_BROWN_OUT_PD_RF_ENA (BIT(15)) 2097 #define RTC_CNTL_BROWN_OUT_PD_RF_ENA_M (BIT(15)) 2098 #define RTC_CNTL_BROWN_OUT_PD_RF_ENA_V 0x1 2099 #define RTC_CNTL_BROWN_OUT_PD_RF_ENA_S 15 2100 /* RTC_CNTL_BROWN_OUT_CLOSE_FLASH_ENA : R/W ;bitpos:[14] ;default: 1'b0 ; */ 2101 /*description: enable close flash when brown out happens*/ 2102 #define RTC_CNTL_BROWN_OUT_CLOSE_FLASH_ENA (BIT(14)) 2103 #define RTC_CNTL_BROWN_OUT_CLOSE_FLASH_ENA_M (BIT(14)) 2104 #define RTC_CNTL_BROWN_OUT_CLOSE_FLASH_ENA_V 0x1 2105 #define RTC_CNTL_BROWN_OUT_CLOSE_FLASH_ENA_S 14 2106 /* RTC_CNTL_BROWN_OUT_INT_WAIT : R/W ;bitpos:[13:4] ;default: 10'h1 ; */ 2107 /*description: brown out interrupt wait cycles*/ 2108 #define RTC_CNTL_BROWN_OUT_INT_WAIT 0x000003FF 2109 #define RTC_CNTL_BROWN_OUT_INT_WAIT_M ((RTC_CNTL_BROWN_OUT_INT_WAIT_V)<<(RTC_CNTL_BROWN_OUT_INT_WAIT_S)) 2110 #define RTC_CNTL_BROWN_OUT_INT_WAIT_V 0x3FF 2111 #define RTC_CNTL_BROWN_OUT_INT_WAIT_S 4 2112 2113 #define RTC_CNTL_TIME_LOW1_REG (DR_REG_RTCCNTL_BASE + 0x00DC) 2114 /* RTC_CNTL_TIMER_VALUE1_LOW : RO ;bitpos:[31:0] ;default: 32'h0 ; */ 2115 /*description: RTC timer low 32 bits*/ 2116 #define RTC_CNTL_TIMER_VALUE1_LOW 0xFFFFFFFF 2117 #define RTC_CNTL_TIMER_VALUE1_LOW_M ((RTC_CNTL_TIMER_VALUE1_LOW_V)<<(RTC_CNTL_TIMER_VALUE1_LOW_S)) 2118 #define RTC_CNTL_TIMER_VALUE1_LOW_V 0xFFFFFFFF 2119 #define RTC_CNTL_TIMER_VALUE1_LOW_S 0 2120 2121 #define RTC_CNTL_TIME_HIGH1_REG (DR_REG_RTCCNTL_BASE + 0x00E0) 2122 /* RTC_CNTL_TIMER_VALUE1_HIGH : RO ;bitpos:[15:0] ;default: 16'h0 ; */ 2123 /*description: RTC timer high 16 bits*/ 2124 #define RTC_CNTL_TIMER_VALUE1_HIGH 0x0000FFFF 2125 #define RTC_CNTL_TIMER_VALUE1_HIGH_M ((RTC_CNTL_TIMER_VALUE1_HIGH_V)<<(RTC_CNTL_TIMER_VALUE1_HIGH_S)) 2126 #define RTC_CNTL_TIMER_VALUE1_HIGH_V 0xFFFF 2127 #define RTC_CNTL_TIMER_VALUE1_HIGH_S 0 2128 2129 #define RTC_CNTL_XTAL32K_CLK_FACTOR_REG (DR_REG_RTCCNTL_BASE + 0x00E4) 2130 /* RTC_CNTL_XTAL32K_CLK_FACTOR : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ 2131 /*description: xtal 32k watch dog backup clock factor*/ 2132 #define RTC_CNTL_XTAL32K_CLK_FACTOR 0xFFFFFFFF 2133 #define RTC_CNTL_XTAL32K_CLK_FACTOR_M ((RTC_CNTL_XTAL32K_CLK_FACTOR_V)<<(RTC_CNTL_XTAL32K_CLK_FACTOR_S)) 2134 #define RTC_CNTL_XTAL32K_CLK_FACTOR_V 0xFFFFFFFF 2135 #define RTC_CNTL_XTAL32K_CLK_FACTOR_S 0 2136 2137 #define RTC_CNTL_XTAL32K_CONF_REG (DR_REG_RTCCNTL_BASE + 0x00E8) 2138 /* RTC_CNTL_XTAL32K_STABLE_THRES : R/W ;bitpos:[31:28] ;default: 4'h0 ; */ 2139 /*description: if restarted xtal32k period is smaller than this*/ 2140 #define RTC_CNTL_XTAL32K_STABLE_THRES 0x0000000F 2141 #define RTC_CNTL_XTAL32K_STABLE_THRES_M ((RTC_CNTL_XTAL32K_STABLE_THRES_V)<<(RTC_CNTL_XTAL32K_STABLE_THRES_S)) 2142 #define RTC_CNTL_XTAL32K_STABLE_THRES_V 0xF 2143 #define RTC_CNTL_XTAL32K_STABLE_THRES_S 28 2144 /* RTC_CNTL_XTAL32K_WDT_TIMEOUT : R/W ;bitpos:[27:20] ;default: 8'hff ; */ 2145 /*description: If no clock detected for this amount of time*/ 2146 #define RTC_CNTL_XTAL32K_WDT_TIMEOUT 0x000000FF 2147 #define RTC_CNTL_XTAL32K_WDT_TIMEOUT_M ((RTC_CNTL_XTAL32K_WDT_TIMEOUT_V)<<(RTC_CNTL_XTAL32K_WDT_TIMEOUT_S)) 2148 #define RTC_CNTL_XTAL32K_WDT_TIMEOUT_V 0xFF 2149 #define RTC_CNTL_XTAL32K_WDT_TIMEOUT_S 20 2150 /* RTC_CNTL_XTAL32K_RESTART_WAIT : R/W ;bitpos:[19:4] ;default: 16'h0 ; */ 2151 /*description: cycles to wait to repower on xtal 32k*/ 2152 #define RTC_CNTL_XTAL32K_RESTART_WAIT 0x0000FFFF 2153 #define RTC_CNTL_XTAL32K_RESTART_WAIT_M ((RTC_CNTL_XTAL32K_RESTART_WAIT_V)<<(RTC_CNTL_XTAL32K_RESTART_WAIT_S)) 2154 #define RTC_CNTL_XTAL32K_RESTART_WAIT_V 0xFFFF 2155 #define RTC_CNTL_XTAL32K_RESTART_WAIT_S 4 2156 /* RTC_CNTL_XTAL32K_RETURN_WAIT : R/W ;bitpos:[3:0] ;default: 4'h0 ; */ 2157 /*description: cycles to wait to return noral xtal 32k*/ 2158 #define RTC_CNTL_XTAL32K_RETURN_WAIT 0x0000000F 2159 #define RTC_CNTL_XTAL32K_RETURN_WAIT_M ((RTC_CNTL_XTAL32K_RETURN_WAIT_V)<<(RTC_CNTL_XTAL32K_RETURN_WAIT_S)) 2160 #define RTC_CNTL_XTAL32K_RETURN_WAIT_V 0xF 2161 #define RTC_CNTL_XTAL32K_RETURN_WAIT_S 0 2162 2163 #define RTC_CNTL_USB_CONF_REG (DR_REG_RTCCNTL_BASE + 0x00EC) 2164 /* RTC_CNTL_IO_MUX_RESET_DISABLE : R/W ;bitpos:[18] ;default: 1'd0 ; */ 2165 /*description: */ 2166 #define RTC_CNTL_IO_MUX_RESET_DISABLE (BIT(18)) 2167 #define RTC_CNTL_IO_MUX_RESET_DISABLE_M (BIT(18)) 2168 #define RTC_CNTL_IO_MUX_RESET_DISABLE_V 0x1 2169 #define RTC_CNTL_IO_MUX_RESET_DISABLE_S 18 2170 2171 #define RTC_CNTL_SLP_REJECT_CAUSE_REG (DR_REG_RTCCNTL_BASE + 0x00F0) 2172 /* RTC_CNTL_REJECT_CAUSE : RO ;bitpos:[17:0] ;default: 18'd0 ; */ 2173 /*description: sleep reject cause*/ 2174 #define RTC_CNTL_REJECT_CAUSE 0x0003FFFF 2175 #define RTC_CNTL_REJECT_CAUSE_M ((RTC_CNTL_REJECT_CAUSE_V)<<(RTC_CNTL_REJECT_CAUSE_S)) 2176 #define RTC_CNTL_REJECT_CAUSE_V 0x3FFFF 2177 #define RTC_CNTL_REJECT_CAUSE_S 0 2178 2179 #define RTC_CNTL_OPTION1_REG (DR_REG_RTCCNTL_BASE + 0x00F4) 2180 /* RTC_CNTL_FORCE_DOWNLOAD_BOOT : R/W ;bitpos:[0] ;default: 1'd0 ; */ 2181 /*description: */ 2182 #define RTC_CNTL_FORCE_DOWNLOAD_BOOT (BIT(0)) 2183 #define RTC_CNTL_FORCE_DOWNLOAD_BOOT_M (BIT(0)) 2184 #define RTC_CNTL_FORCE_DOWNLOAD_BOOT_V 0x1 2185 #define RTC_CNTL_FORCE_DOWNLOAD_BOOT_S 0 2186 2187 #define RTC_CNTL_SLP_WAKEUP_CAUSE_REG (DR_REG_RTCCNTL_BASE + 0x00F8) 2188 /* RTC_CNTL_WAKEUP_CAUSE : RO ;bitpos:[16:0] ;default: 17'd0 ; */ 2189 /*description: sleep wakeup cause*/ 2190 #define RTC_CNTL_WAKEUP_CAUSE 0x0001FFFF 2191 #define RTC_CNTL_WAKEUP_CAUSE_M ((RTC_CNTL_WAKEUP_CAUSE_V)<<(RTC_CNTL_WAKEUP_CAUSE_S)) 2192 #define RTC_CNTL_WAKEUP_CAUSE_V 0x1FFFF 2193 #define RTC_CNTL_WAKEUP_CAUSE_S 0 2194 2195 #define RTC_CNTL_ULP_CP_TIMER_1_REG (DR_REG_RTCCNTL_BASE + 0x00FC) 2196 /* RTC_CNTL_ULP_CP_TIMER_SLP_CYCLE : R/W ;bitpos:[31:8] ;default: 24'd200 ; */ 2197 /*description: sleep cycles for ULP-coprocessor timer*/ 2198 #define RTC_CNTL_ULP_CP_TIMER_SLP_CYCLE 0x00FFFFFF 2199 #define RTC_CNTL_ULP_CP_TIMER_SLP_CYCLE_M ((RTC_CNTL_ULP_CP_TIMER_SLP_CYCLE_V)<<(RTC_CNTL_ULP_CP_TIMER_SLP_CYCLE_S)) 2200 #define RTC_CNTL_ULP_CP_TIMER_SLP_CYCLE_V 0xFFFFFF 2201 #define RTC_CNTL_ULP_CP_TIMER_SLP_CYCLE_S 8 2202 2203 #define RTC_CNTL_INT_ENA_W1TS_REG (DR_REG_RTCCNTL_BASE + 0x0100) 2204 /* RTC_CNTL_BBPLL_CAL_INT_ENA_W1TS : WO ;bitpos:[20] ;default: 1'b0 ; */ 2205 /*description: */ 2206 #define RTC_CNTL_BBPLL_CAL_INT_ENA_W1TS (BIT(20)) 2207 #define RTC_CNTL_BBPLL_CAL_INT_ENA_W1TS_M (BIT(20)) 2208 #define RTC_CNTL_BBPLL_CAL_INT_ENA_W1TS_V 0x1 2209 #define RTC_CNTL_BBPLL_CAL_INT_ENA_W1TS_S 20 2210 /* RTC_CNTL_GLITCH_DET_INT_ENA_W1TS : WO ;bitpos:[19] ;default: 1'b0 ; */ 2211 /*description: enbale gitch det interrupt*/ 2212 #define RTC_CNTL_GLITCH_DET_INT_ENA_W1TS (BIT(19)) 2213 #define RTC_CNTL_GLITCH_DET_INT_ENA_W1TS_M (BIT(19)) 2214 #define RTC_CNTL_GLITCH_DET_INT_ENA_W1TS_V 0x1 2215 #define RTC_CNTL_GLITCH_DET_INT_ENA_W1TS_S 19 2216 /* RTC_CNTL_XTAL32K_DEAD_INT_ENA_W1TS : WO ;bitpos:[16] ;default: 1'b0 ; */ 2217 /*description: enable xtal32k_dead interrupt*/ 2218 #define RTC_CNTL_XTAL32K_DEAD_INT_ENA_W1TS (BIT(16)) 2219 #define RTC_CNTL_XTAL32K_DEAD_INT_ENA_W1TS_M (BIT(16)) 2220 #define RTC_CNTL_XTAL32K_DEAD_INT_ENA_W1TS_V 0x1 2221 #define RTC_CNTL_XTAL32K_DEAD_INT_ENA_W1TS_S 16 2222 /* RTC_CNTL_SWD_INT_ENA_W1TS : WO ;bitpos:[15] ;default: 1'b0 ; */ 2223 /*description: enable super watch dog interrupt*/ 2224 #define RTC_CNTL_SWD_INT_ENA_W1TS (BIT(15)) 2225 #define RTC_CNTL_SWD_INT_ENA_W1TS_M (BIT(15)) 2226 #define RTC_CNTL_SWD_INT_ENA_W1TS_V 0x1 2227 #define RTC_CNTL_SWD_INT_ENA_W1TS_S 15 2228 /* RTC_CNTL_MAIN_TIMER_INT_ENA_W1TS : WO ;bitpos:[10] ;default: 1'b0 ; */ 2229 /*description: enable RTC main timer interrupt*/ 2230 #define RTC_CNTL_MAIN_TIMER_INT_ENA_W1TS (BIT(10)) 2231 #define RTC_CNTL_MAIN_TIMER_INT_ENA_W1TS_M (BIT(10)) 2232 #define RTC_CNTL_MAIN_TIMER_INT_ENA_W1TS_V 0x1 2233 #define RTC_CNTL_MAIN_TIMER_INT_ENA_W1TS_S 10 2234 /* RTC_CNTL_BROWN_OUT_INT_ENA_W1TS : WO ;bitpos:[9] ;default: 1'b0 ; */ 2235 /*description: enable brown out interrupt*/ 2236 #define RTC_CNTL_BROWN_OUT_INT_ENA_W1TS (BIT(9)) 2237 #define RTC_CNTL_BROWN_OUT_INT_ENA_W1TS_M (BIT(9)) 2238 #define RTC_CNTL_BROWN_OUT_INT_ENA_W1TS_V 0x1 2239 #define RTC_CNTL_BROWN_OUT_INT_ENA_W1TS_S 9 2240 /* RTC_CNTL_WDT_INT_ENA_W1TS : WO ;bitpos:[3] ;default: 1'b0 ; */ 2241 /*description: enable RTC WDT interrupt*/ 2242 #define RTC_CNTL_WDT_INT_ENA_W1TS (BIT(3)) 2243 #define RTC_CNTL_WDT_INT_ENA_W1TS_M (BIT(3)) 2244 #define RTC_CNTL_WDT_INT_ENA_W1TS_V 0x1 2245 #define RTC_CNTL_WDT_INT_ENA_W1TS_S 3 2246 /* RTC_CNTL_SLP_REJECT_INT_ENA_W1TS : WO ;bitpos:[1] ;default: 1'b0 ; */ 2247 /*description: enable sleep reject interrupt*/ 2248 #define RTC_CNTL_SLP_REJECT_INT_ENA_W1TS (BIT(1)) 2249 #define RTC_CNTL_SLP_REJECT_INT_ENA_W1TS_M (BIT(1)) 2250 #define RTC_CNTL_SLP_REJECT_INT_ENA_W1TS_V 0x1 2251 #define RTC_CNTL_SLP_REJECT_INT_ENA_W1TS_S 1 2252 /* RTC_CNTL_SLP_WAKEUP_INT_ENA_W1TS : WO ;bitpos:[0] ;default: 1'b0 ; */ 2253 /*description: enable sleep wakeup interrupt*/ 2254 #define RTC_CNTL_SLP_WAKEUP_INT_ENA_W1TS (BIT(0)) 2255 #define RTC_CNTL_SLP_WAKEUP_INT_ENA_W1TS_M (BIT(0)) 2256 #define RTC_CNTL_SLP_WAKEUP_INT_ENA_W1TS_V 0x1 2257 #define RTC_CNTL_SLP_WAKEUP_INT_ENA_W1TS_S 0 2258 2259 #define RTC_CNTL_INT_ENA_W1TC_REG (DR_REG_RTCCNTL_BASE + 0x0104) 2260 /* RTC_CNTL_BBPLL_CAL_INT_ENA_W1TC : WO ;bitpos:[20] ;default: 1'b0 ; */ 2261 /*description: */ 2262 #define RTC_CNTL_BBPLL_CAL_INT_ENA_W1TC (BIT(20)) 2263 #define RTC_CNTL_BBPLL_CAL_INT_ENA_W1TC_M (BIT(20)) 2264 #define RTC_CNTL_BBPLL_CAL_INT_ENA_W1TC_V 0x1 2265 #define RTC_CNTL_BBPLL_CAL_INT_ENA_W1TC_S 20 2266 /* RTC_CNTL_GLITCH_DET_INT_ENA_W1TC : WO ;bitpos:[19] ;default: 1'b0 ; */ 2267 /*description: enbale gitch det interrupt*/ 2268 #define RTC_CNTL_GLITCH_DET_INT_ENA_W1TC (BIT(19)) 2269 #define RTC_CNTL_GLITCH_DET_INT_ENA_W1TC_M (BIT(19)) 2270 #define RTC_CNTL_GLITCH_DET_INT_ENA_W1TC_V 0x1 2271 #define RTC_CNTL_GLITCH_DET_INT_ENA_W1TC_S 19 2272 /* RTC_CNTL_XTAL32K_DEAD_INT_ENA_W1TC : WO ;bitpos:[16] ;default: 1'b0 ; */ 2273 /*description: enable xtal32k_dead interrupt*/ 2274 #define RTC_CNTL_XTAL32K_DEAD_INT_ENA_W1TC (BIT(16)) 2275 #define RTC_CNTL_XTAL32K_DEAD_INT_ENA_W1TC_M (BIT(16)) 2276 #define RTC_CNTL_XTAL32K_DEAD_INT_ENA_W1TC_V 0x1 2277 #define RTC_CNTL_XTAL32K_DEAD_INT_ENA_W1TC_S 16 2278 /* RTC_CNTL_SWD_INT_ENA_W1TC : WO ;bitpos:[15] ;default: 1'b0 ; */ 2279 /*description: enable super watch dog interrupt*/ 2280 #define RTC_CNTL_SWD_INT_ENA_W1TC (BIT(15)) 2281 #define RTC_CNTL_SWD_INT_ENA_W1TC_M (BIT(15)) 2282 #define RTC_CNTL_SWD_INT_ENA_W1TC_V 0x1 2283 #define RTC_CNTL_SWD_INT_ENA_W1TC_S 15 2284 /* RTC_CNTL_MAIN_TIMER_INT_ENA_W1TC : WO ;bitpos:[10] ;default: 1'b0 ; */ 2285 /*description: enable RTC main timer interrupt*/ 2286 #define RTC_CNTL_MAIN_TIMER_INT_ENA_W1TC (BIT(10)) 2287 #define RTC_CNTL_MAIN_TIMER_INT_ENA_W1TC_M (BIT(10)) 2288 #define RTC_CNTL_MAIN_TIMER_INT_ENA_W1TC_V 0x1 2289 #define RTC_CNTL_MAIN_TIMER_INT_ENA_W1TC_S 10 2290 /* RTC_CNTL_BROWN_OUT_INT_ENA_W1TC : WO ;bitpos:[9] ;default: 1'b0 ; */ 2291 /*description: enable brown out interrupt*/ 2292 #define RTC_CNTL_BROWN_OUT_INT_ENA_W1TC (BIT(9)) 2293 #define RTC_CNTL_BROWN_OUT_INT_ENA_W1TC_M (BIT(9)) 2294 #define RTC_CNTL_BROWN_OUT_INT_ENA_W1TC_V 0x1 2295 #define RTC_CNTL_BROWN_OUT_INT_ENA_W1TC_S 9 2296 /* RTC_CNTL_WDT_INT_ENA_W1TC : WO ;bitpos:[3] ;default: 1'b0 ; */ 2297 /*description: enable RTC WDT interrupt*/ 2298 #define RTC_CNTL_WDT_INT_ENA_W1TC (BIT(3)) 2299 #define RTC_CNTL_WDT_INT_ENA_W1TC_M (BIT(3)) 2300 #define RTC_CNTL_WDT_INT_ENA_W1TC_V 0x1 2301 #define RTC_CNTL_WDT_INT_ENA_W1TC_S 3 2302 /* RTC_CNTL_SLP_REJECT_INT_ENA_W1TC : WO ;bitpos:[1] ;default: 1'b0 ; */ 2303 /*description: enable sleep reject interrupt*/ 2304 #define RTC_CNTL_SLP_REJECT_INT_ENA_W1TC (BIT(1)) 2305 #define RTC_CNTL_SLP_REJECT_INT_ENA_W1TC_M (BIT(1)) 2306 #define RTC_CNTL_SLP_REJECT_INT_ENA_W1TC_V 0x1 2307 #define RTC_CNTL_SLP_REJECT_INT_ENA_W1TC_S 1 2308 /* RTC_CNTL_SLP_WAKEUP_INT_ENA_W1TC : WO ;bitpos:[0] ;default: 1'b0 ; */ 2309 /*description: enable sleep wakeup interrupt*/ 2310 #define RTC_CNTL_SLP_WAKEUP_INT_ENA_W1TC (BIT(0)) 2311 #define RTC_CNTL_SLP_WAKEUP_INT_ENA_W1TC_M (BIT(0)) 2312 #define RTC_CNTL_SLP_WAKEUP_INT_ENA_W1TC_V 0x1 2313 #define RTC_CNTL_SLP_WAKEUP_INT_ENA_W1TC_S 0 2314 2315 #define RTC_CNTL_RETENTION_CTRL_REG (DR_REG_RTCCNTL_BASE + 0x0108) 2316 /* RTC_CNTL_RETENTION_WAIT : R/W ;bitpos:[31:27] ;default: 5'd20 ; */ 2317 /*description: wait cycles for rention operation*/ 2318 #define RTC_CNTL_RETENTION_WAIT 0x0000001F 2319 #define RTC_CNTL_RETENTION_WAIT_M ((RTC_CNTL_RETENTION_WAIT_V)<<(RTC_CNTL_RETENTION_WAIT_S)) 2320 #define RTC_CNTL_RETENTION_WAIT_V 0x1F 2321 #define RTC_CNTL_RETENTION_WAIT_S 27 2322 /* RTC_CNTL_RETENTION_EN : R/W ;bitpos:[26] ;default: 1'd0 ; */ 2323 /*description: */ 2324 #define RTC_CNTL_RETENTION_EN (BIT(26)) 2325 #define RTC_CNTL_RETENTION_EN_M (BIT(26)) 2326 #define RTC_CNTL_RETENTION_EN_V 0x1 2327 #define RTC_CNTL_RETENTION_EN_S 26 2328 /* RTC_CNTL_RETENTION_CLKOFF_WAIT : R/W ;bitpos:[25:22] ;default: 4'd3 ; */ 2329 /*description: */ 2330 #define RTC_CNTL_RETENTION_CLKOFF_WAIT 0x0000000F 2331 #define RTC_CNTL_RETENTION_CLKOFF_WAIT_M ((RTC_CNTL_RETENTION_CLKOFF_WAIT_V)<<(RTC_CNTL_RETENTION_CLKOFF_WAIT_S)) 2332 #define RTC_CNTL_RETENTION_CLKOFF_WAIT_V 0xF 2333 #define RTC_CNTL_RETENTION_CLKOFF_WAIT_S 22 2334 /* RTC_CNTL_RETENTION_DONE_WAIT : R/W ;bitpos:[21:19] ;default: 3'd2 ; */ 2335 /*description: */ 2336 #define RTC_CNTL_RETENTION_DONE_WAIT 0x00000007 2337 #define RTC_CNTL_RETENTION_DONE_WAIT_M ((RTC_CNTL_RETENTION_DONE_WAIT_V)<<(RTC_CNTL_RETENTION_DONE_WAIT_S)) 2338 #define RTC_CNTL_RETENTION_DONE_WAIT_V 0x7 2339 #define RTC_CNTL_RETENTION_DONE_WAIT_S 19 2340 /* RTC_CNTL_RETENTION_CLK_SEL : R/W ;bitpos:[18] ;default: 1'b0 ; */ 2341 /*description: */ 2342 #define RTC_CNTL_RETENTION_CLK_SEL (BIT(18)) 2343 #define RTC_CNTL_RETENTION_CLK_SEL_M (BIT(18)) 2344 #define RTC_CNTL_RETENTION_CLK_SEL_V 0x1 2345 #define RTC_CNTL_RETENTION_CLK_SEL_S 18 2346 2347 #define RTC_CNTL_FIB_SEL_REG (DR_REG_RTCCNTL_BASE + 0x010C) 2348 /* RTC_CNTL_FIB_SEL : R/W ;bitpos:[2:0] ;default: 3'd7 ; */ 2349 /*description: select use analog fib signal*/ 2350 #define RTC_CNTL_FIB_SEL 0x00000007 2351 #define RTC_CNTL_FIB_SEL_M ((RTC_CNTL_FIB_SEL_V)<<(RTC_CNTL_FIB_SEL_S)) 2352 #define RTC_CNTL_FIB_SEL_V 0x7 2353 #define RTC_CNTL_FIB_SEL_S 0 2354 2355 #define RTC_CNTL_FIB_GLITCH_RST BIT(0) 2356 #define RTC_CNTL_FIB_BOD_RST BIT(1) 2357 #define RTC_CNTL_FIB_SUPER_WDT_RST BIT(2) 2358 2359 #define RTC_CNTL_GPIO_WAKEUP_REG (DR_REG_RTCCNTL_BASE + 0x0110) 2360 /* RTC_CNTL_GPIO_PIN0_WAKEUP_ENABLE : R/W ;bitpos:[31] ;default: 1'b0 ; */ 2361 /*description: */ 2362 #define RTC_CNTL_GPIO_PIN0_WAKEUP_ENABLE (BIT(31)) 2363 #define RTC_CNTL_GPIO_PIN0_WAKEUP_ENABLE_M (BIT(31)) 2364 #define RTC_CNTL_GPIO_PIN0_WAKEUP_ENABLE_V 0x1 2365 #define RTC_CNTL_GPIO_PIN0_WAKEUP_ENABLE_S 31 2366 /* RTC_CNTL_GPIO_PIN1_WAKEUP_ENABLE : R/W ;bitpos:[30] ;default: 1'b0 ; */ 2367 /*description: */ 2368 #define RTC_CNTL_GPIO_PIN1_WAKEUP_ENABLE (BIT(30)) 2369 #define RTC_CNTL_GPIO_PIN1_WAKEUP_ENABLE_M (BIT(30)) 2370 #define RTC_CNTL_GPIO_PIN1_WAKEUP_ENABLE_V 0x1 2371 #define RTC_CNTL_GPIO_PIN1_WAKEUP_ENABLE_S 30 2372 /* RTC_CNTL_GPIO_PIN2_WAKEUP_ENABLE : R/W ;bitpos:[29] ;default: 1'b0 ; */ 2373 /*description: */ 2374 #define RTC_CNTL_GPIO_PIN2_WAKEUP_ENABLE (BIT(29)) 2375 #define RTC_CNTL_GPIO_PIN2_WAKEUP_ENABLE_M (BIT(29)) 2376 #define RTC_CNTL_GPIO_PIN2_WAKEUP_ENABLE_V 0x1 2377 #define RTC_CNTL_GPIO_PIN2_WAKEUP_ENABLE_S 29 2378 /* RTC_CNTL_GPIO_PIN3_WAKEUP_ENABLE : R/W ;bitpos:[28] ;default: 1'b0 ; */ 2379 /*description: */ 2380 #define RTC_CNTL_GPIO_PIN3_WAKEUP_ENABLE (BIT(28)) 2381 #define RTC_CNTL_GPIO_PIN3_WAKEUP_ENABLE_M (BIT(28)) 2382 #define RTC_CNTL_GPIO_PIN3_WAKEUP_ENABLE_V 0x1 2383 #define RTC_CNTL_GPIO_PIN3_WAKEUP_ENABLE_S 28 2384 /* RTC_CNTL_GPIO_PIN4_WAKEUP_ENABLE : R/W ;bitpos:[27] ;default: 1'b0 ; */ 2385 /*description: */ 2386 #define RTC_CNTL_GPIO_PIN4_WAKEUP_ENABLE (BIT(27)) 2387 #define RTC_CNTL_GPIO_PIN4_WAKEUP_ENABLE_M (BIT(27)) 2388 #define RTC_CNTL_GPIO_PIN4_WAKEUP_ENABLE_V 0x1 2389 #define RTC_CNTL_GPIO_PIN4_WAKEUP_ENABLE_S 27 2390 /* RTC_CNTL_GPIO_PIN5_WAKEUP_ENABLE : R/W ;bitpos:[26] ;default: 1'b0 ; */ 2391 /*description: */ 2392 #define RTC_CNTL_GPIO_PIN5_WAKEUP_ENABLE (BIT(26)) 2393 #define RTC_CNTL_GPIO_PIN5_WAKEUP_ENABLE_M (BIT(26)) 2394 #define RTC_CNTL_GPIO_PIN5_WAKEUP_ENABLE_V 0x1 2395 #define RTC_CNTL_GPIO_PIN5_WAKEUP_ENABLE_S 26 2396 /* RTC_CNTL_GPIO_PIN0_INT_TYPE : R/W ;bitpos:[25:23] ;default: 3'd0 ; */ 2397 /*description: */ 2398 #define RTC_CNTL_GPIO_PIN0_INT_TYPE 0x00000007 2399 #define RTC_CNTL_GPIO_PIN0_INT_TYPE_M ((RTC_CNTL_GPIO_PIN0_INT_TYPE_V)<<(RTC_CNTL_GPIO_PIN0_INT_TYPE_S)) 2400 #define RTC_CNTL_GPIO_PIN0_INT_TYPE_V 0x7 2401 #define RTC_CNTL_GPIO_PIN0_INT_TYPE_S 23 2402 /* RTC_CNTL_GPIO_PIN1_INT_TYPE : R/W ;bitpos:[22:20] ;default: 3'd0 ; */ 2403 /*description: */ 2404 #define RTC_CNTL_GPIO_PIN1_INT_TYPE 0x00000007 2405 #define RTC_CNTL_GPIO_PIN1_INT_TYPE_M ((RTC_CNTL_GPIO_PIN1_INT_TYPE_V)<<(RTC_CNTL_GPIO_PIN1_INT_TYPE_S)) 2406 #define RTC_CNTL_GPIO_PIN1_INT_TYPE_V 0x7 2407 #define RTC_CNTL_GPIO_PIN1_INT_TYPE_S 20 2408 /* RTC_CNTL_GPIO_PIN2_INT_TYPE : R/W ;bitpos:[19:17] ;default: 3'd0 ; */ 2409 /*description: */ 2410 #define RTC_CNTL_GPIO_PIN2_INT_TYPE 0x00000007 2411 #define RTC_CNTL_GPIO_PIN2_INT_TYPE_M ((RTC_CNTL_GPIO_PIN2_INT_TYPE_V)<<(RTC_CNTL_GPIO_PIN2_INT_TYPE_S)) 2412 #define RTC_CNTL_GPIO_PIN2_INT_TYPE_V 0x7 2413 #define RTC_CNTL_GPIO_PIN2_INT_TYPE_S 17 2414 /* RTC_CNTL_GPIO_PIN3_INT_TYPE : R/W ;bitpos:[16:14] ;default: 3'd0 ; */ 2415 /*description: */ 2416 #define RTC_CNTL_GPIO_PIN3_INT_TYPE 0x00000007 2417 #define RTC_CNTL_GPIO_PIN3_INT_TYPE_M ((RTC_CNTL_GPIO_PIN3_INT_TYPE_V)<<(RTC_CNTL_GPIO_PIN3_INT_TYPE_S)) 2418 #define RTC_CNTL_GPIO_PIN3_INT_TYPE_V 0x7 2419 #define RTC_CNTL_GPIO_PIN3_INT_TYPE_S 14 2420 /* RTC_CNTL_GPIO_PIN4_INT_TYPE : R/W ;bitpos:[13:11] ;default: 3'd0 ; */ 2421 /*description: */ 2422 #define RTC_CNTL_GPIO_PIN4_INT_TYPE 0x00000007 2423 #define RTC_CNTL_GPIO_PIN4_INT_TYPE_M ((RTC_CNTL_GPIO_PIN4_INT_TYPE_V)<<(RTC_CNTL_GPIO_PIN4_INT_TYPE_S)) 2424 #define RTC_CNTL_GPIO_PIN4_INT_TYPE_V 0x7 2425 #define RTC_CNTL_GPIO_PIN4_INT_TYPE_S 11 2426 /* RTC_CNTL_GPIO_PIN5_INT_TYPE : R/W ;bitpos:[10:8] ;default: 3'd0 ; */ 2427 /*description: */ 2428 #define RTC_CNTL_GPIO_PIN5_INT_TYPE 0x00000007 2429 #define RTC_CNTL_GPIO_PIN5_INT_TYPE_M ((RTC_CNTL_GPIO_PIN5_INT_TYPE_V)<<(RTC_CNTL_GPIO_PIN5_INT_TYPE_S)) 2430 #define RTC_CNTL_GPIO_PIN5_INT_TYPE_V 0x7 2431 #define RTC_CNTL_GPIO_PIN5_INT_TYPE_S 8 2432 /* RTC_CNTL_GPIO_PIN_CLK_GATE : R/W ;bitpos:[7] ;default: 1'b0 ; */ 2433 /*description: */ 2434 #define RTC_CNTL_GPIO_PIN_CLK_GATE (BIT(7)) 2435 #define RTC_CNTL_GPIO_PIN_CLK_GATE_M (BIT(7)) 2436 #define RTC_CNTL_GPIO_PIN_CLK_GATE_V 0x1 2437 #define RTC_CNTL_GPIO_PIN_CLK_GATE_S 7 2438 /* RTC_CNTL_GPIO_WAKEUP_STATUS_CLR : R/W ;bitpos:[6] ;default: 1'b0 ; */ 2439 /*description: */ 2440 #define RTC_CNTL_GPIO_WAKEUP_STATUS_CLR (BIT(6)) 2441 #define RTC_CNTL_GPIO_WAKEUP_STATUS_CLR_M (BIT(6)) 2442 #define RTC_CNTL_GPIO_WAKEUP_STATUS_CLR_V 0x1 2443 #define RTC_CNTL_GPIO_WAKEUP_STATUS_CLR_S 6 2444 /* RTC_CNTL_GPIO_WAKEUP_STATUS : RO ;bitpos:[5:0] ;default: 6'b0 ; */ 2445 /*description: */ 2446 #define RTC_CNTL_GPIO_WAKEUP_STATUS 0x0000003F 2447 #define RTC_CNTL_GPIO_WAKEUP_STATUS_M ((RTC_CNTL_GPIO_WAKEUP_STATUS_V)<<(RTC_CNTL_GPIO_WAKEUP_STATUS_S)) 2448 #define RTC_CNTL_GPIO_WAKEUP_STATUS_V 0x3F 2449 #define RTC_CNTL_GPIO_WAKEUP_STATUS_S 0 2450 2451 #define RTC_CNTL_DBG_SEL_REG (DR_REG_RTCCNTL_BASE + 0x0114) 2452 /* RTC_CNTL_DEBUG_SEL4 : R/W ;bitpos:[31:27] ;default: 5'd0 ; */ 2453 /*description: */ 2454 #define RTC_CNTL_DEBUG_SEL4 0x0000001F 2455 #define RTC_CNTL_DEBUG_SEL4_M ((RTC_CNTL_DEBUG_SEL4_V)<<(RTC_CNTL_DEBUG_SEL4_S)) 2456 #define RTC_CNTL_DEBUG_SEL4_V 0x1F 2457 #define RTC_CNTL_DEBUG_SEL4_S 27 2458 /* RTC_CNTL_DEBUG_SEL3 : R/W ;bitpos:[26:22] ;default: 5'd0 ; */ 2459 /*description: */ 2460 #define RTC_CNTL_DEBUG_SEL3 0x0000001F 2461 #define RTC_CNTL_DEBUG_SEL3_M ((RTC_CNTL_DEBUG_SEL3_V)<<(RTC_CNTL_DEBUG_SEL3_S)) 2462 #define RTC_CNTL_DEBUG_SEL3_V 0x1F 2463 #define RTC_CNTL_DEBUG_SEL3_S 22 2464 /* RTC_CNTL_DEBUG_SEL2 : R/W ;bitpos:[21:17] ;default: 5'd0 ; */ 2465 /*description: */ 2466 #define RTC_CNTL_DEBUG_SEL2 0x0000001F 2467 #define RTC_CNTL_DEBUG_SEL2_M ((RTC_CNTL_DEBUG_SEL2_V)<<(RTC_CNTL_DEBUG_SEL2_S)) 2468 #define RTC_CNTL_DEBUG_SEL2_V 0x1F 2469 #define RTC_CNTL_DEBUG_SEL2_S 17 2470 /* RTC_CNTL_DEBUG_SEL1 : R/W ;bitpos:[16:12] ;default: 5'd0 ; */ 2471 /*description: */ 2472 #define RTC_CNTL_DEBUG_SEL1 0x0000001F 2473 #define RTC_CNTL_DEBUG_SEL1_M ((RTC_CNTL_DEBUG_SEL1_V)<<(RTC_CNTL_DEBUG_SEL1_S)) 2474 #define RTC_CNTL_DEBUG_SEL1_V 0x1F 2475 #define RTC_CNTL_DEBUG_SEL1_S 12 2476 /* RTC_CNTL_DEBUG_SEL0 : R/W ;bitpos:[11:7] ;default: 5'd0 ; */ 2477 /*description: */ 2478 #define RTC_CNTL_DEBUG_SEL0 0x0000001F 2479 #define RTC_CNTL_DEBUG_SEL0_M ((RTC_CNTL_DEBUG_SEL0_V)<<(RTC_CNTL_DEBUG_SEL0_S)) 2480 #define RTC_CNTL_DEBUG_SEL0_V 0x1F 2481 #define RTC_CNTL_DEBUG_SEL0_S 7 2482 /* RTC_CNTL_DEBUG_BIT_SEL : R/W ;bitpos:[6:2] ;default: 5'd0 ; */ 2483 /*description: */ 2484 #define RTC_CNTL_DEBUG_BIT_SEL 0x0000001F 2485 #define RTC_CNTL_DEBUG_BIT_SEL_M ((RTC_CNTL_DEBUG_BIT_SEL_V)<<(RTC_CNTL_DEBUG_BIT_SEL_S)) 2486 #define RTC_CNTL_DEBUG_BIT_SEL_V 0x1F 2487 #define RTC_CNTL_DEBUG_BIT_SEL_S 2 2488 /* RTC_CNTL_DEBUG_12M_NO_GATING : R/W ;bitpos:[1] ;default: 1'b0 ; */ 2489 /*description: */ 2490 #define RTC_CNTL_DEBUG_12M_NO_GATING (BIT(1)) 2491 #define RTC_CNTL_DEBUG_12M_NO_GATING_M (BIT(1)) 2492 #define RTC_CNTL_DEBUG_12M_NO_GATING_V 0x1 2493 #define RTC_CNTL_DEBUG_12M_NO_GATING_S 1 2494 2495 #define RTC_CNTL_DBG_MAP_REG (DR_REG_RTCCNTL_BASE + 0x0118) 2496 /* RTC_CNTL_GPIO_PIN0_FUN_SEL : R/W ;bitpos:[31:28] ;default: 4'd0 ; */ 2497 /*description: */ 2498 #define RTC_CNTL_GPIO_PIN0_FUN_SEL 0x0000000F 2499 #define RTC_CNTL_GPIO_PIN0_FUN_SEL_M ((RTC_CNTL_GPIO_PIN0_FUN_SEL_V)<<(RTC_CNTL_GPIO_PIN0_FUN_SEL_S)) 2500 #define RTC_CNTL_GPIO_PIN0_FUN_SEL_V 0xF 2501 #define RTC_CNTL_GPIO_PIN0_FUN_SEL_S 28 2502 /* RTC_CNTL_GPIO_PIN1_FUN_SEL : R/W ;bitpos:[27:24] ;default: 4'd0 ; */ 2503 /*description: */ 2504 #define RTC_CNTL_GPIO_PIN1_FUN_SEL 0x0000000F 2505 #define RTC_CNTL_GPIO_PIN1_FUN_SEL_M ((RTC_CNTL_GPIO_PIN1_FUN_SEL_V)<<(RTC_CNTL_GPIO_PIN1_FUN_SEL_S)) 2506 #define RTC_CNTL_GPIO_PIN1_FUN_SEL_V 0xF 2507 #define RTC_CNTL_GPIO_PIN1_FUN_SEL_S 24 2508 /* RTC_CNTL_GPIO_PIN2_FUN_SEL : R/W ;bitpos:[23:20] ;default: 4'd0 ; */ 2509 /*description: */ 2510 #define RTC_CNTL_GPIO_PIN2_FUN_SEL 0x0000000F 2511 #define RTC_CNTL_GPIO_PIN2_FUN_SEL_M ((RTC_CNTL_GPIO_PIN2_FUN_SEL_V)<<(RTC_CNTL_GPIO_PIN2_FUN_SEL_S)) 2512 #define RTC_CNTL_GPIO_PIN2_FUN_SEL_V 0xF 2513 #define RTC_CNTL_GPIO_PIN2_FUN_SEL_S 20 2514 /* RTC_CNTL_GPIO_PIN3_FUN_SEL : R/W ;bitpos:[19:16] ;default: 4'd0 ; */ 2515 /*description: */ 2516 #define RTC_CNTL_GPIO_PIN3_FUN_SEL 0x0000000F 2517 #define RTC_CNTL_GPIO_PIN3_FUN_SEL_M ((RTC_CNTL_GPIO_PIN3_FUN_SEL_V)<<(RTC_CNTL_GPIO_PIN3_FUN_SEL_S)) 2518 #define RTC_CNTL_GPIO_PIN3_FUN_SEL_V 0xF 2519 #define RTC_CNTL_GPIO_PIN3_FUN_SEL_S 16 2520 /* RTC_CNTL_GPIO_PIN4_FUN_SEL : R/W ;bitpos:[15:12] ;default: 4'd0 ; */ 2521 /*description: */ 2522 #define RTC_CNTL_GPIO_PIN4_FUN_SEL 0x0000000F 2523 #define RTC_CNTL_GPIO_PIN4_FUN_SEL_M ((RTC_CNTL_GPIO_PIN4_FUN_SEL_V)<<(RTC_CNTL_GPIO_PIN4_FUN_SEL_S)) 2524 #define RTC_CNTL_GPIO_PIN4_FUN_SEL_V 0xF 2525 #define RTC_CNTL_GPIO_PIN4_FUN_SEL_S 12 2526 /* RTC_CNTL_GPIO_PIN5_FUN_SEL : R/W ;bitpos:[11:8] ;default: 4'd0 ; */ 2527 /*description: */ 2528 #define RTC_CNTL_GPIO_PIN5_FUN_SEL 0x0000000F 2529 #define RTC_CNTL_GPIO_PIN5_FUN_SEL_M ((RTC_CNTL_GPIO_PIN5_FUN_SEL_V)<<(RTC_CNTL_GPIO_PIN5_FUN_SEL_S)) 2530 #define RTC_CNTL_GPIO_PIN5_FUN_SEL_V 0xF 2531 #define RTC_CNTL_GPIO_PIN5_FUN_SEL_S 8 2532 /* RTC_CNTL_GPIO_PIN0_MUX_SEL : R/W ;bitpos:[7] ;default: 1'b0 ; */ 2533 /*description: */ 2534 #define RTC_CNTL_GPIO_PIN0_MUX_SEL (BIT(7)) 2535 #define RTC_CNTL_GPIO_PIN0_MUX_SEL_M (BIT(7)) 2536 #define RTC_CNTL_GPIO_PIN0_MUX_SEL_V 0x1 2537 #define RTC_CNTL_GPIO_PIN0_MUX_SEL_S 7 2538 /* RTC_CNTL_GPIO_PIN1_MUX_SEL : R/W ;bitpos:[6] ;default: 1'b0 ; */ 2539 /*description: */ 2540 #define RTC_CNTL_GPIO_PIN1_MUX_SEL (BIT(6)) 2541 #define RTC_CNTL_GPIO_PIN1_MUX_SEL_M (BIT(6)) 2542 #define RTC_CNTL_GPIO_PIN1_MUX_SEL_V 0x1 2543 #define RTC_CNTL_GPIO_PIN1_MUX_SEL_S 6 2544 /* RTC_CNTL_GPIO_PIN2_MUX_SEL : R/W ;bitpos:[5] ;default: 1'b0 ; */ 2545 /*description: */ 2546 #define RTC_CNTL_GPIO_PIN2_MUX_SEL (BIT(5)) 2547 #define RTC_CNTL_GPIO_PIN2_MUX_SEL_M (BIT(5)) 2548 #define RTC_CNTL_GPIO_PIN2_MUX_SEL_V 0x1 2549 #define RTC_CNTL_GPIO_PIN2_MUX_SEL_S 5 2550 /* RTC_CNTL_GPIO_PIN3_MUX_SEL : R/W ;bitpos:[4] ;default: 1'b0 ; */ 2551 /*description: */ 2552 #define RTC_CNTL_GPIO_PIN3_MUX_SEL (BIT(4)) 2553 #define RTC_CNTL_GPIO_PIN3_MUX_SEL_M (BIT(4)) 2554 #define RTC_CNTL_GPIO_PIN3_MUX_SEL_V 0x1 2555 #define RTC_CNTL_GPIO_PIN3_MUX_SEL_S 4 2556 /* RTC_CNTL_GPIO_PIN4_MUX_SEL : R/W ;bitpos:[3] ;default: 1'b0 ; */ 2557 /*description: */ 2558 #define RTC_CNTL_GPIO_PIN4_MUX_SEL (BIT(3)) 2559 #define RTC_CNTL_GPIO_PIN4_MUX_SEL_M (BIT(3)) 2560 #define RTC_CNTL_GPIO_PIN4_MUX_SEL_V 0x1 2561 #define RTC_CNTL_GPIO_PIN4_MUX_SEL_S 3 2562 /* RTC_CNTL_GPIO_PIN5_MUX_SEL : R/W ;bitpos:[2] ;default: 1'b0 ; */ 2563 /*description: */ 2564 #define RTC_CNTL_GPIO_PIN5_MUX_SEL (BIT(2)) 2565 #define RTC_CNTL_GPIO_PIN5_MUX_SEL_M (BIT(2)) 2566 #define RTC_CNTL_GPIO_PIN5_MUX_SEL_V 0x1 2567 #define RTC_CNTL_GPIO_PIN5_MUX_SEL_S 2 2568 2569 #define RTC_CNTL_SENSOR_CTRL_REG (DR_REG_RTCCNTL_BASE + 0x011C) 2570 /* RTC_CNTL_FORCE_XPD_SAR : R/W ;bitpos:[31:30] ;default: 2'b0 ; */ 2571 /*description: */ 2572 #define RTC_CNTL_FORCE_XPD_SAR 0x00000003 2573 #define RTC_CNTL_FORCE_XPD_SAR_M ((RTC_CNTL_FORCE_XPD_SAR_V)<<(RTC_CNTL_FORCE_XPD_SAR_S)) 2574 #define RTC_CNTL_FORCE_XPD_SAR_V 0x3 2575 #define RTC_CNTL_FORCE_XPD_SAR_S 30 2576 /* RTC_CNTL_SAR2_PWDET_CCT : R/W ;bitpos:[29:27] ;default: 3'd0 ; */ 2577 /*description: */ 2578 #define RTC_CNTL_SAR2_PWDET_CCT 0x00000007 2579 #define RTC_CNTL_SAR2_PWDET_CCT_M ((RTC_CNTL_SAR2_PWDET_CCT_V)<<(RTC_CNTL_SAR2_PWDET_CCT_S)) 2580 #define RTC_CNTL_SAR2_PWDET_CCT_V 0x7 2581 #define RTC_CNTL_SAR2_PWDET_CCT_S 27 2582 2583 #define RTC_CNTL_DBG_SAR_SEL_REG (DR_REG_RTCCNTL_BASE + 0x0120) 2584 /* RTC_CNTL_SAR_DEBUG_SEL : R/W ;bitpos:[31:27] ;default: 5'd0 ; */ 2585 /*description: */ 2586 #define RTC_CNTL_SAR_DEBUG_SEL 0x0000001F 2587 #define RTC_CNTL_SAR_DEBUG_SEL_M ((RTC_CNTL_SAR_DEBUG_SEL_V)<<(RTC_CNTL_SAR_DEBUG_SEL_S)) 2588 #define RTC_CNTL_SAR_DEBUG_SEL_V 0x1F 2589 #define RTC_CNTL_SAR_DEBUG_SEL_S 27 2590 2591 #define RTC_CNTL_PG_CTRL_REG (DR_REG_RTCCNTL_BASE + 0x0124) 2592 /* RTC_CNTL_POWER_GLITCH_EN : R/W ;bitpos:[31] ;default: 1'b0 ; */ 2593 /*description: */ 2594 #define RTC_CNTL_POWER_GLITCH_EN (BIT(31)) 2595 #define RTC_CNTL_POWER_GLITCH_EN_M (BIT(31)) 2596 #define RTC_CNTL_POWER_GLITCH_EN_V 0x1 2597 #define RTC_CNTL_POWER_GLITCH_EN_S 31 2598 /* RTC_CNTL_POWER_GLITCH_EFUSE_SEL : R/W ;bitpos:[30] ;default: 1'b0 ; */ 2599 /*description: */ 2600 #define RTC_CNTL_POWER_GLITCH_EFUSE_SEL (BIT(30)) 2601 #define RTC_CNTL_POWER_GLITCH_EFUSE_SEL_M (BIT(30)) 2602 #define RTC_CNTL_POWER_GLITCH_EFUSE_SEL_V 0x1 2603 #define RTC_CNTL_POWER_GLITCH_EFUSE_SEL_S 30 2604 /* RTC_CNTL_POWER_GLITCH_FORCE_PU : R/W ;bitpos:[29] ;default: 1'b0 ; */ 2605 /*description: */ 2606 #define RTC_CNTL_POWER_GLITCH_FORCE_PU (BIT(29)) 2607 #define RTC_CNTL_POWER_GLITCH_FORCE_PU_M (BIT(29)) 2608 #define RTC_CNTL_POWER_GLITCH_FORCE_PU_V 0x1 2609 #define RTC_CNTL_POWER_GLITCH_FORCE_PU_S 29 2610 /* RTC_CNTL_POWER_GLITCH_FORCE_PD : R/W ;bitpos:[28] ;default: 1'b0 ; */ 2611 /*description: */ 2612 #define RTC_CNTL_POWER_GLITCH_FORCE_PD (BIT(28)) 2613 #define RTC_CNTL_POWER_GLITCH_FORCE_PD_M (BIT(28)) 2614 #define RTC_CNTL_POWER_GLITCH_FORCE_PD_V 0x1 2615 #define RTC_CNTL_POWER_GLITCH_FORCE_PD_S 28 2616 /* RTC_CNTL_POWER_GLITCH_DSENSE : R/W ;bitpos:[27:26] ;default: 2'b0 ; */ 2617 /*description: */ 2618 #define RTC_CNTL_POWER_GLITCH_DSENSE 0x00000003 2619 #define RTC_CNTL_POWER_GLITCH_DSENSE_M ((RTC_CNTL_POWER_GLITCH_DSENSE_V)<<(RTC_CNTL_POWER_GLITCH_DSENSE_S)) 2620 #define RTC_CNTL_POWER_GLITCH_DSENSE_V 0x3 2621 #define RTC_CNTL_POWER_GLITCH_DSENSE_S 26 2622 2623 #define RTC_CNTL_DATE_REG (DR_REG_RTCCNTL_BASE + 0x01fc) 2624 /* RTC_CNTL_CNTL_DATE : R/W ;bitpos:[27:0] ;default: 28'h2007270 ; */ 2625 /*description: */ 2626 #define RTC_CNTL_CNTL_DATE 0x0FFFFFFF 2627 #define RTC_CNTL_CNTL_DATE_M ((RTC_CNTL_CNTL_DATE_V)<<(RTC_CNTL_CNTL_DATE_S)) 2628 #define RTC_CNTL_CNTL_DATE_V 0xFFFFFFF 2629 #define RTC_CNTL_CNTL_DATE_S 0 2630 2631 #ifdef __cplusplus 2632 } 2633 #endif 2634 2635 2636 2637 #endif /*_SOC_RTC_CNTL_REG_H_ */ 2638
