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/hal_silabs-3.7.0/gecko/Device/SiliconLabs/EFM32PG1B/Include/
Defm32pg1b100f128gm32.h319 #define RTCC_BASE (0x40042000UL) /**< RTCC base address */ macro
Defm32pg1b100f128im32.h319 #define RTCC_BASE (0x40042000UL) /**< RTCC base address */ macro
Defm32pg1b100f256gm32.h319 #define RTCC_BASE (0x40042000UL) /**< RTCC base address */ macro
Defm32pg1b100f256im32.h319 #define RTCC_BASE (0x40042000UL) /**< RTCC base address */ macro
Defm32pg1b200f128gm32.h321 #define RTCC_BASE (0x40042000UL) /**< RTCC base address */ macro
Defm32pg1b200f128im32.h321 #define RTCC_BASE (0x40042000UL) /**< RTCC base address */ macro
Defm32pg1b200f256gm32.h321 #define RTCC_BASE (0x40042000UL) /**< RTCC base address */ macro
Defm32pg1b200f256gm48.h321 #define RTCC_BASE (0x40042000UL) /**< RTCC base address */ macro
Defm32pg1b200f256im32.h321 #define RTCC_BASE (0x40042000UL) /**< RTCC base address */ macro
Defm32pg1b200f256im48.h321 #define RTCC_BASE (0x40042000UL) /**< RTCC base address */ macro
Defm32pg1b200f128gm48.h321 #define RTCC_BASE (0x40042000UL) /**< RTCC base address */ macro
/hal_silabs-3.7.0/gecko/Device/SiliconLabs/EFR32FG1P/Include/
Defr32fg1p133f256gm48.h335 #define RTCC_BASE (0x40042000UL) /**< RTCC base address */ macro
Defr32fg1p131f256gm32.h335 #define RTCC_BASE (0x40042000UL) /**< RTCC base address */ macro
Defr32fg1p131f256im32.h335 #define RTCC_BASE (0x40042000UL) /**< RTCC base address */ macro
Defr32fg1p132f64gm32.h335 #define RTCC_BASE (0x40042000UL) /**< RTCC base address */ macro
Defr32fg1p133f64gm48.h335 #define RTCC_BASE (0x40042000UL) /**< RTCC base address */ macro
Defr32fg1p131f128gm32.h335 #define RTCC_BASE (0x40042000UL) /**< RTCC base address */ macro
Defr32fg1p133f256gm32.h335 #define RTCC_BASE (0x40042000UL) /**< RTCC base address */ macro
Defr32fg1p131f128gm48.h335 #define RTCC_BASE (0x40042000UL) /**< RTCC base address */ macro
Defr32fg1p131f256gm48.h335 #define RTCC_BASE (0x40042000UL) /**< RTCC base address */ macro
Defr32fg1p131f256im48.h335 #define RTCC_BASE (0x40042000UL) /**< RTCC base address */ macro
Defr32fg1p131f64gm32.h335 #define RTCC_BASE (0x40042000UL) /**< RTCC base address */ macro
Defr32fg1p131f64gm48.h335 #define RTCC_BASE (0x40042000UL) /**< RTCC base address */ macro
Defr32fg1p132f128gm32.h335 #define RTCC_BASE (0x40042000UL) /**< RTCC base address */ macro
Defr32fg1p132f128gm48.h335 #define RTCC_BASE (0x40042000UL) /**< RTCC base address */ macro

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