1 /* 2 * Copyright (c) 2024 Jianxiong Gu <jianxiong.gu@outlook.com> 3 * SPDX-License-Identifier: Apache-2.0 4 */ 5 6 #ifndef ZEPHYR_DRIVERS_USBC_TCPC_RT1715_H_ 7 #define ZEPHYR_DRIVERS_USBC_TCPC_RT1715_H_ 8 9 #define RT1715_REG_SYS_CTRL_1 0x90 10 /** VCONN OVP occurs and discharge path turn-on */ 11 #define RT1715_REG_SYS_CTRL_1_VCONN_DISCHARGE_EN BIT(5) 12 /** Low power mode Rd or Rp */ 13 #define RT1715_REG_SYS_CTRL_1_BMCIO_LPR_PRD BIT(4) 14 /** Low power mode enable */ 15 #define RT1715_REG_SYS_CTRL_1_BMCIO_LP_EN BIT(3) 16 /** BMCIO BandGap enable */ 17 #define RT1715_REG_SYS_CTRL_1_BMCIO_BG_EN BIT(2) 18 /** VBUS detection enable */ 19 #define RT1715_REG_SYS_CTRL_1_VBUS_DETECT_EN BIT(1) 20 /** 24M oscillator for BMC communication */ 21 #define RT1715_REG_SYS_CTRL_1_BMCIO_OSC_EN BIT(0) 22 23 #define RT1715_REG_OCP 0x93 24 /** VCONN over-current control selection */ 25 #define RT1715_REG_OCP_BMCIO_VCON_OCP GENMASK(7, 5) 26 #define RT1715_VCON_OCP_200MA (0 << 5) 27 #define RT1715_VCON_OCP_300MA (1 << 5) 28 #define RT1715_VCON_OCP_400MA (2 << 5) 29 #define RT1715_VCON_OCP_500MA (3 << 5) 30 #define RT1715_VCON_OCP_600MA (4 << 5) 31 32 #define RT1715_REG_RT_ST 0x97 33 /** If VBUS under 0.8V */ 34 #define RT1715_REG_RT_ST_VBUS_80 BIT(1) 35 36 #define RT1715_REG_RT_INT 0x98 37 /** Ra detach */ 38 #define RT1715_REG_RT_INT_RA_DETACH BIT(5) 39 /** VBUS under 0.8V */ 40 #define RT1715_REG_RT_INT_VBUS_80 BIT(1) 41 /** Low power mode exited */ 42 #define RT1715_REG_RT_INT_WAKEUP BIT(0) 43 44 #define RT1715_REG_RT_INT_MASK 0x99 45 46 #define RT1715_REG_LP_CTRL 0x9B 47 /** Clock_300K divided from Clock_24M */ 48 #define RT1715_REG_LP_CTRL_CK_300K_SEL BIT(7) 49 /** Non-Shutdown mode */ 50 #define RT1715_REG_LP_CTRL_SHUTDOWN_OFF BIT(5) 51 /** Enable PD3.0 Extended message */ 52 #define RT1715_REG_LP_CTRL_ENEXTMSG BIT(4) 53 /** Auto enter idle mode enable */ 54 #define RT1715_REG_LP_CTRL_AUTOIDLE_EN BIT(3) 55 /** Enter idle mode timeout time */ 56 #define RT1715_REG_LP_CTRL_AUTOIDLE_TIMEOUT GENMASK(2, 0) 57 #define RT1715_AUTOIDLE_TIMEOUT_96P0_MS 7 58 #define RT1715_AUTOIDLE_TIMEOUT_83P2_MS 6 59 #define RT1715_AUTOIDLE_TIMEOUT_70P4_MS 5 60 #define RT1715_AUTOIDLE_TIMEOUT_57P6_MS 4 61 #define RT1715_AUTOIDLE_TIMEOUT_44P8_MS 3 62 #define RT1715_AUTOIDLE_TIMEOUT_32P0_MS 2 63 #define RT1715_AUTOIDLE_TIMEOUT_19P2_MS 1 64 #define RT1715_AUTOIDLE_TIMEOUT_6P4_MS 0 65 66 #define RT1715_REG_SYS_WAKEUP 0x9F 67 /** Wakeup function enable */ 68 #define RT1715_REG_SYS_WAKEUP_EN BIT(7) 69 70 #define RT1715_REG_SW_RST 0xA0 71 /** Write 1 to trigger software reset */ 72 #define RT1715_REG_SW_RST_EN BIT(0) 73 74 #define RT1715_REG_DRP_CTRL_1 0xA2 75 /** 76 * The period a DRP will complete a Source to Sink and back advertisement. 77 * (Period = TDRP * 6.4 + 51.2ms) 78 */ 79 #define RT1715_REG_DRP_CTRL_1_TDRP GENMASK(3, 0) 80 81 #define RT1715_REG_DRP_CTRL_2 0xA3 82 /** 83 * The percent of time that a DRP will advertise Source during tDRP. 84 * (DUTY = (DCSRCDRP[9:0] + 1) / 1024) 85 */ 86 #define RT1715_REG_DRP_CTRL_2_DCSRCDRP GENMASK(9, 0) 87 88 #endif /* ZEPHYR_DRIVERS_USBC_TCPC_UCPD_NUMAKER_H_ */ 89
