1 /*******************************************************************************
2 * @file rsi_udma.h
3 *******************************************************************************
4 * # License
5 * <b>Copyright 2024 Silicon Laboratories Inc. www.silabs.com</b>
6 *******************************************************************************
7 *
8 * SPDX-License-Identifier: Zlib
9 *
10 * The licensor of this software is Silicon Laboratories Inc.
11 *
12 * This software is provided 'as-is', without any express or implied
13 * warranty. In no event will the authors be held liable for any damages
14 * arising from the use of this software.
15 *
16 * Permission is granted to anyone to use this software for any purpose,
17 * including commercial applications, and to alter it and redistribute it
18 * freely, subject to the following restrictions:
19 *
20 * 1. The origin of this software must not be misrepresented; you must not
21 * claim that you wrote the original software. If you use this software
22 * in a product, an acknowledgment in the product documentation would be
23 * appreciated but is not required.
24 * 2. Altered source versions must be plainly marked as such, and must not be
25 * misrepresented as being the original software.
26 * 3. This notice may not be removed or altered from any source distribution.
27 *
28 ******************************************************************************/
29 //Include Files
30
31 #include "rsi_ccp_common.h"
32 #include "rsi_error.h"
33 #include "rsi_packing.h"
34
35 #ifndef RSI_UDMA_H
36 #define RSI_UDMA_H
37
38 #ifdef __cplusplus
39 extern "C" {
40 #endif
41
42 #ifndef UNUSED_PARAMETER
43 #define UNUSED_PARAMETER(x) (void)(x)
44 #endif // UNUSED_PARAMETER
45
46 #define RSI_UDMA_DRV_VERSION RSI_DRIVER_VERSION_MAJOR_MINOR(02, 00) // driver version
47 #define RSI_UDMA_API_VERSION RSI_DRIVER_VERSION_MAJOR_MINOR(00, 01) // API version
48 #define UDMA_CHANNEL_NUM 32
49
50 #define M4SS_UDMA_INTR_SEL (*((uint32_t volatile *)(0x46110000 + 0x0C)))
51 #define ULP_DYN_CLK_CTRL_DIS_REG (*((uint32_t volatile *)(0x24041400 + 0xA0)))
52 #define ULP_UDMA_STATIC_CLK_EN (1UL << 17)
53 #define PERIPHERAL_UDMA_DMA_SEL (*((uint32_t volatile *)(0x46008000UL + 0x58)))
54
55 #define UDMA_ATTR_USEBURST 0x1
56 #define UDMA_ATTR_ALTSELECT 0x2
57 #define UDMA_ATTR_HIGH_PRIORITY 0x4
58 #define UDMA_ATTR_REQMASK 0x8
59 #define UDMA_ATTR_ALL 0xF
60
61 // DMA control modes
62
63 #define CHNL0_INTR (1UL << 0) // Channel0 interrupt flag
64 #define CHNL1_INTR (1UL << 1) // Channel1 interrupt flag
65 #define CHNL2_INTR (1UL << 2) // Channel2 interrupt flag
66 #define CHNL3_INTR (1UL << 3) // Channel3 interrupt flag
67 #define CHNL4_INTR (1UL << 4) // Channel4 interrupt flag
68 #define CHNL5_INTR (1UL << 5) // Channel5 interrupt flag
69 #define CHNL6_INTR (1UL << 6) // Channel6 interrupt flag
70 #define CHNL7_INTR (1UL << 7) // Channel7 interrupt flag
71 #define CHNL8_INTR (1UL << 8) // Channel8 interrupt flag
72 #define CHNL9_INTR (1UL << 9) // Channel9 interrupt flag
73 #define CHNL10_INTR (1UL << 10) // Channel10 interrupt flag
74 #define CHNL11_INTR (1UL << 11) // Channel11 interrupt flag
75 #define CHNL12_INTR (1UL << 12) // Channel12 interrupt flag
76 #define CHNL13_INTR (1UL << 13) // Channel13 interrupt flag
77 #define CHNL14_INTR (1UL << 14) // Channel14 interrupt flag
78 #define CHNL15_INTR (1UL << 15) // Channel15 interrupt flag
79 #define CHNL16_INTR (1UL << 16) // Channel16 interrupt flag
80 #define CHNL17_INTR (1UL << 17) // Channel17 interrupt flag
81 #define CHNL18_INTR (1UL << 18) // Channel18 interrupt flag
82 #define CHNL19_INTR (1UL << 19) // Channel19 interrupt flag
83 #define CHNL20_INTR (1UL << 20) // Channel20 interrupt flag
84 #define CHNL21_INTR (1UL << 21) // Channel21 interrupt flag
85 #define CHNL22_INTR (1UL << 22) // Channel22 interrupt flag
86 #define CHNL23_INTR (1UL << 23) // Channel23 interrupt flag
87 #define CHNL24_INTR (1UL << 24) // Channel24 interrupt flag
88 #define CHNL25_INTR (1UL << 25) // Channel25 interrupt flag
89 #define CHNL26_INTR (1UL << 26) // Channel26 interrupt flag
90 #define CHNL27_INTR (1UL << 27) // Channel27 interrupt flag
91 #define CHNL28_INTR (1UL << 28) // Channel28 interrupt flag
92 #define CHNL29_INTR (1UL << 29) // Channel29 interrupt flag
93 #define CHNL30_INTR (1UL << 30) // Channel30 interrupt flag
94 #define CHNL31_INTR (1UL << 31) // Channel31 interrupt flag
95
96 #define UDMA_MODE_STOP 0x0
97 #define UDMA_MODE_BASIC 0x1
98 #define UDMA_MODE_AUTO 0x2
99 #define UDMA_MODE_PINGPONG 0x3
100 #define UDMA_MODE_MEM_SCATTER_GATHER 0x4
101 #define UDMA_MODE_MEM_ALT_SCATTER_GATHER 0x5
102 #define UDMA_MODE_PER_SCATTER_GATHER 0x6
103 #define UDMA_MODE_ALT_SELECT 0x1
104 #define UDMA_SOFTWARE_TRIGG 0X2
105
106 #define UDMA_DST_INC_NONE 0x3
107 #define UDMA_SRC_INC_NONE 0x3
108
109 #define UDMA_PRI_SELECT 0x00
110 #define UDMA_ALT_SELECT 0x20
111 #define UDMA_ULPALT_SELECT 0x10
112
113 #define UDMA_CHCTL_XFERSIZE_M 0x3FF
114 #define UDMA_CHCTL_XFERMODE_M 0x07
115 #define UDMA_CHCTL_XFERSIZE_S 0x04
116
117 #define SRC_SIZE_32 0x2
118 #define SRC_SIZE_16 0x1
119 #define SRC_SIZE_8 0x0
120
121 #define DST_SIZE_32 0x2
122 #define DST_SIZE_16 0x1
123 #define DST_SIZE_8 0x0
124
125 #define SRC_INC_NONE 0x3
126 #define SRC_INC_32 0x2
127 #define SRC_INC_16 0x1
128 #define SRC_INC_8 0x0
129
130 #define DST_INC_NONE 0x3
131 #define DST_INC_32 0x2
132 #define DST_INC_16 0x1
133 #define DST_INC_8 0x0
134
135 #define ARBSIZE_1 0x00
136 #define ARBSIZE_2 0x01
137 #define ARBSIZE_4 0x02
138 #define ARBSIZE_8 0x03
139 #define ARBSIZE_16 0x04
140 #define ARBSIZE_32 0x05
141 #define ARBSIZE_64 0x06
142 #define ARBSIZE_128 0x07
143 #define ARBSIZE_256 0x08
144 #define ARBSIZE_512 0x09
145 #define ARBSIZE_1024 0x0A
146
147 #define DMA_XFERS_1 0x0
148 #define DMA_XFERS_2 0x1
149 #define DMA_XFERS_3 0x2
150 #define DMA_XFERS_4 0x3
151 #define DMA_XFERS_5 0x4
152 #define DMA_XFERS_6 0x5
153 #define DMA_XFERS_7 0x6
154 #define DMA_XFERS_8 0x7
155 #define DMA_XFERS_9 0x8
156 #define DMA_XFERS_10 0x9
157 #define DMA_XFERS_11 0xA
158 #define DMA_XFERS_16 0xF
159 #define DMA_XFERS_31 0x1F
160 #define DMA_XFERS_101 0x64
161 #define DMA_XFERS_256 0xFF
162 #define DMA_XFERS_1024 0x3FF
163
164 #define USART0_ACK 0x1
165 #define UART1_ACK 0x2
166 #define UART3_ACK 0x3
167 #define SSISLAVE_ACK 0x4
168 #define SSIMASTER_ACK 0x5
169 #define SSISLAVE1_ACK 0x6
170 #define I2C_ACK 0x7
171 #define CHNL_0 0
172 #define CHNL_31 31
173
174 #define PRIMARY 0
175 #define ALTERNATE 1
176 #define CHNL_0 0
177 #define CHNL_1 1
178
179 #define SRC_SIZE_32 0x2
180 #define SRC_SIZE_16 0x1
181 #define SRC_SIZE_8 0x0
182
183 #define DST_SIZE_32 0x2
184 #define DST_SIZE_16 0x1
185 #define DST_SIZE_8 0x0
186
187 #define SRC_INC_32 0x2
188 #define SRC_INC_16 0x1
189 #define SRC_INC_8 0x0
190
191 #define DST_INC_32 0x2
192 #define DST_INC_16 0x1
193 #define DST_INC_8 0x0
194
195 #define SRC_DST_SIZE_32 2
196 #define SRC_DST_SIZE_16 1
197 #define SRC_DTS_SIZE_8 0
198
199 #define MEM_SG 0
200 #define PERI_SG 1
201
202 typedef UDMA0_Type RSI_UDMA_T;
203
204 // brief RPDMA handle type
205 typedef void *RSI_UDMA_HANDLE_T;
206
207 // brief UDMA Driver Capabilities.
208 typedef struct {
209 uint32_t noOfChannels; // Number of DMA channels
210 uint32_t maxNoOfTxferPerCycle; // Maximum number of transfers per DMA cycle
211 } RSI_UDMA_CAPABILITIES_T;
212
213 // brief UDMA Channel Config structure
214 typedef struct {
215 unsigned int transferType : 3; // The operating mode of the DMA cycle
216 unsigned int
217 nextBurst : 1; // Used to force the channel to only respond to burst requests at the tail end of a scatter-gather transfer
218 unsigned int totalNumOfDMATrans : 10; // total number of DMA transfers that the DMA cycle contains
219 unsigned int rPower : 4; // Number of DMA transfers can occur before the controller rearbitrates
220 unsigned int srcProtCtrl : 3; // Performs control operation when the controller reads the source data
221 unsigned int dstProtCtrl : 3; // Performs control operation when the controller writes the destination data
222 unsigned int srcSize : 2; // Source data size
223 unsigned int srcInc : 2; // Source address increment
224 unsigned int dstSize : 2; // Destination data size
225 unsigned int dstInc : 2; // Destination address increment
226 } RSI_UDMA_CHA_CONFIG_DATA_T;
227
228 // brief UDMA Control Structure.
229 typedef struct {
230 volatile void *pSrcEndAddr; // The ending source address of the data transfer
231 volatile void *pDstEndAddr; // The ending destination address of the data transfer
232 volatile RSI_UDMA_CHA_CONFIG_DATA_T vsUDMAChaConfigData1; // The Channel Config Structure
233 volatile uint32_t Spare; // An unused location
234 } RSI_UDMA_DESC_T;
235
236 typedef void (*udmaTransferCompleteCB)(RSI_UDMA_HANDLE_T udmaHandle, RSI_UDMA_DESC_T *pTranDesc, uint32_t dmaCh);
237
238 // brief RPDMA controller callback IDs
239 typedef enum {
240 ROM_UDMA_XFERCOMPLETE_CB = 0, // Callback ID for UDMA transfer descriptor chain complete
241 } ROM_UDMA_CALLBACK_T;
242
243 // Private data structure used for the RPDMA controller driver, holds the driver and peripheral context
244 typedef struct {
245 void *pUserData; // Pointer to user data used by driver instance, use NULL if not used
246 RSI_UDMA_T *base; // UDMA base address
247 RSI_UDMA_DESC_T *sramBase; // SRAM descriptor table (all channels)
248 RSI_UDMA_DESC_T *desc; // descriptor structure
249 udmaTransferCompleteCB udmaCompCB; // Transfer complete callback
250 uint32_t dmaCh;
251 } RSI_UDMA_DATACONTEXT_T;
252
253 // RPDMA Init structure
254 typedef PRE_PACK struct POST_PACK {
255 void *pUserData; // Pointer to user data used by driver instance, use NULL if not used
256 uint32_t base; // Pointer to RPDMA global register instance
257 uint32_t sramBase; // Pointer to memory used for RPDMA descriptor storage, must be 512 byte aligned
258 } RSI_UDMA_INIT_T;
259
260 // brief RPDMA transfer channel setup structure (use this structure as const if possible)
261 typedef PRE_PACK struct POST_PACK {
262 uint32_t channelPrioHigh; // Channel priority level
263 uint32_t altStruct; // Primary or alternate control structure
264 uint32_t burstReq; // Burst request
265 uint32_t reqMask; // Mask channel request
266 uint32_t periphReq; // Peripheral request
267 uint32_t periAck; // dma ACK for peripheral
268 uint32_t dmaCh;
269 } RSI_UDMA_CHA_CFG_T;
270 /** @addtogroup SOC18
271 * @{
272 */
273
274 /*===================================================*/
275 /**
276 * @fn uint32_t RSI_UDMA_GetMemSize(void)
277 * @brief This API is used to Get memory size in bytes needed for UDMA controller driver context
278 * @return Size in bytes needed for the ROM driver
279 */
RSI_UDMA_GetMemSize(void)280 STATIC INLINE uint32_t RSI_UDMA_GetMemSize(void)
281 {
282 return sizeof(RSI_UDMA_DATACONTEXT_T);
283 }
284
285 /*===================================================*/
286 /**
287 * @fn void RSI_UDMA_RegisterCallback(RSI_UDMA_HANDLE_T pHandle, void *pCB)
288 * @brief Registers an DMA controller callback for a queue
289 * @param[in] pHandle : Pointer to driver context handle
290 * @param[in] pCB : Pointer to callback function
291 * @return none
292 */
RSI_UDMA_RegisterCallback(RSI_UDMA_HANDLE_T pHandle,udmaTransferCompleteCB pCB)293 STATIC INLINE void RSI_UDMA_RegisterCallback(RSI_UDMA_HANDLE_T pHandle, udmaTransferCompleteCB pCB)
294 {
295 RSI_UDMA_DATACONTEXT_T *pDrv = (RSI_UDMA_DATACONTEXT_T *)pHandle;
296
297 pDrv->udmaCompCB = pCB;
298 }
299
300 /*===================================================*/
301 /**
302 * @fn void RSI_UDMA_UDMAEnable(RSI_UDMA_HANDLE_T pHandle)
303 * @brief This API is used to enable the UDMA interface
304 * @param[in] pHandle : Pointer to driver context handle
305 * @return none
306 */
RSI_UDMA_UDMAEnable(RSI_UDMA_HANDLE_T pHandle)307 STATIC INLINE void RSI_UDMA_UDMAEnable(RSI_UDMA_HANDLE_T pHandle)
308 {
309 RSI_UDMA_DATACONTEXT_T *pDrv = (RSI_UDMA_DATACONTEXT_T *)pHandle;
310 pDrv->base->DMA_CFG_b.MASTER_ENABLE = ENABLE;
311 }
312
313 /*===================================================*/
314 /**
315 * @fn void RSI_UDMA_UDMADisable(RSI_UDMA_HANDLE_T pHandle)
316 * @brief This API is used to disable the UDMA interface
317 * @param[in] pHandle : Pointer to driver context handle
318 * @return none
319 */
320
RSI_UDMA_UDMADisable(RSI_UDMA_HANDLE_T pHandle)321 STATIC INLINE void RSI_UDMA_UDMADisable(RSI_UDMA_HANDLE_T pHandle)
322 {
323 RSI_UDMA_DATACONTEXT_T *pDrv = (RSI_UDMA_DATACONTEXT_T *)pHandle;
324
325 pDrv->base->DMA_CFG_b.MASTER_ENABLE = DISABLE;
326 }
327
328 /*===================================================*/
329 /**
330 * @fn uint8_t RSI_UDMA_ErrorStatusGet(const RSI_UDMA_T *pUDMA)
331 * @brief This API is used to get the error status/sets the signal low of UDMA.
332 * @param[in] pUDMA : Pointer to the UDMA instance register area
333 * @return Returns error status as below
334 * - 0 : Error is LOW
335 * - 1 : Error is HIGH
336 */
RSI_UDMA_ErrorStatusGet(const RSI_UDMA_T * pUDMA)337 STATIC INLINE uint8_t RSI_UDMA_ErrorStatusGet(const RSI_UDMA_T *pUDMA)
338 {
339 return (pUDMA->ERR_CLR_b.ERR_CLR);
340 }
341 /*===================================================*/
342 /**
343 * @fn void RSI_UDMA_ErrorStatusClear(RSI_UDMA_HANDLE_T pHandle)
344 * @brief This API is used to clear the errors of UDMA
345 * @param[in] pHandle : Pointer to driver context handle
346 * @return none
347 */
RSI_UDMA_ErrorStatusClear(RSI_UDMA_HANDLE_T pHandle)348 STATIC INLINE void RSI_UDMA_ErrorStatusClear(RSI_UDMA_HANDLE_T pHandle)
349 {
350 RSI_UDMA_DATACONTEXT_T *pDrv = (RSI_UDMA_DATACONTEXT_T *)pHandle;
351 pDrv->base->ERR_CLR_b.ERR_CLR = 0x1;
352 }
353
354 /*===================================================*/
355 /**
356 * @fn rsi_error_t RSI_UDMA_ChannelEnable(RSI_UDMA_HANDLE_T pHandle,uint8_t dmaCh)
357 * @brief This API is used to enable the required channel of UDMA
358 * @param[in] pHandle : Pointer to driver context handle
359 * @param[in] dmaCh : Channel number(1 to 32)
360 * @return RSI_OK if no errors occured, or an error code
361 */
RSI_UDMA_ChannelEnable(RSI_UDMA_HANDLE_T pHandle,uint8_t dmaCh)362 STATIC INLINE rsi_error_t RSI_UDMA_ChannelEnable(RSI_UDMA_HANDLE_T pHandle, uint8_t dmaCh)
363 {
364 RSI_UDMA_DATACONTEXT_T *pDrv = (RSI_UDMA_DATACONTEXT_T *)pHandle;
365 if (dmaCh <= CHNL_31) {
366 // Enables required channel
367 pDrv->base->CHNL_ENABLE_SET = SET_BIT(dmaCh);
368 return RSI_OK;
369 } else {
370 return ERROR_UDMA_INVALIDCHNLNUM;
371 }
372 }
373
374 /*===================================================*/
375 /**
376 * @fn rsi_error_t RSI_UDMA_ChannelDisable(RSI_UDMA_HANDLE_T pHandle,uint8_t dmaCh)
377 * @brief This API is used to disable the required channel of UDMA
378 * @param[in] pHandle : Pointer to driver context handle
379 * @param[in] dmaCh : Channel number(1 to 32)
380 * @return RSI_OK if no errors occured, or an error code
381 */
RSI_UDMA_ChannelDisable(RSI_UDMA_HANDLE_T pHandle,uint8_t dmaCh)382 STATIC INLINE rsi_error_t RSI_UDMA_ChannelDisable(RSI_UDMA_HANDLE_T pHandle, uint8_t dmaCh)
383 {
384 RSI_UDMA_DATACONTEXT_T *pDrv = (RSI_UDMA_DATACONTEXT_T *)pHandle;
385 if (dmaCh <= CHNL_31) {
386 // Disables required channel
387 pDrv->base->CHNL_ENABLE_CLR = SET_BIT(dmaCh);
388 return RSI_OK;
389 } else
390 return ERROR_UDMA_INVALIDCHNLNUM;
391 }
392
393 /*===================================================*/
394 /**
395 * @fn rsi_error_t RSI_UDMA_ChannelIsEnabled(RSI_UDMA_HANDLE_T pHandle, uint8_t dmaCh)
396 * @brief This API is used to check the required UDMA channel is enabled or not
397 * @param[in] pHandle : Pointer to driver context handle
398 * @param[in] dmaCh : Channel number(0 to 31)
399 * @return If process is successful then return RSI_OK else RSI_FAIL If requied channel is not enabled
400 */
RSI_UDMA_ChannelIsEnabled(RSI_UDMA_HANDLE_T pHandle,uint8_t dmaCh)401 STATIC INLINE rsi_error_t RSI_UDMA_ChannelIsEnabled(RSI_UDMA_HANDLE_T pHandle, uint8_t dmaCh)
402 {
403 const RSI_UDMA_DATACONTEXT_T *pDrv = (const RSI_UDMA_DATACONTEXT_T *)pHandle;
404 if (dmaCh <= CHNL_31) {
405 if (((pDrv->base->CHNL_ENABLE_SET) & SET_BIT(dmaCh)) != 0) {
406 return RSI_OK;
407 } else {
408 return RSI_FAIL;
409 }
410 } else {
411 return ERROR_UDMA_INVALIDCHNLNUM;
412 }
413 }
414
415 /*===================================================*/
416 /**
417 * @fn void *RSI_UDMA_GetControlBaseAddress(RSI_UDMA_HANDLE_T pHandle)
418 * @brief This API is used to get the UDMA control base address
419 * @param[in] pHandle : Pointer to driver context handle
420 * @return Control structure base pointer
421 */
RSI_UDMA_GetControlBaseAddress(RSI_UDMA_HANDLE_T pHandle)422 STATIC INLINE void *RSI_UDMA_GetControlBaseAddress(RSI_UDMA_HANDLE_T pHandle)
423 {
424 RSI_UDMA_DATACONTEXT_T *pDrv = (RSI_UDMA_DATACONTEXT_T *)pHandle;
425 return ((void *)pDrv->base->CTRL_BASE_PTR);
426 }
427
428 /*===================================================*/
429 /**
430 * @fn void *RSI_UDMA_GetControlAlternateBase(RSI_UDMA_HANDLE_T pHandle)
431 * @brief This API is used to get the required UDMA channel alternate control base
432 * @param[in] pHandle : Pointer to driver context handle
433 * @return Alternate control structure base pointer
434 */
RSI_UDMA_GetControlAlternateBase(RSI_UDMA_HANDLE_T pHandle)435 STATIC INLINE void *RSI_UDMA_GetControlAlternateBase(RSI_UDMA_HANDLE_T pHandle)
436 {
437 RSI_UDMA_DATACONTEXT_T *pDrv = (RSI_UDMA_DATACONTEXT_T *)pHandle;
438 return ((void *)pDrv->base->ALT_CTRL_BASE_PTR);
439 }
440
441 /*===================================================*/
442 /**
443 * @fn rsi_error_t RSI_UDMA_ChannelSoftwareTrigger(RSI_UDMA_HANDLE_T pHandle, uint8_t dmaCh)
444 * @brief This API is used to to generate a software UDMA request on the corresponding UDMA channel
445 * @param[in] pHandle : Pointer to driver context handle
446 * @param[in] dmaCh : channel number (0 to 31).
447 * @return return ERROR_UDMA_INVALID_ARG if channel is greater than 31 or channel is invalid , and on success return RSI_OK(0).
448 */
RSI_UDMA_ChannelSoftwareTrigger(RSI_UDMA_HANDLE_T pHandle,uint8_t dmaCh)449 STATIC INLINE rsi_error_t RSI_UDMA_ChannelSoftwareTrigger(RSI_UDMA_HANDLE_T pHandle, uint8_t dmaCh)
450 {
451 RSI_UDMA_DATACONTEXT_T *pDrv = (RSI_UDMA_DATACONTEXT_T *)pHandle;
452 if (dmaCh <= CHNL_31) {
453 pDrv->base->CHNL_SW_REQUEST |= SET_BIT(dmaCh);
454 return RSI_OK;
455 } else
456 return ERROR_UDMA_INVALIDCHNLNUM;
457 }
458
459 /*===================================================*/
460 /**
461 * @fn rsi_error_t RSI_UDMA_InterruptClear(RSI_UDMA_HANDLE_T pHandle, uint8_t dmaCh)
462 * @brief This API is used to to generate a UDMA interrupt clear.
463 * @param[in] pHandle : Pointer to driver context handle
464 * @param[in] dmaCh : channel number (0 to 31).
465 * @return return ERROR_UDMA_INVALID_ARG if channel is greater than 31 or channel is invalid ,
466 * and on success return RSI_OK(0).
467 */
RSI_UDMA_InterruptClear(RSI_UDMA_HANDLE_T pHandle,uint8_t dmaCh)468 STATIC INLINE rsi_error_t RSI_UDMA_InterruptClear(RSI_UDMA_HANDLE_T pHandle, uint8_t dmaCh)
469 {
470 RSI_UDMA_DATACONTEXT_T *pDrv = (RSI_UDMA_DATACONTEXT_T *)pHandle;
471 if (dmaCh <= CHNL_31) {
472 pDrv->base->UDMA_DONE_STATUS_REG = SET_BIT(dmaCh);
473 } else {
474 return ERROR_UDMA_INVALIDCHNLNUM;
475 }
476 return RSI_OK;
477 }
478
479 /*===================================================*/
480 /**
481 * @fn uint32_t RSI_UDMA_InterruptStatus(RSI_UDMA_HANDLE_T pHandle, uint8_t dmaCh)
482 * @brief Gets interrupt status of required channel.
483 * @param[in] pHandle : Pointer to driver context handle
484 * @param[in] dmaCh : Channel number(0 to 31),Possible values are as below
485 - \b 0 : Channel disable
486 - \b 1 : Channel enable
487 * @return Interrupt status of required channel
488 */
RSI_UDMA_InterruptStatus(RSI_UDMA_HANDLE_T pHandle,uint8_t dmaCh)489 STATIC INLINE uint32_t RSI_UDMA_InterruptStatus(RSI_UDMA_HANDLE_T pHandle, uint8_t dmaCh)
490 {
491 uint32_t intr_stat = 0;
492 const RSI_UDMA_DATACONTEXT_T *pDrv = (const RSI_UDMA_DATACONTEXT_T *)pHandle;
493
494 intr_stat = pDrv->base->UDMA_DONE_STATUS_REG;
495 return (intr_stat & SET_BIT(dmaCh));
496 }
497
498 /*===================================================*/
499 /**
500 * @fn uint8_t RSI_UDMA_GetControllerEnableStatus(RSI_UDMA_HANDLE_T pHandle)
501 * @brief This API is used to get the enable status of controller
502 * @param[in] pHandle : Pointer to driver context handle
503 * @return If 1 controller is enabled ,if 0 controller is disabled
504 */
RSI_UDMA_GetControllerEnableStatus(RSI_UDMA_HANDLE_T pHandle)505 STATIC INLINE uint8_t RSI_UDMA_GetControllerEnableStatus(RSI_UDMA_HANDLE_T pHandle)
506 {
507 RSI_UDMA_DATACONTEXT_T *pDrv = (RSI_UDMA_DATACONTEXT_T *)pHandle;
508 return (pDrv->base->DMA_STATUS_b.MASTER_ENABLE);
509 }
510
511 /*===================================================*/
512 /**
513 * @fn uint32_t RSI_UDMA_GetControlState(RSI_UDMA_HANDLE_T pHandle)
514 * @brief This API is used to get the current state of the control state machine
515 * @param[in] pHandle : Pointer to driver context handle
516 * @return returns state of the control state machine
517 possible values are as below
518 - 0000 = idle
519 - 0001 = reading channel controller data
520 - 0010 = reading source data end pointer
521 - 0011 = reading destination data end pointer
522 - 0100 = reading source data
523 - 0101 = writing destination data
524 - 0110 = waiting for DMA request to clear
525 - 0111 = writing channel controller data
526 - 1000 = stalled
527 - 1001 = done
528 - 1010 = peripheral scatter-gather transition
529 - 1011-1111 = undefined.
530 */
RSI_UDMA_GetControlState(RSI_UDMA_HANDLE_T pHandle)531 STATIC INLINE uint32_t RSI_UDMA_GetControlState(RSI_UDMA_HANDLE_T pHandle)
532 {
533 const RSI_UDMA_DATACONTEXT_T *pDrv = (const RSI_UDMA_DATACONTEXT_T *)pHandle;
534 return (pDrv->base->DMA_STATUS_b.STATE);
535 }
536
537 // FUNCTION PROTOTYPES
538 RSI_DRIVER_VERSION_M4 RSI_UDMA_GetVersion(void);
539
540 RSI_UDMA_CAPABILITIES_T RSI_UDMA_GetCapabilities(void);
541
542 RSI_UDMA_HANDLE_T udma_init(void *mem, const RSI_UDMA_INIT_T *pInit);
543
544 uint32_t udma_get_channel_transfer_mode(RSI_UDMA_HANDLE_T pHandle, const RSI_UDMA_CHA_CFG_T *pCfg);
545
546 rsi_error_t udma_setup_channel_transfer(RSI_UDMA_HANDLE_T pHandle,
547 const RSI_UDMA_CHA_CFG_T *pCfg,
548 RSI_UDMA_CHA_CONFIG_DATA_T vsUdmaChaConfigData,
549 void *pSrcAddr,
550 volatile void *pDstAddr);
551
552 rsi_error_t udma_set_channel_scatter_gather_transfer(RSI_UDMA_HANDLE_T pHandle,
553 uint8_t dmaCh,
554 uint32_t taskCount,
555 void *pTaskList,
556 uint32_t transferType);
557
558 uint32_t udma_get_channel_transfer_length(RSI_UDMA_HANDLE_T pHandle,
559 const RSI_UDMA_CHA_CFG_T *pCfg,
560 RSI_UDMA_CHA_CONFIG_DATA_T vsUDMAChaConfigData);
561
562 rsi_error_t udma_setup_channel(RSI_UDMA_HANDLE_T pHandle, const RSI_UDMA_CHA_CFG_T *pCfg);
563
564 void udma_deInit(RSI_UDMA_HANDLE_T pHandle, const RSI_UDMA_CHA_CFG_T *pCfg);
565
566 void udma_interrupt_handler(RSI_UDMA_HANDLE_T pHandle);
567
568 rsi_error_t udma_interrupt_enable(RSI_UDMA_HANDLE_T pHandle, uint8_t dmaCh);
569 rsi_error_t RSI_UDMA_ChannelControlsDisable(RSI_UDMA_HANDLE_T pHandle, const RSI_UDMA_CHA_CFG_T *pCfg);
570 void RSI_UDMA_SetSingleRequest(RSI_UDMA_HANDLE_T pHandle);
571 void RSI_UDMA_AckEnable(const void *pHandle, uint32_t peripheral);
572
573 #ifdef __cplusplus
574 }
575 #endif
576
577 #endif // RSI_UDMA_H
578 /** @} */
579
