1 /* 2 * Copyright (c) 2019-2024 Arm Limited 3 * 4 * Licensed under the Apache License Version 2.0 (the "License"); 5 * you may not use this file except in compliance with the License. 6 * You may obtain a copy of the License at 7 * 8 * http://www.apache.org/licenses/LICENSE-2.0 9 * 10 * Unless required by applicable law or agreed to in writing software 11 * distributed under the License is distributed on an "AS IS" BASIS 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND either express or implied. 13 * See the License for the specific language governing permissions and 14 * limitations under the License. 15 */ 16 17 /** 18 * \file platform_base_address.h 19 * \brief This file defines all the peripheral base addresses for RSE platform. 20 */ 21 22 #ifndef __PLATFORM_BASE_ADDRESS_H__ 23 #define __PLATFORM_BASE_ADDRESS_H__ 24 25 #include "rse_memory_sizes.h" 26 #ifdef RSE_HAS_EXPANSION_PERIPHERALS 27 #include "rse_expansion_base_address.h" 28 #endif /* RSE_HAS_EXPANSION_PERIPHERALS */ 29 30 /* ======= Defines peripherals memory map addresses ======= */ 31 /* Non-secure memory map addresses */ 32 #define ITCM_BASE_NS 0x00000000 /* Instruction TCM Non-Secure base address */ 33 #define SIC_HOST_BASE_NS 0x02000000 /* Secure I-Cache Non-Secure mapping base address */ 34 #define ITCM_CPU0_BASE_NS 0x0A000000 /* CPU0 Instruction TCM Non-Secure base address */ 35 #define DTCM_BASE_NS 0x20000000 /* Data TCM Non-Secure base address */ 36 #define VM0_BASE_NS 0x21000000 /* Volatile Memory 0 Non-Secure base address */ 37 #define DTCM_CPU0_BASE_NS 0x24000000 /* CPU0 Data TCM Non-Secure base address */ 38 #define VM1_BASE_NS (VM0_BASE_NS + VM0_SIZE) /* Volatile Memory 1 Secure base address */ 39 /* Non-Secure Private CPU region */ 40 #define CPU0_PWRCTRL_BASE_NS 0x40012000 /* CPU 0 Power Control Block Non-Secure base address */ 41 #define CPU0_IDENTITY_BASE_NS 0x4001F000 /* CPU 0 Identity Block Non-Secure base address */ 42 /* Non-Secure Peripheral region */ 43 #define DMA_350_BASE_NS 0x40002000 /* DMA350 Non-Secure base address */ 44 #define RSE_NSACFG_BASE_NS 0x40080000 /* RSE Non-Secure Access Configuration Register Block Non-Secure base address */ 45 #define GPIO0_BASE_NS 0x40100000 /* Primecell GPIO0 Non-Secure base address */ 46 #define GPIO1_BASE_NS 0x40101000 /* Primecell GPIO1 Non-Secure base address */ 47 #define MHU0_SENDER_BASE_NS 0x40160000 /* Combined MHU 0 Sender Non-Secure base address */ 48 #define MHU0_RECEIVER_BASE_NS 0x40170000 /* Combined MHU 0 Receiver Non-Secure base address */ 49 #define MHU1_SENDER_BASE_NS 0x40180000 /* Combined MHU 1 Sender Non-Secure base address */ 50 #define MHU1_RECEIVER_BASE_NS 0x40190000 /* Combined MHU 1 Receiver Non-Secure base address */ 51 #define MHU2_SENDER_BASE_NS 0x401A0000 /* Combined MHU 2 Sender Non-Secure base address */ 52 #define MHU2_RECEIVER_BASE_NS 0x401B0000 /* Combined MHU 2 Receiver Non-Secure base address */ 53 #define MHU3_SENDER_BASE_NS 0x401C0000 /* Combined MHU 3 Sender Non-Secure base address */ 54 #define MHU3_RECEIVER_BASE_NS 0x401D0000 /* Combined MHU 3 Receiver Non-Secure base address */ 55 #define MHU4_SENDER_BASE_NS 0x401E0000 /* Combined MHU 4 Sender Non-Secure base address */ 56 #define MHU4_RECEIVER_BASE_NS 0x401F0000 /* Combined MHU 4 Receiver Non-Secure base address */ 57 #define MHU5_SENDER_BASE_NS 0x40200000 /* Combined MHU 5 Sender Non-Secure base address */ 58 #define MHU5_RECEIVER_BASE_NS 0x40210000 /* Combined MHU 5 Receiver Non-Secure base address */ 59 #define MHU6_SENDER_BASE_NS 0x40220000 /* Combined MHU 6 Sender Non-Secure base address */ 60 #define MHU6_RECEIVER_BASE_NS 0x40230000 /* Combined MHU 6 Receiver Non-Secure base address */ 61 #define MHU7_SENDER_BASE_NS 0x40240000 /* Combined MHU 7 Sender Non-Secure base address */ 62 #define MHU7_RECEIVER_BASE_NS 0x40250000 /* Combined MHU 7 Receiver Non-Secure base address */ 63 #define MHU8_SENDER_BASE_NS 0x40260000 /* Combined MHU 8 Sender Non-Secure base address */ 64 #define MHU8_RECEIVER_BASE_NS 0x40270000 /* Combined MHU 8 Receiver Non-Secure base address */ 65 #define SYSTIMER0_ARMV8_M_BASE_NS 0x48000000 /* System Timer 0 Non-Secure base address */ 66 #define SYSTIMER1_ARMV8_M_BASE_NS 0x48001000 /* System Timer 1 Non-Secure base address */ 67 #define SYSTIMER2_ARMV8_M_BASE_NS 0x48002000 /* System Timer 2 Non-Secure base address */ 68 #define SYSTIMER3_ARMV8_M_BASE_NS 0x48003000 /* System Timer 3 Non-Secure base address */ 69 #define RSE_SYSINFO_BASE_NS 0x48020000 /* RSE System info Block Non-Secure base address */ 70 #define SLOWCLK_TIMER_CMSDK_BASE_NS 0x4802F000 /* CMSDK based SLOWCLK Timer Non-Secure base address */ 71 #define SYSWDOG_ARMV8_M_CNTRL_BASE_NS 0x48040000 /* Non-Secure Watchdog Timer control frame Non-Secure base address */ 72 #define SYSWDOG_ARMV8_M_REFRESH_BASE_NS 0x48041000 /* Non-Secure Watchdog Timer refresh frame Non-Secure base address */ 73 #define RSE_DEBUG_UART0_BASE_NS 0xE0305000 /* Debug UART attached to RSE subsystem */ 74 /* Non-Secure Host region */ 75 #define HOST_ACCESS_BASE_NS 0x60000000 /* Can access the Host region based on ATU config */ 76 #define HOST_ACCESS_LIMIT_NS (HOST_ACCESS_BASE_NS + HOST_ACCESS_SIZE - 1) 77 /* ATU regions open in bootloader and runtime */ 78 #ifdef RSE_USE_HOST_UART 79 #define HOST_UART0_BASE_NS (HOST_ACCESS_BASE_NS + 0xFF00000) /* UART 0 Non-Secure base address */ 80 #endif /* RSE_USE_HOST_UART */ 81 82 /* Secure memory map addresses */ 83 #define ITCM_BASE_S 0x10000000 /* Instruction TCM Secure base address */ 84 #define ROM_BASE_S 0x11000000 /* CODE ROM Secure base address. No NS alias for ROM */ 85 #define SIC_HOST_BASE_S 0x12000000 /* Secure I-Cache Secure mapping base address */ 86 #define ITCM_CPU0_BASE_S 0x1A000000 /* CPU0 Instruction TCM Secure base address */ 87 #define DTCM_BASE_S 0x30000000 /* Data TCM Secure base address */ 88 #define VM0_BASE_S 0x31000000 /* Volatile Memory 0 Secure base address */ 89 #define DTCM_CPU0_BASE_S 0x34000000 /* CPU0 Data TCM Secure base address */ 90 #define VM1_BASE_S (VM0_BASE_S + VM0_SIZE) /* Volatile Memory 1 Secure base address */ 91 /* Secure Private CPU region */ 92 #define CPU0_SECCTRL_BASE_S 0x50011000 /* CPU 0 Local Security Control Block Secure base address */ 93 #define CPU0_PWRCTRL_BASE_S 0x50012000 /* CPU 0 Power Control Block Secure base address */ 94 #define CPU0_IDENTITY_BASE_S 0x5001F000 /* CPU 0 Identity Block Secure base address */ 95 /* Secure Peripheral region */ 96 #define DMA_350_BASE_S 0x50002000 /* DMA350 Secure base address */ 97 #define RSE_SACFG_BASE_S 0x50080000 /* RSE Secure Access Configuration Register Secure base address */ 98 #define MPC_VM0_BASE_S 0x50083000 /* VM0 Memory Protection Controller Secure base address */ 99 #define MPC_VM1_BASE_S 0x50084000 /* VM1 Memory Protection Controller Secure base address */ 100 #define KMU_BASE_S 0x5009E000 /* KMU Secure base address */ 101 #define SAM_BASE_S 0x5009F000 /* SAM Secure base address */ 102 #define LCM_BASE_S 0x500A0000 /* LCM Secure base address */ 103 #define GPIO0_BASE_S 0x50100000 /* Primecell GPIO0 Secure base address */ 104 #define GPIO1_BASE_S 0x50101000 /* Primecell GPIO1 Secure base address */ 105 #define SIC_BASE_S 0x50140000 /* SIC Secure base address */ 106 #define ATU_BASE_S 0x50150000 /* ATU Secure base address */ 107 #define MPC_SIC_BASE_S 0x50151000 /* SIC Memory Protection Controller Secure base address */ 108 #define CC3XX_BASE_S 0x50154000 /* CryptoCell CC3XX Secure base address */ 109 #define SYSCNTR_CNTRL_BASE_S 0x5015A000 /* System Counter Control Secure base address */ 110 #define SYSCNTR_READ_BASE_S 0x5015B000 /* System Counter Read Secure base address */ 111 #define INTEGRITY_CHECKER_BASE_S 0x5015C000 /* Integrity Checker Secure base address */ 112 #define TRAM_BASE_S 0x5015D000 /* TRAM Secure base address */ 113 #define MHU0_SENDER_BASE_S 0x50160000 /* Combined MHU 0 Sender Secure base address */ 114 #define MHU0_RECEIVER_BASE_S 0x50170000 /* Combined MHU 0 Receiver Secure base address */ 115 #define MHU1_SENDER_BASE_S 0x50180000 /* Combined MHU 1 Sender Secure base address */ 116 #define MHU1_RECEIVER_BASE_S 0x50190000 /* Combined MHU 1 Receiver Secure base address */ 117 #define MHU2_SENDER_BASE_S 0x501A0000 /* Combined MHU 2 Sender Secure base address */ 118 #define MHU2_RECEIVER_BASE_S 0x501B0000 /* Combined MHU 2 Receiver Secure base address */ 119 #define MHU3_SENDER_BASE_S 0x501C0000 /* Combined MHU 3 Sender Secure base address */ 120 #define MHU3_RECEIVER_BASE_S 0x501D0000 /* Combined MHU 3 Receiver Secure base address */ 121 #define MHU4_SENDER_BASE_S 0x501E0000 /* Combined MHU 4 Sender Secure base address */ 122 #define MHU4_RECEIVER_BASE_S 0x501F0000 /* Combined MHU 4 Receiver Secure base address */ 123 #define MHU5_SENDER_BASE_S 0x50200000 /* Combined MHU 5 Sender Secure base address */ 124 #define MHU5_RECEIVER_BASE_S 0x50210000 /* Combined MHU 5 Receiver Secure base address */ 125 #define MHU6_SENDER_BASE_S 0x50220000 /* Combined MHU 6 Sender Secure base address */ 126 #define MHU6_RECEIVER_BASE_S 0x50230000 /* Combined MHU 6 Receiver Secure base address */ 127 #define MHU7_SENDER_BASE_S 0x50240000 /* Combined MHU 7 Sender Secure base address */ 128 #define MHU7_RECEIVER_BASE_S 0x50250000 /* Combined MHU 7 Receiver Secure base address */ 129 #define MHU8_SENDER_BASE_S 0x50260000 /* Combined MHU 8 Sender Secure base address */ 130 #define MHU8_RECEIVER_BASE_S 0x50270000 /* Combined MHU 8 Receiver Secure base address */ 131 #define SYSTIMER0_ARMV8_M_BASE_S 0x58000000 /* System Timer 0 Secure base address */ 132 #define SYSTIMER1_ARMV8_M_BASE_S 0x58001000 /* System Timer 1 Secure base address */ 133 #define SYSTIMER2_ARMV8_M_BASE_S 0x58002000 /* System Timer 2 Secure base address */ 134 #define SYSTIMER3_ARMV8_M_BASE_S 0x58003000 /* System Timer 3 Secure base address */ 135 #define RSE_SYSINFO_BASE_S 0x58020000 /* RSE System info Block Secure base address */ 136 #define RSE_SYSCTRL_BASE_S 0x58021000 /* RSE System control Block Secure base address */ 137 #define RSE_SYSPPU_BASE_S 0x58022000 /* RSE System Power Policy Unit Secure base address */ 138 #define RSE_CPU0PPU_BASE_S 0x58023000 /* RSE CPU 0 Power Policy Unit Secure base address */ 139 #define RSE_MGMTPPU_BASE_S 0x58028000 /* RSE Management Power Policy Unit Secure base address */ 140 #define RSE_DBGPPU_BASE_S 0x58029000 /* RSE Debug Power Policy Unit Secure base address */ 141 #define SLOWCLK_WDOG_CMSDK_BASE_S 0x5802E000 /* CMSDK based SLOWCLK Watchdog Secure base address */ 142 #define SLOWCLK_TIMER_CMSDK_BASE_S 0x5802F000 /* CMSDK based SLOWCLK Timer Secure base address */ 143 #define SYSWDOG_ARMV8_M_CNTRL_BASE_S 0x58040000 /* Secure Watchdog Timer control frame Secure base address */ 144 #define SYSWDOG_ARMV8_M_REFRESH_BASE_S 0x58041000 /* Secure Watchdog Timer refresh frame Secure base address */ 145 #define RSE_DEBUG_UART0_BASE_S 0xF0305000 /* Debug UART attached to RSE subsystem */ 146 147 /* Secure Host region */ 148 #define HOST_ACCESS_BASE_S 0x70000000 /* Can access the Host region based on ATU config */ 149 #define HOST_ACCESS_LIMIT_S ((uint32_t)HOST_ACCESS_BASE_S + (uint32_t)HOST_ACCESS_SIZE - 1) 150 151 #define HOST_IMAGE_MAX_SIZE 0x1000000 /* 16 MiB */ 152 153 /* ATU regions open in bootloader and runtime */ 154 #ifdef RSE_USE_HOST_UART 155 #define HOST_UART0_BASE_S (HOST_ACCESS_BASE_S + 0xFF00000) /* UART 0 Secure base address */ 156 #endif /* RSE_USE_HOST_UART */ 157 /* ATU regions open in BL1 */ 158 #define HOST_FLASH0_TEMP_BASE_S (HOST_ACCESS_BASE_S + 2 * HOST_IMAGE_MAX_SIZE) /* Temporary address for mapping host flash areas */ 159 #define HOST_FLASH0_IMAGE0_BASE_S (HOST_ACCESS_BASE_S + 3 * HOST_IMAGE_MAX_SIZE) /* Host flash image 0 input secure address */ 160 #define HOST_FLASH0_IMAGE1_BASE_S (HOST_ACCESS_BASE_S + 4 * HOST_IMAGE_MAX_SIZE) /* Host flash image 1 input secure address */ 161 /* ATU regions open in BL2 */ 162 #define HOST_BOOT_IMAGE0_LOAD_BASE_S (HOST_ACCESS_BASE_S + 0 * HOST_IMAGE_MAX_SIZE) /* Host boot image 0 output secure address */ 163 #define HOST_BOOT_IMAGE1_LOAD_BASE_S (HOST_ACCESS_BASE_S + 1 * HOST_IMAGE_MAX_SIZE) /* Host boot image 1 output secure address */ 164 #define HOST_FLASH0_TEMP0_BASE_S (HOST_ACCESS_BASE_S + 2 * HOST_IMAGE_MAX_SIZE) /* Temporary secure address for mapping host flash areas */ 165 #define HOST_FLASH0_IMAGE0_BASE_S (HOST_ACCESS_BASE_S + 3 * HOST_IMAGE_MAX_SIZE) /* Host flash image 0 input secure address */ 166 #define HOST_FLASH0_IMAGE1_BASE_S (HOST_ACCESS_BASE_S + 4 * HOST_IMAGE_MAX_SIZE) /* Host flash image 1 input secure address */ 167 /* ATU regions open at runtime */ 168 #define FWU_HOST_IMAGE_BASE_S (HOST_ACCESS_BASE_S + 0 * HOST_IMAGE_MAX_SIZE) /* Region to allow writing new RSE FW images */ 169 #define HOST_COMMS_MAPPABLE_BASE_S (HOST_ACCESS_BASE_S + 1 * HOST_IMAGE_MAX_SIZE) /* Region into which to map host comms pointers */ 170 #ifdef TFM_PARTITION_PROTECTED_STORAGE 171 #define HOST_ACCESS_PS_BASE_S (HOST_ACCESS_BASE_S + 2 * HOST_IMAGE_MAX_SIZE) /* Region into which to map Protected Storage */ 172 #define HOST_ACCESS_PS_BASE_OFFSET (HOST_ACCESS_PS_BASE_S - HOST_ACCESS_BASE_S) 173 #endif /* TFM_PARTITION_PROTECTED_STORAGE */ 174 175 /* SIC regions open in BL2 and runtime. These must be contiguous */ 176 #define RSE_RUNTIME_S_XIP_BASE_S SIC_HOST_BASE_S /* RSE runtime secure image XIP secure address */ 177 #define RSE_RUNTIME_NS_XIP_BASE_S (SIC_HOST_BASE_S + FLASH_S_PARTITION_SIZE) /* RSE runtime non-secure image XIP secure address */ 178 179 #define RSE_RUNTIME_NS_XIP_BASE_NS (SIC_HOST_BASE_NS + FLASH_S_PARTITION_SIZE) /* RSE runtime non-secure image XIP non-secure address */ 180 181 /* Memory map addresses exempt from memory attribution by both the SAU and IDAU */ 182 #define RSE_EWIC_BASE 0xE0047000 /* External Wakeup Interrupt Controller 183 * Access from Non-secure software is only allowed 184 * if AIRCR.BFHFNMINS is set to 1 */ 185 186 /* Memory size definitions */ 187 #define ITCM_SIZE 0x00008000 /* 32 kB */ 188 #define ROM_SIZE 0x00020000 /* 128 kB */ 189 #define DTCM_SIZE 0x00008000 /* 32 kB */ 190 #define HOST_ACCESS_SIZE 0x10000000 /* 256 MB */ 191 #define SIC_MAPPABLE_SIZE 0x01000000 /* 16 MB */ 192 193 /* Defines for Driver MPC's */ 194 /* VM0 -- 8 MB */ 195 #define MPC_VM0_RANGE_BASE_NS (VM0_BASE_NS) 196 #define MPC_VM0_RANGE_LIMIT_NS (VM0_BASE_NS + VM0_SIZE-1) 197 #define MPC_VM0_RANGE_OFFSET_NS (0x0) 198 #define MPC_VM0_RANGE_BASE_S (VM0_BASE_S) 199 #define MPC_VM0_RANGE_LIMIT_S (VM0_BASE_S + VM0_SIZE-1) 200 #define MPC_VM0_RANGE_OFFSET_S (0x0) 201 202 /* VM1 -- 8 MB */ 203 #define MPC_VM1_RANGE_BASE_NS (VM1_BASE_NS) 204 #define MPC_VM1_RANGE_LIMIT_NS (VM1_BASE_NS + VM1_SIZE-1) 205 #define MPC_VM1_RANGE_OFFSET_NS (0x0) 206 #define MPC_VM1_RANGE_BASE_S (VM1_BASE_S) 207 #define MPC_VM1_RANGE_LIMIT_S (VM1_BASE_S + VM1_SIZE-1) 208 #define MPC_VM1_RANGE_OFFSET_S (0x0) 209 210 /* SIC -- 1 MiB */ 211 #define MPC_SIC_RANGE_BASE_NS (SIC_HOST_BASE_NS) 212 #define MPC_SIC_RANGE_LIMIT_NS (SIC_HOST_BASE_NS + SIC_MAPPABLE_SIZE-1) 213 #define MPC_SIC_RANGE_OFFSET_NS (0x0) 214 #define MPC_SIC_RANGE_BASE_S (SIC_HOST_BASE_S) 215 #define MPC_SIC_RANGE_LIMIT_S (SIC_HOST_BASE_S + SIC_MAPPABLE_SIZE-1) 216 #define MPC_SIC_RANGE_OFFSET_S (0x0) 217 218 #endif /* __PLATFORM_BASE_ADDRESS_H__ */ 219
