1 /** 2 * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 #pragma once 7 8 #include <stdint.h> 9 #include "soc/soc.h" 10 #ifdef __cplusplus 11 extern "C" { 12 #endif 13 14 /** RSA_M_MEM register 15 * Represents M 16 */ 17 #define RSA_M_MEM_REG (DR_REG_RSA_BASE + 0x0) 18 #define RSA_M_MEM_SIZE_BYTES 16 19 20 /** RSA_Z_MEM register 21 * Represents Z 22 */ 23 #define RSA_Z_MEM_REG (DR_REG_RSA_BASE + 0x200) 24 #define RSA_Z_MEM_SIZE_BYTES 16 25 26 /** RSA_Y_MEM register 27 * Represents Y 28 */ 29 #define RSA_Y_MEM_REG (DR_REG_RSA_BASE + 0x400) 30 #define RSA_Y_MEM_SIZE_BYTES 16 31 32 /** RSA_X_MEM register 33 * Represents X 34 */ 35 #define RSA_X_MEM_REG (DR_REG_RSA_BASE + 0x600) 36 #define RSA_X_MEM_SIZE_BYTES 16 37 38 /** RSA_M_PRIME_REG register 39 * Represents M’ 40 */ 41 #define RSA_M_PRIME_REG (DR_REG_RSA_BASE + 0x800) 42 /** RSA_M_PRIME : R/W; bitpos: [31:0]; default: 0; 43 * Represents M’ 44 */ 45 #define RSA_M_PRIME 0xFFFFFFFFU 46 #define RSA_M_PRIME_M (RSA_M_PRIME_V << RSA_M_PRIME_S) 47 #define RSA_M_PRIME_V 0xFFFFFFFFU 48 #define RSA_M_PRIME_S 0 49 50 /** RSA_MODE_REG register 51 * Configures RSA length 52 */ 53 #define RSA_MODE_REG (DR_REG_RSA_BASE + 0x804) 54 /** RSA_MODE : R/W; bitpos: [6:0]; default: 0; 55 * Configures the RSA length. 56 */ 57 #define RSA_MODE 0x0000007FU 58 #define RSA_MODE_M (RSA_MODE_V << RSA_MODE_S) 59 #define RSA_MODE_V 0x0000007FU 60 #define RSA_MODE_S 0 61 62 /** RSA_QUERY_CLEAN_REG register 63 * RSA clean register 64 */ 65 #define RSA_QUERY_CLEAN_REG (DR_REG_RSA_BASE + 0x808) 66 /** RSA_QUERY_CLEAN : RO; bitpos: [0]; default: 0; 67 * Represents whether or not the RSA memory completes initialization. 68 * 69 * 0: Not complete 70 * 71 * 1: Completed 72 * 73 */ 74 #define RSA_QUERY_CLEAN (BIT(0)) 75 #define RSA_QUERY_CLEAN_M (RSA_QUERY_CLEAN_V << RSA_QUERY_CLEAN_S) 76 #define RSA_QUERY_CLEAN_V 0x00000001U 77 #define RSA_QUERY_CLEAN_S 0 78 79 /** RSA_SET_START_MODEXP_REG register 80 * Starts modular exponentiation 81 */ 82 #define RSA_SET_START_MODEXP_REG (DR_REG_RSA_BASE + 0x80c) 83 /** RSA_SET_START_MODEXP : WT; bitpos: [0]; default: 0; 84 * Configure whether or not to start the modular exponentiation. 85 * 86 * 0: No effect 87 * 88 * 1: Start 89 * 90 */ 91 #define RSA_SET_START_MODEXP (BIT(0)) 92 #define RSA_SET_START_MODEXP_M (RSA_SET_START_MODEXP_V << RSA_SET_START_MODEXP_S) 93 #define RSA_SET_START_MODEXP_V 0x00000001U 94 #define RSA_SET_START_MODEXP_S 0 95 96 /** RSA_SET_START_MODMULT_REG register 97 * Starts modular multiplication 98 */ 99 #define RSA_SET_START_MODMULT_REG (DR_REG_RSA_BASE + 0x810) 100 /** RSA_SET_START_MODMULT : WT; bitpos: [0]; default: 0; 101 * Configure whether or not to start the modular multiplication. 102 * 103 * 0: No effect 104 * 105 * 1: Start 106 * 107 */ 108 #define RSA_SET_START_MODMULT (BIT(0)) 109 #define RSA_SET_START_MODMULT_M (RSA_SET_START_MODMULT_V << RSA_SET_START_MODMULT_S) 110 #define RSA_SET_START_MODMULT_V 0x00000001U 111 #define RSA_SET_START_MODMULT_S 0 112 113 /** RSA_SET_START_MULT_REG register 114 * Starts multiplication 115 */ 116 #define RSA_SET_START_MULT_REG (DR_REG_RSA_BASE + 0x814) 117 /** RSA_SET_START_MULT : WT; bitpos: [0]; default: 0; 118 * Configure whether or not to start the multiplication. 119 * 120 * 0: No effect 121 * 122 * 1: Start 123 * 124 */ 125 #define RSA_SET_START_MULT (BIT(0)) 126 #define RSA_SET_START_MULT_M (RSA_SET_START_MULT_V << RSA_SET_START_MULT_S) 127 #define RSA_SET_START_MULT_V 0x00000001U 128 #define RSA_SET_START_MULT_S 0 129 130 /** RSA_QUERY_IDLE_REG register 131 * Represents the RSA status 132 */ 133 #define RSA_QUERY_IDLE_REG (DR_REG_RSA_BASE + 0x818) 134 /** RSA_QUERY_IDLE : RO; bitpos: [0]; default: 0; 135 * Represents the RSA status. 136 * 137 * 0: Busy 138 * 139 * 1: Idle 140 * 141 */ 142 #define RSA_QUERY_IDLE (BIT(0)) 143 #define RSA_QUERY_IDLE_M (RSA_QUERY_IDLE_V << RSA_QUERY_IDLE_S) 144 #define RSA_QUERY_IDLE_V 0x00000001U 145 #define RSA_QUERY_IDLE_S 0 146 147 /** RSA_INT_CLR_REG register 148 * Clears RSA interrupt 149 */ 150 #define RSA_INT_CLR_REG (DR_REG_RSA_BASE + 0x81c) 151 /** RSA_CLEAR_INTERRUPT : WT; bitpos: [0]; default: 0; 152 * Write 1 to clear the RSA interrupt. 153 */ 154 #define RSA_CLEAR_INTERRUPT (BIT(0)) 155 #define RSA_CLEAR_INTERRUPT_M (RSA_CLEAR_INTERRUPT_V << RSA_CLEAR_INTERRUPT_S) 156 #define RSA_CLEAR_INTERRUPT_V 0x00000001U 157 #define RSA_CLEAR_INTERRUPT_S 0 158 159 /** RSA_CONSTANT_TIME_REG register 160 * Configures the constant_time option 161 */ 162 #define RSA_CONSTANT_TIME_REG (DR_REG_RSA_BASE + 0x820) 163 /** RSA_CONSTANT_TIME : R/W; bitpos: [0]; default: 1; 164 * Configures the constant_time option. 165 * 166 * 0: Acceleration 167 * 168 * 1: No acceleration (default) 169 * 170 */ 171 #define RSA_CONSTANT_TIME (BIT(0)) 172 #define RSA_CONSTANT_TIME_M (RSA_CONSTANT_TIME_V << RSA_CONSTANT_TIME_S) 173 #define RSA_CONSTANT_TIME_V 0x00000001U 174 #define RSA_CONSTANT_TIME_S 0 175 176 /** RSA_SEARCH_ENABLE_REG register 177 * Configures the search option 178 */ 179 #define RSA_SEARCH_ENABLE_REG (DR_REG_RSA_BASE + 0x824) 180 /** RSA_SEARCH_ENABLE : R/W; bitpos: [0]; default: 0; 181 * Configure the search option. 182 * 183 * 0: No acceleration (default) 184 * 185 * 1: Acceleration 186 * 187 * This option should be used together with RSA_SEARCH_POS. 188 */ 189 #define RSA_SEARCH_ENABLE (BIT(0)) 190 #define RSA_SEARCH_ENABLE_M (RSA_SEARCH_ENABLE_V << RSA_SEARCH_ENABLE_S) 191 #define RSA_SEARCH_ENABLE_V 0x00000001U 192 #define RSA_SEARCH_ENABLE_S 0 193 194 /** RSA_SEARCH_POS_REG register 195 * Configures the search position 196 */ 197 #define RSA_SEARCH_POS_REG (DR_REG_RSA_BASE + 0x828) 198 /** RSA_SEARCH_POS : R/W; bitpos: [11:0]; default: 0; 199 * Configures the starting address to start search. This field should be used together 200 * with RSA_SEARCH_ENABLE. The field is only valid when RSA_SEARCH_ENABLE is high. 201 */ 202 #define RSA_SEARCH_POS 0x00000FFFU 203 #define RSA_SEARCH_POS_M (RSA_SEARCH_POS_V << RSA_SEARCH_POS_S) 204 #define RSA_SEARCH_POS_V 0x00000FFFU 205 #define RSA_SEARCH_POS_S 0 206 207 /** RSA_INT_ENA_REG register 208 * Enables the RSA interrupt 209 */ 210 #define RSA_INT_ENA_REG (DR_REG_RSA_BASE + 0x82c) 211 /** RSA_INT_ENA : R/W; bitpos: [0]; default: 0; 212 * Write 1 to enable the RSA interrupt. 213 */ 214 #define RSA_INT_ENA (BIT(0)) 215 #define RSA_INT_ENA_M (RSA_INT_ENA_V << RSA_INT_ENA_S) 216 #define RSA_INT_ENA_V 0x00000001U 217 #define RSA_INT_ENA_S 0 218 219 /** RSA_DATE_REG register 220 * Version control register 221 */ 222 #define RSA_DATE_REG (DR_REG_RSA_BASE + 0x830) 223 /** RSA_DATE : R/W; bitpos: [29:0]; default: 538969624; 224 * Version control register. 225 */ 226 #define RSA_DATE 0x3FFFFFFFU 227 #define RSA_DATE_M (RSA_DATE_V << RSA_DATE_S) 228 #define RSA_DATE_V 0x3FFFFFFFU 229 #define RSA_DATE_S 0 230 231 #ifdef __cplusplus 232 } 233 #endif 234
