1 /* 2 * Copyright 2020 Broadcom 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7 #ifndef DMA_IPROC_PAX_V1 8 #define DMA_IPROC_PAX_V1 9 10 #include "dma_iproc_pax.h" 11 12 /* Register RM_CONTROL fields */ 13 #define RM_COMM_MSI_INTERRUPT_STATUS_MASK 0x30d0 14 #define RM_COMM_MSI_INTERRUPT_STATUS_CLEAR 0x30d4 15 16 #define RM_COMM_CONTROL_MODE_MASK 0x3 17 #define RM_COMM_CONTROL_MODE_SHIFT 0 18 #define RM_COMM_CONTROL_MODE_TOGGLE 0x2 19 #define RM_COMM_CONTROL_CONFIG_DONE BIT(2) 20 #define RM_COMM_CONTROL_LINE_INTR_EN_SHIFT 4 21 #define RM_COMM_CONTROL_LINE_INTR_EN BIT(4) 22 #define RM_COMM_CONTROL_AE_TIMEOUT_EN_SHIFT 5 23 #define RM_COMM_CONTROL_AE_TIMEOUT_EN BIT(5) 24 #define RM_COMM_MSI_DISABLE_VAL 3 25 26 #define PAX_DMA_TYPE_DMA_DESC 0x3 27 #define PAX_DMA_NUM_BD_BUFFS 8 28 /* DMA desc count: 3 entries per packet */ 29 #define PAX_DMA_RM_DESC_BDCOUNT 3 30 /* 1 DMA packet desc takes 3 BDs */ 31 #define PAX_DMA_DMA_DESC_SIZE (PAX_DMA_RM_DESC_BDWIDTH * \ 32 PAX_DMA_RM_DESC_BDCOUNT) 33 /* Max size of transfer in single packet */ 34 #define PAX_DMA_MAX_DMA_SIZE_PER_BD (16 * 1024 * 1024) 35 36 /* ascii signature 'V' 'K' */ 37 #define PAX_DMA_WRITE_SYNC_SIGNATURE 0x564B 38 39 /* DMA transfers supported from 4 bytes thru 16M, size aligned to 4 bytes */ 40 #define PAX_DMA_MIN_SIZE 4 41 #define PAX_DMA_MAX_SIZE (16 * 1024 * 1024) 42 43 /* Bits 0:1 ignored by PAX DMA, i.e. 4-byte address alignment */ 44 #define PAX_DMA_PCI_ADDR_LS_IGNORE_BITS 2 45 #define PAX_DMA_PCI_ADDR_ALIGNMT_SHIFT PAX_DMA_PCI_ADDR_LS_IGNORE_BITS 46 47 /* s/w payload struct, enough space for 1020 sglist elements */ 48 #define PAX_DMA_PAYLOAD_BUFF_SIZE (32 * 1024) 49 50 /* 51 * Per-ring memory, with 8K & 4K alignment 52 * Alignment may not be ensured by allocator 53 * s/w need to allocate extra upto 8K to 54 * ensure aligned memory space. 55 */ 56 #define PAX_DMA_PER_RING_ALLOC_SIZE (PAX_DMA_RM_CMPL_RING_SIZE * 2 + \ 57 PAX_DMA_NUM_BD_BUFFS * \ 58 PAX_DMA_RM_DESC_RING_SIZE + \ 59 PAX_DMA_PAYLOAD_BUFF_SIZE) 60 61 /* RM header desc field */ 62 struct rm_header { 63 uint64_t opq : 16; /*pkt_id 15:0*/ 64 uint64_t res1 : 20; /*reserved 35:16*/ 65 uint64_t bdcount : 5; /*bdcount 40:36*/ 66 uint64_t prot : 2; /*prot 41:40*/ 67 uint64_t res2 : 13; /*reserved 55:43*/ 68 uint64_t start : 1; /*start pkt :56*/ 69 uint64_t end : 1; /*end pkt :57*/ 70 uint64_t toggle : 1; /*toggle :58*/ 71 uint64_t res3 : 1; /*reserved :59*/ 72 uint64_t type : 4; /*type 63:60*/ 73 } __attribute__ ((__packed__)); 74 75 /* dma desc header field */ 76 struct dma_header_desc { 77 uint64_t length : 25; /*transfer length in bytes 24:0*/ 78 uint64_t res1: 31; /*reserved 55:25*/ 79 uint64_t opcode : 4; /*opcode 59:56*/ 80 uint64_t res2: 2; /*reserved 61:60*/ 81 uint64_t type : 2; /*type 63:62 set to b'11*/ 82 } __attribute__ ((__packed__)); 83 84 /* dma desc AXI addr field */ 85 struct axi_addr_desc { 86 uint64_t axi_addr : 48; /*axi_addr[47:0]*/ 87 uint64_t res : 14; /*reserved 48:61*/ 88 uint64_t type : 2; /*63:62 set to b'11*/ 89 } __attribute__ ((__packed__)); 90 91 /* dma desc PCI addr field */ 92 struct pci_addr_desc { 93 uint64_t pcie_addr : 62; /*pcie_addr[63:2]*/ 94 uint64_t type : 2; /*63:62 set to b'11*/ 95 } __attribute__ ((__packed__)); 96 97 /* DMA descriptor */ 98 struct dma_desc { 99 struct dma_header_desc hdr; 100 struct axi_addr_desc axi; 101 struct pci_addr_desc pci; 102 } __attribute__ ((__packed__)); 103 104 struct next_ptr_desc { 105 uint64_t addr : 44; /*Address 43:0*/ 106 uint64_t res1 : 14;/*Reserved*/ 107 uint64_t toggle : 1; /*Toggle Bit:58*/ 108 uint64_t res2 : 1;/*Reserved 59:59*/ 109 uint64_t type : 4;/*descriptor type 63:60*/ 110 } __attribute__ ((__packed__)); 111 112 #endif 113
