1 /** 2 ****************************************************************************** 3 * @file stm32n6xx_hal_rif.h 4 * @author MCD Application Team 5 * @brief Header file of RIF HAL module. 6 ****************************************************************************** 7 * @attention 8 * 9 * Copyright (c) 2023 STMicroelectronics. 10 * All rights reserved. 11 * 12 * This software is licensed under terms that can be found in the LICENSE file 13 * in the root directory of this software component. 14 * If no LICENSE file comes with this software, it is provided AS-IS. 15 * 16 ****************************************************************************** 17 */ 18 19 /* Define to prevent recursive inclusion -------------------------------------*/ 20 #ifndef STM32N6xx_HAL_RIF_H 21 #define STM32N6xx_HAL_RIF_H 22 23 #ifdef __cplusplus 24 extern "C" { 25 #endif 26 27 /* Includes ------------------------------------------------------------------*/ 28 #include "stm32n6xx_hal_def.h" 29 30 /** @addtogroup STM32N6xx_HAL_Driver 31 * @{ 32 */ 33 34 /** @addtogroup RIF 35 * @{ 36 */ 37 38 /* Exported constants --------------------------------------------------------*/ 39 /** @defgroup RIF_EXPORTED_CONSTANTS_COMMON RIF exported constants - Common 40 * @{ 41 */ 42 43 /** @defgroup RIF_COMPARTMENT_ID RIF CID number definition 44 * @{ 45 */ 46 #define RIF_CID_NONE 0x00000000U 47 #define RIF_CID_0 0x00000001U 48 #define RIF_CID_1 0x00000002U 49 #define RIF_CID_2 0x00000004U 50 #define RIF_CID_3 0x00000008U 51 #define RIF_CID_4 0x00000010U 52 #define RIF_CID_5 0x00000020U 53 #define RIF_CID_6 0x00000040U 54 #define RIF_CID_7 0x00000080U 55 /** 56 * @} 57 */ 58 59 /** @defgroup RIF_MASTER_INDEX RIF Master index 60 * @{ 61 */ 62 #define RIF_MASTER_INDEX_ETR 0U 63 #if defined(NPU_PRESENT) 64 #define RIF_MASTER_INDEX_NPU 1U 65 #endif /* defined(NPU_PRESENT) */ 66 #define RIF_MASTER_INDEX_SDMMC1 2U 67 #define RIF_MASTER_INDEX_SDMMC2 3U 68 #define RIF_MASTER_INDEX_OTG1 4U 69 #define RIF_MASTER_INDEX_OTG2 5U 70 #define RIF_MASTER_INDEX_ETH1 6U 71 #define RIF_MASTER_INDEX_GPU2D 7U 72 #define RIF_MASTER_INDEX_DMA2D 8U 73 #define RIF_MASTER_INDEX_DCMIPP 9U 74 #define RIF_MASTER_INDEX_LTDC1 10U 75 #define RIF_MASTER_INDEX_LTDC2 11U 76 #define RIF_MASTER_INDEX_VENC 12U 77 /** 78 * @} 79 */ 80 81 /** @defgroup RIF_PERIPHERAL_INDEX RIF RISUP Peripheral index 82 * @{ 83 */ 84 /** @defgroup RIF_PERIPH_PERIPHERAL_INDEX RIF RISUP Peripheral index 85 * @{ 86 */ 87 #define RIF_RISC_PERIPH_INDEX_SPI1 (RIF_PERIPH_REG0 | RIFSC_RISC_SECCFGRx_SEC0_Pos) 88 #define RIF_RISC_PERIPH_INDEX_SPI2 (RIF_PERIPH_REG0 | RIFSC_RISC_SECCFGRx_SEC1_Pos) 89 #define RIF_RISC_PERIPH_INDEX_SPI3 (RIF_PERIPH_REG0 | RIFSC_RISC_SECCFGRx_SEC2_Pos) 90 #define RIF_RISC_PERIPH_INDEX_SPI4 (RIF_PERIPH_REG0 | RIFSC_RISC_SECCFGRx_SEC3_Pos) 91 #define RIF_RISC_PERIPH_INDEX_SPI5 (RIF_PERIPH_REG0 | RIFSC_RISC_SECCFGRx_SEC4_Pos) 92 #define RIF_RISC_PERIPH_INDEX_SPI6 (RIF_PERIPH_REG0 | RIFSC_RISC_SECCFGRx_SEC5_Pos) 93 #define RIF_RISC_PERIPH_INDEX_SAI1 (RIF_PERIPH_REG0 | RIFSC_RISC_SECCFGRx_SEC6_Pos) 94 #define RIF_RISC_PERIPH_INDEX_SAI2 (RIF_PERIPH_REG0 | RIFSC_RISC_SECCFGRx_SEC8_Pos) 95 #define RIF_RISC_PERIPH_INDEX_I2C1 (RIF_PERIPH_REG0 | RIFSC_RISC_SECCFGRx_SEC9_Pos) 96 #define RIF_RISC_PERIPH_INDEX_I2C2 (RIF_PERIPH_REG0 | RIFSC_RISC_SECCFGRx_SEC10_Pos) 97 #define RIF_RISC_PERIPH_INDEX_I2C3 (RIF_PERIPH_REG0 | RIFSC_RISC_SECCFGRx_SEC11_Pos) 98 #define RIF_RISC_PERIPH_INDEX_I2C4 (RIF_PERIPH_REG0 | RIFSC_RISC_SECCFGRx_SEC12_Pos) 99 #define RIF_RISC_PERIPH_INDEX_I3C1 (RIF_PERIPH_REG0 | RIFSC_RISC_SECCFGRx_SEC13_Pos) 100 #define RIF_RISC_PERIPH_INDEX_I3C2 (RIF_PERIPH_REG0 | RIFSC_RISC_SECCFGRx_SEC14_Pos) 101 #define RIF_RISC_PERIPH_INDEX_USART1 (RIF_PERIPH_REG0 | RIFSC_RISC_SECCFGRx_SEC15_Pos) 102 #define RIF_RISC_PERIPH_INDEX_USART2 (RIF_PERIPH_REG0 | RIFSC_RISC_SECCFGRx_SEC16_Pos) 103 #define RIF_RISC_PERIPH_INDEX_USART3 (RIF_PERIPH_REG0 | RIFSC_RISC_SECCFGRx_SEC17_Pos) 104 #define RIF_RISC_PERIPH_INDEX_UART4 (RIF_PERIPH_REG0 | RIFSC_RISC_SECCFGRx_SEC18_Pos) 105 #define RIF_RISC_PERIPH_INDEX_UART5 (RIF_PERIPH_REG0 | RIFSC_RISC_SECCFGRx_SEC19_Pos) 106 #define RIF_RISC_PERIPH_INDEX_USART6 (RIF_PERIPH_REG0 | RIFSC_RISC_SECCFGRx_SEC20_Pos) 107 #define RIF_RISC_PERIPH_INDEX_UART7 (RIF_PERIPH_REG0 | RIFSC_RISC_SECCFGRx_SEC21_Pos) 108 #define RIF_RISC_PERIPH_INDEX_UART8 (RIF_PERIPH_REG0 | RIFSC_RISC_SECCFGRx_SEC22_Pos) 109 #define RIF_RISC_PERIPH_INDEX_UART9 (RIF_PERIPH_REG0 | RIFSC_RISC_SECCFGRx_SEC23_Pos) 110 #define RIF_RISC_PERIPH_INDEX_USART10 (RIF_PERIPH_REG0 | RIFSC_RISC_SECCFGRx_SEC24_Pos) 111 #define RIF_RISC_PERIPH_INDEX_LPUART1 (RIF_PERIPH_REG0 | RIFSC_RISC_SECCFGRx_SEC25_Pos) 112 #define RIF_RISC_PERIPH_INDEX_FDCAN1 (RIF_PERIPH_REG0 | RIFSC_RISC_SECCFGRx_SEC26_Pos) 113 #define RIF_RISC_PERIPH_INDEX_TIM1 (RIF_PERIPH_REG0 | RIFSC_RISC_SECCFGRx_SEC27_Pos) 114 #define RIF_RISC_PERIPH_INDEX_TIM2 (RIF_PERIPH_REG0 | RIFSC_RISC_SECCFGRx_SEC28_Pos) 115 #define RIF_RISC_PERIPH_INDEX_TIM3 (RIF_PERIPH_REG0 | RIFSC_RISC_SECCFGRx_SEC29_Pos) 116 #define RIF_RISC_PERIPH_INDEX_TIM4 (RIF_PERIPH_REG0 | RIFSC_RISC_SECCFGRx_SEC30_Pos) 117 #define RIF_RISC_PERIPH_INDEX_TIM5 (RIF_PERIPH_REG0 | RIFSC_RISC_SECCFGRx_SEC31_Pos) 118 #define RIF_RISC_PERIPH_INDEX_TIM6 (RIF_PERIPH_REG1 | RIFSC_RISC_SECCFGRx_SEC0_Pos) 119 #define RIF_RISC_PERIPH_INDEX_TIM7 (RIF_PERIPH_REG1 | RIFSC_RISC_SECCFGRx_SEC1_Pos) 120 #define RIF_RISC_PERIPH_INDEX_TIM8 (RIF_PERIPH_REG1 | RIFSC_RISC_SECCFGRx_SEC2_Pos) 121 #define RIF_RISC_PERIPH_INDEX_TIM9 (RIF_PERIPH_REG1 | RIFSC_RISC_SECCFGRx_SEC3_Pos) 122 #define RIF_RISC_PERIPH_INDEX_TIM10 (RIF_PERIPH_REG1 | RIFSC_RISC_SECCFGRx_SEC4_Pos) 123 #define RIF_RISC_PERIPH_INDEX_TIM11 (RIF_PERIPH_REG1 | RIFSC_RISC_SECCFGRx_SEC5_Pos) 124 #define RIF_RISC_PERIPH_INDEX_TIM12 (RIF_PERIPH_REG1 | RIFSC_RISC_SECCFGRx_SEC6_Pos) 125 #define RIF_RISC_PERIPH_INDEX_TIM13 (RIF_PERIPH_REG1 | RIFSC_RISC_SECCFGRx_SEC7_Pos) 126 #define RIF_RISC_PERIPH_INDEX_TIM14 (RIF_PERIPH_REG1 | RIFSC_RISC_SECCFGRx_SEC8_Pos) 127 #define RIF_RISC_PERIPH_INDEX_TIM15 (RIF_PERIPH_REG1 | RIFSC_RISC_SECCFGRx_SEC9_Pos) 128 #define RIF_RISC_PERIPH_INDEX_TIM16 (RIF_PERIPH_REG1 | RIFSC_RISC_SECCFGRx_SEC10_Pos) 129 #define RIF_RISC_PERIPH_INDEX_TIM17 (RIF_PERIPH_REG1 | RIFSC_RISC_SECCFGRx_SEC11_Pos) 130 #define RIF_RISC_PERIPH_INDEX_TIM18 (RIF_PERIPH_REG1 | RIFSC_RISC_SECCFGRx_SEC12_Pos) 131 #define RIF_RISC_PERIPH_INDEX_GFXTIM (RIF_PERIPH_REG1 | RIFSC_RISC_SECCFGRx_SEC13_Pos) 132 #define RIF_RISC_PERIPH_INDEX_LPTIM1 (RIF_PERIPH_REG1 | RIFSC_RISC_SECCFGRx_SEC14_Pos) 133 #define RIF_RISC_PERIPH_INDEX_LPTIM2 (RIF_PERIPH_REG1 | RIFSC_RISC_SECCFGRx_SEC15_Pos) 134 #define RIF_RISC_PERIPH_INDEX_LPTIM3 (RIF_PERIPH_REG1 | RIFSC_RISC_SECCFGRx_SEC16_Pos) 135 #define RIF_RISC_PERIPH_INDEX_LPTIM4 (RIF_PERIPH_REG1 | RIFSC_RISC_SECCFGRx_SEC17_Pos) 136 #define RIF_RISC_PERIPH_INDEX_LPTIM5 (RIF_PERIPH_REG1 | RIFSC_RISC_SECCFGRx_SEC18_Pos) 137 #define RIF_RISC_PERIPH_INDEX_ADF1 (RIF_PERIPH_REG1 | RIFSC_RISC_SECCFGRx_SEC19_Pos) 138 #define RIF_RISC_PERIPH_INDEX_MDF1 (RIF_PERIPH_REG1 | RIFSC_RISC_SECCFGRx_SEC20_Pos) 139 #define RIF_RISC_PERIPH_INDEX_SDMMC1 (RIF_PERIPH_REG1 | RIFSC_RISC_SECCFGRx_SEC21_Pos) 140 #define RIF_RISC_PERIPH_INDEX_SDMMC2 (RIF_PERIPH_REG1 | RIFSC_RISC_SECCFGRx_SEC22_Pos) 141 #define RIF_RISC_PERIPH_INDEX_MDIOS (RIF_PERIPH_REG1 | RIFSC_RISC_SECCFGRx_SEC23_Pos) 142 #define RIF_RISC_PERIPH_INDEX_OTG1HS (RIF_PERIPH_REG1 | RIFSC_RISC_SECCFGRx_SEC24_Pos) 143 #define RIF_RISC_PERIPH_INDEX_OTG2HS (RIF_PERIPH_REG1 | RIFSC_RISC_SECCFGRx_SEC25_Pos) 144 #define RIF_RISC_PERIPH_INDEX_UCPD1 (RIF_PERIPH_REG1 | RIFSC_RISC_SECCFGRx_SEC26_Pos) 145 #define RIF_RISC_PERIPH_INDEX_ETH1 (RIF_PERIPH_REG1 | RIFSC_RISC_SECCFGRx_SEC28_Pos) 146 #define RIF_RISC_PERIPH_INDEX_SPDIFRX (RIF_PERIPH_REG1 | RIFSC_RISC_SECCFGRx_SEC29_Pos) 147 #define RIF_RISC_PERIPH_INDEX_SYSCFG (RIF_PERIPH_REG1 | RIFSC_RISC_SECCFGRx_SEC30_Pos) 148 #define RIF_RISC_PERIPH_INDEX_ADC12 (RIF_PERIPH_REG2 | RIFSC_RISC_SECCFGRx_SEC0_Pos) 149 #define RIF_RISC_PERIPH_INDEX_VREFBUF (RIF_PERIPH_REG2 | RIFSC_RISC_SECCFGRx_SEC1_Pos) 150 #define RIF_RISC_PERIPH_INDEX_CRC (RIF_PERIPH_REG2 | RIFSC_RISC_SECCFGRx_SEC3_Pos) 151 #define RIF_RISC_PERIPH_INDEX_IWDG (RIF_PERIPH_REG2 | RIFSC_RISC_SECCFGRx_SEC4_Pos) 152 #define RIF_RISC_PERIPH_INDEX_WWDG (RIF_PERIPH_REG2 | RIFSC_RISC_SECCFGRx_SEC5_Pos) 153 #define RIF_RISC_PERIPH_INDEX_RNG (RIF_PERIPH_REG2 | RIFSC_RISC_SECCFGRx_SEC12_Pos) 154 #define RIF_RISC_PERIPH_INDEX_PKA (RIF_PERIPH_REG2 | RIFSC_RISC_SECCFGRx_SEC13_Pos) 155 #if defined(CRYP) 156 #define RIF_RISC_PERIPH_INDEX_SAES (RIF_PERIPH_REG2 | RIFSC_RISC_SECCFGRx_SEC14_Pos) 157 #endif /* defined(CRYP) */ 158 #define RIF_RISC_PERIPH_INDEX_HASH (RIF_PERIPH_REG2 | RIFSC_RISC_SECCFGRx_SEC15_Pos) 159 #if defined(CRYP) 160 #define RIF_RISC_PERIPH_INDEX_CRYP (RIF_PERIPH_REG2 | RIFSC_RISC_SECCFGRx_SEC16_Pos) 161 #define RIF_RISC_PERIPH_INDEX_MCE1 (RIF_PERIPH_REG2 | RIFSC_RISC_SECCFGRx_SEC17_Pos) 162 #define RIF_RISC_PERIPH_INDEX_MCE2 (RIF_PERIPH_REG2 | RIFSC_RISC_SECCFGRx_SEC18_Pos) 163 #define RIF_RISC_PERIPH_INDEX_MCE3 (RIF_PERIPH_REG2 | RIFSC_RISC_SECCFGRx_SEC19_Pos) 164 #define RIF_RISC_PERIPH_INDEX_MCE4 (RIF_PERIPH_REG2 | RIFSC_RISC_SECCFGRx_SEC20_Pos) 165 #endif /* defined(CRYP) */ 166 #define RIF_RISC_PERIPH_INDEX_XSPI1 (RIF_PERIPH_REG2 | RIFSC_RISC_SECCFGRx_SEC22_Pos) 167 #define RIF_RISC_PERIPH_INDEX_XSPI2 (RIF_PERIPH_REG2 | RIFSC_RISC_SECCFGRx_SEC23_Pos) 168 #define RIF_RISC_PERIPH_INDEX_XSPI3 (RIF_PERIPH_REG2 | RIFSC_RISC_SECCFGRx_SEC24_Pos) 169 #define RIF_RISC_PERIPH_INDEX_XSPIM (RIF_PERIPH_REG2 | RIFSC_RISC_SECCFGRx_SEC25_Pos) 170 #define RIF_RISC_PERIPH_INDEX_FMC (RIF_PERIPH_REG2 | RIFSC_RISC_SECCFGRx_SEC26_Pos) 171 #define RIF_RISC_PERIPH_INDEX_CSI (RIF_PERIPH_REG2 | RIFSC_RISC_SECCFGRx_SEC28_Pos) 172 #define RIF_RISC_PERIPH_INDEX_DCMIPP (RIF_PERIPH_REG2 | RIFSC_RISC_SECCFGRx_SEC29_Pos) 173 #define RIF_RISC_PERIPH_INDEX_DCMI (RIF_PERIPH_REG2 | RIFSC_RISC_SECCFGRx_SEC30_Pos) 174 #define RIF_RISC_PERIPH_INDEX_JPEG (RIF_PERIPH_REG3 | RIFSC_RISC_SECCFGRx_SEC0_Pos) 175 #define RIF_RISC_PERIPH_INDEX_VENC (RIF_PERIPH_REG3 | RIFSC_RISC_SECCFGRx_SEC1_Pos) 176 #define RIF_RISC_PERIPH_INDEX_ICACHE (RIF_PERIPH_REG3 | RIFSC_RISC_SECCFGRx_SEC2_Pos) 177 #define RIF_RISC_PERIPH_INDEX_GPU2D (RIF_PERIPH_REG3 | RIFSC_RISC_SECCFGRx_SEC3_Pos) 178 #define RIF_RISC_PERIPH_INDEX_GFXMMU (RIF_PERIPH_REG3 | RIFSC_RISC_SECCFGRx_SEC4_Pos) 179 #define RIF_RISC_PERIPH_INDEX_DMA2D (RIF_PERIPH_REG3 | RIFSC_RISC_SECCFGRx_SEC5_Pos) 180 #define RIF_RISC_PERIPH_INDEX_LTDC (RIF_PERIPH_REG3 | RIFSC_RISC_SECCFGRx_SEC6_Pos) 181 #define RIF_RISC_PERIPH_INDEX_LTDCL1 (RIF_PERIPH_REG3 | RIFSC_RISC_SECCFGRx_SEC7_Pos) 182 #define RIF_RISC_PERIPH_INDEX_LTDCL2 (RIF_PERIPH_REG3 | RIFSC_RISC_SECCFGRx_SEC8_Pos) 183 #if defined(NPU_PRESENT) 184 #define RIF_RISC_PERIPH_INDEX_NPU (RIF_PERIPH_REG3 | RIFSC_RISC_SECCFGRx_SEC10_Pos) 185 #endif /* defined(NPU_PRESENT) */ 186 /** 187 * @} 188 */ 189 190 /** @defgroup RIF_RCC_PERIPHERAL_INDEX RIF RCC Security Control Peripheral index 191 * @{ 192 */ 193 #define RIF_RCC_PERIPH_INDEX_GPDMA1 (RIF_PERIPH_REG4 | RIFSC_RISC_SECCFGRx_SEC2_Pos) 194 #define RIF_RCC_PERIPH_INDEX_HPDMA1 (RIF_PERIPH_REG4 | RIFSC_RISC_SECCFGRx_SEC3_Pos) 195 #define RIF_RCC_PERIPH_INDEX_RTC (RIF_PERIPH_REG4 | RIFSC_RISC_SECCFGRx_SEC5_Pos) 196 #define RIF_RCC_PERIPH_INDEX_AXISRAM1 (RIF_PERIPH_REG4 | RIFSC_RISC_SECCFGRx_SEC12_Pos) 197 #define RIF_RCC_PERIPH_INDEX_AXISRAM2 (RIF_PERIPH_REG4 | RIFSC_RISC_SECCFGRx_SEC13_Pos) 198 #define RIF_RCC_PERIPH_INDEX_FLEXRAM (RIF_PERIPH_REG4 | RIFSC_RISC_SECCFGRx_SEC17_Pos) 199 #define RIF_RCC_PERIPH_INDEX_CACHEAXIRAM (RIF_PERIPH_REG4 | RIFSC_RISC_SECCFGRx_SEC18_Pos) 200 #define RIF_RCC_PERIPH_INDEX_VENCRAM (RIF_PERIPH_REG4 | RIFSC_RISC_SECCFGRx_SEC19_Pos) 201 #if defined(NPU_PRESENT) 202 #define RIF_RCC_PERIPH_INDEX_CACHECONFIG (RIF_PERIPH_REG4 | RIFSC_RISC_SECCFGRx_SEC25_Pos) 203 #endif /* defined(NPU_PRESENT) */ 204 #define RIF_RCC_PERIPH_INDEX_AHBRAM1 (RIF_PERIPH_REG4 | RIFSC_RISC_SECCFGRx_SEC27_Pos) 205 #define RIF_RCC_PERIPH_INDEX_AHBRAM2 (RIF_PERIPH_REG4 | RIFSC_RISC_SECCFGRx_SEC28_Pos) 206 #define RIF_RCC_PERIPH_INDEX_BKPRAM (RIF_PERIPH_REG4 | RIFSC_RISC_SECCFGRx_SEC29_Pos) 207 #define RIF_RCC_PERIPH_INDEX_GPIOA (RIF_PERIPH_REG4 | RIFSC_RISC_SECCFGRx_SEC31_Pos) 208 #define RIF_RCC_PERIPH_INDEX_GPIOB (RIF_PERIPH_REG5 | RIFSC_RISC_SECCFGRx_SEC0_Pos) 209 #define RIF_RCC_PERIPH_INDEX_GPIOC (RIF_PERIPH_REG5 | RIFSC_RISC_SECCFGRx_SEC1_Pos) 210 #define RIF_RCC_PERIPH_INDEX_GPIOD (RIF_PERIPH_REG5 | RIFSC_RISC_SECCFGRx_SEC2_Pos) 211 #define RIF_RCC_PERIPH_INDEX_GPIOE (RIF_PERIPH_REG5 | RIFSC_RISC_SECCFGRx_SEC3_Pos) 212 #define RIF_RCC_PERIPH_INDEX_GPIOF (RIF_PERIPH_REG5 | RIFSC_RISC_SECCFGRx_SEC4_Pos) 213 #define RIF_RCC_PERIPH_INDEX_GPIOG (RIF_PERIPH_REG5 | RIFSC_RISC_SECCFGRx_SEC5_Pos) 214 #define RIF_RCC_PERIPH_INDEX_GPIOH (RIF_PERIPH_REG5 | RIFSC_RISC_SECCFGRx_SEC6_Pos) 215 #define RIF_RCC_PERIPH_INDEX_GPION (RIF_PERIPH_REG5 | RIFSC_RISC_SECCFGRx_SEC8_Pos) 216 #define RIF_RCC_PERIPH_INDEX_GPIOO (RIF_PERIPH_REG5 | RIFSC_RISC_SECCFGRx_SEC9_Pos) 217 #define RIF_RCC_PERIPH_INDEX_GPIOP (RIF_PERIPH_REG5 | RIFSC_RISC_SECCFGRx_SEC10_Pos) 218 #define RIF_RCC_PERIPH_INDEX_GPIOQ (RIF_PERIPH_REG5 | RIFSC_RISC_SECCFGRx_SEC11_Pos) 219 #define RIF_RCC_PERIPH_INDEX_DTS (RIF_PERIPH_REG5 | RIFSC_RISC_SECCFGRx_SEC13_Pos) 220 #define RIF_RCC_PERIPH_INDEX_MCO1 (RIF_PERIPH_REG5 | RIFSC_RISC_SECCFGRx_SEC14_Pos) 221 #define RIF_RCC_PERIPH_INDEX_MCO2 (RIF_PERIPH_REG5 | RIFSC_RISC_SECCFGRx_SEC15_Pos) 222 #if defined(NPU_PRESENT) 223 #define RIF_RCC_PERIPH_INDEX_NPURAM0 (RIF_PERIPH_REG5 | RIFSC_RISC_SECCFGRx_SEC17_Pos) 224 #define RIF_RCC_PERIPH_INDEX_NPURAM1 (RIF_PERIPH_REG5 | RIFSC_RISC_SECCFGRx_SEC18_Pos) 225 #define RIF_RCC_PERIPH_INDEX_NPURAM2 (RIF_PERIPH_REG5 | RIFSC_RISC_SECCFGRx_SEC19_Pos) 226 #define RIF_RCC_PERIPH_INDEX_NPURAM3 (RIF_PERIPH_REG5 | RIFSC_RISC_SECCFGRx_SEC20_Pos) 227 #endif /* defined(NPU_PRESENT) */ 228 #define RIF_RCC_PERIPH_INDEX_XSPIPHYCOMP (RIF_PERIPH_REG5 | RIFSC_RISC_SECCFGRx_SEC22_Pos) 229 #define RIF_RCC_PERIPH_INDEX_XSPIPHY1 (RIF_PERIPH_REG5 | RIFSC_RISC_SECCFGRx_SEC23_Pos) 230 #define RIF_RCC_PERIPH_INDEX_XSPIPHY2 (RIF_PERIPH_REG5 | RIFSC_RISC_SECCFGRx_SEC24_Pos) 231 #define RIF_RCC_PERIPH_INDEX_HDP (RIF_PERIPH_REG5 | RIFSC_RISC_SECCFGRx_SEC27_Pos) 232 #define RIF_RCC_PERIPH_INDEX_RAMCFG (RIF_PERIPH_REG5 | RIFSC_RISC_SECCFGRx_SEC30_Pos) 233 /** 234 * @} 235 */ 236 237 /** @defgroup RIF_AWARE_PERIPHERAL_INDEX RIF-aware Peripheral index 238 * @{ 239 */ 240 #define RIF_AWARE_PERIPH_INDEX_CM55 (RIF_PERIPH_REG4 | IAC_IERx_IAIE0_Pos) 241 #define RIF_AWARE_PERIPH_INDEX_EXTI (RIF_PERIPH_REG4 | IAC_IERx_IAIE1_Pos) 242 #define RIF_AWARE_PERIPH_INDEX_GPDMA1 RIF_RCC_PERIPH_INDEX_GPDMA1 243 #define RIF_AWARE_PERIPH_INDEX_HPDMA1 RIF_RCC_PERIPH_INDEX_HPDMA1 244 #define RIF_AWARE_PERIPH_INDEX_RTC RIF_RCC_PERIPH_INDEX_RTC 245 #define RIF_AWARE_PERIPH_INDEX_TAMP (RIF_PERIPH_REG4 | IAC_IERx_IAIE6_Pos) 246 #define RIF_AWARE_PERIPH_INDEX_BSEC (RIF_PERIPH_REG4 | IAC_IERx_IAIE7_Pos) 247 #define RIF_AWARE_PERIPH_INDEX_RCC (RIF_PERIPH_REG4 | IAC_IERx_IAIE8_Pos) 248 #define RIF_AWARE_PERIPH_INDEX_PWR (RIF_PERIPH_REG4 | IAC_IERx_IAIE9_Pos) 249 #define RIF_AWARE_PERIPH_INDEX_IAC (RIF_PERIPH_REG4 | IAC_IERx_IAIE10_Pos) 250 #define RIF_AWARE_PERIPH_INDEX_RISAF1 (RIF_PERIPH_REG4 | IAC_IERx_IAIE11_Pos) 251 #define RIF_AWARE_PERIPH_INDEX_RISAF2 RIF_RCC_PERIPH_INDEX_AXISRAM1 252 #define RIF_AWARE_PERIPH_INDEX_RISAF3 RIF_RCC_PERIPH_INDEX_AXISRAM2 253 #if defined(NPU_PRESENT) 254 #define RIF_AWARE_PERIPH_INDEX_RISAF4 (RIF_PERIPH_REG4 | IAC_IERx_IAIE14_Pos) 255 #define RIF_AWARE_PERIPH_INDEX_RISAF5 (RIF_PERIPH_REG4 | IAC_IERx_IAIE15_Pos) 256 #endif /* if defined(NPU_PRESENT) */ 257 #define RIF_AWARE_PERIPH_INDEX_RISAF6 (RIF_PERIPH_REG4 | IAC_IERx_IAIE16_Pos) 258 #define RIF_AWARE_PERIPH_INDEX_RISAF7 RIF_RCC_PERIPH_INDEX_FLEXRAM 259 #define RIF_AWARE_PERIPH_INDEX_RISAF8 RIF_RCC_PERIPH_INDEX_CACHEAXIRAM 260 #define RIF_AWARE_PERIPH_INDEX_RISAF9 RIF_RCC_PERIPH_INDEX_VENCRAM 261 #define RIF_AWARE_PERIPH_INDEX_RISAF11 (RIF_PERIPH_REG4 | IAC_IERx_IAIE21_Pos) 262 #define RIF_AWARE_PERIPH_INDEX_RISAF12 (RIF_PERIPH_REG4 | IAC_IERx_IAIE22_Pos) 263 #define RIF_AWARE_PERIPH_INDEX_RISAF13 (RIF_PERIPH_REG4 | IAC_IERx_IAIE23_Pos) 264 #define RIF_AWARE_PERIPH_INDEX_RISAF14 (RIF_PERIPH_REG4 | IAC_IERx_IAIE24_Pos) 265 #if defined(NPU_PRESENT) 266 #define RIF_AWARE_PERIPH_INDEX_RISAF15 RIF_RCC_PERIPH_INDEX_CACHECONFIG 267 #endif /* if defined(NPU_PRESENT) */ 268 #define RIF_AWARE_PERIPH_INDEX_RISAF21 RIF_RCC_PERIPH_INDEX_AHBRAM1 269 #define RIF_AWARE_PERIPH_INDEX_RISAF22 RIF_RCC_PERIPH_INDEX_AHBRAM2 270 #define RIF_AWARE_PERIPH_INDEX_RISAF23 RIF_RCC_PERIPH_INDEX_BKPRAM 271 #define RIF_AWARE_PERIPH_INDEX_RIFSC (RIF_PERIPH_REG4 | IAC_IERx_IAIE30_Pos) 272 /** 273 * @} 274 */ 275 /** 276 * @} 277 */ 278 279 /** @defgroup RIF_SEC_PRIV RIF Secure Privileged attributes definitions 280 * @{ 281 */ 282 #define RIF_ATTRIBUTE_NSEC 0x00000000U 283 #define RIF_ATTRIBUTE_SEC 0x00000001U 284 #define RIF_ATTRIBUTE_NPRIV 0x00000000U 285 #define RIF_ATTRIBUTE_PRIV 0x00000002U 286 /** 287 * @} 288 */ 289 290 /** @defgroup RIF_ACCESS_TYPE RIF Access type definitions 291 * @{ 292 */ 293 #define RIF_ACCTYPE_READ_FETCH 0U 294 #define RIF_ACCTYPE_WRITE 1U 295 /** 296 * @} 297 */ 298 299 /** @defgroup RIF_LOCK_STATE RIF Lock states definitions 300 * @{ 301 */ 302 #define RIF_LOCK_DISABLE 0U 303 #define RIF_LOCK_ENABLE RIFSC_RIMC_CR_GLOCK 304 /** 305 * @} 306 */ 307 308 /** 309 * @} 310 */ 311 312 313 /** @defgroup RIF_EXPORTED_CONSTANTS_RISAF RIF Exported Constants - RISAF 314 * @{ 315 */ 316 317 /** @defgroup RIF_RISAF_REGION RISAF Base region definitions 318 * @{ 319 */ 320 #define RISAF_REGION_1 0U 321 #define RISAF_REGION_2 1U 322 #define RISAF_REGION_3 2U 323 #define RISAF_REGION_4 3U 324 #define RISAF_REGION_5 4U 325 #define RISAF_REGION_6 5U 326 #define RISAF_REGION_7 6U 327 #define RISAF_REGION_8 7U 328 #define RISAF_REGION_9 8U 329 #define RISAF_REGION_10 9U 330 #define RISAF_REGION_11 10U 331 #define RISAF_REGION_12 11U 332 #define RISAF_REGION_13 12U 333 #define RISAF_REGION_14 13U 334 #define RISAF_REGION_15 14U 335 /** 336 * @} 337 */ 338 339 /** @defgroup RIF_RISAF_GRANULARITY RISAF granularity definitions 340 * @{ 341 */ 342 #if !defined(NPU_PRESENT) 343 #define RISAF1_GRANULARITY 0x1000U 344 #define RISAF2_GRANULARITY 0x1000U 345 #define RISAF3_GRANULARITY 0x1000U 346 #define RISAF6_GRANULARITY 0x1000U 347 #define RISAF7_GRANULARITY 0x1000U 348 #define RISAF8_GRANULARITY 0x1000U 349 #define RISAF9_GRANULARITY 0x1000U 350 #define RISAF11_GRANULARITY 0x1000U 351 #define RISAF12_GRANULARITY 0x1000U 352 #define RISAF13_GRANULARITY 0x1000U 353 #define RISAF14_GRANULARITY 0x1000U 354 #define RISAF21_GRANULARITY 0x0200U 355 #define RISAF22_GRANULARITY 0x0200U 356 #define RISAF23_GRANULARITY 0x0200U 357 #else 358 #define RISAF1_GRANULARITY 0x1000U 359 #define RISAF2_GRANULARITY 0x1000U 360 #define RISAF3_GRANULARITY 0x1000U 361 #define RISAF4_GRANULARITY 0x1000U 362 #define RISAF5_GRANULARITY 0x1000U 363 #define RISAF6_GRANULARITY 0x1000U 364 #define RISAF7_GRANULARITY 0x1000U 365 #define RISAF8_GRANULARITY 0x1000U 366 #define RISAF9_GRANULARITY 0x1000U 367 #define RISAF11_GRANULARITY 0x1000U 368 #define RISAF12_GRANULARITY 0x1000U 369 #define RISAF13_GRANULARITY 0x1000U 370 #define RISAF14_GRANULARITY 0x1000U 371 #define RISAF15_GRANULARITY 0x0004U 372 #define RISAF21_GRANULARITY 0x0200U 373 #define RISAF22_GRANULARITY 0x0200U 374 #define RISAF23_GRANULARITY 0x0200U 375 #endif /* !defined(NPU_PRESENT) */ 376 /** 377 * @} 378 */ 379 380 /** @defgroup RIF_RISAF_ADDSPACE RISAF address space sizes definitions 381 * @{ 382 */ 383 #if !defined(NPU_PRESENT) 384 #define RISAF1_LIMIT_ADDRESS_SPACE_SIZE 0x3FFFFFFFU 385 #define RISAF2_LIMIT_ADDRESS_SPACE_SIZE 0x000FFFFFU 386 #define RISAF3_LIMIT_ADDRESS_SPACE_SIZE 0x000FFFFFU 387 #define RISAF6_LIMIT_ADDRESS_SPACE_SIZE 0xFFFFFFFFU 388 #define RISAF7_LIMIT_ADDRESS_SPACE_SIZE 0x0007FFFFU 389 #define RISAF8_LIMIT_ADDRESS_SPACE_SIZE 0x0003FFFFU 390 #define RISAF9_LIMIT_ADDRESS_SPACE_SIZE 0x0001FFFFU 391 #define RISAF11_LIMIT_ADDRESS_SPACE_SIZE 0x0FFFFFFFU 392 #define RISAF12_LIMIT_ADDRESS_SPACE_SIZE 0x0FFFFFFFU 393 #define RISAF13_LIMIT_ADDRESS_SPACE_SIZE 0x0FFFFFFFU 394 #define RISAF14_LIMIT_ADDRESS_SPACE_SIZE 0x0FFFFFFFU 395 #define RISAF21_LIMIT_ADDRESS_SPACE_SIZE 0x00001FFFU 396 #define RISAF22_LIMIT_ADDRESS_SPACE_SIZE 0x00001FFFU 397 #define RISAF23_LIMIT_ADDRESS_SPACE_SIZE 0x00000FFFU 398 #else 399 #define RISAF1_LIMIT_ADDRESS_SPACE_SIZE 0x3FFFFFFFU 400 #define RISAF2_LIMIT_ADDRESS_SPACE_SIZE 0x000FFFFFU 401 #define RISAF3_LIMIT_ADDRESS_SPACE_SIZE 0x000FFFFFU 402 #define RISAF4_LIMIT_ADDRESS_SPACE_SIZE 0xFFFFFFFFU 403 #define RISAF5_LIMIT_ADDRESS_SPACE_SIZE 0xFFFFFFFFU 404 #define RISAF6_LIMIT_ADDRESS_SPACE_SIZE 0xFFFFFFFFU 405 #define RISAF7_LIMIT_ADDRESS_SPACE_SIZE 0x0007FFFFU 406 #define RISAF8_LIMIT_ADDRESS_SPACE_SIZE 0x0003FFFFU 407 #define RISAF9_LIMIT_ADDRESS_SPACE_SIZE 0x0001FFFFU 408 #define RISAF11_LIMIT_ADDRESS_SPACE_SIZE 0x0FFFFFFFU 409 #define RISAF12_LIMIT_ADDRESS_SPACE_SIZE 0x0FFFFFFFU 410 #define RISAF13_LIMIT_ADDRESS_SPACE_SIZE 0x0FFFFFFFU 411 #define RISAF14_LIMIT_ADDRESS_SPACE_SIZE 0x0FFFFFFFU 412 #define RISAF15_LIMIT_ADDRESS_SPACE_SIZE 0x00000FFFU 413 #define RISAF21_LIMIT_ADDRESS_SPACE_SIZE 0x00001FFFU 414 #define RISAF22_LIMIT_ADDRESS_SPACE_SIZE 0x00001FFFU 415 #define RISAF23_LIMIT_ADDRESS_SPACE_SIZE 0x00000FFFU 416 #endif /* !defined(NPU_PRESENT) */ 417 /** 418 * @} 419 */ 420 421 /** @defgroup RIF_RISAF_SUBREGION RIF subregion definitions 422 * @{ 423 */ 424 #define RISAF_SUBREGION_A 0U 425 #define RISAF_SUBREGION_B 1U 426 /** 427 * @} 428 */ 429 430 /** @defgroup RIF_RISAF_FILTERING_MODE RISAF Filtering mode definitions 431 * @{ 432 */ 433 #define RISAF_FILTER_DISABLE 0U 434 #define RISAF_FILTER_ENABLE RISAF_REGx_CFGR_BREN 435 /** 436 * @} 437 */ 438 439 /** @defgroup RIF_RISAF_DELEGATION_MODE RISAF Delegation mode definitions 440 * @{ 441 */ 442 #define RISAF_DELEGATION_DISABLE 0U 443 #define RISAF_DELEGATION_ENABLE RISAF_REGx_zNESTR_DCEN 444 /** 445 * @} 446 */ 447 448 /** @defgroup RIF_RISAF_READ_WRITE RISAF Read/Write definitions 449 * @{ 450 */ 451 #define RISAF_READ_DISABLE 0U 452 #define RISAF_READ_ENABLE RISAF_REGx_zCFGR_RDEN 453 #define RISAF_WRITE_DISABLE 0U 454 #define RISAF_WRITE_ENABLE RISAF_REGx_zCFGR_WREN 455 /** 456 * @} 457 */ 458 459 /** @defgroup RIF_RISAF_ILLEGAL_ACCESS RISAF Illegal Access definitions 460 * @{ 461 */ 462 #define RISAF_ILLEGAL_ACCESS_NONE 0U 463 #define RISAF_ILLEGAL_CONFIGURATION_ACCESS RISAF_IASR_CAEF 464 #define RISAF_ILLEGAL_ACCESS RISAF_IASR_IAEF 465 /** 466 * @} 467 */ 468 469 /** 470 * @} 471 */ 472 473 /* Exported types ------------------------------------------------------------*/ 474 /** @defgroup RIF_Exported_Types RIF Exported Types 475 * @{ 476 */ 477 478 /** 479 * @brief RIFSC Master CID attributes configuration structure 480 */ 481 typedef struct 482 { 483 uint32_t MasterCID; /*!< One of @ref RIF_COMPARTMENT_ID */ 484 uint32_t SecPriv; /*!< A combination of @ref RIF_SEC_PRIV */ 485 } RIMC_MasterConfig_t; 486 487 /** 488 * @brief RISAF base region configuration structure 489 */ 490 typedef struct 491 { 492 uint32_t Filtering; /*!< One of @ref RIF_RISAF_FILTERING_MODE */ 493 uint32_t Secure; /*!< One of @ref RIF_SEC_PRIV */ 494 uint32_t PrivWhitelist; /*!< A combination of @ref RIF_COMPARTMENT_ID */ 495 uint32_t ReadWhitelist; /*!< A combination of @ref RIF_COMPARTMENT_ID */ 496 uint32_t WriteWhitelist; /*!< A combination of @ref RIF_COMPARTMENT_ID */ 497 uint32_t StartAddress; /*!< Base region start, address offset to the base address of the protected address space */ 498 uint32_t EndAddress; /*!< Base region end, address offset to the base address of the protected address space */ 499 } RISAF_BaseRegionConfig_t; 500 501 /** 502 * @brief RISAF subregion configuration structure 503 */ 504 typedef struct 505 { 506 uint32_t Filtering; /*!< One of @ref RIF_RISAF_FILTERING_MODE */ 507 uint32_t CID; /*!< One of @ref RIF_COMPARTMENT_ID */ 508 uint32_t SecPriv; /*!< A combination of @ref RIF_SEC_PRIV */ 509 uint32_t ReadWrite; /*!< A combination of @ref RIF_RISAF_READ_WRITE */ 510 uint32_t Lock; /*!< One of @ref RIF_LOCK_STATE */ 511 uint32_t StartAddress; /*!< Subregion start, address offset to the base address of the protected address space */ 512 uint32_t EndAddress; /*!< Subregion end, address offset to the base address of the protected address space */ 513 } RISAF_SubRegionConfig_t; 514 515 /** 516 * @brief RISAF delegation structure 517 */ 518 typedef struct 519 { 520 uint32_t Delegation; /*!< Enable or Disable */ 521 uint32_t DelegatedCID; /*!< One of @ref RIF_COMPARTMENT_ID */ 522 } RISAF_DelegationConfig_t; 523 524 /** 525 * @brief RISAF illegal access detection structure 526 */ 527 /** 528 * @brief RISAF illegal access detection data structure 529 */ 530 typedef struct 531 { 532 uint32_t CID; /*!< One of @ref RIF_COMPARTMENT_ID */ 533 uint32_t SecPriv; /*!< A combination of @ref RIF_SEC_PRIV */ 534 uint32_t AccessType; /*!< One of @ref RIF_ACCESS_TYPE */ 535 uint32_t Address; 536 } RISAF_IllegalAccessData_t; 537 538 typedef struct 539 { 540 uint32_t ErrorType; /*!< One of @ref RIF_RISAF_ILLEGAL_ACCESS */ 541 RISAF_IllegalAccessData_t Data; 542 } RISAF_IllegalAccess_t; 543 544 /** 545 * @} 546 */ 547 548 /* Private constants ---------------------------------------------------------*/ 549 /** @defgroup RCC_Private_Constants RCC Private Constants 550 * @{ 551 */ 552 553 /** @defgroup RIF_REG_INDEX RIF register index definition 554 * @{ 555 */ 556 /* Composition definition for Peripheral identifier parameter (PeriphId) used in 557 * RIF RISC and IAC related functions. 558 * Bitmap Definition 559 * bits[31:28] Field "register". Define the register index a peripheral belongs to. 560 * bits[4:0] Field "bit position". Define the bit position within the 561 * register dedicated to the peripheral, value from 0 to 31. 562 */ 563 #define RIF_PERIPH_REG_SHIFT 28U 564 #define RIF_PERIPH_REG 0xF0000000U 565 #define RIF_PERIPH_REG0 0x00000000U 566 #define RIF_PERIPH_REG1 0x10000000U 567 #define RIF_PERIPH_REG2 0x20000000U 568 #define RIF_PERIPH_REG3 0x30000000U 569 #define RIF_PERIPH_REG4 0x40000000U 570 #define RIF_PERIPH_REG5 0x50000000U 571 #define RIF_PERIPH_BIT_POSITION 0x0000001FU 572 /** 573 * @} 574 */ 575 576 /** @defgroup RIF_MASK RIF register masks 577 * @{ 578 */ 579 #define RIF_CID_MASK 0x000000FFU 580 #define RIF_ATTRIBUTE_MASK 0x00000003U 581 #define RISAF_READ_WRITE_MASK (RISAF_READ_ENABLE | RISAF_WRITE_ENABLE) 582 /** 583 * @} 584 */ 585 586 /** 587 * @} 588 */ 589 590 /* Private macros ------------------------------------------------------------*/ 591 /** @defgroup RIF_Private_Macros_Common RIF Private Macros - Common 592 * @{ 593 */ 594 #define IS_RIF_CID(__CID__) (((uint32_t)(__CID__) & ~RIF_CID_MASK) == 0x00U) 595 596 #define IS_RIF_SINGLE_CID(__CID__) (((__CID__) == RIF_CID_0) || \ 597 ((__CID__) == RIF_CID_1) || \ 598 ((__CID__) == RIF_CID_2) || \ 599 ((__CID__) == RIF_CID_3) || \ 600 ((__CID__) == RIF_CID_4) || \ 601 ((__CID__) == RIF_CID_5) || \ 602 ((__CID__) == RIF_CID_6) || \ 603 ((__CID__) == RIF_CID_7)) 604 605 #define IS_RIF_MASTER_CID(__CID__) (((uint32_t)(__CID__) != RIF_CID_7) && \ 606 (((uint32_t)(__CID__) & ~RIF_CID_MASK) == 0x00U)) 607 608 609 #if defined(NPU_PRESENT) 610 #define IS_RIF_MASTER_INDEX(__INDEX__) (((__INDEX__) == RIF_MASTER_INDEX_ETR) || \ 611 ((__INDEX__) == RIF_MASTER_INDEX_NPU) || \ 612 ((__INDEX__) == RIF_MASTER_INDEX_SDMMC1) || \ 613 ((__INDEX__) == RIF_MASTER_INDEX_SDMMC2) || \ 614 ((__INDEX__) == RIF_MASTER_INDEX_OTG1) || \ 615 ((__INDEX__) == RIF_MASTER_INDEX_OTG2) || \ 616 ((__INDEX__) == RIF_MASTER_INDEX_ETH1) || \ 617 ((__INDEX__) == RIF_MASTER_INDEX_GPU2D) || \ 618 ((__INDEX__) == RIF_MASTER_INDEX_DMA2D) || \ 619 ((__INDEX__) == RIF_MASTER_INDEX_DCMIPP) || \ 620 ((__INDEX__) == RIF_MASTER_INDEX_LTDC1) || \ 621 ((__INDEX__) == RIF_MASTER_INDEX_LTDC2) || \ 622 ((__INDEX__) == RIF_MASTER_INDEX_VENC)) 623 #else 624 #define IS_RIF_MASTER_INDEX(__INDEX__) (((__INDEX__) == RIF_MASTER_INDEX_ETR) || \ 625 ((__INDEX__) == RIF_MASTER_INDEX_SDMMC1) || \ 626 ((__INDEX__) == RIF_MASTER_INDEX_SDMMC2) || \ 627 ((__INDEX__) == RIF_MASTER_INDEX_OTG1) || \ 628 ((__INDEX__) == RIF_MASTER_INDEX_OTG2) || \ 629 ((__INDEX__) == RIF_MASTER_INDEX_ETH1) || \ 630 ((__INDEX__) == RIF_MASTER_INDEX_GPU2D) || \ 631 ((__INDEX__) == RIF_MASTER_INDEX_DMA2D) || \ 632 ((__INDEX__) == RIF_MASTER_INDEX_DCMIPP) || \ 633 ((__INDEX__) == RIF_MASTER_INDEX_LTDC1) || \ 634 ((__INDEX__) == RIF_MASTER_INDEX_LTDC2) || \ 635 ((__INDEX__) == RIF_MASTER_INDEX_VENC)) 636 #endif /* defined(NPU_PRESENT) */ 637 638 #if !defined(NPU_PRESENT) && !defined(CRYP) 639 #define IS_RIF_RISC_PERIPH_INDEX(__INDEX__) (((__INDEX__) == RIF_RISC_PERIPH_INDEX_SPI1) || \ 640 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_SPI2) || \ 641 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_SPI3) || \ 642 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_SPI4) || \ 643 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_SPI5) || \ 644 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_SPI6) || \ 645 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_SAI1) || \ 646 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_SAI2) || \ 647 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_I2C1) || \ 648 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_I2C2) || \ 649 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_I2C3) || \ 650 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_I2C4) || \ 651 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_I3C1) || \ 652 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_I3C2) || \ 653 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_USART1) || \ 654 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_USART2) || \ 655 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_USART3) || \ 656 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_UART4) || \ 657 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_UART5) || \ 658 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_USART6) || \ 659 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_UART7) || \ 660 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_UART8) || \ 661 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_UART9) || \ 662 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_USART10) || \ 663 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_LPUART1) || \ 664 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_FDCAN1) || \ 665 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_TIM1) || \ 666 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_TIM2) || \ 667 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_TIM3) || \ 668 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_TIM4) || \ 669 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_TIM5) || \ 670 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_TIM6) || \ 671 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_TIM7) || \ 672 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_TIM8) || \ 673 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_TIM9) || \ 674 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_TIM10) || \ 675 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_TIM11) || \ 676 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_TIM12) || \ 677 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_TIM13) || \ 678 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_TIM14) || \ 679 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_TIM15) || \ 680 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_TIM16) || \ 681 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_TIM17) || \ 682 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_TIM18) || \ 683 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_GFXTIM) || \ 684 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_LPTIM1) || \ 685 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_LPTIM2) || \ 686 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_LPTIM3) || \ 687 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_LPTIM4) || \ 688 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_LPTIM5) || \ 689 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_ADF1) || \ 690 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_MDF1) || \ 691 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_SDMMC1) || \ 692 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_SDMMC2) || \ 693 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_MDIOS) || \ 694 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_OTG1HS) || \ 695 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_OTG2HS) || \ 696 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_UCPD1) || \ 697 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_ETH1) || \ 698 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_SPDIFRX) || \ 699 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_SYSCFG) || \ 700 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_ADC12) || \ 701 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_VREFBUF) || \ 702 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_CRC) || \ 703 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_IWDG) || \ 704 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_WWDG) || \ 705 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_RNG) || \ 706 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_PKA) || \ 707 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_HASH) || \ 708 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_XSPI1) || \ 709 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_XSPI2) || \ 710 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_XSPI3) || \ 711 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_XSPIM) || \ 712 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_FMC) || \ 713 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_CSI) || \ 714 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_DCMIPP) || \ 715 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_DCMI) || \ 716 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_JPEG) || \ 717 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_VENC) || \ 718 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_ICACHE) || \ 719 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_GPU2D) || \ 720 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_GFXMMU) || \ 721 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_DMA2D) || \ 722 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_LTDC) || \ 723 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_LTDCL1) || \ 724 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_LTDCL2)) 725 726 #define IS_RIF_RCC_PERIPH_INDEX(__INDEX__) (((__INDEX__) == RIF_RCC_PERIPH_INDEX_GPDMA1) || \ 727 ((__INDEX__) == RIF_RCC_PERIPH_INDEX_HPDMA1) || \ 728 ((__INDEX__) == RIF_RCC_PERIPH_INDEX_RTC) || \ 729 ((__INDEX__) == RIF_RCC_PERIPH_INDEX_AXISRAM1) || \ 730 ((__INDEX__) == RIF_RCC_PERIPH_INDEX_AXISRAM2) || \ 731 ((__INDEX__) == RIF_RCC_PERIPH_INDEX_FLEXRAM) || \ 732 ((__INDEX__) == RIF_RCC_PERIPH_INDEX_CACHEAXIRAM) || \ 733 ((__INDEX__) == RIF_RCC_PERIPH_INDEX_VENCRAM) || \ 734 ((__INDEX__) == RIF_RCC_PERIPH_INDEX_AHBRAM1) || \ 735 ((__INDEX__) == RIF_RCC_PERIPH_INDEX_AHBRAM2) || \ 736 ((__INDEX__) == RIF_RCC_PERIPH_INDEX_BKPRAM) || \ 737 ((__INDEX__) == RIF_RCC_PERIPH_INDEX_GPIOA) || \ 738 ((__INDEX__) == RIF_RCC_PERIPH_INDEX_GPIOB) || \ 739 ((__INDEX__) == RIF_RCC_PERIPH_INDEX_GPIOC) || \ 740 ((__INDEX__) == RIF_RCC_PERIPH_INDEX_GPIOD) || \ 741 ((__INDEX__) == RIF_RCC_PERIPH_INDEX_GPIOE) || \ 742 ((__INDEX__) == RIF_RCC_PERIPH_INDEX_GPIOF) || \ 743 ((__INDEX__) == RIF_RCC_PERIPH_INDEX_GPIOG) || \ 744 ((__INDEX__) == RIF_RCC_PERIPH_INDEX_GPIOH) || \ 745 ((__INDEX__) == RIF_RCC_PERIPH_INDEX_GPION) || \ 746 ((__INDEX__) == RIF_RCC_PERIPH_INDEX_GPIOO) || \ 747 ((__INDEX__) == RIF_RCC_PERIPH_INDEX_GPIOP) || \ 748 ((__INDEX__) == RIF_RCC_PERIPH_INDEX_GPIOQ) || \ 749 ((__INDEX__) == RIF_RCC_PERIPH_INDEX_DTS) || \ 750 ((__INDEX__) == RIF_RCC_PERIPH_INDEX_MCO1) || \ 751 ((__INDEX__) == RIF_RCC_PERIPH_INDEX_MCO2) || \ 752 ((__INDEX__) == RIF_RCC_PERIPH_INDEX_XSPIPHYCOMP) || \ 753 ((__INDEX__) == RIF_RCC_PERIPH_INDEX_XSPIPHY1) || \ 754 ((__INDEX__) == RIF_RCC_PERIPH_INDEX_XSPIPHY2) || \ 755 ((__INDEX__) == RIF_RCC_PERIPH_INDEX_HDP) || \ 756 ((__INDEX__) == RIF_RCC_PERIPH_INDEX_RAMCFG)) 757 758 #define IS_RIF_AWARE_PERIPH_INDEX(__INDEX__) (((__INDEX__) == RIF_AWARE_PERIPH_INDEX_CM55) || \ 759 ((__INDEX__) == RIF_AWARE_PERIPH_INDEX_EXTI) || \ 760 ((__INDEX__) == RIF_AWARE_PERIPH_INDEX_GPDMA1) || \ 761 ((__INDEX__) == RIF_AWARE_PERIPH_INDEX_HPDMA1) || \ 762 ((__INDEX__) == RIF_AWARE_PERIPH_INDEX_RTC) || \ 763 ((__INDEX__) == RIF_AWARE_PERIPH_INDEX_TAMP) || \ 764 ((__INDEX__) == RIF_AWARE_PERIPH_INDEX_BSEC) || \ 765 ((__INDEX__) == RIF_AWARE_PERIPH_INDEX_RCC) || \ 766 ((__INDEX__) == RIF_AWARE_PERIPH_INDEX_PWR) || \ 767 ((__INDEX__) == RIF_AWARE_PERIPH_INDEX_IAC) || \ 768 ((__INDEX__) == RIF_AWARE_PERIPH_INDEX_RISAF1) || \ 769 ((__INDEX__) == RIF_AWARE_PERIPH_INDEX_RISAF2) || \ 770 ((__INDEX__) == RIF_AWARE_PERIPH_INDEX_RISAF3) || \ 771 ((__INDEX__) == RIF_AWARE_PERIPH_INDEX_RISAF6) || \ 772 ((__INDEX__) == RIF_AWARE_PERIPH_INDEX_RISAF7) || \ 773 ((__INDEX__) == RIF_AWARE_PERIPH_INDEX_RISAF8) || \ 774 ((__INDEX__) == RIF_AWARE_PERIPH_INDEX_RISAF9) || \ 775 ((__INDEX__) == RIF_AWARE_PERIPH_INDEX_RISAF11) || \ 776 ((__INDEX__) == RIF_AWARE_PERIPH_INDEX_RISAF12) || \ 777 ((__INDEX__) == RIF_AWARE_PERIPH_INDEX_RISAF13) || \ 778 ((__INDEX__) == RIF_AWARE_PERIPH_INDEX_RISAF14) || \ 779 ((__INDEX__) == RIF_AWARE_PERIPH_INDEX_RISAF21) || \ 780 ((__INDEX__) == RIF_AWARE_PERIPH_INDEX_RISAF22) || \ 781 ((__INDEX__) == RIF_AWARE_PERIPH_INDEX_RISAF23) || \ 782 ((__INDEX__) == RIF_AWARE_PERIPH_INDEX_RIFSC)) 783 #endif /* !defined(NPU_PRESENT) && !defined(CRYP) */ 784 785 #if defined(NPU_PRESENT) && !defined(CRYP) 786 #define IS_RIF_RISC_PERIPH_INDEX(__INDEX__) (((__INDEX__) == RIF_RISC_PERIPH_INDEX_SPI1) || \ 787 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_SPI2) || \ 788 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_SPI3) || \ 789 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_SPI4) || \ 790 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_SPI5) || \ 791 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_SPI6) || \ 792 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_SAI1) || \ 793 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_SAI2) || \ 794 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_I2C1) || \ 795 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_I2C2) || \ 796 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_I2C3) || \ 797 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_I2C4) || \ 798 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_I3C1) || \ 799 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_I3C2) || \ 800 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_USART1) || \ 801 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_USART2) || \ 802 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_USART3) || \ 803 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_UART4) || \ 804 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_UART5) || \ 805 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_USART6) || \ 806 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_UART7) || \ 807 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_UART8) || \ 808 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_UART9) || \ 809 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_USART10) || \ 810 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_LPUART1) || \ 811 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_FDCAN1) || \ 812 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_TIM1) || \ 813 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_TIM2) || \ 814 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_TIM3) || \ 815 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_TIM4) || \ 816 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_TIM5) || \ 817 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_TIM6) || \ 818 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_TIM7) || \ 819 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_TIM8) || \ 820 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_TIM9) || \ 821 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_TIM10) || \ 822 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_TIM11) || \ 823 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_TIM12) || \ 824 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_TIM13) || \ 825 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_TIM14) || \ 826 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_TIM15) || \ 827 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_TIM16) || \ 828 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_TIM17) || \ 829 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_TIM18) || \ 830 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_GFXTIM) || \ 831 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_LPTIM1) || \ 832 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_LPTIM2) || \ 833 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_LPTIM3) || \ 834 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_LPTIM4) || \ 835 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_LPTIM5) || \ 836 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_ADF1) || \ 837 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_MDF1) || \ 838 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_SDMMC1) || \ 839 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_SDMMC2) || \ 840 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_MDIOS) || \ 841 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_OTG1HS) || \ 842 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_OTG2HS) || \ 843 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_UCPD1) || \ 844 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_ETH1) || \ 845 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_SPDIFRX) || \ 846 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_SYSCFG) || \ 847 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_ADC12) || \ 848 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_VREFBUF) || \ 849 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_CRC) || \ 850 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_IWDG) || \ 851 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_WWDG) || \ 852 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_RNG) || \ 853 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_PKA) || \ 854 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_HASH) || \ 855 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_XSPI1) || \ 856 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_XSPI2) || \ 857 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_XSPI3) || \ 858 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_XSPIM) || \ 859 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_FMC) || \ 860 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_CSI) || \ 861 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_DCMIPP) || \ 862 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_DCMI) || \ 863 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_JPEG) || \ 864 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_VENC) || \ 865 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_ICACHE) || \ 866 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_GPU2D) || \ 867 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_GFXMMU) || \ 868 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_DMA2D) || \ 869 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_LTDC) || \ 870 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_LTDCL1) || \ 871 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_LTDCL2) || \ 872 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_NPU)) 873 874 #define IS_RIF_RCC_PERIPH_INDEX(__INDEX__) (((__INDEX__) == RIF_RCC_PERIPH_INDEX_GPDMA1) || \ 875 ((__INDEX__) == RIF_RCC_PERIPH_INDEX_HPDMA1) || \ 876 ((__INDEX__) == RIF_RCC_PERIPH_INDEX_RTC) || \ 877 ((__INDEX__) == RIF_RCC_PERIPH_INDEX_AXISRAM1) || \ 878 ((__INDEX__) == RIF_RCC_PERIPH_INDEX_AXISRAM2) || \ 879 ((__INDEX__) == RIF_RCC_PERIPH_INDEX_FLEXRAM) || \ 880 ((__INDEX__) == RIF_RCC_PERIPH_INDEX_CACHEAXIRAM) || \ 881 ((__INDEX__) == RIF_RCC_PERIPH_INDEX_VENCRAM) || \ 882 ((__INDEX__) == RIF_RCC_PERIPH_INDEX_CACHECONFIG) || \ 883 ((__INDEX__) == RIF_RCC_PERIPH_INDEX_AHBRAM1) || \ 884 ((__INDEX__) == RIF_RCC_PERIPH_INDEX_AHBRAM2) || \ 885 ((__INDEX__) == RIF_RCC_PERIPH_INDEX_BKPRAM) || \ 886 ((__INDEX__) == RIF_RCC_PERIPH_INDEX_GPIOA) || \ 887 ((__INDEX__) == RIF_RCC_PERIPH_INDEX_GPIOB) || \ 888 ((__INDEX__) == RIF_RCC_PERIPH_INDEX_GPIOC) || \ 889 ((__INDEX__) == RIF_RCC_PERIPH_INDEX_GPIOD) || \ 890 ((__INDEX__) == RIF_RCC_PERIPH_INDEX_GPIOE) || \ 891 ((__INDEX__) == RIF_RCC_PERIPH_INDEX_GPIOF) || \ 892 ((__INDEX__) == RIF_RCC_PERIPH_INDEX_GPIOG) || \ 893 ((__INDEX__) == RIF_RCC_PERIPH_INDEX_GPIOH) || \ 894 ((__INDEX__) == RIF_RCC_PERIPH_INDEX_GPION) || \ 895 ((__INDEX__) == RIF_RCC_PERIPH_INDEX_GPIOO) || \ 896 ((__INDEX__) == RIF_RCC_PERIPH_INDEX_GPIOP) || \ 897 ((__INDEX__) == RIF_RCC_PERIPH_INDEX_GPIOQ) || \ 898 ((__INDEX__) == RIF_RCC_PERIPH_INDEX_DTS) || \ 899 ((__INDEX__) == RIF_RCC_PERIPH_INDEX_MCO1) || \ 900 ((__INDEX__) == RIF_RCC_PERIPH_INDEX_MCO2) || \ 901 ((__INDEX__) == RIF_RCC_PERIPH_INDEX_NPURAM0) || \ 902 ((__INDEX__) == RIF_RCC_PERIPH_INDEX_NPURAM1) || \ 903 ((__INDEX__) == RIF_RCC_PERIPH_INDEX_NPURAM2) || \ 904 ((__INDEX__) == RIF_RCC_PERIPH_INDEX_NPURAM3) || \ 905 ((__INDEX__) == RIF_RCC_PERIPH_INDEX_XSPIPHYCOMP) || \ 906 ((__INDEX__) == RIF_RCC_PERIPH_INDEX_XSPIPHY1) || \ 907 ((__INDEX__) == RIF_RCC_PERIPH_INDEX_XSPIPHY2) || \ 908 ((__INDEX__) == RIF_RCC_PERIPH_INDEX_HDP) || \ 909 ((__INDEX__) == RIF_RCC_PERIPH_INDEX_RAMCFG)) 910 911 #define IS_RIF_AWARE_PERIPH_INDEX(__INDEX__) (((__INDEX__) == RIF_AWARE_PERIPH_INDEX_CM55) || \ 912 ((__INDEX__) == RIF_AWARE_PERIPH_INDEX_EXTI) || \ 913 ((__INDEX__) == RIF_AWARE_PERIPH_INDEX_GPDMA1) || \ 914 ((__INDEX__) == RIF_AWARE_PERIPH_INDEX_HPDMA1) || \ 915 ((__INDEX__) == RIF_AWARE_PERIPH_INDEX_RTC) || \ 916 ((__INDEX__) == RIF_AWARE_PERIPH_INDEX_TAMP) || \ 917 ((__INDEX__) == RIF_AWARE_PERIPH_INDEX_BSEC) || \ 918 ((__INDEX__) == RIF_AWARE_PERIPH_INDEX_RCC) || \ 919 ((__INDEX__) == RIF_AWARE_PERIPH_INDEX_PWR) || \ 920 ((__INDEX__) == RIF_AWARE_PERIPH_INDEX_IAC) || \ 921 ((__INDEX__) == RIF_AWARE_PERIPH_INDEX_RISAF1) || \ 922 ((__INDEX__) == RIF_AWARE_PERIPH_INDEX_RISAF2) || \ 923 ((__INDEX__) == RIF_AWARE_PERIPH_INDEX_RISAF3) || \ 924 ((__INDEX__) == RIF_AWARE_PERIPH_INDEX_RISAF4) || \ 925 ((__INDEX__) == RIF_AWARE_PERIPH_INDEX_RISAF5) || \ 926 ((__INDEX__) == RIF_AWARE_PERIPH_INDEX_RISAF6) || \ 927 ((__INDEX__) == RIF_AWARE_PERIPH_INDEX_RISAF7) || \ 928 ((__INDEX__) == RIF_AWARE_PERIPH_INDEX_RISAF8) || \ 929 ((__INDEX__) == RIF_AWARE_PERIPH_INDEX_RISAF9) || \ 930 ((__INDEX__) == RIF_AWARE_PERIPH_INDEX_RISAF11) || \ 931 ((__INDEX__) == RIF_AWARE_PERIPH_INDEX_RISAF12) || \ 932 ((__INDEX__) == RIF_AWARE_PERIPH_INDEX_RISAF13) || \ 933 ((__INDEX__) == RIF_AWARE_PERIPH_INDEX_RISAF14) || \ 934 ((__INDEX__) == RIF_AWARE_PERIPH_INDEX_RISAF15) || \ 935 ((__INDEX__) == RIF_AWARE_PERIPH_INDEX_RISAF21) || \ 936 ((__INDEX__) == RIF_AWARE_PERIPH_INDEX_RISAF22) || \ 937 ((__INDEX__) == RIF_AWARE_PERIPH_INDEX_RISAF23) || \ 938 ((__INDEX__) == RIF_AWARE_PERIPH_INDEX_RIFSC)) 939 #endif /* defined(NPU_PRESENT) && !defined(CRYP) */ 940 941 #if !defined(NPU_PRESENT) && defined(CRYP) 942 #define IS_RIF_RISC_PERIPH_INDEX(__INDEX__) (((__INDEX__) == RIF_RISC_PERIPH_INDEX_SPI1) || \ 943 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_SPI2) || \ 944 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_SPI3) || \ 945 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_SPI4) || \ 946 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_SPI5) || \ 947 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_SPI6) || \ 948 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_SAI1) || \ 949 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_SAI2) || \ 950 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_I2C1) || \ 951 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_I2C2) || \ 952 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_I2C3) || \ 953 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_I2C4) || \ 954 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_I3C1) || \ 955 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_I3C2) || \ 956 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_USART1) || \ 957 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_USART2) || \ 958 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_USART3) || \ 959 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_UART4) || \ 960 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_UART5) || \ 961 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_USART6) || \ 962 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_UART7) || \ 963 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_UART8) || \ 964 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_UART9) || \ 965 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_USART10) || \ 966 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_LPUART1) || \ 967 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_FDCAN1) || \ 968 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_TIM1) || \ 969 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_TIM2) || \ 970 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_TIM3) || \ 971 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_TIM4) || \ 972 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_TIM5) || \ 973 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_TIM6) || \ 974 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_TIM7) || \ 975 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_TIM8) || \ 976 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_TIM9) || \ 977 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_TIM10) || \ 978 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_TIM11) || \ 979 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_TIM12) || \ 980 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_TIM13) || \ 981 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_TIM14) || \ 982 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_TIM15) || \ 983 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_TIM16) || \ 984 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_TIM17) || \ 985 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_TIM18) || \ 986 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_GFXTIM) || \ 987 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_LPTIM1) || \ 988 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_LPTIM2) || \ 989 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_LPTIM3) || \ 990 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_LPTIM4) || \ 991 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_LPTIM5) || \ 992 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_ADF1) || \ 993 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_MDF1) || \ 994 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_SDMMC1) || \ 995 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_SDMMC2) || \ 996 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_MDIOS) || \ 997 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_OTG1HS) || \ 998 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_OTG2HS) || \ 999 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_UCPD1) || \ 1000 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_ETH1) || \ 1001 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_SPDIFRX) || \ 1002 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_SYSCFG) || \ 1003 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_ADC12) || \ 1004 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_VREFBUF) || \ 1005 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_CRC) || \ 1006 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_IWDG) || \ 1007 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_WWDG) || \ 1008 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_RNG) || \ 1009 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_PKA) || \ 1010 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_SAES) || \ 1011 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_HASH) || \ 1012 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_CRYP) || \ 1013 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_MCE1) || \ 1014 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_MCE2) || \ 1015 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_MCE3) || \ 1016 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_MCE4) || \ 1017 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_XSPI1) || \ 1018 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_XSPI2) || \ 1019 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_XSPI3) || \ 1020 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_XSPIM) || \ 1021 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_FMC) || \ 1022 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_CSI) || \ 1023 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_DCMIPP) || \ 1024 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_DCMI) || \ 1025 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_JPEG) || \ 1026 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_VENC) || \ 1027 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_ICACHE) || \ 1028 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_GPU2D) || \ 1029 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_GFXMMU) || \ 1030 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_DMA2D) || \ 1031 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_LTDC) || \ 1032 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_LTDCL1) || \ 1033 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_LTDCL2)) 1034 1035 #define IS_RIF_RCC_PERIPH_INDEX(__INDEX__) (((__INDEX__) == RIF_RCC_PERIPH_INDEX_GPDMA1) || \ 1036 ((__INDEX__) == RIF_RCC_PERIPH_INDEX_HPDMA1) || \ 1037 ((__INDEX__) == RIF_RCC_PERIPH_INDEX_RTC) || \ 1038 ((__INDEX__) == RIF_RCC_PERIPH_INDEX_AXISRAM1) || \ 1039 ((__INDEX__) == RIF_RCC_PERIPH_INDEX_AXISRAM2) || \ 1040 ((__INDEX__) == RIF_RCC_PERIPH_INDEX_FLEXRAM) || \ 1041 ((__INDEX__) == RIF_RCC_PERIPH_INDEX_CACHEAXIRAM) || \ 1042 ((__INDEX__) == RIF_RCC_PERIPH_INDEX_VENCRAM) || \ 1043 ((__INDEX__) == RIF_RCC_PERIPH_INDEX_AHBRAM1) || \ 1044 ((__INDEX__) == RIF_RCC_PERIPH_INDEX_AHBRAM2) || \ 1045 ((__INDEX__) == RIF_RCC_PERIPH_INDEX_BKPRAM) || \ 1046 ((__INDEX__) == RIF_RCC_PERIPH_INDEX_GPIOA) || \ 1047 ((__INDEX__) == RIF_RCC_PERIPH_INDEX_GPIOB) || \ 1048 ((__INDEX__) == RIF_RCC_PERIPH_INDEX_GPIOC) || \ 1049 ((__INDEX__) == RIF_RCC_PERIPH_INDEX_GPIOD) || \ 1050 ((__INDEX__) == RIF_RCC_PERIPH_INDEX_GPIOE) || \ 1051 ((__INDEX__) == RIF_RCC_PERIPH_INDEX_GPIOF) || \ 1052 ((__INDEX__) == RIF_RCC_PERIPH_INDEX_GPIOG) || \ 1053 ((__INDEX__) == RIF_RCC_PERIPH_INDEX_GPIOH) || \ 1054 ((__INDEX__) == RIF_RCC_PERIPH_INDEX_GPION) || \ 1055 ((__INDEX__) == RIF_RCC_PERIPH_INDEX_GPIOO) || \ 1056 ((__INDEX__) == RIF_RCC_PERIPH_INDEX_GPIOP) || \ 1057 ((__INDEX__) == RIF_RCC_PERIPH_INDEX_GPIOQ) || \ 1058 ((__INDEX__) == RIF_RCC_PERIPH_INDEX_DTS) || \ 1059 ((__INDEX__) == RIF_RCC_PERIPH_INDEX_MCO1) || \ 1060 ((__INDEX__) == RIF_RCC_PERIPH_INDEX_MCO2) || \ 1061 ((__INDEX__) == RIF_RCC_PERIPH_INDEX_XSPIPHYCOMP) || \ 1062 ((__INDEX__) == RIF_RCC_PERIPH_INDEX_XSPIPHY1) || \ 1063 ((__INDEX__) == RIF_RCC_PERIPH_INDEX_XSPIPHY2) || \ 1064 ((__INDEX__) == RIF_RCC_PERIPH_INDEX_HDP) || \ 1065 ((__INDEX__) == RIF_RCC_PERIPH_INDEX_RAMCFG)) 1066 1067 #define IS_RIF_AWARE_PERIPH_INDEX(__INDEX__) (((__INDEX__) == RIF_AWARE_PERIPH_INDEX_CM55) || \ 1068 ((__INDEX__) == RIF_AWARE_PERIPH_INDEX_EXTI) || \ 1069 ((__INDEX__) == RIF_AWARE_PERIPH_INDEX_GPDMA1) || \ 1070 ((__INDEX__) == RIF_AWARE_PERIPH_INDEX_HPDMA1) || \ 1071 ((__INDEX__) == RIF_AWARE_PERIPH_INDEX_RTC) || \ 1072 ((__INDEX__) == RIF_AWARE_PERIPH_INDEX_TAMP) || \ 1073 ((__INDEX__) == RIF_AWARE_PERIPH_INDEX_BSEC) || \ 1074 ((__INDEX__) == RIF_AWARE_PERIPH_INDEX_RCC) || \ 1075 ((__INDEX__) == RIF_AWARE_PERIPH_INDEX_PWR) || \ 1076 ((__INDEX__) == RIF_AWARE_PERIPH_INDEX_IAC) || \ 1077 ((__INDEX__) == RIF_AWARE_PERIPH_INDEX_RISAF1) || \ 1078 ((__INDEX__) == RIF_AWARE_PERIPH_INDEX_RISAF2) || \ 1079 ((__INDEX__) == RIF_AWARE_PERIPH_INDEX_RISAF3) || \ 1080 ((__INDEX__) == RIF_AWARE_PERIPH_INDEX_RISAF6) || \ 1081 ((__INDEX__) == RIF_AWARE_PERIPH_INDEX_RISAF7) || \ 1082 ((__INDEX__) == RIF_AWARE_PERIPH_INDEX_RISAF8) || \ 1083 ((__INDEX__) == RIF_AWARE_PERIPH_INDEX_RISAF9) || \ 1084 ((__INDEX__) == RIF_AWARE_PERIPH_INDEX_RISAF11) || \ 1085 ((__INDEX__) == RIF_AWARE_PERIPH_INDEX_RISAF12) || \ 1086 ((__INDEX__) == RIF_AWARE_PERIPH_INDEX_RISAF13) || \ 1087 ((__INDEX__) == RIF_AWARE_PERIPH_INDEX_RISAF14) || \ 1088 ((__INDEX__) == RIF_AWARE_PERIPH_INDEX_RISAF21) || \ 1089 ((__INDEX__) == RIF_AWARE_PERIPH_INDEX_RISAF22) || \ 1090 ((__INDEX__) == RIF_AWARE_PERIPH_INDEX_RISAF23) || \ 1091 ((__INDEX__) == RIF_AWARE_PERIPH_INDEX_RIFSC)) 1092 #endif /* !defined(NPU_PRESENT) && defined(CRYP) */ 1093 1094 #if defined(NPU_PRESENT) && defined(CRYP) 1095 #define IS_RIF_RISC_PERIPH_INDEX(__INDEX__) (((__INDEX__) == RIF_RISC_PERIPH_INDEX_SPI1) || \ 1096 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_SPI2) || \ 1097 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_SPI3) || \ 1098 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_SPI4) || \ 1099 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_SPI5) || \ 1100 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_SPI6) || \ 1101 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_SAI1) || \ 1102 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_SAI2) || \ 1103 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_I2C1) || \ 1104 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_I2C2) || \ 1105 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_I2C3) || \ 1106 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_I2C4) || \ 1107 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_I3C1) || \ 1108 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_I3C2) || \ 1109 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_USART1) || \ 1110 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_USART2) || \ 1111 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_USART3) || \ 1112 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_UART4) || \ 1113 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_UART5) || \ 1114 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_USART6) || \ 1115 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_UART7) || \ 1116 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_UART8) || \ 1117 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_UART9) || \ 1118 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_USART10) || \ 1119 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_LPUART1) || \ 1120 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_FDCAN1) || \ 1121 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_TIM1) || \ 1122 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_TIM2) || \ 1123 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_TIM3) || \ 1124 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_TIM4) || \ 1125 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_TIM5) || \ 1126 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_TIM6) || \ 1127 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_TIM7) || \ 1128 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_TIM8) || \ 1129 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_TIM9) || \ 1130 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_TIM10) || \ 1131 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_TIM11) || \ 1132 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_TIM12) || \ 1133 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_TIM13) || \ 1134 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_TIM14) || \ 1135 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_TIM15) || \ 1136 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_TIM16) || \ 1137 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_TIM17) || \ 1138 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_TIM18) || \ 1139 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_GFXTIM) || \ 1140 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_LPTIM1) || \ 1141 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_LPTIM2) || \ 1142 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_LPTIM3) || \ 1143 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_LPTIM4) || \ 1144 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_LPTIM5) || \ 1145 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_ADF1) || \ 1146 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_MDF1) || \ 1147 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_SDMMC1) || \ 1148 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_SDMMC2) || \ 1149 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_MDIOS) || \ 1150 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_OTG1HS) || \ 1151 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_OTG2HS) || \ 1152 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_UCPD1) || \ 1153 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_ETH1) || \ 1154 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_SPDIFRX) || \ 1155 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_SYSCFG) || \ 1156 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_ADC12) || \ 1157 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_VREFBUF) || \ 1158 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_CRC) || \ 1159 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_IWDG) || \ 1160 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_WWDG) || \ 1161 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_RNG) || \ 1162 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_PKA) || \ 1163 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_SAES) || \ 1164 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_HASH) || \ 1165 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_CRYP) || \ 1166 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_MCE1) || \ 1167 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_MCE2) || \ 1168 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_MCE3) || \ 1169 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_MCE4) || \ 1170 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_XSPI1) || \ 1171 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_XSPI2) || \ 1172 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_XSPI3) || \ 1173 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_XSPIM) || \ 1174 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_FMC) || \ 1175 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_CSI) || \ 1176 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_DCMIPP) || \ 1177 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_DCMI) || \ 1178 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_JPEG) || \ 1179 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_VENC) || \ 1180 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_ICACHE) || \ 1181 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_GPU2D) || \ 1182 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_GFXMMU) || \ 1183 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_DMA2D) || \ 1184 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_LTDC) || \ 1185 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_LTDCL1) || \ 1186 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_LTDCL2) || \ 1187 ((__INDEX__) == RIF_RISC_PERIPH_INDEX_NPU)) 1188 1189 #define IS_RIF_RCC_PERIPH_INDEX(__INDEX__) (((__INDEX__) == RIF_RCC_PERIPH_INDEX_GPDMA1) || \ 1190 ((__INDEX__) == RIF_RCC_PERIPH_INDEX_HPDMA1) || \ 1191 ((__INDEX__) == RIF_RCC_PERIPH_INDEX_RTC) || \ 1192 ((__INDEX__) == RIF_RCC_PERIPH_INDEX_AXISRAM1) || \ 1193 ((__INDEX__) == RIF_RCC_PERIPH_INDEX_AXISRAM2) || \ 1194 ((__INDEX__) == RIF_RCC_PERIPH_INDEX_FLEXRAM) || \ 1195 ((__INDEX__) == RIF_RCC_PERIPH_INDEX_CACHEAXIRAM) || \ 1196 ((__INDEX__) == RIF_RCC_PERIPH_INDEX_VENCRAM) || \ 1197 ((__INDEX__) == RIF_RCC_PERIPH_INDEX_CACHECONFIG) || \ 1198 ((__INDEX__) == RIF_RCC_PERIPH_INDEX_AHBRAM1) || \ 1199 ((__INDEX__) == RIF_RCC_PERIPH_INDEX_AHBRAM2) || \ 1200 ((__INDEX__) == RIF_RCC_PERIPH_INDEX_BKPRAM) || \ 1201 ((__INDEX__) == RIF_RCC_PERIPH_INDEX_GPIOA) || \ 1202 ((__INDEX__) == RIF_RCC_PERIPH_INDEX_GPIOB) || \ 1203 ((__INDEX__) == RIF_RCC_PERIPH_INDEX_GPIOC) || \ 1204 ((__INDEX__) == RIF_RCC_PERIPH_INDEX_GPIOD) || \ 1205 ((__INDEX__) == RIF_RCC_PERIPH_INDEX_GPIOE) || \ 1206 ((__INDEX__) == RIF_RCC_PERIPH_INDEX_GPIOF) || \ 1207 ((__INDEX__) == RIF_RCC_PERIPH_INDEX_GPIOG) || \ 1208 ((__INDEX__) == RIF_RCC_PERIPH_INDEX_GPIOH) || \ 1209 ((__INDEX__) == RIF_RCC_PERIPH_INDEX_GPION) || \ 1210 ((__INDEX__) == RIF_RCC_PERIPH_INDEX_GPIOO) || \ 1211 ((__INDEX__) == RIF_RCC_PERIPH_INDEX_GPIOP) || \ 1212 ((__INDEX__) == RIF_RCC_PERIPH_INDEX_GPIOQ) || \ 1213 ((__INDEX__) == RIF_RCC_PERIPH_INDEX_DTS) || \ 1214 ((__INDEX__) == RIF_RCC_PERIPH_INDEX_MCO1) || \ 1215 ((__INDEX__) == RIF_RCC_PERIPH_INDEX_MCO2) || \ 1216 ((__INDEX__) == RIF_RCC_PERIPH_INDEX_NPURAM0) || \ 1217 ((__INDEX__) == RIF_RCC_PERIPH_INDEX_NPURAM1) || \ 1218 ((__INDEX__) == RIF_RCC_PERIPH_INDEX_NPURAM2) || \ 1219 ((__INDEX__) == RIF_RCC_PERIPH_INDEX_NPURAM3) || \ 1220 ((__INDEX__) == RIF_RCC_PERIPH_INDEX_XSPIPHYCOMP) || \ 1221 ((__INDEX__) == RIF_RCC_PERIPH_INDEX_XSPIPHY1) || \ 1222 ((__INDEX__) == RIF_RCC_PERIPH_INDEX_XSPIPHY2) || \ 1223 ((__INDEX__) == RIF_RCC_PERIPH_INDEX_HDP) || \ 1224 ((__INDEX__) == RIF_RCC_PERIPH_INDEX_RAMCFG)) 1225 1226 #define IS_RIF_AWARE_PERIPH_INDEX(__INDEX__) (((__INDEX__) == RIF_AWARE_PERIPH_INDEX_CM55) || \ 1227 ((__INDEX__) == RIF_AWARE_PERIPH_INDEX_EXTI) || \ 1228 ((__INDEX__) == RIF_AWARE_PERIPH_INDEX_GPDMA1) || \ 1229 ((__INDEX__) == RIF_AWARE_PERIPH_INDEX_HPDMA1) || \ 1230 ((__INDEX__) == RIF_AWARE_PERIPH_INDEX_RTC) || \ 1231 ((__INDEX__) == RIF_AWARE_PERIPH_INDEX_TAMP) || \ 1232 ((__INDEX__) == RIF_AWARE_PERIPH_INDEX_BSEC) || \ 1233 ((__INDEX__) == RIF_AWARE_PERIPH_INDEX_RCC) || \ 1234 ((__INDEX__) == RIF_AWARE_PERIPH_INDEX_PWR) || \ 1235 ((__INDEX__) == RIF_AWARE_PERIPH_INDEX_IAC) || \ 1236 ((__INDEX__) == RIF_AWARE_PERIPH_INDEX_RISAF1) || \ 1237 ((__INDEX__) == RIF_AWARE_PERIPH_INDEX_RISAF2) || \ 1238 ((__INDEX__) == RIF_AWARE_PERIPH_INDEX_RISAF3) || \ 1239 ((__INDEX__) == RIF_AWARE_PERIPH_INDEX_RISAF4) || \ 1240 ((__INDEX__) == RIF_AWARE_PERIPH_INDEX_RISAF5) || \ 1241 ((__INDEX__) == RIF_AWARE_PERIPH_INDEX_RISAF6) || \ 1242 ((__INDEX__) == RIF_AWARE_PERIPH_INDEX_RISAF7) || \ 1243 ((__INDEX__) == RIF_AWARE_PERIPH_INDEX_RISAF8) || \ 1244 ((__INDEX__) == RIF_AWARE_PERIPH_INDEX_RISAF9) || \ 1245 ((__INDEX__) == RIF_AWARE_PERIPH_INDEX_RISAF11) || \ 1246 ((__INDEX__) == RIF_AWARE_PERIPH_INDEX_RISAF12) || \ 1247 ((__INDEX__) == RIF_AWARE_PERIPH_INDEX_RISAF13) || \ 1248 ((__INDEX__) == RIF_AWARE_PERIPH_INDEX_RISAF14) || \ 1249 ((__INDEX__) == RIF_AWARE_PERIPH_INDEX_RISAF15) || \ 1250 ((__INDEX__) == RIF_AWARE_PERIPH_INDEX_RISAF21) || \ 1251 ((__INDEX__) == RIF_AWARE_PERIPH_INDEX_RISAF22) || \ 1252 ((__INDEX__) == RIF_AWARE_PERIPH_INDEX_RISAF23) || \ 1253 ((__INDEX__) == RIF_AWARE_PERIPH_INDEX_RIFSC)) 1254 #endif /* defined(NPU_PRESENT) && defined(CRYP) */ 1255 1256 #define IS_RIF_SEC_PRIV_ATTRIBUTE(__ATTRIBUTE__) (((uint32_t)(__ATTRIBUTE__) & ~RIF_ATTRIBUTE_MASK) == 0x00U) 1257 1258 #define IS_RIF_ACCESS_TYPE(__ACCTYPE__) (((__ACCTYPE__) == RIF_ACCTYPE_READ_FETCH) || \ 1259 ((__ACCTYPE__) == RIF_ACCTYPE_WRITE)) 1260 1261 #define IS_RIF_LOCK_STATE(__LOCK__) (((__LOCK__) == RIF_LOCK_DISABLE) || \ 1262 ((__LOCK__) == RIF_LOCK_ENABLE)) 1263 /** 1264 * @} 1265 */ 1266 1267 /** @defgroup RIF_Private_Macros_RISAF RIF Private Macros - RISAF 1268 * @{ 1269 */ 1270 1271 #if !defined(NPU_PRESENT) 1272 #define IS_RISAF_INSTANCE(__INSTANCE__) (((__INSTANCE__) == RISAF1) || \ 1273 ((__INSTANCE__) == RISAF2) || \ 1274 ((__INSTANCE__) == RISAF3) || \ 1275 ((__INSTANCE__) == RISAF6) || \ 1276 ((__INSTANCE__) == RISAF7) || \ 1277 ((__INSTANCE__) == RISAF8) || \ 1278 ((__INSTANCE__) == RISAF9) || \ 1279 ((__INSTANCE__) == RISAF11) || \ 1280 ((__INSTANCE__) == RISAF12) || \ 1281 ((__INSTANCE__) == RISAF13) || \ 1282 ((__INSTANCE__) == RISAF14) || \ 1283 ((__INSTANCE__) == RISAF21) || \ 1284 ((__INSTANCE__) == RISAF22) || \ 1285 ((__INSTANCE__) == RISAF23)) 1286 #else 1287 #define IS_RISAF_INSTANCE(__INSTANCE__) (((__INSTANCE__) == RISAF1) || \ 1288 ((__INSTANCE__) == RISAF2) || \ 1289 ((__INSTANCE__) == RISAF3) || \ 1290 ((__INSTANCE__) == RISAF4) || \ 1291 ((__INSTANCE__) == RISAF5) || \ 1292 ((__INSTANCE__) == RISAF6) || \ 1293 ((__INSTANCE__) == RISAF7) || \ 1294 ((__INSTANCE__) == RISAF8) || \ 1295 ((__INSTANCE__) == RISAF9) || \ 1296 ((__INSTANCE__) == RISAF11) || \ 1297 ((__INSTANCE__) == RISAF12) || \ 1298 ((__INSTANCE__) == RISAF13) || \ 1299 ((__INSTANCE__) == RISAF14) || \ 1300 ((__INSTANCE__) == RISAF15) || \ 1301 ((__INSTANCE__) == RISAF21) || \ 1302 ((__INSTANCE__) == RISAF22) || \ 1303 ((__INSTANCE__) == RISAF23)) 1304 #endif /* !defined(NPU_PRESENT) */ 1305 1306 #define IS_RISAF_REGION(__REGION__) (((__REGION__) == RISAF_REGION_1) || \ 1307 ((__REGION__) == RISAF_REGION_2) || \ 1308 ((__REGION__) == RISAF_REGION_3) || \ 1309 ((__REGION__) == RISAF_REGION_4) || \ 1310 ((__REGION__) == RISAF_REGION_5) || \ 1311 ((__REGION__) == RISAF_REGION_6) || \ 1312 ((__REGION__) == RISAF_REGION_7) || \ 1313 ((__REGION__) == RISAF_REGION_8) || \ 1314 ((__REGION__) == RISAF_REGION_9) || \ 1315 ((__REGION__) == RISAF_REGION_10) || \ 1316 ((__REGION__) == RISAF_REGION_11) || \ 1317 ((__REGION__) == RISAF_REGION_12) || \ 1318 ((__REGION__) == RISAF_REGION_13) || \ 1319 ((__REGION__) == RISAF_REGION_14) || \ 1320 ((__REGION__) == RISAF_REGION_15)) 1321 1322 #if !defined(NPU_PRESENT) 1323 #define IS_RISAF_MAX_REGION(__INSTANCE__, __REGION__) (((__INSTANCE__) == RISAF1) ? ((__REGION__) <= RISAF_REGION_7) : \ 1324 ((__INSTANCE__) == RISAF2) ? ((__REGION__) <= RISAF_REGION_7) : \ 1325 ((__INSTANCE__) == RISAF3) ? ((__REGION__) <= RISAF_REGION_7) : \ 1326 ((__INSTANCE__) == RISAF6) ? ((__REGION__) <= RISAF_REGION_11) : \ 1327 ((__INSTANCE__) == RISAF7) ? ((__REGION__) <= RISAF_REGION_7) : \ 1328 ((__INSTANCE__) == RISAF8) ? ((__REGION__) <= RISAF_REGION_7) : \ 1329 ((__INSTANCE__) == RISAF9) ? ((__REGION__) <= RISAF_REGION_7) : \ 1330 ((__INSTANCE__) == RISAF11) ? ((__REGION__) <= RISAF_REGION_7) : \ 1331 ((__INSTANCE__) == RISAF12) ? ((__REGION__) <= RISAF_REGION_7) : \ 1332 ((__INSTANCE__) == RISAF13) ? ((__REGION__) <= RISAF_REGION_7) : \ 1333 ((__INSTANCE__) == RISAF14) ? ((__REGION__) <= RISAF_REGION_7) : \ 1334 ((__INSTANCE__) == RISAF21) ? ((__REGION__) <= RISAF_REGION_7) : \ 1335 ((__INSTANCE__) == RISAF22) ? ((__REGION__) <= RISAF_REGION_7) : \ 1336 ((__REGION__) <= RISAF_REGION_3)) 1337 #else 1338 #define IS_RISAF_MAX_REGION(__INSTANCE__, __REGION__) (((__INSTANCE__) == RISAF1) ? ((__REGION__) <= RISAF_REGION_7) : \ 1339 ((__INSTANCE__) == RISAF2) ? ((__REGION__) <= RISAF_REGION_7) : \ 1340 ((__INSTANCE__) == RISAF3) ? ((__REGION__) <= RISAF_REGION_7) : \ 1341 ((__INSTANCE__) == RISAF4) ? ((__REGION__) <= RISAF_REGION_11) : \ 1342 ((__INSTANCE__) == RISAF5) ? ((__REGION__) <= RISAF_REGION_11) : \ 1343 ((__INSTANCE__) == RISAF6) ? ((__REGION__) <= RISAF_REGION_11) : \ 1344 ((__INSTANCE__) == RISAF7) ? ((__REGION__) <= RISAF_REGION_7) : \ 1345 ((__INSTANCE__) == RISAF8) ? ((__REGION__) <= RISAF_REGION_7) : \ 1346 ((__INSTANCE__) == RISAF9) ? ((__REGION__) <= RISAF_REGION_7) : \ 1347 ((__INSTANCE__) == RISAF11) ? ((__REGION__) <= RISAF_REGION_7) : \ 1348 ((__INSTANCE__) == RISAF12) ? ((__REGION__) <= RISAF_REGION_7) : \ 1349 ((__INSTANCE__) == RISAF13) ? ((__REGION__) <= RISAF_REGION_7) : \ 1350 ((__INSTANCE__) == RISAF14) ? ((__REGION__) <= RISAF_REGION_7) : \ 1351 ((__INSTANCE__) == RISAF15) ? ((__REGION__) <= RISAF_REGION_2) : \ 1352 ((__INSTANCE__) == RISAF21) ? ((__REGION__) <= RISAF_REGION_7) : \ 1353 ((__INSTANCE__) == RISAF22) ? ((__REGION__) <= RISAF_REGION_7) : \ 1354 ((__REGION__) <= RISAF_REGION_3)) 1355 #endif /* !defined(NPU_PRESENT) */ 1356 1357 #if !defined(NPU_PRESENT) 1358 #define IS_RISAF_GRANULARITY(__INSTANCE__, __ADDRESS__) ((((__INSTANCE__) == RISAF1) ? ((__ADDRESS__) % RISAF1_GRANULARITY) : \ 1359 ((__INSTANCE__) == RISAF2) ? ((__ADDRESS__) % RISAF2_GRANULARITY) : \ 1360 ((__INSTANCE__) == RISAF3) ? ((__ADDRESS__) % RISAF3_GRANULARITY) : \ 1361 ((__INSTANCE__) == RISAF6) ? ((__ADDRESS__) % RISAF6_GRANULARITY) : \ 1362 ((__INSTANCE__) == RISAF7) ? ((__ADDRESS__) % RISAF7_GRANULARITY) : \ 1363 ((__INSTANCE__) == RISAF8) ? ((__ADDRESS__) % RISAF8_GRANULARITY) : \ 1364 ((__INSTANCE__) == RISAF9) ? ((__ADDRESS__) % RISAF9_GRANULARITY) : \ 1365 ((__INSTANCE__) == RISAF11) ? ((__ADDRESS__) % RISAF11_GRANULARITY) : \ 1366 ((__INSTANCE__) == RISAF12) ? ((__ADDRESS__) % RISAF12_GRANULARITY) : \ 1367 ((__INSTANCE__) == RISAF13) ? ((__ADDRESS__) % RISAF13_GRANULARITY) : \ 1368 ((__INSTANCE__) == RISAF14) ? ((__ADDRESS__) % RISAF14_GRANULARITY) : \ 1369 ((__INSTANCE__) == RISAF21) ? ((__ADDRESS__) % RISAF21_GRANULARITY) : \ 1370 ((__INSTANCE__) == RISAF22) ? ((__ADDRESS__) % RISAF22_GRANULARITY) : \ 1371 ((__ADDRESS__) % RISAF23_GRANULARITY)) == 0x00U) 1372 #else 1373 #define IS_RISAF_GRANULARITY(__INSTANCE__, __ADDRESS__) ((((__INSTANCE__) == RISAF1) ? ((__ADDRESS__) % RISAF1_GRANULARITY) : \ 1374 ((__INSTANCE__) == RISAF2) ? ((__ADDRESS__) % RISAF2_GRANULARITY) : \ 1375 ((__INSTANCE__) == RISAF3) ? ((__ADDRESS__) % RISAF3_GRANULARITY) : \ 1376 ((__INSTANCE__) == RISAF4) ? ((__ADDRESS__) % RISAF4_GRANULARITY) : \ 1377 ((__INSTANCE__) == RISAF5) ? ((__ADDRESS__) % RISAF5_GRANULARITY) : \ 1378 ((__INSTANCE__) == RISAF6) ? ((__ADDRESS__) % RISAF6_GRANULARITY) : \ 1379 ((__INSTANCE__) == RISAF7) ? ((__ADDRESS__) % RISAF7_GRANULARITY) : \ 1380 ((__INSTANCE__) == RISAF8) ? ((__ADDRESS__) % RISAF8_GRANULARITY) : \ 1381 ((__INSTANCE__) == RISAF9) ? ((__ADDRESS__) % RISAF9_GRANULARITY) : \ 1382 ((__INSTANCE__) == RISAF11) ? ((__ADDRESS__) % RISAF11_GRANULARITY) : \ 1383 ((__INSTANCE__) == RISAF12) ? ((__ADDRESS__) % RISAF12_GRANULARITY) : \ 1384 ((__INSTANCE__) == RISAF13) ? ((__ADDRESS__) % RISAF13_GRANULARITY) : \ 1385 ((__INSTANCE__) == RISAF14) ? ((__ADDRESS__) % RISAF14_GRANULARITY) : \ 1386 ((__INSTANCE__) == RISAF15) ? ((__ADDRESS__) % RISAF15_GRANULARITY) : \ 1387 ((__INSTANCE__) == RISAF21) ? ((__ADDRESS__) % RISAF21_GRANULARITY) : \ 1388 ((__INSTANCE__) == RISAF22) ? ((__ADDRESS__) % RISAF22_GRANULARITY) : \ 1389 ((__ADDRESS__) % RISAF23_GRANULARITY)) == 0x00U) 1390 #endif /* !defined(NPU_PRESENT) */ 1391 1392 #if !defined(NPU_PRESENT) 1393 #define IS_RISAF_LIMIT_ADDRESS_SPACE_SIZE(__INSTANCE__, __ADDRESS__) ((((__INSTANCE__) == RISAF1) && ((__ADDRESS__) < (RISAF1_LIMIT_ADDRESS_SPACE_SIZE + 1U))) || \ 1394 (((__INSTANCE__) == RISAF2) && ((__ADDRESS__) < (RISAF2_LIMIT_ADDRESS_SPACE_SIZE + 1U))) || \ 1395 (((__INSTANCE__) == RISAF3) && ((__ADDRESS__) < (RISAF3_LIMIT_ADDRESS_SPACE_SIZE + 1U))) || \ 1396 ((__INSTANCE__) == RISAF6) || \ 1397 (((__INSTANCE__) == RISAF7) && ((__ADDRESS__) < (RISAF7_LIMIT_ADDRESS_SPACE_SIZE + 1U))) || \ 1398 (((__INSTANCE__) == RISAF8) && ((__ADDRESS__) < (RISAF8_LIMIT_ADDRESS_SPACE_SIZE + 1U))) || \ 1399 (((__INSTANCE__) == RISAF9) && ((__ADDRESS__) < (RISAF9_LIMIT_ADDRESS_SPACE_SIZE + 1U))) || \ 1400 (((__INSTANCE__) == RISAF11) && ((__ADDRESS__) < (RISAF11_LIMIT_ADDRESS_SPACE_SIZE + 1U))) || \ 1401 (((__INSTANCE__) == RISAF12) && ((__ADDRESS__) < (RISAF12_LIMIT_ADDRESS_SPACE_SIZE + 1U))) || \ 1402 (((__INSTANCE__) == RISAF13) && ((__ADDRESS__) < (RISAF13_LIMIT_ADDRESS_SPACE_SIZE + 1U))) || \ 1403 (((__INSTANCE__) == RISAF14) && ((__ADDRESS__) < (RISAF14_LIMIT_ADDRESS_SPACE_SIZE + 1U))) || \ 1404 (((__INSTANCE__) == RISAF21) && ((__ADDRESS__) < (RISAF21_LIMIT_ADDRESS_SPACE_SIZE + 1U))) || \ 1405 (((__INSTANCE__) == RISAF22) && ((__ADDRESS__) < (RISAF22_LIMIT_ADDRESS_SPACE_SIZE + 1U))) || \ 1406 (((__INSTANCE__) == RISAF23) && ((__ADDRESS__) < (RISAF23_LIMIT_ADDRESS_SPACE_SIZE + 1U)))) 1407 #else 1408 #define IS_RISAF_LIMIT_ADDRESS_SPACE_SIZE(__INSTANCE__, __ADDRESS__) ((((__INSTANCE__) == RISAF1) && ((__ADDRESS__) < (RISAF1_LIMIT_ADDRESS_SPACE_SIZE + 1U))) || \ 1409 (((__INSTANCE__) == RISAF2) && ((__ADDRESS__) < (RISAF2_LIMIT_ADDRESS_SPACE_SIZE + 1U))) || \ 1410 (((__INSTANCE__) == RISAF3) && ((__ADDRESS__) < (RISAF3_LIMIT_ADDRESS_SPACE_SIZE + 1U))) || \ 1411 ((__INSTANCE__) == RISAF4) || \ 1412 ((__INSTANCE__) == RISAF5) || \ 1413 ((__INSTANCE__) == RISAF6) || \ 1414 (((__INSTANCE__) == RISAF7) && ((__ADDRESS__) < (RISAF7_LIMIT_ADDRESS_SPACE_SIZE + 1U))) || \ 1415 (((__INSTANCE__) == RISAF8) && ((__ADDRESS__) < (RISAF8_LIMIT_ADDRESS_SPACE_SIZE + 1U))) || \ 1416 (((__INSTANCE__) == RISAF9) && ((__ADDRESS__) < (RISAF9_LIMIT_ADDRESS_SPACE_SIZE + 1U))) || \ 1417 (((__INSTANCE__) == RISAF11) && ((__ADDRESS__) < (RISAF11_LIMIT_ADDRESS_SPACE_SIZE + 1U))) || \ 1418 (((__INSTANCE__) == RISAF12) && ((__ADDRESS__) < (RISAF12_LIMIT_ADDRESS_SPACE_SIZE + 1U))) || \ 1419 (((__INSTANCE__) == RISAF13) && ((__ADDRESS__) < (RISAF13_LIMIT_ADDRESS_SPACE_SIZE + 1U))) || \ 1420 (((__INSTANCE__) == RISAF14) && ((__ADDRESS__) < (RISAF14_LIMIT_ADDRESS_SPACE_SIZE + 1U))) || \ 1421 (((__INSTANCE__) == RISAF15) && ((__ADDRESS__) < (RISAF15_LIMIT_ADDRESS_SPACE_SIZE + 1U))) || \ 1422 (((__INSTANCE__) == RISAF21) && ((__ADDRESS__) < (RISAF21_LIMIT_ADDRESS_SPACE_SIZE + 1U))) || \ 1423 (((__INSTANCE__) == RISAF22) && ((__ADDRESS__) < (RISAF22_LIMIT_ADDRESS_SPACE_SIZE + 1U))) || \ 1424 (((__INSTANCE__) == RISAF23) && ((__ADDRESS__) < (RISAF23_LIMIT_ADDRESS_SPACE_SIZE + 1U)))) 1425 #endif /* !defined(NPU_PRESENT) */ 1426 1427 #define IS_RISAF_SUBREGION(__SUBREGION__) (((__SUBREGION__) == RISAF_SUBREGION_A) || \ 1428 ((__SUBREGION__) == RISAF_SUBREGION_B)) 1429 1430 #define IS_RISAF_FILTERING(__FILTERING__) (((__FILTERING__) == RISAF_FILTER_DISABLE) || \ 1431 ((__FILTERING__) == RISAF_FILTER_ENABLE)) 1432 1433 #define IS_RISAF_DELEGATION(__DELEGATION__) (((__DELEGATION__) == RISAF_DELEGATION_DISABLE) || \ 1434 ((__DELEGATION__) == RISAF_DELEGATION_ENABLE)) 1435 1436 1437 #define IS_RISAF_READ_WRITE(__RW__) (((uint32_t)(__RW__) == RISAF_READ_DISABLE) || \ 1438 (((uint32_t)(__RW__) & ~RISAF_READ_WRITE_MASK) == 0x00U)) 1439 /** 1440 * @} 1441 */ 1442 1443 /* Exported functions --------------------------------------------------------*/ 1444 /** @defgroup RIF_Exported_Functions RIF Exported Functions 1445 * @{ 1446 */ 1447 /** @defgroup RIF_Exported_Functions_Group1 RIMC Configuration functions 1448 * @{ 1449 */ 1450 #if defined(CPU_AS_TRUSTED_DOMAIN) 1451 void HAL_RIF_RIMC_Lock(void); 1452 #endif /* CPU_AS_TRUSTED_DOMAIN */ 1453 uint32_t HAL_RIF_RIMC_GetLock(void); 1454 #if defined(CPU_AS_TRUSTED_DOMAIN) 1455 void HAL_RIF_RIMC_SetDebugAccessPortCID(uint32_t CID); 1456 #endif /* CPU_AS_TRUSTED_DOMAIN */ 1457 uint32_t HAL_RIF_RIMC_GetDebugAccessPortCID(void); 1458 #if defined(CPU_AS_TRUSTED_DOMAIN) 1459 void HAL_RIF_RIMC_ConfigMasterAttributes(uint32_t MasterId, const RIMC_MasterConfig_t *pConfig); 1460 void HAL_RIF_RIMC_GetConfigMasterAttributes(uint32_t MasterId, RIMC_MasterConfig_t *pConfig); 1461 #endif /* CPU_AS_TRUSTED_DOMAIN */ 1462 /** 1463 * @} 1464 */ 1465 1466 /** @defgroup RIF_Exported_Functions_Group2 RIFSC Configuration functions 1467 * @{ 1468 */ 1469 #if defined(CPU_AS_TRUSTED_DOMAIN) 1470 void HAL_RIF_RISC_Lock(void); 1471 #endif /* CPU_AS_TRUSTED_DOMAIN */ 1472 uint32_t HAL_RIF_RISC_GetLock(void); 1473 void HAL_RIF_RISC_SetSlaveSecureAttributes(uint32_t PeriphId, uint32_t SecPriv); 1474 uint32_t HAL_RIF_RISC_GetSlaveSecureAttributes(uint32_t PeriphId); 1475 void HAL_RIF_RISC_SlaveConfigLock(uint32_t PeriphId); 1476 uint32_t HAL_RIF_RISC_GetSlaveConfigLock(uint32_t PeriphId); 1477 /** 1478 * @} 1479 */ 1480 1481 /** @defgroup RIF_Exported_Functions_Group4 RISAF Configuration functions 1482 * @{ 1483 */ 1484 #if defined(CPU_AS_TRUSTED_DOMAIN) 1485 void HAL_RIF_RISAF_Lock(RISAF_TypeDef *RISAFx); 1486 #endif /* CPU_AS_TRUSTED_DOMAIN */ 1487 uint32_t HAL_RIF_RISAF_GetLock(const RISAF_TypeDef *RISAFx); 1488 #if defined(CPU_AS_TRUSTED_DOMAIN) 1489 void HAL_RIF_RISAF_ConfigBaseRegion(RISAF_TypeDef *RISAFx, uint32_t Region, 1490 const RISAF_BaseRegionConfig_t *pConfig); 1491 #endif /* CPU_AS_TRUSTED_DOMAIN */ 1492 void HAL_RIF_RISAF_GetConfigBaseRegion(const RISAF_TypeDef *RISAFx, uint32_t Region, 1493 RISAF_BaseRegionConfig_t *pConfig); 1494 #if defined(CPU_AS_TRUSTED_DOMAIN) 1495 void HAL_RIF_RISAF_ConfigSubRegionDelegation(RISAF_TypeDef *RISAFx, uint32_t Region, uint32_t SubRegion, 1496 const RISAF_DelegationConfig_t *pConfig); 1497 #endif /* CPU_AS_TRUSTED_DOMAIN */ 1498 void HAL_RIF_RISAF_GetConfigSubRegionDelegation(const RISAF_TypeDef *RISAFx, uint32_t Region, uint32_t SubRegion, 1499 RISAF_DelegationConfig_t *pConfig); 1500 #if defined(CPU_AS_TRUSTED_DOMAIN) 1501 void HAL_RIF_RISAF_ConfigSubRegion(RISAF_TypeDef *RISAFx, uint32_t Region, uint32_t SubRegion, 1502 const RISAF_SubRegionConfig_t *pConfig); 1503 #endif /* CPU_AS_TRUSTED_DOMAIN */ 1504 void HAL_RIF_RISAF_GetConfigSubRegion(const RISAF_TypeDef *RISAFx, uint32_t Region, uint32_t SubRegion, 1505 RISAF_SubRegionConfig_t *pConfig); 1506 #if defined(CPU_AS_TRUSTED_DOMAIN) 1507 void HAL_RIF_RISAF_GetIllegalAccess(RISAF_TypeDef *RISAFx, RISAF_IllegalAccess_t *IllegalAccess); 1508 #endif /* CPU_AS_TRUSTED_DOMAIN */ 1509 /** 1510 * @} 1511 */ 1512 1513 /** @defgroup RIF_Exported_Functions_Group6 IAC Configuration functions 1514 * @{ 1515 */ 1516 #if defined(CPU_AS_TRUSTED_DOMAIN) && defined(CPU_IN_SECURE_STATE) 1517 void HAL_RIF_IAC_EnableIT(uint32_t PeriphId); 1518 void HAL_RIF_IAC_DisableIT(uint32_t PeriphId); 1519 uint32_t HAL_RIF_IAC_GetFlag(uint32_t PeriphId); 1520 void HAL_RIF_IAC_ClearFlag(uint32_t PeriphId); 1521 void HAL_RIF_IRQHandler(void); 1522 void HAL_RIF_ILA_Callback(uint32_t PeriphId); 1523 #endif /* CPU_AS_TRUSTED_DOMAIN && CPU_IN_SECURE_STATE */ 1524 /** 1525 * @} 1526 */ 1527 1528 /** 1529 * @} 1530 */ 1531 1532 /** 1533 * @} 1534 */ 1535 1536 /** 1537 * @} 1538 */ 1539 1540 #ifdef __cplusplus 1541 } 1542 #endif 1543 1544 #endif /* STM32N6xx_HAL_RIF_H */ 1545 1546
