1 /* 2 * Copyright (c) 2018 Foundries.io Ltd 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7 #ifndef SOC_RISCV32_OPENISA_RV32M1_SOC_RI5CY_H_ 8 #define SOC_RISCV32_OPENISA_RV32M1_SOC_RI5CY_H_ 9 10 /* Control and Status Registers (CSRs) available for RI5CY. */ 11 #define RI5CY_USTATUS 0x000 12 #define RI5CY_UTVEC 0x005 13 #define RI5CY_UHARTID 0x014 14 #define RI5CY_UEPC 0x041 15 #define RI5CY_UCAUSE 0x042 16 #define RI5CY_MSTATUS 0x300 17 #define RI5CY_MTVEC 0x305 18 #define RI5CY_MEPC 0x341 19 #define RI5CY_MCAUSE 0x342 20 #define RI5CY_PCCR0 0x780 21 #define RI5CY_PCCR1 0x781 22 #define RI5CY_PCCR2 0x782 23 #define RI5CY_PCCR3 0x783 24 #define RI5CY_PCCR4 0x784 25 #define RI5CY_PCCR5 0x785 26 #define RI5CY_PCCR6 0x786 27 #define RI5CY_PCCR7 0x787 28 #define RI5CY_PCCR8 0x788 29 #define RI5CY_PCCR9 0x789 30 #define RI5CY_PCCR10 0x78A 31 #define RI5CY_PCCR11 0x78B 32 #define RI5CY_PCER 0x7A0 33 #define RI5CY_PCMR 0x7A1 34 #define RI5CY_LPSTART0 0x7B0 35 #define RI5CY_LPEND0 0x7B1 36 #define RI5CY_LPCOUNT0 0x7B2 37 #define RI5CY_LPSTART1 0x7B4 38 #define RI5CY_LPEND1 0x7B5 39 #define RI5CY_LPCOUNT1 0x7B6 40 #define RI5CY_PRIVLV 0xC10 41 #define RI5CY_MHARTID 0xF14 42 43 #endif /* SOC_RISCV32_OPENISA_RV32M1_SOC_RI5CY_H_ */ 44
