1 /** 2 ****************************************************************************** 3 * @file stm32wb0x_hal_rcc_ex.h 4 * @author MCD Application Team 5 * @brief Header file of RCC HAL Extended module. 6 ****************************************************************************** 7 * @attention 8 * 9 * Copyright (c) 2024 STMicroelectronics. 10 * All rights reserved. 11 * 12 * This software is licensed under terms that can be found in the LICENSE file 13 * in the root directory of this software component. 14 * If no LICENSE file comes with this software, it is provided AS-IS. 15 * 16 ****************************************************************************** 17 */ 18 19 /* Define to prevent recursive inclusion -------------------------------------*/ 20 #ifndef STM32WB0x_HAL_RCC_EX_H 21 #define STM32WB0x_HAL_RCC_EX_H 22 23 #ifdef __cplusplus 24 extern "C" { 25 #endif /* __cplusplus */ 26 27 /* Includes ------------------------------------------------------------------*/ 28 #include "stm32wb0x_hal_def.h" 29 30 31 /** @addtogroup STM32WB0x_HAL_Driver 32 * @{ 33 */ 34 35 /** @addtogroup RCCEx 36 * @{ 37 */ 38 /* Private constants ---------------------------------------------------------*/ 39 /* Private macros ------------------------------------------------------------*/ 40 /** @addtogroup RCCEx_Private_Macros 41 * @{ 42 */ 43 44 #define IS_RCC_LSCOSOURCE(__SOURCE__) (((__SOURCE__) == RCC_LSCOSOURCE_NOCLOCK) || \ 45 ((__SOURCE__) == RCC_LSCOSOURCE_LSI) || \ 46 ((__SOURCE__) == RCC_LSCOSOURCE_LSE)) 47 48 #define IS_RCC_LSCO(__LSCOX__) ( ((__LSCOX__) == RCC_LSCO1) ||\ 49 ((__LSCOX__) == RCC_LSCO2) ||\ 50 ((__LSCOX__) == RCC_LSCO3) ) 51 52 #if defined(STM32WB06) || defined(STM32WB07) 53 #define RCC_PERIPHCLOCK_ALL ( RCC_PERIPHCLK_RF | \ 54 RCC_PERIPHCLK_SMPS | \ 55 RCC_PERIPHCLK_SPI2_I2S | \ 56 RCC_PERIPHCLK_SPI3_I2S | \ 57 RCC_PERIPHCLK_RTC_WDG_BLEWKUP) 58 #elif defined(STM32WB05) || defined(STM32WB09) 59 #define RCC_PERIPHCLOCK_ALL ( RCC_PERIPHCLK_RF | \ 60 RCC_PERIPHCLK_SMPS | \ 61 RCC_PERIPHCLK_SPI3_I2S | \ 62 RCC_PERIPHCLK_LPUART1 | \ 63 RCC_PERIPHCLK_RTC_WDG_BLEWKUP) 64 #else 65 #error "Define device type." 66 #endif 67 #define IS_RCC_PERIPHCLOCK(__SELECTION__) ((((__SELECTION__) & RCC_PERIPHCLOCK_ALL) != 0x00u) && \ 68 (((__SELECTION__) & ~RCC_PERIPHCLOCK_ALL) == 0x00u)) 69 70 #define IS_RCC_RF_BLE_CLOCK_SOURCE(__SOURCE__) \ 71 ((((__SOURCE__) & RCC_RF_CLK_32M) == RCC_RF_CLK_32M) || \ 72 (((__SOURCE__) & RCC_RF_CLK_16M) == RCC_RF_CLK_16M)) 73 74 #define IS_RCC_SMPS_CLOCK_SOURCE(__SOURCE__) \ 75 ((((__SOURCE__) & RCC_SMPSCLKSOURCE_RC64MPLL) == RCC_SMPSCLKSOURCE_RC64MPLL)) 76 77 #define IS_RCC_SMPS_CLOCK_PRESC(__PRESC__) \ 78 ((((__PRESC__) & RCC_SMPSCLK_DIV2) == RCC_SMPSCLK_DIV2) || \ 79 (((__PRESC__) & RCC_SMPSCLK_DIV4) == RCC_SMPSCLK_DIV4)) 80 81 #if defined(SPI2) 82 #define IS_RCC_SPI2I2S_CLOCK_SOURCE(__SOURCE__) \ 83 ((((__SOURCE__) & RCC_SPI2I2S_CLKSOURCE_16M) == RCC_SPI2I2S_CLKSOURCE_16M) || \ 84 (((__SOURCE__) & RCC_SPI2I2S_CLKSOURCE_32M) == RCC_SPI2I2S_CLKSOURCE_32M)) 85 #endif 86 87 #if defined(SPI3) 88 #if defined(STM32WB05) || defined(STM32WB09) 89 #define IS_RCC_SPI3I2S_CLOCK_SOURCE(__SOURCE__) \ 90 ((((__SOURCE__) & RCC_SPI3I2S_CLKSOURCE_16M) == RCC_SPI3I2S_CLKSOURCE_16M) || \ 91 (((__SOURCE__) & RCC_SPI3I2S_CLKSOURCE_32M) == RCC_SPI3I2S_CLKSOURCE_32M) || \ 92 (((__SOURCE__) & RCC_SPI3I2S_CLKSOURCE_64M) == RCC_SPI3I2S_CLKSOURCE_64M)) 93 #else 94 #define IS_RCC_SPI3I2S_CLOCK_SOURCE(__SOURCE__) \ 95 ((((__SOURCE__) & RCC_SPI3I2S_CLKSOURCE_16M) == RCC_SPI3I2S_CLKSOURCE_16M) || \ 96 (((__SOURCE__) & RCC_SPI3I2S_CLKSOURCE_32M) == RCC_SPI3I2S_CLKSOURCE_32M)) 97 #endif 98 #endif 99 100 #if defined(RCC_CFGR_LPUCLKSEL) 101 #define IS_RCC_LPUART1_CLOCK_SOURCE(__SOURCE__) \ 102 ((((__SOURCE__) & RCC_LPUART1_CLKSOURCE_16M) == RCC_LPUART1_CLKSOURCE_16M) || \ 103 (((__SOURCE__) & RCC_LPUART1_CLKSOURCE_LSE) == RCC_LPUART1_CLKSOURCE_LSE)) 104 #endif /* RCC_CFGR_LPUCLKSEL */ 105 106 #define IS_RCC_RTC_WDG_BLEWKUP_CLOCK_SOURCE(__SOURCE__) \ 107 ((((__SOURCE__) & RCC_RTC_WDG_BLEWKUP_CLKSOURCE_LSE) == RCC_RTC_WDG_BLEWKUP_CLKSOURCE_LSE) || \ 108 (((__SOURCE__) & RCC_RTC_WDG_BLEWKUP_CLKSOURCE_LSI) == RCC_RTC_WDG_BLEWKUP_CLKSOURCE_LSI) || \ 109 (((__SOURCE__) & RCC_RTC_WDG_BLEWKUP_CLKSOURCE_HSI64M_DIV2048) == RCC_RTC_WDG_BLEWKUP_CLKSOURCE_HSI64M_DIV2048)) 110 111 #define IS_RCC_TRIMOSC(__OSC_TYPE__) ((((__OSC_TYPE__) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)) 112 113 /** 114 * @} 115 */ 116 117 /* Exported types ------------------------------------------------------------*/ 118 119 /** @defgroup RCCEx_Exported_Types RCCEx Exported Types 120 * @{ 121 */ 122 123 /** 124 * @brief RCC extended clocks structure definition 125 */ 126 typedef struct 127 { 128 uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured. 129 This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */ 130 131 #if defined(SPI2) 132 uint32_t SPI2I2SClockSelection; /*!< Specifies SPI2_I2S clock source. 133 This parameter can be a value of @ref RCCEx_SPI2_I2S_Clock_Source */ 134 #endif 135 #if defined(SPI3) 136 uint32_t SPI3I2SClockSelection; /*!< Specifies SPI3_I2S clock source. 137 This parameter can be a value of @ref RCCEx_SPI3_I2S_Clock_Source */ 138 #endif 139 uint32_t RTCWDGBLEWKUPClockSelection; /*!< Specifies RTC, WDG and BLEWKUP clock source. 140 This parameter can be a value of @ref RCCEx_RTC_WDG_BLEWKUP_Clock_Source */ 141 142 #if defined(RCC_CFGR_LPUCLKSEL) 143 uint32_t LPUART1ClockSelection; /*!< Specifies LPUART1 clock source. 144 This parameter can be a value of @ref RCCEx_LPUART1_Clock_Source */ 145 #endif /* RCC_CFGR_LPUCLKSEL */ 146 147 uint32_t RFClockSelection; /*!< RADIO IP does not use directly the system clock for its APB / AHB 148 interfaces but the system clock with a potential divider (2 or 4). 149 This parameter can be a value of @ref RCC_RF_Clock 150 The supported configurations are: 151 - CLK_SYS = 1 MHz / 2 MHz / 4 MHz / 8 MHz --> Not possible to use RADIO IP 152 - CLK_SYS = 64 MHz / 32 MHz / 16 MHz --> Allow the use of the RADIO IP. 153 The only constraint is that the CLK_SYS shall be bigger or equal than RADIO IP clk */ 154 155 uint32_t SmpsDivSelection; /*!< Specifies SMPS clock prescaling factor. 156 This parameter can be a value of @ref RCCEx_SMPS_Clock_Divider */ 157 158 } RCC_PeriphCLKInitTypeDef; 159 160 161 /** 162 * @} 163 */ 164 165 /* Exported constants --------------------------------------------------------*/ 166 /** @defgroup RCCEx_Exported_Constants RCCEx Exported Constants 167 * @{ 168 */ 169 170 /** @defgroup RCC_LSCO_Index LSCO Index 171 * @{ 172 */ 173 #define RCC_LSCO1 0x00000000U /*!< LSCO1 index */ 174 #define RCC_LSCO2 0x00000001U /*!< LSCO2 index */ 175 #define RCC_LSCO3 0x00000002U /*!< LSCO3 index */ 176 177 /** 178 * @} 179 */ 180 181 /** @defgroup RCC_LSCO_Clock_Source LSCO Clock Source 182 * @{ 183 */ 184 #define RCC_LSCOSOURCE_NOCLOCK LL_RCC_LSCOSOURCE_NOCLOCK /*!< LSCO output disabled, no clock on LSCO */ 185 #define RCC_LSCOSOURCE_LSI LL_RCC_LSCOSOURCE_LSI /*!< LSI selection as LSCO source */ 186 #define RCC_LSCOSOURCE_LSE LL_RCC_LSCOSOURCE_LSE /*!< LSE selection as LSCO source */ 187 /** 188 * @} 189 */ 190 191 192 /** @defgroup RCCEx_Periph_Clock_Selection Periph Clock Selection 193 * @{ 194 */ 195 #define RCC_PERIPHCLK_RF 0x00000001U /*!< RADIO IP Peripheral Clock Selection */ 196 #define RCC_PERIPHCLK_SMPS 0x00000002U /*!< SMPS Peripheral Clock Selection */ 197 #if defined(SPI2) 198 #define RCC_PERIPHCLK_SPI2_I2S 0x00000004U /*!< SPI2 I2S Peripheral Clock Selection */ 199 #endif 200 #if defined(SPI3) 201 #define RCC_PERIPHCLK_SPI3_I2S 0x00000008U /*!< SPI3 I2S Peripheral Clock Selection */ 202 #endif 203 #if defined(RCC_CFGR_LPUCLKSEL) 204 #define RCC_PERIPHCLK_LPUART1 0x00000010U /*!< LPUART1 Peripheral Clock Selection */ 205 #endif /* RCC_CFGR_LPUCLKSEL */ 206 #define RCC_PERIPHCLK_RTC_WDG_BLEWKUP 0x00000020U /*!< RTC WDG SUBG BLE_WKUP Peripheral Clock Selection */ 207 208 209 /** 210 * @} 211 */ 212 213 #if defined(SPI2) 214 /** @defgroup RCCEx_SPI2_I2S_Clock_Source SPI2_I2S Clock Source 215 * @{ 216 */ 217 #define RCC_SPI2I2S_CLKSOURCE_16M LL_RCC_SPI2_I2S_CLK16M /*!< SPI2 I2S 16 MHz clock source selection */ 218 #define RCC_SPI2I2S_CLKSOURCE_32M LL_RCC_SPI2_I2S_CLK32M /*!< SPI2 I2S 32 MHz clock source selection */ 219 /** 220 * @} 221 */ 222 #endif 223 224 #if defined(SPI3) 225 /** @defgroup RCCEx_SPI3_I2S_Clock_Source SPI3_I2S Clock Source 226 * @{ 227 */ 228 #define RCC_SPI3I2S_CLKSOURCE_16M LL_RCC_SPI3_I2S_CLK16M /*!< SPI3 I2S 16 MHz clock source selection */ 229 #define RCC_SPI3I2S_CLKSOURCE_32M LL_RCC_SPI3_I2S_CLK32M /*!< SPI3 I2S 32 MHz clock source selection */ 230 #if defined(STM32WB05) || defined(STM32WB09) 231 #define RCC_SPI3I2S_CLKSOURCE_64M LL_RCC_SPI3_I2S_CLK64M /*!< SPI3 I2S 64 MHz clock source selection */ 232 #endif 233 /** 234 * @} 235 */ 236 #endif 237 238 #if defined(RCC_CFGR_LPUCLKSEL) 239 /** @defgroup RCCEx_LPUART1_Clock_Source LPUART1 Clock Source 240 * @{ 241 */ 242 #define RCC_LPUART1_CLKSOURCE_16M LL_RCC_LPUCLKSEL_CLK16M /*!< LPUART1 16 MHz clock source selection */ 243 #define RCC_LPUART1_CLKSOURCE_LSE LL_RCC_LPUCLKSEL_CLKLSE /*!< LPUART1 LSE clock source selection */ 244 /** 245 * @} 246 */ 247 #endif /* RCC_CFGR_LPUCLKSEL */ 248 249 /** @defgroup RCCEx_SMPS_Clock_Divider SMPS clock prescaling factor 250 * @{ 251 */ 252 #define RCC_SMPSCLK_DIV2 LL_RCC_SMPS_DIV_2 /*!< SMPS clock division 2 (SMPS clock is 8 MHz if ANADIV = 1)*/ 253 #define RCC_SMPSCLK_DIV4 LL_RCC_SMPS_DIV_4 /*!< SMPS clock division 4 (SMPS clock is 4 MHz if ANADIV = 1)*/ 254 /** 255 * @} 256 */ 257 258 /** @defgroup RCCEx_RTC_WDG_BLEWKUP_Clock_Source RTC, WDG, BLEWKUP Clock Source 259 * @{ 260 */ 261 #define RCC_RTC_WDG_BLEWKUP_CLKSOURCE_LSE LL_RCC_LSCO_CLKSOURCE_LSE /*!< RTC, WDG and BLEWKUP LSE clock source selection */ 262 #define RCC_RTC_WDG_BLEWKUP_CLKSOURCE_LSI LL_RCC_LSCO_CLKSOURCE_LSI /*!< RTC, WDG and BLEWKUP LSI clock source selection */ 263 #define RCC_RTC_WDG_BLEWKUP_CLKSOURCE_HSI64M_DIV2048 LL_RCC_LSCO_CLKSOURCE_HSI64M_DIV2048 /*!< RTC, WDG and BLEWKUP 32K clock source selection */ 264 265 /** 266 * @} 267 */ 268 269 270 /** 271 * @} 272 */ 273 274 /* Exported macros -----------------------------------------------------------*/ 275 /** @defgroup RCCEx_Exported_Macros RCCEx Exported Macros 276 * @{ 277 */ 278 279 /** 280 * @brief Macro to configure the LSCO clock. 281 * @param __LSCOCLKSOURCE__ specifies the LSCO clock source. 282 * This parameter can be one of the following values: 283 * @arg @ref RCC_LSCOSOURCE_NOCLOCK LSCO output disabled 284 * @arg @ref RCC_LSCOSOURCE_LSI LSI clock selected as LSCO source 285 * @arg @ref RCC_LSCOSOURCE_LSE LSE clock selected as LSCO source 286 */ 287 #define __HAL_RCC_LSCO_CONFIG(__LSCOCLKSOURCE__) LL_RCC_ConfigLSCO((__LSCOCLKSOURCE__)) 288 289 /** @brief Macro to configure the SMPS clock prescaling factor. 290 * 291 * @param __SMPSCLKDIV__ specifies the division factor for SMPS clock. 292 * This parameter can be one of the following values: 293 * @arg @ref RCC_SMPSCLK_DIV2 SMPS clock division 2 (SMPS clock is 8 MHz) 294 * @arg @ref RCC_SMPSCLK_DIV4 SMPS clock division 4 (SMPS clock is 4 MHz) 295 * 296 * @retval None 297 */ 298 #define __HAL_RCC_SMPS_DIV_CONFIG(__SMPSCLKDIV__) LL_RCC_SetSMPSPrescaler(__SMPSCLKDIV__) 299 300 /** @brief Macro to get the SMPS clock prescaling factor. 301 * 302 * This parameter can be one of the following values: 303 * @arg @ref RCC_SMPSCLK_DIV2 SMPS clock division 2 (SMPS clock is 8 MHz) 304 * @arg @ref RCC_SMPSCLK_DIV4 SMPS clock division 4 (SMPS clock is 4 MHz) 305 * 306 */ 307 #define __HAL_RCC_GET_SMPS_DIV() LL_RCC_GetSMPSPrescaler() 308 309 #if defined(SPI2) 310 /** @brief Macro to configure the SPI2_I2S clock. 311 * 312 * @param __SPI2I2S_CLKSOURCE__ specifies the SPI2I2S clock source. 313 * This parameter can be one of the following values: 314 * @arg @ref RCC_SPI2I2S_CLKSOURCE_16M 315 * @arg @ref RCC_SPI2I2S_CLKSOURCE_32M 316 * @retval None 317 */ 318 #define __HAL_RCC_SPI2I2S_CLK_CONFIG(__SPI2I2S_CLKSOURCE__) LL_RCC_SetSPI2I2SClockSource(__SPI2I2S_CLKSOURCE__) 319 320 /** @brief Macro to get the SPI2_I2S clock source. 321 * @retval The clock source can be one of the following values: 322 * @arg @ref RCC_SPI2I2S_CLKSOURCE_16M 323 * @arg @ref RCC_SPI2I2S_CLKSOURCE_32M 324 */ 325 #define __HAL_RCC_GET_SPI2I2S_CLK_CONFIG() LL_RCC_GetSPI2I2SClockSource() 326 #endif 327 328 #if defined(SPI3) 329 /** @brief Macro to configure the SPI3_I2S clock. 330 * 331 * @param __SPI3I2S_CLKSOURCE__ specifies the SPI3I2S clock source. 332 * This parameter can be one of the following values: 333 * @arg @ref RCC_SPI3I2S_CLKSOURCE_16M 334 * @arg @ref RCC_SPI3I2S_CLKSOURCE_32M 335 * @arg @ref RCC_SPI3I2S_CLKSOURCE_64M 336 * @retval None 337 */ 338 #define __HAL_RCC_SPI3I2S_CLK_CONFIG(__SPI3I2S_CLKSOURCE__) LL_RCC_SetSPI3I2SClockSource(__SPI3I2S_CLKSOURCE__) 339 340 /** @brief Macro to get the SPI3_I2S clock source. 341 * @retval The clock source can be one of the following values: 342 * @arg @ref RCC_SPI3I2S_CLKSOURCE_16M 343 * @arg @ref RCC_SPI3I2S_CLKSOURCE_32M 344 * @arg @ref RCC_SPI3I2S_CLKSOURCE_64M 345 */ 346 #define __HAL_RCC_GET_SPI3I2S_CLK_CONFIG() LL_RCC_GetSPI3I2SClockSource() 347 #endif 348 349 #if defined(RCC_CFGR_LPUCLKSEL) 350 /** @brief Macro to configure the LPUART1 clock. 351 * 352 * @param __LPUART1_CLKSOURCE__ specifies the LPUART1 clock source. 353 * This parameter can be one of the following values: 354 * @arg @ref RCC_LPUART1_CLKSOURCE_16M 355 * @arg @ref RCC_LPUART1_CLKSOURCE_LSE 356 * @retval None 357 */ 358 #define __HAL_RCC_LPUART1_CLK_CONFIG(__LPUART1_CLKSOURCE__) LL_RCC_SetLPUARTClockSource(__LPUART1_CLKSOURCE__) 359 360 /** @brief Macro to get the LPUART1 clock source. 361 * @retval The clock source can be one of the following values: 362 * @arg @ref RCC_LPUART1_CLKSOURCE_16M 363 * @arg @ref RCC_LPUART1_CLKSOURCE_LSE 364 */ 365 #define __HAL_RCC_GET_LPUART1_CLK_CONFIG() LL_RCC_GetLPUARTClockSource() 366 #endif /* RCC_CFGR_LPUCLKSEL */ 367 368 369 /** @brief Macro to configure the RTC, WDG and BLEWKUP clock source. 370 * 371 * @param __RTC_WDG_BLEWKUP_CLKSOURCE__ specifies the RTC, WDG and BLEWKUP clock source. 372 * This parameter can be one of the following values: 373 * @arg @ref RCC_RTC_WDG_BLEWKUP_CLKSOURCE_LSE 374 * @arg @ref RCC_RTC_WDG_BLEWKUP_CLKSOURCE_LSI 375 * @arg @ref RCC_RTC_WDG_BLEWKUP_CLKSOURCE_HSI64M_DIV2048 376 * @retval None 377 */ 378 #define __HAL_RCC_RTC_WDG_BLEWKUP_CLK_CONFIG( __RTC_WDG_BLEWKUP_CLKSOURCE__ ) LL_RCC_LSCO_SetSource( __RTC_WDG_BLEWKUP_CLKSOURCE__ ) 379 380 /** @brief Macro to get the RTC, WDG and BLEWKUP clock source. 381 * @retval The clock source can be one of the following values: 382 * @arg @ref RCC_RTC_WDG_BLEWKUP_CLKSOURCE_LSE 383 * @arg @ref RCC_RTC_WDG_BLEWKUP_CLKSOURCE_LSI 384 * @arg @ref RCC_RTC_WDG_BLEWKUP_CLKSOURCE_HSI64M_DIV2048 385 */ 386 #define __HAL_RCC_GET_RTC_WDG_BLEWKUP_CLK_CONFIG() LL_RCC_LSCO_GetSource() 387 388 /** 389 * @} 390 */ 391 392 /* Exported functions --------------------------------------------------------*/ 393 /** @addtogroup RCCEx_Exported_Functions 394 * @{ 395 */ 396 397 /** @addtogroup RCCEx_Exported_Functions_Group1 398 * @{ 399 */ 400 401 HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit); 402 void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit); 403 uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk); 404 405 /** 406 * @} 407 */ 408 409 /** @addtogroup RCCEx_Exported_Functions_Group2 410 * @{ 411 */ 412 413 void HAL_RCCEx_EnableLSCO(uint32_t RCC_LSCOx, uint32_t RCC_LSCOSource); 414 void HAL_RCCEx_DisableLSCO(void); 415 void HAL_RCCEx_EnableLSCOinDEEPSTOP(uint32_t LSCOSource); 416 417 HAL_StatusTypeDef HAL_RCCEx_TrimOsc(uint32_t OscillatorType); 418 419 /** 420 * @} 421 */ 422 423 /** 424 * @} 425 */ 426 427 /** 428 * @} 429 */ 430 431 /** 432 * @} 433 */ 434 435 #ifdef __cplusplus 436 } 437 #endif /* __cplusplus */ 438 439 #endif /* STM32WB0x_HAL_RCC_EX_H */ 440
