1 /* 2 * Copyright (c) 2016, The OpenThread Authors. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are met: 7 * 1. Redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer. 9 * 2. Redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution. 12 * 3. Neither the name of the copyright holder nor the 13 * names of its contributors may be used to endorse or promote products 14 * derived from this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 17 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 20 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26 * POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 /** 30 * @file 31 * This file includes CC2538 register definitions. 32 * 33 */ 34 35 #ifndef CC2538_REG_H_ 36 #define CC2538_REG_H_ 37 38 #include <stdint.h> 39 40 // clang-format off 41 42 #define HWREG(x) (*((volatile uint32_t *)(x))) 43 44 /*! 45 * For registers that are arrays of 32-bit integers. 46 * 47 * @param reg Register address 48 * @param idx Register array index 49 */ 50 #define HWREG_ARR(reg, idx) HWREG((reg) + ((idx) << 2)) 51 52 #define NVIC_ST_CTRL 0xE000E010 // SysTick Control and Status 53 #define NVIC_ST_RELOAD 0xE000E014 // SysTick Reload Value Register 54 #define NVIC_EN0 0xE000E100 // Interrupt 0-31 Set Enable 55 56 #define NVIC_ST_CTRL_COUNT 0x00010000 // Count Flag 57 #define NVIC_ST_CTRL_CLK_SRC 0x00000004 // Clock Source 58 #define NVIC_ST_CTRL_INTEN 0x00000002 // Interrupt Enable 59 #define NVIC_ST_CTRL_ENABLE 0x00000001 // Enable 60 61 #define RFCORE_XREG_SRCMATCH_EN 0x00000001 // SRCMATCH.SRC_MATCH_EN(1) 62 #define RFCORE_XREG_SRCMATCH_AUTOPEND 0x00000002 // SRCMATCH.AUTOPEND(1) 63 #define RFCORE_XREG_SRCMATCH_PEND_DATAREQ_ONLY 0x00000004 // SRCMATCH.PEND_DATAREQ_ONLY(1) 64 65 #define RFCORE_XREG_SRCMATCH_ENABLE_STATUS_SIZE 3 // Num of register for source match enable status 66 #define RFCORE_XREG_SRCMATCH_SHORT_ENTRIES 24 // 24 short address entries in maximum 67 #define RFCORE_XREG_SRCMATCH_EXT_ENTRIES 12 // 12 extended address entries in maximum 68 #define RFCORE_XREG_SRCMATCH_SHORT_ENTRY_OFFSET 4 // address offset for one short address entry 69 #define RFCORE_XREG_SRCMATCH_EXT_ENTRY_OFFSET 8 // address offset for one extended address entry 70 71 #define INT_UART0 21 // UART0 Rx and Tx 72 73 #define IEEE_EUI64 0x00280028 // Address of IEEE EUI-64 address 74 75 #define RFCORE_FFSM_SRCADDRESS_TABLE 0x40088400 // Source Address Table 76 77 #define RFCORE_FFSM_SRCEXTPENDEN0 0x40088590 // Enable/Disable automatic pending per extended address 78 #define RFCORE_FFSM_SRCSHORTPENDEN0 0x4008859C // Enable/Disable automatic pending per short address 79 #define RFCORE_FFSM_EXT_ADDR0 0x400885A8 // Local address information 80 #define RFCORE_FFSM_PAN_ID0 0x400885C8 // Local address information 81 #define RFCORE_FFSM_PAN_ID1 0x400885CC // Local address information 82 #define RFCORE_FFSM_SHORT_ADDR0 0x400885D0 // Local address information 83 #define RFCORE_FFSM_SHORT_ADDR1 0x400885D4 // Local address information 84 #define RFCORE_XREG_FRMFILT0 0x40088600 // The frame filtering function 85 #define RFCORE_XREG_SRCMATCH 0x40088608 // Source address matching and pending bits 86 #define RFCORE_XREG_SRCSHORTEN0 0x4008860C // Short address matching 87 #define RFCORE_XREG_SRCEXTEN0 0x40088618 // Extended address matching 88 89 #define RFCORE_XREG_FRMCTRL0 0x40088624 // Frame handling 90 #define RFCORE_XREG_FRMCTRL1 0x40088628 // Frame handling 91 #define RFCORE_XREG_RXENABLE 0x4008862C // RX enabling 92 #define RFCORE_XREG_FREQCTRL 0x4008863C // Controls the RF frequency 93 #define RFCORE_XREG_TXPOWER 0x40088640 // Controls the output power 94 #define RFCORE_XREG_FSMSTAT0 0x40088648 // Radio finite state machine status 95 #define RFCORE_XREG_FSMSTAT1 0x4008864C // Radio status register 96 #define RFCORE_XREG_FIFOPCTRL 0x40088650 // FIFOP threshold 97 #define RFCORE_XREG_CCACTRL0 0x40088658 // CCA threshold 98 #define RFCORE_XREG_RSSI 0x40088660 // RSSI status register 99 #define RFCORE_XREG_RSSISTAT 0x40088664 // RSSI valid status register 100 #define RFCORE_XREG_AGCCTRL1 0x400886C8 // AGC reference level 101 #define RFCORE_XREG_RFC_OBS_CTRL 0x400887AC // RF Core observable output 102 #define RFCORE_XREG_TXFILTCFG 0x400887E8 // TX filter configuration 103 #define RFCORE_XREG_RFRND 0x4008869C // Random data 104 #define RFCORE_SFR_RFDATA 0x40088828 // The TX FIFO and RX FIFO 105 #define RFCORE_SFR_RFERRF 0x4008882C // RF error interrupt flags 106 #define RFCORE_SFR_RFIRQF0 0x40088834 // RF interrupt flags 107 #define RFCORE_SFR_RFST 0x40088838 // RF CSMA-CA/strobe processor 108 #define CCTEST_OBSSEL 0x44010014 // CCTEST observable output route 109 110 #define RFCORE_XREG_FRMFILT0_FRAME_FILTER_EN 0x00000001 // Enables frame filtering 111 112 #define RFCORE_XREG_FRMCTRL0_AUTOACK 0x00000020 113 #define RFCORE_XREG_FRMCTRL0_ENERGY_SCAN 0x00000010 114 #define RFCORE_XREG_FRMCTRL0_AUTOCRC 0x00000040 115 #define RFCORE_XREG_FRMCTRL0_INFINITY_RX 0x00000008 116 117 #define RFCORE_XREG_FRMCTRL1_PENDING_OR 0x00000004 118 119 #define RFCORE_XREG_RFRND_IRND 0x00000001 120 121 #define RFCORE_XREG_FSMSTAT0_STATE_MASK 0x0000003F 122 #define RFCORE_XREG_FSMSTAT0_CAL_DONE 0x00000080 123 #define RFCORE_XREG_FSMSTAT0_CAL_RUN 0x00000040 124 125 #define RFCORE_XREG_FSMSTAT0_STATE_IDLE 0x00000000 126 #define RFCORE_XREG_FSMSTAT0_STATE_RX_CAL 0x00000002 127 #define RFCORE_XREG_FSMSTAT0_STATE_SFD_WAIT0 0x00000003 128 #define RFCORE_XREG_FSMSTAT0_STATE_SFD_WAIT1 0x00000004 129 #define RFCORE_XREG_FSMSTAT0_STATE_SFD_WAIT2 0x00000005 130 #define RFCORE_XREG_FSMSTAT0_STATE_SFD_WAIT3 0x00000006 131 #define RFCORE_XREG_FSMSTAT0_STATE_RX0 0x00000007 132 #define RFCORE_XREG_FSMSTAT0_STATE_RX1 0x00000008 133 #define RFCORE_XREG_FSMSTAT0_STATE_RX2 0x00000009 134 #define RFCORE_XREG_FSMSTAT0_STATE_RX3 0x0000000A 135 #define RFCORE_XREG_FSMSTAT0_STATE_RX4 0x0000000B 136 #define RFCORE_XREG_FSMSTAT0_STATE_RX5 0x0000000C 137 #define RFCORE_XREG_FSMSTAT0_STATE_RX6 0x0000000D 138 #define RFCORE_XREG_FSMSTAT0_STATE_RX_WAIT 0x0000000E 139 #define RFCORE_XREG_FSMSTAT0_STATE_RX_FRST 0x00000010 140 #define RFCORE_XREG_FSMSTAT0_STATE_RX_OVER 0x00000011 141 #define RFCORE_XREG_FSMSTAT0_STATE_TX_CAL 0x00000020 142 #define RFCORE_XREG_FSMSTAT0_STATE_TX0 0x00000022 143 #define RFCORE_XREG_FSMSTAT0_STATE_TX1 0x00000023 144 #define RFCORE_XREG_FSMSTAT0_STATE_TX2 0x00000024 145 #define RFCORE_XREG_FSMSTAT0_STATE_TX3 0x00000025 146 #define RFCORE_XREG_FSMSTAT0_STATE_TX4 0x00000026 147 #define RFCORE_XREG_FSMSTAT0_STATE_TX_FINAL 0x00000027 148 #define RFCORE_XREG_FSMSTAT0_STATE_RXTX_TRANS 0x00000028 149 #define RFCORE_XREG_FSMSTAT0_STATE_ACK_CAL 0x00000030 150 #define RFCORE_XREG_FSMSTAT0_STATE_ACK0 0x00000031 151 #define RFCORE_XREG_FSMSTAT0_STATE_ACK1 0x00000032 152 #define RFCORE_XREG_FSMSTAT0_STATE_ACK2 0x00000033 153 #define RFCORE_XREG_FSMSTAT0_STATE_ACK3 0x00000034 154 #define RFCORE_XREG_FSMSTAT0_STATE_ACK4 0x00000035 155 #define RFCORE_XREG_FSMSTAT0_STATE_ACK5 0x00000036 156 #define RFCORE_XREG_FSMSTAT0_STATE_ACK_DELAY 0x00000037 157 #define RFCORE_XREG_FSMSTAT0_STATE_TX_UNDER 0x00000038 158 #define RFCORE_XREG_FSMSTAT0_STATE_TX_DOWN0 0x0000001A 159 #define RFCORE_XREG_FSMSTAT0_STATE_TX_DOWN1 0x0000003A 160 161 #define RFCORE_XREG_FSMSTAT1_RX_ACTIVE 0x00000001 162 #define RFCORE_XREG_FSMSTAT1_TX_ACTIVE 0x00000002 163 #define RFCORE_XREG_FSMSTAT1_LOCK_STATUS 0x00000004 164 #define RFCORE_XREG_FSMSTAT1_SAMPLED_CCA 0x00000008 165 #define RFCORE_XREG_FSMSTAT1_CCA 0x00000010 // Clear channel assessment 166 #define RFCORE_XREG_FSMSTAT1_SFD 0x00000020 167 #define RFCORE_XREG_FSMSTAT1_FIFOP 0x00000040 168 #define RFCORE_XREG_FSMSTAT1_FIFO 0x00000080 169 170 #define RFCORE_XREG_RSSISTAT_RSSI_VALID 0x00000001 // RSSI value is valid. 171 172 #define RFCORE_XREG_RFC_OBS_POL_INV 0x00000040 // Invert polarity of OBS signal 173 #define RFCORE_XREG_RFC_OBS_MUX_ZERO 0x00000000 // Observable = constant zero 174 #define RFCORE_XREG_RFC_OBS_MUX_ONE 0x00000001 // Observable = constant one 175 #define RFCORE_XREG_RFC_OBS_MUX_SNIFF_DATA 0x00000008 // RFC sniff data 176 #define RFCORE_XREG_RFC_OBS_MUX_SNIFF_CLK 0x00000009 // RFC sniff clock 177 #define RFCORE_XREG_RFC_OBS_MUX_RSSI_VALID 0x0000000c // RSSI valid 178 #define RFCORE_XREG_RFC_OBS_MUX_DEMOD_CCA 0x0000000d // Clear channel assessment 179 #define RFCORE_XREG_RFC_OBS_MUX_SAMPLED_CCA 0x0000000e // Sampled CCA signal 180 #define RFCORE_XREG_RFC_OBS_MUX_SFD_SYNC 0x0000000f // SFD received or transmitted 181 #define RFCORE_XREG_RFC_OBS_MUX_TX_ACTIVE 0x00000010 // Transmitter is active 182 #define RFCORE_XREG_RFC_OBS_MUX_RX_ACTIVE 0x00000011 // Receiver is active 183 #define RFCORE_XREG_RFC_OBS_MUX_FFCTRL_FIFO 0x00000012 // One or more bytes in FIFO 184 #define RFCORE_XREG_RFC_OBS_MUX_FFCTRL_FIFOP 0x00000013 // One or more frames in FIFO 185 #define RFCORE_XREG_RFC_OBS_MUX_PACKET_DONE 0x00000014 // Packet received 186 #define RFCORE_XREG_RFC_OBS_MUX_RFC_XOR_RAND_IQ 0x00000016 // RAND I ^ RAND Q 187 #define RFCORE_XREG_RFC_OBS_MUX_RFC_RAND_Q 0x00000017 // Random data from Q channel 188 #define RFCORE_XREG_RFC_OBS_MUX_RFC_RAND_I 0x00000018 // Random data from I channel 189 #define RFCORE_XREG_RFC_OBS_MUX_LOCK_STATUS 0x00000019 // PLL is in lock 190 #define RFCORE_XREG_RFC_OBS_MUX_PA_PD 0x00000028 // Power amp power down 191 #define RFCORE_XREG_RFC_OBS_MUX_LNA_PD 0x0000002a // LNA power down 192 193 #define RFCORE_SFR_RFERRF_NLOCK 0x00000001 // Failed to achieve PLL lock. 194 #define RFCORE_SFR_RFERRF_RXABO 0x00000002 // RX Aborted. 195 #define RFCORE_SFR_RFERRF_RXOVERF 0x00000004 // RX FIFO overflowed. 196 #define RFCORE_SFR_RFERRF_RXUNDERF 0x00000008 // RX FIFO underflowed. 197 #define RFCORE_SFR_RFERRF_TXOVERF 0x00000010 // TX FIFO overflowed. 198 #define RFCORE_SFR_RFERRF_TXUNDERF 0x00000020 // TX FIFO underflowed. 199 #define RFCORE_SFR_RFERRF_STROBEERR 0x00000040 // Command Strobe Error. 200 201 #define RFCORE_SFR_RFST_INSTR_RXON 0xE3 // Instruction set RX on 202 #define RFCORE_SFR_RFST_INSTR_TXON 0xE9 // Instruction set TX on 203 #define RFCORE_SFR_RFST_INSTR_RFOFF 0xEF // Instruction set RF off 204 #define RFCORE_SFR_RFST_INSTR_FLUSHRX 0xED // Instruction set flush rx buffer 205 #define RFCORE_SFR_RFST_INSTR_FLUSHTX 0xEE // Instruction set flush tx buffer 206 207 #define CCTEST_OBSSEL_EN 0x00000080 // Enable the OBS output on this pin 208 #define CCTEST_OBSSEL_SEL_OBS0 0x00000000 // Route OBS0 to pin 209 #define CCTEST_OBSSEL_SEL_OBS1 0x00000001 // Route OBS1 to pin 210 #define CCTEST_OBSSEL_SEL_OBS2 0x00000002 // Route OBS2 to pin 211 212 #define ANA_REGS_BASE 0x400D6000 // ANA_REGS 213 #define ANA_REGS_O_IVCTRL 0x00000004 // Analog control register 214 215 #define SYS_CTRL_CLOCK_CTRL 0x400D2000 // The clock control register 216 #define SYS_CTRL_SYSDIV_32MHZ 0x00000000 // Sys_div for sysclk 32MHz 217 #define SYS_CTRL_CLOCK_CTRL_AMP_DET 0x00200000 218 219 #define SYS_CTRL_PWRDBG 0x400D2074 220 #define SYS_CTRL_PWRDBG_FORCE_WARM_RESET 0x00000008 221 222 #define SYS_CTRL_RCGCUART 0x400D2028 223 #define SYS_CTRL_SCGCUART 0x400D202C 224 #define SYS_CTRL_DCGCUART 0x400D2030 225 #define SYS_CTRL_I_MAP 0x400D2098 226 #define SYS_CTRL_RCGCRFC 0x400D20A8 227 #define SYS_CTRL_SCGCRFC 0x400D20AC 228 #define SYS_CTRL_DCGCRFC 0x400D20B0 229 #define SYS_CTRL_EMUOVR 0x400D20B4 230 231 #define SYS_CTRL_RCGCRFC_RFC0 0x00000001 232 #define SYS_CTRL_SCGCRFC_RFC0 0x00000001 233 #define SYS_CTRL_DCGCRFC_RFC0 0x00000001 234 235 #define SYS_CTRL_I_MAP_ALTMAP 0x00000001 236 237 #define SYS_CTRL_RCGCUART_UART0 0x00000001 238 #define SYS_CTRL_SCGCUART_UART0 0x00000001 239 #define SYS_CTRL_DCGCUART_UART0 0x00000001 240 241 #define SYS_CTRL_RCGCUART_UART1 0x00000002 242 #define SYS_CTRL_SCGCUART_UART1 0x00000002 243 #define SYS_CTRL_DCGCUART_UART1 0x00000002 244 245 #define IOC_PA0_SEL 0x400D4000 // Peripheral select control 246 #define IOC_PA1_SEL 0x400D4004 // Peripheral select control 247 #define IOC_PA2_SEL 0x400D4008 248 #define IOC_PA3_SEL 0x400D400C 249 #define IOC_UARTRXD_UART0 0x400D4100 250 #define IOC_UARTRXD_UART1 0x400D4108 251 252 #define IOC_PA0_OVER 0x400D4080 253 #define IOC_PA1_OVER 0x400D4084 254 #define IOC_PA2_OVER 0x400D4088 255 #define IOC_PA3_OVER 0x400D408C 256 257 #define IOC_MUX_OUT_SEL_UART0_TXD 0x00000000 258 #define IOC_MUX_OUT_SEL_UART1_TXD 0x00000002 259 260 #define IOC_OVERRIDE_OE 0x00000008 // PAD Config Override Output Enable 261 #define IOC_OVERRIDE_DIS 0x00000000 // PAD Config Override Disabled 262 263 #define IOC_PAD_IN_SEL_PA0 0x00000000 // PA0 264 #define IOC_PAD_IN_SEL_PA1 0x00000001 // PA1 265 #define IOC_PAD_IN_SEL_PA2 0x00000002 // PA2 266 #define IOC_PAD_IN_SEL_PA3 0x00000003 // PA3 267 268 #define UART0_BASE 0x4000C000 269 #define UART1_BASE 0x4000D000 270 #define GPIO_A_BASE 0x400D9000 // GPIO A 271 #define GPIO_B_BASE 0x400DA000 // GPIO B 272 #define GPIO_C_BASE 0x400DB000 // GPIO C 273 #define GPIO_D_BASE 0x400DC000 // GPIO D 274 275 #define GPIO_O_DIR 0x00000400 276 #define GPIO_O_AFSEL 0x00000420 277 278 #define GPIO_PIN(x) (1UL << x) // Arbitrary GPIO pin 279 #define GPIO_PIN_0 0x00000001 // GPIO pin 0 280 #define GPIO_PIN_1 0x00000002 // GPIO pin 1 281 #define GPIO_PIN_2 0x00000004 // GPIO pin 2 282 #define GPIO_PIN_3 0x00000008 // GPIO pin 3 283 #define GPIO_PIN_4 0x00000010 // GPIO pin 4 284 #define GPIO_PIN_5 0x00000020 // GPIO pin 5 285 #define GPIO_PIN_6 0x00000040 // GPIO pin 6 286 #define GPIO_PIN_7 0x00000080 // GPIO pin 7 287 288 #define UART_O_DR 0x00000000 // UART data 289 #define UART_O_FR 0x00000018 // UART flag 290 #define UART_O_IBRD 0x00000024 291 #define UART_O_FBRD 0x00000028 292 #define UART_O_LCRH 0x0000002C 293 #define UART_O_CTL 0x00000030 // UART control 294 #define UART_O_IM 0x00000038 // UART interrupt mask 295 #define UART_O_MIS 0x00000040 // UART masked interrupt status 296 #define UART_O_ICR 0x00000044 // UART interrupt clear 297 #define UART_O_CC 0x00000FC8 // UART clock configuration 298 299 #define UART_FR_RXFE 0x00000010 // UART receive FIFO empty 300 #define UART_FR_TXFF 0x00000020 // UART transmit FIFO full 301 #define UART_FR_RXFF 0x00000040 // UART receive FIFO full 302 303 #define UART_CONFIG_WLEN_8 0x00000060 // 8 bit data 304 #define UART_CONFIG_STOP_ONE 0x00000000 // One stop bit 305 #define UART_CONFIG_PAR_NONE 0x00000000 // No parity 306 307 #define UART_CTL_UARTEN 0x00000001 // UART enable 308 #define UART_CTL_TXE 0x00000100 // UART transmit enable 309 #define UART_CTL_RXE 0x00000200 // UART receive enable 310 311 #define UART_IM_RXIM 0x00000010 // UART receive interrupt mask 312 #define UART_IM_RTIM 0x00000040 // UART receive time-out interrupt 313 314 #define SOC_ADC_ADCCON1 0x400D7000 // ADC Control 315 #define SOC_ADC_RNDL 0x400D7014 // RNG low data 316 #define SOC_ADC_RNDH 0x400D7018 // RNG high data 317 318 #define SOC_ADC_ADCCON1_RCTRL0 0x00000004 // ADCCON1 RCTRL bit 0 319 #define SOC_ADC_ADCCON1_RCTRL1 0x00000008 // ADCCON1 RCTRL bit 1 320 321 #define FLASH_CTRL_FCTL 0x400D3008 // Flash control 322 #define FLASH_CTRL_DIECFG0 0x400D3014 // Flash information 323 324 // clang-format on 325 326 #endif 327
