1 /***************************************************************************//** 2 * \file cyip_srss.h 3 * 4 * \brief 5 * SRSS IP definitions 6 * 7 ******************************************************************************** 8 * \copyright 9 * (c) (2016-2024), Cypress Semiconductor Corporation (an Infineon company) or 10 * an affiliate of Cypress Semiconductor Corporation. 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 *******************************************************************************/ 26 27 #ifndef _CYIP_SRSS_H_ 28 #define _CYIP_SRSS_H_ 29 30 #include "cyip_headers.h" 31 32 /******************************************************************************* 33 * SRSS 34 *******************************************************************************/ 35 36 #define CSV_HF_CSV_SECTION_SIZE 0x00000010UL 37 #define CSV_HF_SECTION_SIZE 0x00000100UL 38 #define CSV_REF_CSV_SECTION_SIZE 0x00000010UL 39 #define CSV_REF_SECTION_SIZE 0x00000010UL 40 #define CSV_LF_CSV_SECTION_SIZE 0x00000010UL 41 #define CSV_LF_SECTION_SIZE 0x00000010UL 42 #define CSV_ILO_CSV_SECTION_SIZE 0x00000010UL 43 #define CSV_ILO_SECTION_SIZE 0x00000010UL 44 #define CLK_PLL400M_SECTION_SIZE 0x00000010UL 45 #define CLK_DPLL_LP_SECTION_SIZE 0x00000020UL 46 #define RAM_TRIM_SECTION_SIZE 0x00000008UL 47 #define CLK_TRIM_DPLL_LP_SECTION_SIZE 0x00000020UL 48 #define MCWDT_STRUCT_SECTION_SIZE 0x00000040UL 49 #define SRSS_SECTION_SIZE 0x00010000UL 50 51 /** 52 * \brief Active domain Clock Supervisor (CSV) registers (CSV_HF_CSV) 53 */ 54 typedef struct { 55 __IOM uint32_t REF_CTL; /*!< 0x00000000 Clock Supervision Reference Control */ 56 __IOM uint32_t REF_LIMIT; /*!< 0x00000004 Clock Supervision Reference Limits */ 57 __IOM uint32_t MON_CTL; /*!< 0x00000008 Clock Supervision Monitor Control */ 58 __IM uint32_t RESERVED; 59 } CSV_HF_CSV_Type; /*!< Size = 16 (0x10) */ 60 61 /** 62 * \brief Clock Supervisor (CSV) registers for Root clocks (CSV_HF) 63 */ 64 typedef struct { 65 CSV_HF_CSV_Type CSV[16]; /*!< 0x00000000 Active domain Clock Supervisor (CSV) registers */ 66 } CSV_HF_Type; /*!< Size = 256 (0x100) */ 67 68 /** 69 * \brief Active domain Clock Supervisor (CSV) registers for CSV Reference clock (CSV_REF_CSV) 70 */ 71 typedef struct { 72 __IOM uint32_t REF_CTL; /*!< 0x00000000 Clock Supervision Reference Control */ 73 __IOM uint32_t REF_LIMIT; /*!< 0x00000004 Clock Supervision Reference Limits */ 74 __IOM uint32_t MON_CTL; /*!< 0x00000008 Clock Supervision Monitor Control */ 75 __IM uint32_t RESERVED; 76 } CSV_REF_CSV_Type; /*!< Size = 16 (0x10) */ 77 78 /** 79 * \brief CSV registers for the CSV Reference clock (CSV_REF) 80 */ 81 typedef struct { 82 CSV_REF_CSV_Type CSV; /*!< 0x00000000 Active domain Clock Supervisor (CSV) registers for CSV 83 Reference clock */ 84 } CSV_REF_Type; /*!< Size = 16 (0x10) */ 85 86 /** 87 * \brief LF clock Clock Supervisor registers (CSV_LF_CSV) 88 */ 89 typedef struct { 90 __IOM uint32_t REF_CTL; /*!< 0x00000000 Clock Supervision Reference Control */ 91 __IOM uint32_t REF_LIMIT; /*!< 0x00000004 Clock Supervision Reference Limits */ 92 __IOM uint32_t MON_CTL; /*!< 0x00000008 Clock Supervision Monitor Control */ 93 __IM uint32_t RESERVED; 94 } CSV_LF_CSV_Type; /*!< Size = 16 (0x10) */ 95 96 /** 97 * \brief CSV registers for LF clock (CSV_LF) 98 */ 99 typedef struct { 100 CSV_LF_CSV_Type CSV; /*!< 0x00000000 LF clock Clock Supervisor registers */ 101 } CSV_LF_Type; /*!< Size = 16 (0x10) */ 102 103 /** 104 * \brief HVILO clock DeepSleep domain Clock Supervisor registers (CSV_ILO_CSV) 105 */ 106 typedef struct { 107 __IOM uint32_t REF_CTL; /*!< 0x00000000 Clock Supervision Reference Control */ 108 __IOM uint32_t REF_LIMIT; /*!< 0x00000004 Clock Supervision Reference Limits */ 109 __IOM uint32_t MON_CTL; /*!< 0x00000008 Clock Supervision Monitor Control */ 110 __IM uint32_t RESERVED; 111 } CSV_ILO_CSV_Type; /*!< Size = 16 (0x10) */ 112 113 /** 114 * \brief CSV registers for ILO clock (CSV_ILO) 115 */ 116 typedef struct { 117 CSV_ILO_CSV_Type CSV; /*!< 0x00000000 HVILO clock DeepSleep domain Clock Supervisor registers */ 118 } CSV_ILO_Type; /*!< Size = 16 (0x10) */ 119 120 /** 121 * \brief 400MHz PLL Configuration Register (CLK_PLL400M) 122 */ 123 typedef struct { 124 __IOM uint32_t CONFIG; /*!< 0x00000000 400MHz PLL Configuration Register */ 125 __IOM uint32_t CONFIG2; /*!< 0x00000004 400MHz PLL Configuration Register 2 */ 126 __IOM uint32_t CONFIG3; /*!< 0x00000008 400MHz PLL Configuration Register 3 */ 127 __IOM uint32_t STATUS; /*!< 0x0000000C 400MHz PLL Status Register */ 128 } CLK_PLL400M_Type; /*!< Size = 16 (0x10) */ 129 130 /** 131 * \brief DPLL LP Configuration Register (CLK_DPLL_LP) 132 */ 133 typedef struct { 134 __IOM uint32_t CONFIG; /*!< 0x00000000 DPLL_LP Configuration Register */ 135 __IOM uint32_t CONFIG2; /*!< 0x00000004 DPLL_LP Configuration Register 2 */ 136 __IOM uint32_t CONFIG3; /*!< 0x00000008 DPLL_LP Configuration Register 3 */ 137 __IOM uint32_t CONFIG4; /*!< 0x0000000C DPLL_LP Configuration Register 4 */ 138 __IOM uint32_t CONFIG5; /*!< 0x00000010 DPLL_LP Configuration Register 5 */ 139 __IOM uint32_t CONFIG6; /*!< 0x00000014 DPLL_LP Configuration Register 6 */ 140 __IOM uint32_t CONFIG7; /*!< 0x00000018 DPLL_LP Configuration Register 7 */ 141 __IOM uint32_t STATUS; /*!< 0x0000001C DPLL_LP Status Register */ 142 } CLK_DPLL_LP_Type; /*!< Size = 32 (0x20) */ 143 144 /** 145 * \brief SRAM Trim registers (RAM_TRIM) 146 */ 147 typedef struct { 148 __IOM uint32_t TRIM_RAM_CTL; /*!< 0x00000000 Trim Register for RAM Type 0 */ 149 __IOM uint32_t TRIM_ROM_CTL; /*!< 0x00000004 Trim Register for ROM */ 150 } RAM_TRIM_Type; /*!< Size = 8 (0x8) */ 151 152 /** 153 * \brief DPLL LP Trims (CLK_TRIM_DPLL_LP) 154 */ 155 typedef struct { 156 __IOM uint32_t DPLL_LP_CTL; /*!< 0x00000000 DPLL LP Trim Register */ 157 __IM uint32_t RESERVED; 158 __IOM uint32_t DPLL_LP_CTL3; /*!< 0x00000008 DPLL LP Trim Register 3 */ 159 __IOM uint32_t DPLL_LP_CTL4; /*!< 0x0000000C DPLL LP Trim Register 4 */ 160 __IM uint32_t RESERVED1[3]; 161 __IOM uint32_t DPLL_LP_TEST4; /*!< 0x0000001C DPLL LP Test Register 4 */ 162 } CLK_TRIM_DPLL_LP_Type; /*!< Size = 32 (0x20) */ 163 164 /** 165 * \brief Multi-Counter Watchdog Timer (Type A) (MCWDT_STRUCT) 166 */ 167 typedef struct { 168 __IM uint32_t RESERVED; 169 __IOM uint32_t MCWDT_CNTLOW; /*!< 0x00000004 Multi-Counter Watchdog Sub-counters 0/1 */ 170 __IOM uint32_t MCWDT_CNTHIGH; /*!< 0x00000008 Multi-Counter Watchdog Sub-counter 2 */ 171 __IOM uint32_t MCWDT_MATCH; /*!< 0x0000000C Multi-Counter Watchdog Counter Match Register */ 172 __IOM uint32_t MCWDT_CONFIG; /*!< 0x00000010 Multi-Counter Watchdog Counter Configuration */ 173 __IOM uint32_t MCWDT_CTL; /*!< 0x00000014 Multi-Counter Watchdog Counter Control */ 174 __IOM uint32_t MCWDT_INTR; /*!< 0x00000018 Multi-Counter Watchdog Counter Interrupt Register */ 175 __IOM uint32_t MCWDT_INTR_SET; /*!< 0x0000001C Multi-Counter Watchdog Counter Interrupt Set Register */ 176 __IOM uint32_t MCWDT_INTR_MASK; /*!< 0x00000020 Multi-Counter Watchdog Counter Interrupt Mask Register */ 177 __IM uint32_t MCWDT_INTR_MASKED; /*!< 0x00000024 Multi-Counter Watchdog Counter Interrupt Masked Register */ 178 __IOM uint32_t MCWDT_LOCK; /*!< 0x00000028 Multi-Counter Watchdog Counter Lock Register */ 179 __IOM uint32_t MCWDT_LOWER_LIMIT; /*!< 0x0000002C Multi-Counter Watchdog Counter Lower Limit Register */ 180 __IM uint32_t RESERVED1[4]; 181 } MCWDT_STRUCT_Type; /*!< Size = 64 (0x40) */ 182 183 /** 184 * \brief SRSS Core Registers (SRSS) 185 */ 186 typedef struct { 187 __IM uint32_t RESERVED[16]; 188 __IM uint32_t PWR_LVD_STATUS; /*!< 0x00000040 High Voltage / Low Voltage Detector (HVLVD) Status Register */ 189 __IM uint32_t PWR_LVD_STATUS2; /*!< 0x00000044 High Voltage / Low Voltage Detector (HVLVD) Status Register #2 */ 190 __IM uint32_t RESERVED1[46]; 191 __IOM uint32_t CLK_DSI_SELECT[16]; /*!< 0x00000100 Clock DSI Select Register */ 192 __IOM uint32_t CLK_OUTPUT_FAST; /*!< 0x00000140 Fast Clock Output Select Register */ 193 __IOM uint32_t CLK_OUTPUT_SLOW; /*!< 0x00000144 Slow Clock Output Select Register */ 194 __IOM uint32_t CLK_CAL_CNT1; /*!< 0x00000148 Clock Calibration Counter 1 */ 195 __IM uint32_t CLK_CAL_CNT2; /*!< 0x0000014C Clock Calibration Counter 2 */ 196 __IM uint32_t RESERVED2[44]; 197 __IOM uint32_t SRSS_INTR; /*!< 0x00000200 SRSS Interrupt Register */ 198 __IOM uint32_t SRSS_INTR_SET; /*!< 0x00000204 SRSS Interrupt Set Register */ 199 __IOM uint32_t SRSS_INTR_MASK; /*!< 0x00000208 SRSS Interrupt Mask Register */ 200 __IM uint32_t SRSS_INTR_MASKED; /*!< 0x0000020C SRSS Interrupt Masked Register */ 201 __IM uint32_t RESERVED3[60]; 202 __IOM uint32_t SRSS_AINTR; /*!< 0x00000300 SRSS Additional Interrupt Register */ 203 __IOM uint32_t SRSS_AINTR_SET; /*!< 0x00000304 SRSS Additional Interrupt Set Register */ 204 __IOM uint32_t SRSS_AINTR_MASK; /*!< 0x00000308 SRSS Additional Interrupt Mask Register */ 205 __IM uint32_t SRSS_AINTR_MASKED; /*!< 0x0000030C SRSS Additional Interrupt Masked Register */ 206 __IM uint32_t RESERVED4[61]; 207 __IOM uint32_t BOOT_DLM_CTL; /*!< 0x00000404 Debug Control Register */ 208 __IOM uint32_t BOOT_DLM_CTL2; /*!< 0x00000408 Debug Control Register 2 */ 209 __IOM uint32_t BOOT_DLM_STATUS; /*!< 0x0000040C Debug Status Register */ 210 __IOM uint32_t RES_SOFT_CTL; /*!< 0x00000410 Soft Reset Trigger Register */ 211 __IM uint32_t RESERVED5; 212 __IOM uint32_t BOOT_STATUS; /*!< 0x00000418 Boot Execution Status Register */ 213 __IM uint32_t RESERVED6[5]; 214 __IOM uint32_t BOOT_ENTRY; /*!< 0x00000430 Warm Boot Entry Address */ 215 __IM uint32_t RESERVED7[243]; 216 __IOM uint32_t PWR_HIB_DATA[16]; /*!< 0x00000800 HIBERNATE Data Register */ 217 __IM uint32_t RESERVED8[24]; 218 __IOM uint32_t PWR_HIB_WAKE_CTL; /*!< 0x000008A0 Hibernate Wakeup Mask Register */ 219 __IOM uint32_t PWR_HIB_WAKE_CTL2; /*!< 0x000008A4 Hibernate Wakeup Polarity Register */ 220 __IM uint32_t RESERVED9; 221 __IOM uint32_t PWR_HIB_WAKE_CAUSE; /*!< 0x000008AC Hibernate Wakeup Cause Register */ 222 __IM uint32_t RESERVED10[468]; 223 __IM uint32_t PWR_CTL; /*!< 0x00001000 Power Mode Control */ 224 __IOM uint32_t PWR_CTL2; /*!< 0x00001004 Power Mode Control 2 */ 225 __IOM uint32_t PWR_HIBERNATE; /*!< 0x00001008 HIBERNATE Mode Register */ 226 __IM uint32_t RESERVED11; 227 __IOM uint32_t PWR_BUCK_CTL; /*!< 0x00001010 Buck Control Register */ 228 __IOM uint32_t PWR_BUCK_CTL2; /*!< 0x00001014 Buck Control Register 2 */ 229 __IOM uint32_t PWR_SSV_CTL; /*!< 0x00001018 Supply Supervision Control Register */ 230 __IM uint32_t PWR_SSV_STATUS; /*!< 0x0000101C Supply Supervision Status Register */ 231 __IOM uint32_t PWR_LVD_CTL; /*!< 0x00001020 High Voltage / Low Voltage Detector (HVLVD) Configuration 232 Register */ 233 __IOM uint32_t PWR_LVD_CTL2; /*!< 0x00001024 High Voltage / Low Voltage Detector (HVLVD) Configuration 234 Register #2 */ 235 __IOM uint32_t PWR_REGHC_CTL; /*!< 0x00001028 REGHC Control Register */ 236 __IM uint32_t PWR_REGHC_STATUS; /*!< 0x0000102C REGHC Status Register */ 237 __IOM uint32_t PWR_REGHC_CTL2; /*!< 0x00001030 REGHC Control Register 2 */ 238 __IM uint32_t RESERVED12[35]; 239 __IOM uint32_t PWR_PMIC_CTL; /*!< 0x000010C0 PMIC Control Register */ 240 __IM uint32_t PWR_PMIC_STATUS; /*!< 0x000010C4 PMIC Status Register */ 241 __IOM uint32_t PWR_PMIC_CTL2; /*!< 0x000010C8 PMIC Control Register 2 */ 242 __IM uint32_t RESERVED13; 243 __IOM uint32_t PWR_PMIC_CTL4; /*!< 0x000010D0 PMIC Control Register 4 */ 244 __IM uint32_t RESERVED14[75]; 245 __IOM uint32_t CLK_PATH_SELECT[16]; /*!< 0x00001200 Clock Path Select Register */ 246 __IOM uint32_t CLK_ROOT_SELECT[16]; /*!< 0x00001240 Clock Root Select Register */ 247 __IOM uint32_t CLK_DIRECT_SELECT[16]; /*!< 0x00001280 Clock Root Direct Select Register */ 248 __IM uint32_t RESERVED15[80]; 249 CSV_HF_Type CSV_HF_STRUCT; /*!< 0x00001400 Clock Supervisor (CSV) registers for Root clocks */ 250 __IOM uint32_t CLK_SELECT; /*!< 0x00001500 Clock selection register */ 251 __IM uint32_t RESERVED16; 252 __IOM uint32_t CLK_ILO0_CONFIG; /*!< 0x00001508 ILO0 Configuration */ 253 __IOM uint32_t CLK_ILO1_CONFIG; /*!< 0x0000150C ILO1 Configuration */ 254 __IM uint32_t RESERVED17[2]; 255 __IOM uint32_t CLK_IMO_CONFIG; /*!< 0x00001518 IMO Configuration */ 256 __IOM uint32_t CLK_ECO_CONFIG; /*!< 0x0000151C ECO Configuration Register */ 257 __IOM uint32_t CLK_ECO_PRESCALE; /*!< 0x00001520 ECO Prescaler Configuration Register */ 258 __IM uint32_t CLK_ECO_STATUS; /*!< 0x00001524 ECO Status Register */ 259 __IOM uint32_t CLK_PILO_CONFIG; /*!< 0x00001528 Precision ILO Configuration Register */ 260 __IM uint32_t RESERVED18; 261 __IOM uint32_t CLK_FLL_CONFIG; /*!< 0x00001530 FLL Configuration Register */ 262 __IOM uint32_t CLK_FLL_CONFIG2; /*!< 0x00001534 FLL Configuration Register 2 */ 263 __IOM uint32_t CLK_FLL_CONFIG3; /*!< 0x00001538 FLL Configuration Register 3 */ 264 __IOM uint32_t CLK_FLL_CONFIG4; /*!< 0x0000153C FLL Configuration Register 4 */ 265 __IOM uint32_t CLK_FLL_STATUS; /*!< 0x00001540 FLL Status Register */ 266 __IOM uint32_t CLK_ECO_CONFIG2; /*!< 0x00001544 ECO Configuration Register 2 */ 267 __IOM uint32_t CLK_ILO_CONFIG; /*!< 0x00001548 ILO Configuration */ 268 __IOM uint32_t CLK_TRIM_ILO_CTL; /*!< 0x0000154C ILO Trim Register */ 269 __IOM uint32_t CLK_TRIM_ILO0_CTL; /*!< 0x00001550 ILO0 Trim Register */ 270 __IOM uint32_t CLK_MF_SELECT; /*!< 0x00001554 Medium Frequency Clock Select Register */ 271 __IOM uint32_t CLK_MFO_CONFIG; /*!< 0x00001558 MFO Configuration Register */ 272 __IM uint32_t RESERVED19; 273 __IOM uint32_t CLK_IHO_CONFIG; /*!< 0x00001560 IHO Configuration Register */ 274 __IOM uint32_t CLK_ALTHF_CTL; /*!< 0x00001564 Alternate High Frequency Clock Control Register */ 275 __IM uint32_t RESERVED20[38]; 276 __IOM uint32_t CLK_PLL_CONFIG[15]; /*!< 0x00001600 PLL Configuration Register */ 277 __IM uint32_t RESERVED21; 278 __IOM uint32_t CLK_PLL_STATUS[15]; /*!< 0x00001640 PLL Status Register */ 279 __IM uint32_t RESERVED22[33]; 280 __IOM uint32_t CSV_REF_SEL; /*!< 0x00001700 Select CSV Reference clock for Active domain */ 281 __IM uint32_t RESERVED23[3]; 282 CSV_REF_Type CSV_REF; /*!< 0x00001710 CSV registers for the CSV Reference clock */ 283 CSV_LF_Type CSV_LF_STRUCT; /*!< 0x00001720 CSV registers for LF clock */ 284 CSV_ILO_Type CSV_ILO; /*!< 0x00001730 CSV registers for ILO clock */ 285 __IM uint32_t RESERVED24[48]; 286 __IOM uint32_t RES_CAUSE; /*!< 0x00001800 Reset Cause Observation Register */ 287 __IOM uint32_t RES_CAUSE2; /*!< 0x00001804 Reset Cause Observation Register 2 */ 288 __IOM uint32_t RES_CAUSE_EXTEND; /*!< 0x00001808 Extended Reset Cause Observation Register */ 289 __IM uint32_t RESERVED25[2]; 290 __OM uint32_t RES_PXRES_CTL; /*!< 0x00001814 Programmable XRES Control Register */ 291 __IM uint32_t RESERVED26[58]; 292 CLK_PLL400M_Type CLK_PLL400M[15]; /*!< 0x00001900 400MHz PLL Configuration Register */ 293 __IM uint32_t RESERVED27[4]; 294 CLK_DPLL_LP_Type CLK_DPLL_LP[15]; /*!< 0x00001A00 DPLL LP Configuration Register */ 295 __IM uint32_t RESERVED28[8]; 296 __IOM uint32_t PWR_CBUCK_CTL; /*!< 0x00001C00 Core Buck Control Register */ 297 __IOM uint32_t PWR_CBUCK_CTL2; /*!< 0x00001C04 Core Buck Control Register 2 */ 298 __IOM uint32_t PWR_CBUCK_CTL3; /*!< 0x00001C08 Core Buck Control Register 3 */ 299 __IM uint32_t PWR_CBUCK_STATUS; /*!< 0x00001C0C Core Buck Status Register */ 300 __IOM uint32_t PWR_SDR0_CTL; /*!< 0x00001C10 Step Down Regulator 0 Control Register */ 301 __IOM uint32_t PWR_SDR1_CTL; /*!< 0x00001C14 Step Down Regulator 1 Control Register */ 302 __IM uint32_t RESERVED29[6]; 303 __IOM uint32_t PWR_HVLDO0_CTL; /*!< 0x00001C30 HVLDO0 Control Register */ 304 __IM uint32_t RESERVED30[264]; 305 __IOM uint32_t TST_XRES_SECURE; /*!< 0x00002054 SECURE TEST and FIRMWARE TEST Key control register */ 306 __IM uint32_t RESERVED31[21]; 307 __IOM uint32_t PWR_TRIM_CBUCK_CTL; /*!< 0x000020AC CBUCK Trim Register */ 308 __IM uint32_t RESERVED32[12]; 309 __IOM uint32_t PWR_TRIM_PWRSYS_CTL; /*!< 0x000020E0 Power System Trim Register */ 310 __IOM uint32_t PWR_TRIM_PWRSYS_CTL2; /*!< 0x000020E4 Power System Trim Register 2 */ 311 __IM uint32_t RESERVED33[973]; 312 __IOM uint32_t CLK_TRIM_ECO_CTL; /*!< 0x0000301C ECO Trim Register */ 313 __IM uint32_t RESERVED34[128]; 314 __IOM uint32_t CLK_TRIM_ILO1_CTL; /*!< 0x00003220 ILO1 Trim Register */ 315 __IM uint32_t RESERVED35[887]; 316 RAM_TRIM_Type RAM_TRIM_STRUCT; /*!< 0x00004000 SRAM Trim registers */ 317 __IM uint32_t RESERVED36[126]; 318 CLK_TRIM_DPLL_LP_Type CLK_TRIM_DPLL_LP[15]; /*!< 0x00004200 DPLL LP Trims */ 319 __IM uint32_t RESERVED37[7944]; 320 __IOM uint32_t WDT_CTL; /*!< 0x0000C000 Watchdog Counter Control Register (Type A) */ 321 __IOM uint32_t WDT_CNT; /*!< 0x0000C004 Watchdog Counter Count Register (Type A) */ 322 __IOM uint32_t WDT_MATCH; /*!< 0x0000C008 Watchdog Counter Match Register (Type A) */ 323 __IOM uint32_t WDT_MATCH2; /*!< 0x0000C00C Watchdog Counter Match Register 2 (Type A) */ 324 __IM uint32_t RESERVED38[1020]; 325 MCWDT_STRUCT_Type MCWDT_STRUCT[4]; /*!< 0x0000D000 Multi-Counter Watchdog Timer (Type A) */ 326 } SRSS_Type; /*!< Size = 53504 (0xD100) */ 327 328 329 /* CSV_HF_CSV.REF_CTL */ 330 #define CSV_HF_CSV_REF_CTL_STARTUP_Pos 0UL 331 #define CSV_HF_CSV_REF_CTL_STARTUP_Msk 0xFFFFUL 332 #define CSV_HF_CSV_REF_CTL_CSV_ACTION_Pos 30UL 333 #define CSV_HF_CSV_REF_CTL_CSV_ACTION_Msk 0x40000000UL 334 #define CSV_HF_CSV_REF_CTL_CSV_EN_Pos 31UL 335 #define CSV_HF_CSV_REF_CTL_CSV_EN_Msk 0x80000000UL 336 /* CSV_HF_CSV.REF_LIMIT */ 337 #define CSV_HF_CSV_REF_LIMIT_LOWER_Pos 0UL 338 #define CSV_HF_CSV_REF_LIMIT_LOWER_Msk 0xFFFFUL 339 #define CSV_HF_CSV_REF_LIMIT_UPPER_Pos 16UL 340 #define CSV_HF_CSV_REF_LIMIT_UPPER_Msk 0xFFFF0000UL 341 /* CSV_HF_CSV.MON_CTL */ 342 #define CSV_HF_CSV_MON_CTL_PERIOD_Pos 0UL 343 #define CSV_HF_CSV_MON_CTL_PERIOD_Msk 0xFFFFUL 344 345 346 /* CSV_REF_CSV.REF_CTL */ 347 #define CSV_REF_CSV_REF_CTL_STARTUP_Pos 0UL 348 #define CSV_REF_CSV_REF_CTL_STARTUP_Msk 0xFFFFUL 349 #define CSV_REF_CSV_REF_CTL_CSV_ACTION_Pos 30UL 350 #define CSV_REF_CSV_REF_CTL_CSV_ACTION_Msk 0x40000000UL 351 #define CSV_REF_CSV_REF_CTL_CSV_EN_Pos 31UL 352 #define CSV_REF_CSV_REF_CTL_CSV_EN_Msk 0x80000000UL 353 /* CSV_REF_CSV.REF_LIMIT */ 354 #define CSV_REF_CSV_REF_LIMIT_LOWER_Pos 0UL 355 #define CSV_REF_CSV_REF_LIMIT_LOWER_Msk 0xFFFFUL 356 #define CSV_REF_CSV_REF_LIMIT_UPPER_Pos 16UL 357 #define CSV_REF_CSV_REF_LIMIT_UPPER_Msk 0xFFFF0000UL 358 /* CSV_REF_CSV.MON_CTL */ 359 #define CSV_REF_CSV_MON_CTL_PERIOD_Pos 0UL 360 #define CSV_REF_CSV_MON_CTL_PERIOD_Msk 0xFFFFUL 361 362 363 /* CSV_LF_CSV.REF_CTL */ 364 #define CSV_LF_CSV_REF_CTL_STARTUP_Pos 0UL 365 #define CSV_LF_CSV_REF_CTL_STARTUP_Msk 0xFFUL 366 #define CSV_LF_CSV_REF_CTL_CSV_EN_Pos 31UL 367 #define CSV_LF_CSV_REF_CTL_CSV_EN_Msk 0x80000000UL 368 /* CSV_LF_CSV.REF_LIMIT */ 369 #define CSV_LF_CSV_REF_LIMIT_LOWER_Pos 0UL 370 #define CSV_LF_CSV_REF_LIMIT_LOWER_Msk 0xFFUL 371 #define CSV_LF_CSV_REF_LIMIT_UPPER_Pos 16UL 372 #define CSV_LF_CSV_REF_LIMIT_UPPER_Msk 0xFF0000UL 373 /* CSV_LF_CSV.MON_CTL */ 374 #define CSV_LF_CSV_MON_CTL_PERIOD_Pos 0UL 375 #define CSV_LF_CSV_MON_CTL_PERIOD_Msk 0xFFUL 376 377 378 /* CSV_ILO_CSV.REF_CTL */ 379 #define CSV_ILO_CSV_REF_CTL_STARTUP_Pos 0UL 380 #define CSV_ILO_CSV_REF_CTL_STARTUP_Msk 0xFFUL 381 #define CSV_ILO_CSV_REF_CTL_CSV_EN_Pos 31UL 382 #define CSV_ILO_CSV_REF_CTL_CSV_EN_Msk 0x80000000UL 383 /* CSV_ILO_CSV.REF_LIMIT */ 384 #define CSV_ILO_CSV_REF_LIMIT_LOWER_Pos 0UL 385 #define CSV_ILO_CSV_REF_LIMIT_LOWER_Msk 0xFFUL 386 #define CSV_ILO_CSV_REF_LIMIT_UPPER_Pos 16UL 387 #define CSV_ILO_CSV_REF_LIMIT_UPPER_Msk 0xFF0000UL 388 /* CSV_ILO_CSV.MON_CTL */ 389 #define CSV_ILO_CSV_MON_CTL_PERIOD_Pos 0UL 390 #define CSV_ILO_CSV_MON_CTL_PERIOD_Msk 0xFFUL 391 392 393 /* CLK_PLL400M.CONFIG */ 394 #define CLK_PLL400M_CONFIG_FEEDBACK_DIV_Pos 0UL 395 #define CLK_PLL400M_CONFIG_FEEDBACK_DIV_Msk 0xFFUL 396 #define CLK_PLL400M_CONFIG_REFERENCE_DIV_Pos 8UL 397 #define CLK_PLL400M_CONFIG_REFERENCE_DIV_Msk 0x1F00UL 398 #define CLK_PLL400M_CONFIG_OUTPUT_DIV_Pos 16UL 399 #define CLK_PLL400M_CONFIG_OUTPUT_DIV_Msk 0x1F0000UL 400 #define CLK_PLL400M_CONFIG_LOCK_DELAY_Pos 25UL 401 #define CLK_PLL400M_CONFIG_LOCK_DELAY_Msk 0x6000000UL 402 #define CLK_PLL400M_CONFIG_BYPASS_SEL_Pos 28UL 403 #define CLK_PLL400M_CONFIG_BYPASS_SEL_Msk 0x30000000UL 404 #define CLK_PLL400M_CONFIG_ENABLE_Pos 31UL 405 #define CLK_PLL400M_CONFIG_ENABLE_Msk 0x80000000UL 406 /* CLK_PLL400M.CONFIG2 */ 407 #define CLK_PLL400M_CONFIG2_FRAC_DIV_Pos 0UL 408 #define CLK_PLL400M_CONFIG2_FRAC_DIV_Msk 0xFFFFFFUL 409 #define CLK_PLL400M_CONFIG2_FRAC_DITHER_EN_Pos 28UL 410 #define CLK_PLL400M_CONFIG2_FRAC_DITHER_EN_Msk 0x70000000UL 411 #define CLK_PLL400M_CONFIG2_FRAC_EN_Pos 31UL 412 #define CLK_PLL400M_CONFIG2_FRAC_EN_Msk 0x80000000UL 413 /* CLK_PLL400M.CONFIG3 */ 414 #define CLK_PLL400M_CONFIG3_SSCG_DEPTH_Pos 0UL 415 #define CLK_PLL400M_CONFIG3_SSCG_DEPTH_Msk 0x3FFUL 416 #define CLK_PLL400M_CONFIG3_SSCG_RATE_Pos 16UL 417 #define CLK_PLL400M_CONFIG3_SSCG_RATE_Msk 0x70000UL 418 #define CLK_PLL400M_CONFIG3_SSCG_DITHER_EN_Pos 24UL 419 #define CLK_PLL400M_CONFIG3_SSCG_DITHER_EN_Msk 0x1000000UL 420 #define CLK_PLL400M_CONFIG3_SSCG_MODE_Pos 28UL 421 #define CLK_PLL400M_CONFIG3_SSCG_MODE_Msk 0x10000000UL 422 #define CLK_PLL400M_CONFIG3_SSCG_EN_Pos 31UL 423 #define CLK_PLL400M_CONFIG3_SSCG_EN_Msk 0x80000000UL 424 /* CLK_PLL400M.STATUS */ 425 #define CLK_PLL400M_STATUS_LOCKED_Pos 0UL 426 #define CLK_PLL400M_STATUS_LOCKED_Msk 0x1UL 427 #define CLK_PLL400M_STATUS_UNLOCK_OCCURRED_Pos 1UL 428 #define CLK_PLL400M_STATUS_UNLOCK_OCCURRED_Msk 0x2UL 429 430 431 /* CLK_DPLL_LP.CONFIG */ 432 #define CLK_DPLL_LP_CONFIG_FEEDBACK_DIV_Pos 0UL 433 #define CLK_DPLL_LP_CONFIG_FEEDBACK_DIV_Msk 0xFFUL 434 #define CLK_DPLL_LP_CONFIG_REFERENCE_DIV_Pos 8UL 435 #define CLK_DPLL_LP_CONFIG_REFERENCE_DIV_Msk 0x1F00UL 436 #define CLK_DPLL_LP_CONFIG_OUTPUT_DIV_Pos 16UL 437 #define CLK_DPLL_LP_CONFIG_OUTPUT_DIV_Msk 0x1F0000UL 438 #define CLK_DPLL_LP_CONFIG_PLL_DCO_CODE_MULT_Pos 27UL 439 #define CLK_DPLL_LP_CONFIG_PLL_DCO_CODE_MULT_Msk 0x8000000UL 440 #define CLK_DPLL_LP_CONFIG_BYPASS_SEL_Pos 28UL 441 #define CLK_DPLL_LP_CONFIG_BYPASS_SEL_Msk 0x30000000UL 442 #define CLK_DPLL_LP_CONFIG_ENABLE_Pos 31UL 443 #define CLK_DPLL_LP_CONFIG_ENABLE_Msk 0x80000000UL 444 /* CLK_DPLL_LP.CONFIG2 */ 445 #define CLK_DPLL_LP_CONFIG2_FRAC_DIV_Pos 0UL 446 #define CLK_DPLL_LP_CONFIG2_FRAC_DIV_Msk 0xFFFFFFUL 447 #define CLK_DPLL_LP_CONFIG2_FRAC_DITHER_EN_Pos 28UL 448 #define CLK_DPLL_LP_CONFIG2_FRAC_DITHER_EN_Msk 0x70000000UL 449 #define CLK_DPLL_LP_CONFIG2_FRAC_EN_Pos 31UL 450 #define CLK_DPLL_LP_CONFIG2_FRAC_EN_Msk 0x80000000UL 451 /* CLK_DPLL_LP.CONFIG3 */ 452 #define CLK_DPLL_LP_CONFIG3_SSCG_DEPTH_Pos 0UL 453 #define CLK_DPLL_LP_CONFIG3_SSCG_DEPTH_Msk 0x3FFUL 454 #define CLK_DPLL_LP_CONFIG3_SSCG_RATE_Pos 16UL 455 #define CLK_DPLL_LP_CONFIG3_SSCG_RATE_Msk 0x70000UL 456 #define CLK_DPLL_LP_CONFIG3_SSCG_DITHER_EN_Pos 24UL 457 #define CLK_DPLL_LP_CONFIG3_SSCG_DITHER_EN_Msk 0x1000000UL 458 #define CLK_DPLL_LP_CONFIG3_SSCG_MODE_Pos 28UL 459 #define CLK_DPLL_LP_CONFIG3_SSCG_MODE_Msk 0x10000000UL 460 #define CLK_DPLL_LP_CONFIG3_SSCG_EN_Pos 31UL 461 #define CLK_DPLL_LP_CONFIG3_SSCG_EN_Msk 0x80000000UL 462 /* CLK_DPLL_LP.CONFIG4 */ 463 #define CLK_DPLL_LP_CONFIG4_DCO_CODE_Pos 0UL 464 #define CLK_DPLL_LP_CONFIG4_DCO_CODE_Msk 0x7FFUL 465 #define CLK_DPLL_LP_CONFIG4_ACC_MODE_Pos 16UL 466 #define CLK_DPLL_LP_CONFIG4_ACC_MODE_Msk 0x30000UL 467 #define CLK_DPLL_LP_CONFIG4_TDC_MODE_Pos 18UL 468 #define CLK_DPLL_LP_CONFIG4_TDC_MODE_Msk 0xC0000UL 469 #define CLK_DPLL_LP_CONFIG4_PLL_TG_Pos 20UL 470 #define CLK_DPLL_LP_CONFIG4_PLL_TG_Msk 0x300000UL 471 #define CLK_DPLL_LP_CONFIG4_ACC_CNT_LOCK_Pos 24UL 472 #define CLK_DPLL_LP_CONFIG4_ACC_CNT_LOCK_Msk 0x1000000UL 473 /* CLK_DPLL_LP.CONFIG5 */ 474 #define CLK_DPLL_LP_CONFIG5_KI_INT_Pos 0UL 475 #define CLK_DPLL_LP_CONFIG5_KI_INT_Msk 0x7FUL 476 #define CLK_DPLL_LP_CONFIG5_KP_INT_Pos 8UL 477 #define CLK_DPLL_LP_CONFIG5_KP_INT_Msk 0x7F00UL 478 #define CLK_DPLL_LP_CONFIG5_KI_ACC_INT_Pos 16UL 479 #define CLK_DPLL_LP_CONFIG5_KI_ACC_INT_Msk 0x7F0000UL 480 #define CLK_DPLL_LP_CONFIG5_KP_ACC_INT_Pos 24UL 481 #define CLK_DPLL_LP_CONFIG5_KP_ACC_INT_Msk 0x7F000000UL 482 /* CLK_DPLL_LP.CONFIG6 */ 483 #define CLK_DPLL_LP_CONFIG6_KI_FRACT_Pos 0UL 484 #define CLK_DPLL_LP_CONFIG6_KI_FRACT_Msk 0x7FUL 485 #define CLK_DPLL_LP_CONFIG6_KP_FRACT_Pos 8UL 486 #define CLK_DPLL_LP_CONFIG6_KP_FRACT_Msk 0x7F00UL 487 #define CLK_DPLL_LP_CONFIG6_KI_ACC_FRACT_Pos 16UL 488 #define CLK_DPLL_LP_CONFIG6_KI_ACC_FRACT_Msk 0x7F0000UL 489 #define CLK_DPLL_LP_CONFIG6_KP_ACC_FRACT_Pos 24UL 490 #define CLK_DPLL_LP_CONFIG6_KP_ACC_FRACT_Msk 0x7F000000UL 491 /* CLK_DPLL_LP.CONFIG7 */ 492 #define CLK_DPLL_LP_CONFIG7_KI_SSCG_Pos 0UL 493 #define CLK_DPLL_LP_CONFIG7_KI_SSCG_Msk 0x7FUL 494 #define CLK_DPLL_LP_CONFIG7_KP_SSCG_Pos 8UL 495 #define CLK_DPLL_LP_CONFIG7_KP_SSCG_Msk 0x7F00UL 496 #define CLK_DPLL_LP_CONFIG7_KI_ACC_SSCG_Pos 16UL 497 #define CLK_DPLL_LP_CONFIG7_KI_ACC_SSCG_Msk 0x7F0000UL 498 #define CLK_DPLL_LP_CONFIG7_KP_ACC_SSCG_Pos 24UL 499 #define CLK_DPLL_LP_CONFIG7_KP_ACC_SSCG_Msk 0x7F000000UL 500 /* CLK_DPLL_LP.STATUS */ 501 #define CLK_DPLL_LP_STATUS_LOCKED_Pos 0UL 502 #define CLK_DPLL_LP_STATUS_LOCKED_Msk 0x1UL 503 #define CLK_DPLL_LP_STATUS_UNLOCK_OCCURRED_Pos 1UL 504 #define CLK_DPLL_LP_STATUS_UNLOCK_OCCURRED_Msk 0x2UL 505 506 507 /* RAM_TRIM.TRIM_RAM_CTL */ 508 #define RAM_TRIM_TRIM_RAM_CTL_TRIM_Pos 0UL 509 #define RAM_TRIM_TRIM_RAM_CTL_TRIM_Msk 0xFFFFFFFFUL 510 /* RAM_TRIM.TRIM_ROM_CTL */ 511 #define RAM_TRIM_TRIM_ROM_CTL_TRIM_Pos 0UL 512 #define RAM_TRIM_TRIM_ROM_CTL_TRIM_Msk 0xFFFFFFFFUL 513 514 515 /* CLK_TRIM_DPLL_LP.DPLL_LP_CTL */ 516 #define CLK_TRIM_DPLL_LP_DPLL_LP_CTL_SAR_CYCLE_STOP_Pos 4UL 517 #define CLK_TRIM_DPLL_LP_DPLL_LP_CTL_SAR_CYCLE_STOP_Msk 0xF0UL 518 #define CLK_TRIM_DPLL_LP_DPLL_LP_CTL_SAR_DIS_Pos 8UL 519 #define CLK_TRIM_DPLL_LP_DPLL_LP_CTL_SAR_DIS_Msk 0x100UL 520 #define CLK_TRIM_DPLL_LP_DPLL_LP_CTL_PLL_SAR_FSM_EN_Pos 9UL 521 #define CLK_TRIM_DPLL_LP_DPLL_LP_CTL_PLL_SAR_FSM_EN_Msk 0x200UL 522 #define CLK_TRIM_DPLL_LP_DPLL_LP_CTL_LDO_DCO_TRIM_Pos 12UL 523 #define CLK_TRIM_DPLL_LP_DPLL_LP_CTL_LDO_DCO_TRIM_Msk 0x7000UL 524 #define CLK_TRIM_DPLL_LP_DPLL_LP_CTL_PLL_DCO_SD_SEL_Pos 16UL 525 #define CLK_TRIM_DPLL_LP_DPLL_LP_CTL_PLL_DCO_SD_SEL_Msk 0x30000UL 526 #define CLK_TRIM_DPLL_LP_DPLL_LP_CTL_LDO_PERI_TRIM_Pos 19UL 527 #define CLK_TRIM_DPLL_LP_DPLL_LP_CTL_LDO_PERI_TRIM_Msk 0x380000UL 528 #define CLK_TRIM_DPLL_LP_DPLL_LP_CTL_PLL_FRAC_ORDER_Pos 22UL 529 #define CLK_TRIM_DPLL_LP_DPLL_LP_CTL_PLL_FRAC_ORDER_Msk 0x400000UL 530 #define CLK_TRIM_DPLL_LP_DPLL_LP_CTL_ISOLATE_N_Pos 23UL 531 #define CLK_TRIM_DPLL_LP_DPLL_LP_CTL_ISOLATE_N_Msk 0x800000UL 532 #define CLK_TRIM_DPLL_LP_DPLL_LP_CTL_ISOLATE_CNT_Pos 24UL 533 #define CLK_TRIM_DPLL_LP_DPLL_LP_CTL_ISOLATE_CNT_Msk 0x3F000000UL 534 #define CLK_TRIM_DPLL_LP_DPLL_LP_CTL_ENABLE_CNT_Pos 31UL 535 #define CLK_TRIM_DPLL_LP_DPLL_LP_CTL_ENABLE_CNT_Msk 0x80000000UL 536 /* CLK_TRIM_DPLL_LP.DPLL_LP_CTL3 */ 537 #define CLK_TRIM_DPLL_LP_DPLL_LP_CTL3_PHASE_ACC_CNT_Pos 0UL 538 #define CLK_TRIM_DPLL_LP_DPLL_LP_CTL3_PHASE_ACC_CNT_Msk 0x3FFUL 539 #define CLK_TRIM_DPLL_LP_DPLL_LP_CTL3_PHASE_ACC_CNT_SSCG_Pos 16UL 540 #define CLK_TRIM_DPLL_LP_DPLL_LP_CTL3_PHASE_ACC_CNT_SSCG_Msk 0x3FF0000UL 541 /* CLK_TRIM_DPLL_LP.DPLL_LP_CTL4 */ 542 #define CLK_TRIM_DPLL_LP_DPLL_LP_CTL4_LOCK_WAIT_FALL_Pos 0UL 543 #define CLK_TRIM_DPLL_LP_DPLL_LP_CTL4_LOCK_WAIT_FALL_Msk 0x3UL 544 #define CLK_TRIM_DPLL_LP_DPLL_LP_CTL4_LOCK_WAIT_RISE_Pos 4UL 545 #define CLK_TRIM_DPLL_LP_DPLL_LP_CTL4_LOCK_WAIT_RISE_Msk 0x3FF0UL 546 /* CLK_TRIM_DPLL_LP.DPLL_LP_TEST4 */ 547 #define CLK_TRIM_DPLL_LP_DPLL_LP_TEST4_PLL_USER_DCO_CODE_Pos 0UL 548 #define CLK_TRIM_DPLL_LP_DPLL_LP_TEST4_PLL_USER_DCO_CODE_Msk 0x3FFFUL 549 #define CLK_TRIM_DPLL_LP_DPLL_LP_TEST4_PLL_DIS_FAST_LOCK_Pos 14UL 550 #define CLK_TRIM_DPLL_LP_DPLL_LP_TEST4_PLL_DIS_FAST_LOCK_Msk 0x4000UL 551 #define CLK_TRIM_DPLL_LP_DPLL_LP_TEST4_PLL_READ_EN_Pos 15UL 552 #define CLK_TRIM_DPLL_LP_DPLL_LP_TEST4_PLL_READ_EN_Msk 0x8000UL 553 #define CLK_TRIM_DPLL_LP_DPLL_LP_TEST4_PHASE_ACC_USER_WRITE_INT_Pos 16UL 554 #define CLK_TRIM_DPLL_LP_DPLL_LP_TEST4_PHASE_ACC_USER_WRITE_INT_Msk 0x7F0000UL 555 #define CLK_TRIM_DPLL_LP_DPLL_LP_TEST4_PHASE_ACC_USER_WRITE_FRACT_Pos 23UL 556 #define CLK_TRIM_DPLL_LP_DPLL_LP_TEST4_PHASE_ACC_USER_WRITE_FRACT_Msk 0x3F800000UL 557 558 559 /* MCWDT_STRUCT.MCWDT_CNTLOW */ 560 #define MCWDT_STRUCT_MCWDT_CNTLOW_WDT_CTR0_Pos 0UL 561 #define MCWDT_STRUCT_MCWDT_CNTLOW_WDT_CTR0_Msk 0xFFFFUL 562 #define MCWDT_STRUCT_MCWDT_CNTLOW_WDT_CTR1_Pos 16UL 563 #define MCWDT_STRUCT_MCWDT_CNTLOW_WDT_CTR1_Msk 0xFFFF0000UL 564 /* MCWDT_STRUCT.MCWDT_CNTHIGH */ 565 #define MCWDT_STRUCT_MCWDT_CNTHIGH_WDT_CTR2_Pos 0UL 566 #define MCWDT_STRUCT_MCWDT_CNTHIGH_WDT_CTR2_Msk 0xFFFFFFFFUL 567 /* MCWDT_STRUCT.MCWDT_MATCH */ 568 #define MCWDT_STRUCT_MCWDT_MATCH_WDT_MATCH0_Pos 0UL 569 #define MCWDT_STRUCT_MCWDT_MATCH_WDT_MATCH0_Msk 0xFFFFUL 570 #define MCWDT_STRUCT_MCWDT_MATCH_WDT_MATCH1_Pos 16UL 571 #define MCWDT_STRUCT_MCWDT_MATCH_WDT_MATCH1_Msk 0xFFFF0000UL 572 /* MCWDT_STRUCT.MCWDT_CONFIG */ 573 #define MCWDT_STRUCT_MCWDT_CONFIG_WDT_MODE0_Pos 0UL 574 #define MCWDT_STRUCT_MCWDT_CONFIG_WDT_MODE0_Msk 0x3UL 575 #define MCWDT_STRUCT_MCWDT_CONFIG_WDT_CLEAR0_Pos 2UL 576 #define MCWDT_STRUCT_MCWDT_CONFIG_WDT_CLEAR0_Msk 0x4UL 577 #define MCWDT_STRUCT_MCWDT_CONFIG_WDT_CASCADE0_1_Pos 3UL 578 #define MCWDT_STRUCT_MCWDT_CONFIG_WDT_CASCADE0_1_Msk 0x8UL 579 #define MCWDT_STRUCT_MCWDT_CONFIG_WDT_LOWER_MODE0_Pos 4UL 580 #define MCWDT_STRUCT_MCWDT_CONFIG_WDT_LOWER_MODE0_Msk 0x30UL 581 #define MCWDT_STRUCT_MCWDT_CONFIG_WDT_CARRY0_1_Pos 6UL 582 #define MCWDT_STRUCT_MCWDT_CONFIG_WDT_CARRY0_1_Msk 0x40UL 583 #define MCWDT_STRUCT_MCWDT_CONFIG_WDT_MATCH0_1_Pos 7UL 584 #define MCWDT_STRUCT_MCWDT_CONFIG_WDT_MATCH0_1_Msk 0x80UL 585 #define MCWDT_STRUCT_MCWDT_CONFIG_WDT_MODE1_Pos 8UL 586 #define MCWDT_STRUCT_MCWDT_CONFIG_WDT_MODE1_Msk 0x300UL 587 #define MCWDT_STRUCT_MCWDT_CONFIG_WDT_CLEAR1_Pos 10UL 588 #define MCWDT_STRUCT_MCWDT_CONFIG_WDT_CLEAR1_Msk 0x400UL 589 #define MCWDT_STRUCT_MCWDT_CONFIG_WDT_CASCADE1_2_Pos 11UL 590 #define MCWDT_STRUCT_MCWDT_CONFIG_WDT_CASCADE1_2_Msk 0x800UL 591 #define MCWDT_STRUCT_MCWDT_CONFIG_WDT_LOWER_MODE1_Pos 12UL 592 #define MCWDT_STRUCT_MCWDT_CONFIG_WDT_LOWER_MODE1_Msk 0x3000UL 593 #define MCWDT_STRUCT_MCWDT_CONFIG_WDT_CARRY1_2_Pos 14UL 594 #define MCWDT_STRUCT_MCWDT_CONFIG_WDT_CARRY1_2_Msk 0x4000UL 595 #define MCWDT_STRUCT_MCWDT_CONFIG_WDT_MATCH1_2_Pos 15UL 596 #define MCWDT_STRUCT_MCWDT_CONFIG_WDT_MATCH1_2_Msk 0x8000UL 597 #define MCWDT_STRUCT_MCWDT_CONFIG_WDT_MODE2_Pos 16UL 598 #define MCWDT_STRUCT_MCWDT_CONFIG_WDT_MODE2_Msk 0x10000UL 599 #define MCWDT_STRUCT_MCWDT_CONFIG_WDT_BITS2_Pos 24UL 600 #define MCWDT_STRUCT_MCWDT_CONFIG_WDT_BITS2_Msk 0x1F000000UL 601 /* MCWDT_STRUCT.MCWDT_CTL */ 602 #define MCWDT_STRUCT_MCWDT_CTL_WDT_ENABLE0_Pos 0UL 603 #define MCWDT_STRUCT_MCWDT_CTL_WDT_ENABLE0_Msk 0x1UL 604 #define MCWDT_STRUCT_MCWDT_CTL_WDT_ENABLED0_Pos 1UL 605 #define MCWDT_STRUCT_MCWDT_CTL_WDT_ENABLED0_Msk 0x2UL 606 #define MCWDT_STRUCT_MCWDT_CTL_WDT_RESET0_Pos 3UL 607 #define MCWDT_STRUCT_MCWDT_CTL_WDT_RESET0_Msk 0x8UL 608 #define MCWDT_STRUCT_MCWDT_CTL_WDT_ENABLE1_Pos 8UL 609 #define MCWDT_STRUCT_MCWDT_CTL_WDT_ENABLE1_Msk 0x100UL 610 #define MCWDT_STRUCT_MCWDT_CTL_WDT_ENABLED1_Pos 9UL 611 #define MCWDT_STRUCT_MCWDT_CTL_WDT_ENABLED1_Msk 0x200UL 612 #define MCWDT_STRUCT_MCWDT_CTL_WDT_RESET1_Pos 11UL 613 #define MCWDT_STRUCT_MCWDT_CTL_WDT_RESET1_Msk 0x800UL 614 #define MCWDT_STRUCT_MCWDT_CTL_WDT_ENABLE2_Pos 16UL 615 #define MCWDT_STRUCT_MCWDT_CTL_WDT_ENABLE2_Msk 0x10000UL 616 #define MCWDT_STRUCT_MCWDT_CTL_WDT_ENABLED2_Pos 17UL 617 #define MCWDT_STRUCT_MCWDT_CTL_WDT_ENABLED2_Msk 0x20000UL 618 #define MCWDT_STRUCT_MCWDT_CTL_WDT_RESET2_Pos 19UL 619 #define MCWDT_STRUCT_MCWDT_CTL_WDT_RESET2_Msk 0x80000UL 620 /* MCWDT_STRUCT.MCWDT_INTR */ 621 #define MCWDT_STRUCT_MCWDT_INTR_MCWDT_INT0_Pos 0UL 622 #define MCWDT_STRUCT_MCWDT_INTR_MCWDT_INT0_Msk 0x1UL 623 #define MCWDT_STRUCT_MCWDT_INTR_MCWDT_INT1_Pos 1UL 624 #define MCWDT_STRUCT_MCWDT_INTR_MCWDT_INT1_Msk 0x2UL 625 #define MCWDT_STRUCT_MCWDT_INTR_MCWDT_INT2_Pos 2UL 626 #define MCWDT_STRUCT_MCWDT_INTR_MCWDT_INT2_Msk 0x4UL 627 /* MCWDT_STRUCT.MCWDT_INTR_SET */ 628 #define MCWDT_STRUCT_MCWDT_INTR_SET_MCWDT_INT0_Pos 0UL 629 #define MCWDT_STRUCT_MCWDT_INTR_SET_MCWDT_INT0_Msk 0x1UL 630 #define MCWDT_STRUCT_MCWDT_INTR_SET_MCWDT_INT1_Pos 1UL 631 #define MCWDT_STRUCT_MCWDT_INTR_SET_MCWDT_INT1_Msk 0x2UL 632 #define MCWDT_STRUCT_MCWDT_INTR_SET_MCWDT_INT2_Pos 2UL 633 #define MCWDT_STRUCT_MCWDT_INTR_SET_MCWDT_INT2_Msk 0x4UL 634 /* MCWDT_STRUCT.MCWDT_INTR_MASK */ 635 #define MCWDT_STRUCT_MCWDT_INTR_MASK_MCWDT_INT0_Pos 0UL 636 #define MCWDT_STRUCT_MCWDT_INTR_MASK_MCWDT_INT0_Msk 0x1UL 637 #define MCWDT_STRUCT_MCWDT_INTR_MASK_MCWDT_INT1_Pos 1UL 638 #define MCWDT_STRUCT_MCWDT_INTR_MASK_MCWDT_INT1_Msk 0x2UL 639 #define MCWDT_STRUCT_MCWDT_INTR_MASK_MCWDT_INT2_Pos 2UL 640 #define MCWDT_STRUCT_MCWDT_INTR_MASK_MCWDT_INT2_Msk 0x4UL 641 /* MCWDT_STRUCT.MCWDT_INTR_MASKED */ 642 #define MCWDT_STRUCT_MCWDT_INTR_MASKED_MCWDT_INT0_Pos 0UL 643 #define MCWDT_STRUCT_MCWDT_INTR_MASKED_MCWDT_INT0_Msk 0x1UL 644 #define MCWDT_STRUCT_MCWDT_INTR_MASKED_MCWDT_INT1_Pos 1UL 645 #define MCWDT_STRUCT_MCWDT_INTR_MASKED_MCWDT_INT1_Msk 0x2UL 646 #define MCWDT_STRUCT_MCWDT_INTR_MASKED_MCWDT_INT2_Pos 2UL 647 #define MCWDT_STRUCT_MCWDT_INTR_MASKED_MCWDT_INT2_Msk 0x4UL 648 /* MCWDT_STRUCT.MCWDT_LOCK */ 649 #define MCWDT_STRUCT_MCWDT_LOCK_MCWDT_LOCK_Pos 30UL 650 #define MCWDT_STRUCT_MCWDT_LOCK_MCWDT_LOCK_Msk 0xC0000000UL 651 /* MCWDT_STRUCT.MCWDT_LOWER_LIMIT */ 652 #define MCWDT_STRUCT_MCWDT_LOWER_LIMIT_WDT_LOWER_LIMIT0_Pos 0UL 653 #define MCWDT_STRUCT_MCWDT_LOWER_LIMIT_WDT_LOWER_LIMIT0_Msk 0xFFFFUL 654 #define MCWDT_STRUCT_MCWDT_LOWER_LIMIT_WDT_LOWER_LIMIT1_Pos 16UL 655 #define MCWDT_STRUCT_MCWDT_LOWER_LIMIT_WDT_LOWER_LIMIT1_Msk 0xFFFF0000UL 656 657 658 /* SRSS.PWR_LVD_STATUS */ 659 #define SRSS_PWR_LVD_STATUS_HVLVD1_OK_Pos 0UL 660 #define SRSS_PWR_LVD_STATUS_HVLVD1_OK_Msk 0x1UL 661 /* SRSS.PWR_LVD_STATUS2 */ 662 #define SRSS_PWR_LVD_STATUS2_HVLVD2_OUT_Pos 0UL 663 #define SRSS_PWR_LVD_STATUS2_HVLVD2_OUT_Msk 0x1UL 664 /* SRSS.CLK_DSI_SELECT */ 665 #define SRSS_CLK_DSI_SELECT_DSI_MUX_Pos 0UL 666 #define SRSS_CLK_DSI_SELECT_DSI_MUX_Msk 0x1FUL 667 /* SRSS.CLK_OUTPUT_FAST */ 668 #define SRSS_CLK_OUTPUT_FAST_FAST_SEL0_Pos 0UL 669 #define SRSS_CLK_OUTPUT_FAST_FAST_SEL0_Msk 0xFUL 670 #define SRSS_CLK_OUTPUT_FAST_PATH_SEL0_Pos 4UL 671 #define SRSS_CLK_OUTPUT_FAST_PATH_SEL0_Msk 0xF0UL 672 #define SRSS_CLK_OUTPUT_FAST_HFCLK_SEL0_Pos 8UL 673 #define SRSS_CLK_OUTPUT_FAST_HFCLK_SEL0_Msk 0xF00UL 674 #define SRSS_CLK_OUTPUT_FAST_FAST_SEL1_Pos 16UL 675 #define SRSS_CLK_OUTPUT_FAST_FAST_SEL1_Msk 0xF0000UL 676 #define SRSS_CLK_OUTPUT_FAST_PATH_SEL1_Pos 20UL 677 #define SRSS_CLK_OUTPUT_FAST_PATH_SEL1_Msk 0xF00000UL 678 #define SRSS_CLK_OUTPUT_FAST_HFCLK_SEL1_Pos 24UL 679 #define SRSS_CLK_OUTPUT_FAST_HFCLK_SEL1_Msk 0xF000000UL 680 /* SRSS.CLK_OUTPUT_SLOW */ 681 #define SRSS_CLK_OUTPUT_SLOW_SLOW_SEL0_Pos 0UL 682 #define SRSS_CLK_OUTPUT_SLOW_SLOW_SEL0_Msk 0xFUL 683 #define SRSS_CLK_OUTPUT_SLOW_SLOW_SEL1_Pos 4UL 684 #define SRSS_CLK_OUTPUT_SLOW_SLOW_SEL1_Msk 0xF0UL 685 /* SRSS.CLK_CAL_CNT1 */ 686 #define SRSS_CLK_CAL_CNT1_CAL_COUNTER1_Pos 0UL 687 #define SRSS_CLK_CAL_CNT1_CAL_COUNTER1_Msk 0xFFFFFFUL 688 #define SRSS_CLK_CAL_CNT1_CAL_RESET_Pos 29UL 689 #define SRSS_CLK_CAL_CNT1_CAL_RESET_Msk 0x20000000UL 690 #define SRSS_CLK_CAL_CNT1_CAL_CLK1_PRESENT_Pos 30UL 691 #define SRSS_CLK_CAL_CNT1_CAL_CLK1_PRESENT_Msk 0x40000000UL 692 #define SRSS_CLK_CAL_CNT1_CAL_COUNTER_DONE_Pos 31UL 693 #define SRSS_CLK_CAL_CNT1_CAL_COUNTER_DONE_Msk 0x80000000UL 694 /* SRSS.CLK_CAL_CNT2 */ 695 #define SRSS_CLK_CAL_CNT2_CAL_COUNTER2_Pos 0UL 696 #define SRSS_CLK_CAL_CNT2_CAL_COUNTER2_Msk 0xFFFFFFUL 697 /* SRSS.SRSS_INTR */ 698 #define SRSS_SRSS_INTR_WDT_MATCH_Pos 0UL 699 #define SRSS_SRSS_INTR_WDT_MATCH_Msk 0x1UL 700 #define SRSS_SRSS_INTR_CLK_CAL_Pos 5UL 701 #define SRSS_SRSS_INTR_CLK_CAL_Msk 0x20UL 702 #define SRSS_SRSS_INTR_AINTR_Pos 31UL 703 #define SRSS_SRSS_INTR_AINTR_Msk 0x80000000UL 704 /* SRSS.SRSS_INTR_SET */ 705 #define SRSS_SRSS_INTR_SET_WDT_MATCH_Pos 0UL 706 #define SRSS_SRSS_INTR_SET_WDT_MATCH_Msk 0x1UL 707 #define SRSS_SRSS_INTR_SET_CLK_CAL_Pos 5UL 708 #define SRSS_SRSS_INTR_SET_CLK_CAL_Msk 0x20UL 709 /* SRSS.SRSS_INTR_MASK */ 710 #define SRSS_SRSS_INTR_MASK_WDT_MATCH_Pos 0UL 711 #define SRSS_SRSS_INTR_MASK_WDT_MATCH_Msk 0x1UL 712 #define SRSS_SRSS_INTR_MASK_CLK_CAL_Pos 5UL 713 #define SRSS_SRSS_INTR_MASK_CLK_CAL_Msk 0x20UL 714 /* SRSS.SRSS_INTR_MASKED */ 715 #define SRSS_SRSS_INTR_MASKED_WDT_MATCH_Pos 0UL 716 #define SRSS_SRSS_INTR_MASKED_WDT_MATCH_Msk 0x1UL 717 #define SRSS_SRSS_INTR_MASKED_CLK_CAL_Pos 5UL 718 #define SRSS_SRSS_INTR_MASKED_CLK_CAL_Msk 0x20UL 719 #define SRSS_SRSS_INTR_MASKED_AINTR_Pos 31UL 720 #define SRSS_SRSS_INTR_MASKED_AINTR_Msk 0x80000000UL 721 /* SRSS.SRSS_AINTR */ 722 #define SRSS_SRSS_AINTR_HVLVD1_Pos 1UL 723 #define SRSS_SRSS_AINTR_HVLVD1_Msk 0x2UL 724 #define SRSS_SRSS_AINTR_HVLVD2_Pos 2UL 725 #define SRSS_SRSS_AINTR_HVLVD2_Msk 0x4UL 726 /* SRSS.SRSS_AINTR_SET */ 727 #define SRSS_SRSS_AINTR_SET_HVLVD1_Pos 1UL 728 #define SRSS_SRSS_AINTR_SET_HVLVD1_Msk 0x2UL 729 #define SRSS_SRSS_AINTR_SET_HVLVD2_Pos 2UL 730 #define SRSS_SRSS_AINTR_SET_HVLVD2_Msk 0x4UL 731 /* SRSS.SRSS_AINTR_MASK */ 732 #define SRSS_SRSS_AINTR_MASK_HVLVD1_Pos 1UL 733 #define SRSS_SRSS_AINTR_MASK_HVLVD1_Msk 0x2UL 734 #define SRSS_SRSS_AINTR_MASK_HVLVD2_Pos 2UL 735 #define SRSS_SRSS_AINTR_MASK_HVLVD2_Msk 0x4UL 736 /* SRSS.SRSS_AINTR_MASKED */ 737 #define SRSS_SRSS_AINTR_MASKED_HVLVD1_Pos 1UL 738 #define SRSS_SRSS_AINTR_MASKED_HVLVD1_Msk 0x2UL 739 #define SRSS_SRSS_AINTR_MASKED_HVLVD2_Pos 2UL 740 #define SRSS_SRSS_AINTR_MASKED_HVLVD2_Msk 0x4UL 741 /* SRSS.BOOT_DLM_CTL */ 742 #define SRSS_BOOT_DLM_CTL_REQUEST_Pos 0UL 743 #define SRSS_BOOT_DLM_CTL_REQUEST_Msk 0xFUL 744 #define SRSS_BOOT_DLM_CTL_INPUT_AVAIL_Pos 29UL 745 #define SRSS_BOOT_DLM_CTL_INPUT_AVAIL_Msk 0x20000000UL 746 #define SRSS_BOOT_DLM_CTL_RESET_Pos 30UL 747 #define SRSS_BOOT_DLM_CTL_RESET_Msk 0x40000000UL 748 #define SRSS_BOOT_DLM_CTL_WFA_Pos 31UL 749 #define SRSS_BOOT_DLM_CTL_WFA_Msk 0x80000000UL 750 /* SRSS.BOOT_DLM_CTL2 */ 751 #define SRSS_BOOT_DLM_CTL2_APP_CTL_Pos 0UL 752 #define SRSS_BOOT_DLM_CTL2_APP_CTL_Msk 0xFFFFFFFFUL 753 /* SRSS.BOOT_DLM_STATUS */ 754 #define SRSS_BOOT_DLM_STATUS_DEBUG_STATUS_Pos 0UL 755 #define SRSS_BOOT_DLM_STATUS_DEBUG_STATUS_Msk 0xFFFFFFFFUL 756 /* SRSS.RES_SOFT_CTL */ 757 #define SRSS_RES_SOFT_CTL_TRIGGER_SOFT_Pos 0UL 758 #define SRSS_RES_SOFT_CTL_TRIGGER_SOFT_Msk 0x1UL 759 /* SRSS.BOOT_STATUS */ 760 #define SRSS_BOOT_STATUS_DEBUG_STATUS_Pos 0UL 761 #define SRSS_BOOT_STATUS_DEBUG_STATUS_Msk 0xFFFFFFFFUL 762 /* SRSS.BOOT_ENTRY */ 763 #define SRSS_BOOT_ENTRY_WARM_BOOT_ENTRY_Pos 0UL 764 #define SRSS_BOOT_ENTRY_WARM_BOOT_ENTRY_Msk 0xFFFFFFFFUL 765 /* SRSS.PWR_HIB_DATA */ 766 #define SRSS_PWR_HIB_DATA_HIB_DATA_Pos 0UL 767 #define SRSS_PWR_HIB_DATA_HIB_DATA_Msk 0xFFFFFFFFUL 768 /* SRSS.PWR_HIB_WAKE_CTL */ 769 #define SRSS_PWR_HIB_WAKE_CTL_HIB_WAKE_SRC_Pos 0UL 770 #define SRSS_PWR_HIB_WAKE_CTL_HIB_WAKE_SRC_Msk 0xFFFFFFUL 771 #define SRSS_PWR_HIB_WAKE_CTL_HIB_WAKE_CSV_BAK_Pos 29UL 772 #define SRSS_PWR_HIB_WAKE_CTL_HIB_WAKE_CSV_BAK_Msk 0x20000000UL 773 #define SRSS_PWR_HIB_WAKE_CTL_HIB_WAKE_RTC_Pos 30UL 774 #define SRSS_PWR_HIB_WAKE_CTL_HIB_WAKE_RTC_Msk 0x40000000UL 775 #define SRSS_PWR_HIB_WAKE_CTL_HIB_WAKE_WDT_Pos 31UL 776 #define SRSS_PWR_HIB_WAKE_CTL_HIB_WAKE_WDT_Msk 0x80000000UL 777 /* SRSS.PWR_HIB_WAKE_CTL2 */ 778 #define SRSS_PWR_HIB_WAKE_CTL2_HIB_WAKE_SRC_Pos 0UL 779 #define SRSS_PWR_HIB_WAKE_CTL2_HIB_WAKE_SRC_Msk 0xFFFFFFUL 780 /* SRSS.PWR_HIB_WAKE_CAUSE */ 781 #define SRSS_PWR_HIB_WAKE_CAUSE_HIB_WAKE_SRC_Pos 0UL 782 #define SRSS_PWR_HIB_WAKE_CAUSE_HIB_WAKE_SRC_Msk 0xFFFFFFUL 783 #define SRSS_PWR_HIB_WAKE_CAUSE_HIB_WAKE_CSV_BAK_Pos 29UL 784 #define SRSS_PWR_HIB_WAKE_CAUSE_HIB_WAKE_CSV_BAK_Msk 0x20000000UL 785 #define SRSS_PWR_HIB_WAKE_CAUSE_HIB_WAKE_RTC_Pos 30UL 786 #define SRSS_PWR_HIB_WAKE_CAUSE_HIB_WAKE_RTC_Msk 0x40000000UL 787 #define SRSS_PWR_HIB_WAKE_CAUSE_HIB_WAKE_WDT_Pos 31UL 788 #define SRSS_PWR_HIB_WAKE_CAUSE_HIB_WAKE_WDT_Msk 0x80000000UL 789 /* SRSS.PWR_CTL */ 790 #define SRSS_PWR_CTL_POWER_MODE_Pos 0UL 791 #define SRSS_PWR_CTL_POWER_MODE_Msk 0x3UL 792 #define SRSS_PWR_CTL_DEBUG_SESSION_Pos 4UL 793 #define SRSS_PWR_CTL_DEBUG_SESSION_Msk 0x10UL 794 #define SRSS_PWR_CTL_LPM_READY_Pos 5UL 795 #define SRSS_PWR_CTL_LPM_READY_Msk 0x20UL 796 /* SRSS.PWR_CTL2 */ 797 #define SRSS_PWR_CTL2_LINREG_DIS_Pos 0UL 798 #define SRSS_PWR_CTL2_LINREG_DIS_Msk 0x1UL 799 #define SRSS_PWR_CTL2_LINREG_OK_Pos 1UL 800 #define SRSS_PWR_CTL2_LINREG_OK_Msk 0x2UL 801 #define SRSS_PWR_CTL2_LINREG_LPMODE_Pos 2UL 802 #define SRSS_PWR_CTL2_LINREG_LPMODE_Msk 0x4UL 803 #define SRSS_PWR_CTL2_DPSLP_REG_DIS_Pos 4UL 804 #define SRSS_PWR_CTL2_DPSLP_REG_DIS_Msk 0x10UL 805 #define SRSS_PWR_CTL2_RET_REG_DIS_Pos 8UL 806 #define SRSS_PWR_CTL2_RET_REG_DIS_Msk 0x100UL 807 #define SRSS_PWR_CTL2_NWELL_REG_DIS_Pos 12UL 808 #define SRSS_PWR_CTL2_NWELL_REG_DIS_Msk 0x1000UL 809 #define SRSS_PWR_CTL2_REFV_DIS_Pos 16UL 810 #define SRSS_PWR_CTL2_REFV_DIS_Msk 0x10000UL 811 #define SRSS_PWR_CTL2_REFV_OK_Pos 17UL 812 #define SRSS_PWR_CTL2_REFV_OK_Msk 0x20000UL 813 #define SRSS_PWR_CTL2_REFVBUF_DIS_Pos 20UL 814 #define SRSS_PWR_CTL2_REFVBUF_DIS_Msk 0x100000UL 815 #define SRSS_PWR_CTL2_REFVBUF_OK_Pos 21UL 816 #define SRSS_PWR_CTL2_REFVBUF_OK_Msk 0x200000UL 817 #define SRSS_PWR_CTL2_REFI_DIS_Pos 24UL 818 #define SRSS_PWR_CTL2_REFI_DIS_Msk 0x1000000UL 819 #define SRSS_PWR_CTL2_REFI_OK_Pos 25UL 820 #define SRSS_PWR_CTL2_REFI_OK_Msk 0x2000000UL 821 #define SRSS_PWR_CTL2_REFI_LPMODE_Pos 26UL 822 #define SRSS_PWR_CTL2_REFI_LPMODE_Msk 0x4000000UL 823 #define SRSS_PWR_CTL2_PORBOD_LPMODE_Pos 27UL 824 #define SRSS_PWR_CTL2_PORBOD_LPMODE_Msk 0x8000000UL 825 #define SRSS_PWR_CTL2_BGREF_LPMODE_Pos 28UL 826 #define SRSS_PWR_CTL2_BGREF_LPMODE_Msk 0x10000000UL 827 #define SRSS_PWR_CTL2_FREEZE_DPSLP_Pos 30UL 828 #define SRSS_PWR_CTL2_FREEZE_DPSLP_Msk 0x40000000UL 829 #define SRSS_PWR_CTL2_PLL_LS_BYPASS_Pos 31UL 830 #define SRSS_PWR_CTL2_PLL_LS_BYPASS_Msk 0x80000000UL 831 /* SRSS.PWR_HIBERNATE */ 832 #define SRSS_PWR_HIBERNATE_TOKEN_Pos 0UL 833 #define SRSS_PWR_HIBERNATE_TOKEN_Msk 0xFFUL 834 #define SRSS_PWR_HIBERNATE_UNLOCK_Pos 8UL 835 #define SRSS_PWR_HIBERNATE_UNLOCK_Msk 0xFF00UL 836 #define SRSS_PWR_HIBERNATE_FREEZE_Pos 17UL 837 #define SRSS_PWR_HIBERNATE_FREEZE_Msk 0x20000UL 838 #define SRSS_PWR_HIBERNATE_MASK_HIBALARM_Pos 18UL 839 #define SRSS_PWR_HIBERNATE_MASK_HIBALARM_Msk 0x40000UL 840 #define SRSS_PWR_HIBERNATE_MASK_HIBWDT_Pos 19UL 841 #define SRSS_PWR_HIBERNATE_MASK_HIBWDT_Msk 0x80000UL 842 #define SRSS_PWR_HIBERNATE_POLARITY_HIBPIN_Pos 20UL 843 #define SRSS_PWR_HIBERNATE_POLARITY_HIBPIN_Msk 0xF00000UL 844 #define SRSS_PWR_HIBERNATE_MASK_HIBPIN_Pos 24UL 845 #define SRSS_PWR_HIBERNATE_MASK_HIBPIN_Msk 0xF000000UL 846 #define SRSS_PWR_HIBERNATE_SENSE_MODE_Pos 29UL 847 #define SRSS_PWR_HIBERNATE_SENSE_MODE_Msk 0x20000000UL 848 #define SRSS_PWR_HIBERNATE_HIBERNATE_DISABLE_Pos 30UL 849 #define SRSS_PWR_HIBERNATE_HIBERNATE_DISABLE_Msk 0x40000000UL 850 #define SRSS_PWR_HIBERNATE_HIBERNATE_Pos 31UL 851 #define SRSS_PWR_HIBERNATE_HIBERNATE_Msk 0x80000000UL 852 /* SRSS.PWR_BUCK_CTL */ 853 #define SRSS_PWR_BUCK_CTL_BUCK_OUT1_SEL_Pos 0UL 854 #define SRSS_PWR_BUCK_CTL_BUCK_OUT1_SEL_Msk 0x7UL 855 #define SRSS_PWR_BUCK_CTL_BUCK_EN_Pos 30UL 856 #define SRSS_PWR_BUCK_CTL_BUCK_EN_Msk 0x40000000UL 857 #define SRSS_PWR_BUCK_CTL_BUCK_OUT1_EN_Pos 31UL 858 #define SRSS_PWR_BUCK_CTL_BUCK_OUT1_EN_Msk 0x80000000UL 859 /* SRSS.PWR_BUCK_CTL2 */ 860 #define SRSS_PWR_BUCK_CTL2_BUCK_OUT2_SEL_Pos 0UL 861 #define SRSS_PWR_BUCK_CTL2_BUCK_OUT2_SEL_Msk 0x7UL 862 #define SRSS_PWR_BUCK_CTL2_BUCK_OUT2_HW_SEL_Pos 30UL 863 #define SRSS_PWR_BUCK_CTL2_BUCK_OUT2_HW_SEL_Msk 0x40000000UL 864 #define SRSS_PWR_BUCK_CTL2_BUCK_OUT2_EN_Pos 31UL 865 #define SRSS_PWR_BUCK_CTL2_BUCK_OUT2_EN_Msk 0x80000000UL 866 /* SRSS.PWR_SSV_CTL */ 867 #define SRSS_PWR_SSV_CTL_BODVDDD_VSEL_Pos 0UL 868 #define SRSS_PWR_SSV_CTL_BODVDDD_VSEL_Msk 0x1UL 869 #define SRSS_PWR_SSV_CTL_BODVDDD_ENABLE_Pos 3UL 870 #define SRSS_PWR_SSV_CTL_BODVDDD_ENABLE_Msk 0x8UL 871 #define SRSS_PWR_SSV_CTL_BODVDDA_VSEL_Pos 4UL 872 #define SRSS_PWR_SSV_CTL_BODVDDA_VSEL_Msk 0x10UL 873 #define SRSS_PWR_SSV_CTL_BODVDDA_ACTION_Pos 6UL 874 #define SRSS_PWR_SSV_CTL_BODVDDA_ACTION_Msk 0xC0UL 875 #define SRSS_PWR_SSV_CTL_BODVDDA_ENABLE_Pos 8UL 876 #define SRSS_PWR_SSV_CTL_BODVDDA_ENABLE_Msk 0x100UL 877 #define SRSS_PWR_SSV_CTL_BODVCCD_ENABLE_Pos 11UL 878 #define SRSS_PWR_SSV_CTL_BODVCCD_ENABLE_Msk 0x800UL 879 #define SRSS_PWR_SSV_CTL_OVDVDDD_VSEL_Pos 16UL 880 #define SRSS_PWR_SSV_CTL_OVDVDDD_VSEL_Msk 0x10000UL 881 #define SRSS_PWR_SSV_CTL_OVDVDDD_ENABLE_Pos 19UL 882 #define SRSS_PWR_SSV_CTL_OVDVDDD_ENABLE_Msk 0x80000UL 883 #define SRSS_PWR_SSV_CTL_OVDVDDA_VSEL_Pos 20UL 884 #define SRSS_PWR_SSV_CTL_OVDVDDA_VSEL_Msk 0x100000UL 885 #define SRSS_PWR_SSV_CTL_OVDVDDA_ACTION_Pos 22UL 886 #define SRSS_PWR_SSV_CTL_OVDVDDA_ACTION_Msk 0xC00000UL 887 #define SRSS_PWR_SSV_CTL_OVDVDDA_ENABLE_Pos 24UL 888 #define SRSS_PWR_SSV_CTL_OVDVDDA_ENABLE_Msk 0x1000000UL 889 #define SRSS_PWR_SSV_CTL_OVDVCCD_ENABLE_Pos 27UL 890 #define SRSS_PWR_SSV_CTL_OVDVCCD_ENABLE_Msk 0x8000000UL 891 /* SRSS.PWR_SSV_STATUS */ 892 #define SRSS_PWR_SSV_STATUS_BODVDDD_OK_Pos 0UL 893 #define SRSS_PWR_SSV_STATUS_BODVDDD_OK_Msk 0x1UL 894 #define SRSS_PWR_SSV_STATUS_BODVDDA_OK_Pos 1UL 895 #define SRSS_PWR_SSV_STATUS_BODVDDA_OK_Msk 0x2UL 896 #define SRSS_PWR_SSV_STATUS_BODVCCD_OK_Pos 2UL 897 #define SRSS_PWR_SSV_STATUS_BODVCCD_OK_Msk 0x4UL 898 #define SRSS_PWR_SSV_STATUS_OVDVDDD_OK_Pos 8UL 899 #define SRSS_PWR_SSV_STATUS_OVDVDDD_OK_Msk 0x100UL 900 #define SRSS_PWR_SSV_STATUS_OVDVDDA_OK_Pos 9UL 901 #define SRSS_PWR_SSV_STATUS_OVDVDDA_OK_Msk 0x200UL 902 #define SRSS_PWR_SSV_STATUS_OVDVCCD_OK_Pos 10UL 903 #define SRSS_PWR_SSV_STATUS_OVDVCCD_OK_Msk 0x400UL 904 #define SRSS_PWR_SSV_STATUS_OCD_ACT_LINREG_OK_Pos 16UL 905 #define SRSS_PWR_SSV_STATUS_OCD_ACT_LINREG_OK_Msk 0x10000UL 906 #define SRSS_PWR_SSV_STATUS_OCD_DPSLP_REG_OK_Pos 17UL 907 #define SRSS_PWR_SSV_STATUS_OCD_DPSLP_REG_OK_Msk 0x20000UL 908 /* SRSS.PWR_LVD_CTL */ 909 #define SRSS_PWR_LVD_CTL_HVLVD1_TRIPSEL_Pos 0UL 910 #define SRSS_PWR_LVD_CTL_HVLVD1_TRIPSEL_Msk 0xFUL 911 #define SRSS_PWR_LVD_CTL_HVLVD1_SRCSEL_Pos 4UL 912 #define SRSS_PWR_LVD_CTL_HVLVD1_SRCSEL_Msk 0x70UL 913 #define SRSS_PWR_LVD_CTL_HVLVD1_EN_Pos 7UL 914 #define SRSS_PWR_LVD_CTL_HVLVD1_EN_Msk 0x80UL 915 #define SRSS_PWR_LVD_CTL_HVLVD1_TRIPSEL_HT_Pos 8UL 916 #define SRSS_PWR_LVD_CTL_HVLVD1_TRIPSEL_HT_Msk 0x1F00UL 917 #define SRSS_PWR_LVD_CTL_HVLVD1_DPSLP_EN_HT_Pos 14UL 918 #define SRSS_PWR_LVD_CTL_HVLVD1_DPSLP_EN_HT_Msk 0x4000UL 919 #define SRSS_PWR_LVD_CTL_HVLVD1_EN_HT_Pos 15UL 920 #define SRSS_PWR_LVD_CTL_HVLVD1_EN_HT_Msk 0x8000UL 921 #define SRSS_PWR_LVD_CTL_HVLVD1_EDGE_SEL_Pos 16UL 922 #define SRSS_PWR_LVD_CTL_HVLVD1_EDGE_SEL_Msk 0x30000UL 923 #define SRSS_PWR_LVD_CTL_HVLVD1_ACTION_Pos 18UL 924 #define SRSS_PWR_LVD_CTL_HVLVD1_ACTION_Msk 0x40000UL 925 /* SRSS.PWR_LVD_CTL2 */ 926 #define SRSS_PWR_LVD_CTL2_HVLVD2_TRIPSEL_HT_Pos 8UL 927 #define SRSS_PWR_LVD_CTL2_HVLVD2_TRIPSEL_HT_Msk 0x1F00UL 928 #define SRSS_PWR_LVD_CTL2_HVLVD2_DPSLP_EN_HT_Pos 14UL 929 #define SRSS_PWR_LVD_CTL2_HVLVD2_DPSLP_EN_HT_Msk 0x4000UL 930 #define SRSS_PWR_LVD_CTL2_HVLVD2_EN_HT_Pos 15UL 931 #define SRSS_PWR_LVD_CTL2_HVLVD2_EN_HT_Msk 0x8000UL 932 #define SRSS_PWR_LVD_CTL2_HVLVD2_EDGE_SEL_Pos 16UL 933 #define SRSS_PWR_LVD_CTL2_HVLVD2_EDGE_SEL_Msk 0x30000UL 934 #define SRSS_PWR_LVD_CTL2_HVLVD2_ACTION_Pos 18UL 935 #define SRSS_PWR_LVD_CTL2_HVLVD2_ACTION_Msk 0x40000UL 936 /* SRSS.PWR_REGHC_CTL */ 937 #define SRSS_PWR_REGHC_CTL_REGHC_MODE_Pos 0UL 938 #define SRSS_PWR_REGHC_CTL_REGHC_MODE_Msk 0x1UL 939 #define SRSS_PWR_REGHC_CTL_REGHC_PMIC_DRV_VOUT_Pos 2UL 940 #define SRSS_PWR_REGHC_CTL_REGHC_PMIC_DRV_VOUT_Msk 0xCUL 941 #define SRSS_PWR_REGHC_CTL_REGHC_VADJ_Pos 4UL 942 #define SRSS_PWR_REGHC_CTL_REGHC_VADJ_Msk 0x1F0UL 943 #define SRSS_PWR_REGHC_CTL_REGHC_PMIC_USE_LINREG_Pos 10UL 944 #define SRSS_PWR_REGHC_CTL_REGHC_PMIC_USE_LINREG_Msk 0x400UL 945 #define SRSS_PWR_REGHC_CTL_REGHC_PMIC_USE_RADJ_Pos 11UL 946 #define SRSS_PWR_REGHC_CTL_REGHC_PMIC_USE_RADJ_Msk 0x800UL 947 #define SRSS_PWR_REGHC_CTL_REGHC_PMIC_RADJ_Pos 12UL 948 #define SRSS_PWR_REGHC_CTL_REGHC_PMIC_RADJ_Msk 0x7000UL 949 #define SRSS_PWR_REGHC_CTL_REGHC_PMIC_CTL_OUTEN_Pos 16UL 950 #define SRSS_PWR_REGHC_CTL_REGHC_PMIC_CTL_OUTEN_Msk 0x10000UL 951 #define SRSS_PWR_REGHC_CTL_REGHC_PMIC_CTL_POLARITY_Pos 17UL 952 #define SRSS_PWR_REGHC_CTL_REGHC_PMIC_CTL_POLARITY_Msk 0x20000UL 953 #define SRSS_PWR_REGHC_CTL_REGHC_PMIC_STATUS_INEN_Pos 18UL 954 #define SRSS_PWR_REGHC_CTL_REGHC_PMIC_STATUS_INEN_Msk 0x40000UL 955 #define SRSS_PWR_REGHC_CTL_REGHC_PMIC_STATUS_POLARITY_Pos 19UL 956 #define SRSS_PWR_REGHC_CTL_REGHC_PMIC_STATUS_POLARITY_Msk 0x80000UL 957 #define SRSS_PWR_REGHC_CTL_REGHC_PMIC_STATUS_WAIT_Pos 20UL 958 #define SRSS_PWR_REGHC_CTL_REGHC_PMIC_STATUS_WAIT_Msk 0x3FF00000UL 959 #define SRSS_PWR_REGHC_CTL_REGHC_TRANS_USE_OCD_Pos 30UL 960 #define SRSS_PWR_REGHC_CTL_REGHC_TRANS_USE_OCD_Msk 0x40000000UL 961 #define SRSS_PWR_REGHC_CTL_REGHC_CONFIGURED_Pos 31UL 962 #define SRSS_PWR_REGHC_CTL_REGHC_CONFIGURED_Msk 0x80000000UL 963 /* SRSS.PWR_REGHC_STATUS */ 964 #define SRSS_PWR_REGHC_STATUS_REGHC_ENABLED_Pos 0UL 965 #define SRSS_PWR_REGHC_STATUS_REGHC_ENABLED_Msk 0x1UL 966 #define SRSS_PWR_REGHC_STATUS_REGHC_OCD_OK_Pos 1UL 967 #define SRSS_PWR_REGHC_STATUS_REGHC_OCD_OK_Msk 0x2UL 968 #define SRSS_PWR_REGHC_STATUS_REGHC_CKT_OK_Pos 2UL 969 #define SRSS_PWR_REGHC_STATUS_REGHC_CKT_OK_Msk 0x4UL 970 #define SRSS_PWR_REGHC_STATUS_REGHC_UV_OUT_Pos 8UL 971 #define SRSS_PWR_REGHC_STATUS_REGHC_UV_OUT_Msk 0x100UL 972 #define SRSS_PWR_REGHC_STATUS_REGHC_OV_OUT_Pos 9UL 973 #define SRSS_PWR_REGHC_STATUS_REGHC_OV_OUT_Msk 0x200UL 974 #define SRSS_PWR_REGHC_STATUS_REGHC_PMIC_STATUS_OK_Pos 12UL 975 #define SRSS_PWR_REGHC_STATUS_REGHC_PMIC_STATUS_OK_Msk 0x1000UL 976 #define SRSS_PWR_REGHC_STATUS_REGHC_SEQ_BUSY_Pos 31UL 977 #define SRSS_PWR_REGHC_STATUS_REGHC_SEQ_BUSY_Msk 0x80000000UL 978 /* SRSS.PWR_REGHC_CTL2 */ 979 #define SRSS_PWR_REGHC_CTL2_REGHC_PMIC_STATUS_TIMEOUT_Pos 0UL 980 #define SRSS_PWR_REGHC_CTL2_REGHC_PMIC_STATUS_TIMEOUT_Msk 0xFFUL 981 #define SRSS_PWR_REGHC_CTL2_REGHC_EN_Pos 31UL 982 #define SRSS_PWR_REGHC_CTL2_REGHC_EN_Msk 0x80000000UL 983 /* SRSS.PWR_PMIC_CTL */ 984 #define SRSS_PWR_PMIC_CTL_PMIC_VREF_Pos 2UL 985 #define SRSS_PWR_PMIC_CTL_PMIC_VREF_Msk 0xCUL 986 #define SRSS_PWR_PMIC_CTL_PMIC_VADJ_Pos 4UL 987 #define SRSS_PWR_PMIC_CTL_PMIC_VADJ_Msk 0x1F0UL 988 #define SRSS_PWR_PMIC_CTL_PMIC_USE_LINREG_Pos 10UL 989 #define SRSS_PWR_PMIC_CTL_PMIC_USE_LINREG_Msk 0x400UL 990 #define SRSS_PWR_PMIC_CTL_PMIC_VADJ_BUF_EN_Pos 15UL 991 #define SRSS_PWR_PMIC_CTL_PMIC_VADJ_BUF_EN_Msk 0x8000UL 992 #define SRSS_PWR_PMIC_CTL_PMIC_CTL_OUTEN_Pos 16UL 993 #define SRSS_PWR_PMIC_CTL_PMIC_CTL_OUTEN_Msk 0x10000UL 994 #define SRSS_PWR_PMIC_CTL_PMIC_CTL_POLARITY_Pos 17UL 995 #define SRSS_PWR_PMIC_CTL_PMIC_CTL_POLARITY_Msk 0x20000UL 996 #define SRSS_PWR_PMIC_CTL_PMIC_STATUS_INEN_Pos 18UL 997 #define SRSS_PWR_PMIC_CTL_PMIC_STATUS_INEN_Msk 0x40000UL 998 #define SRSS_PWR_PMIC_CTL_PMIC_STATUS_POLARITY_Pos 19UL 999 #define SRSS_PWR_PMIC_CTL_PMIC_STATUS_POLARITY_Msk 0x80000UL 1000 #define SRSS_PWR_PMIC_CTL_PMIC_STATUS_WAIT_Pos 20UL 1001 #define SRSS_PWR_PMIC_CTL_PMIC_STATUS_WAIT_Msk 0x3FF00000UL 1002 #define SRSS_PWR_PMIC_CTL_PMIC_CONFIGURED_Pos 31UL 1003 #define SRSS_PWR_PMIC_CTL_PMIC_CONFIGURED_Msk 0x80000000UL 1004 /* SRSS.PWR_PMIC_STATUS */ 1005 #define SRSS_PWR_PMIC_STATUS_PMIC_ENABLED_Pos 0UL 1006 #define SRSS_PWR_PMIC_STATUS_PMIC_ENABLED_Msk 0x1UL 1007 #define SRSS_PWR_PMIC_STATUS_PMIC_STATUS_OK_Pos 12UL 1008 #define SRSS_PWR_PMIC_STATUS_PMIC_STATUS_OK_Msk 0x1000UL 1009 #define SRSS_PWR_PMIC_STATUS_PMIC_SEQ_BUSY_Pos 31UL 1010 #define SRSS_PWR_PMIC_STATUS_PMIC_SEQ_BUSY_Msk 0x80000000UL 1011 /* SRSS.PWR_PMIC_CTL2 */ 1012 #define SRSS_PWR_PMIC_CTL2_PMIC_STATUS_TIMEOUT_Pos 0UL 1013 #define SRSS_PWR_PMIC_CTL2_PMIC_STATUS_TIMEOUT_Msk 0xFFUL 1014 #define SRSS_PWR_PMIC_CTL2_PMIC_EN_Pos 31UL 1015 #define SRSS_PWR_PMIC_CTL2_PMIC_EN_Msk 0x80000000UL 1016 /* SRSS.PWR_PMIC_CTL4 */ 1017 #define SRSS_PWR_PMIC_CTL4_PMIC_VADJ_DIS_Pos 30UL 1018 #define SRSS_PWR_PMIC_CTL4_PMIC_VADJ_DIS_Msk 0x40000000UL 1019 #define SRSS_PWR_PMIC_CTL4_PMIC_DPSLP_Pos 31UL 1020 #define SRSS_PWR_PMIC_CTL4_PMIC_DPSLP_Msk 0x80000000UL 1021 /* SRSS.CLK_PATH_SELECT */ 1022 #define SRSS_CLK_PATH_SELECT_PATH_MUX_Pos 0UL 1023 #define SRSS_CLK_PATH_SELECT_PATH_MUX_Msk 0x7UL 1024 /* SRSS.CLK_ROOT_SELECT */ 1025 #define SRSS_CLK_ROOT_SELECT_ROOT_MUX_Pos 0UL 1026 #define SRSS_CLK_ROOT_SELECT_ROOT_MUX_Msk 0xFUL 1027 #define SRSS_CLK_ROOT_SELECT_ROOT_DIV_Pos 4UL 1028 #define SRSS_CLK_ROOT_SELECT_ROOT_DIV_Msk 0x30UL 1029 #define SRSS_CLK_ROOT_SELECT_ROOT_DIV_INT_Pos 8UL 1030 #define SRSS_CLK_ROOT_SELECT_ROOT_DIV_INT_Msk 0xF00UL 1031 #define SRSS_CLK_ROOT_SELECT_ENABLE_Pos 31UL 1032 #define SRSS_CLK_ROOT_SELECT_ENABLE_Msk 0x80000000UL 1033 /* SRSS.CLK_DIRECT_SELECT */ 1034 #define SRSS_CLK_DIRECT_SELECT_DIRECT_MUX_Pos 8UL 1035 #define SRSS_CLK_DIRECT_SELECT_DIRECT_MUX_Msk 0x100UL 1036 /* SRSS.CLK_SELECT */ 1037 #define SRSS_CLK_SELECT_LFCLK_SEL_Pos 0UL 1038 #define SRSS_CLK_SELECT_LFCLK_SEL_Msk 0x7UL 1039 #define SRSS_CLK_SELECT_PUMP_SEL_Pos 8UL 1040 #define SRSS_CLK_SELECT_PUMP_SEL_Msk 0xF00UL 1041 #define SRSS_CLK_SELECT_PUMP_DIV_Pos 12UL 1042 #define SRSS_CLK_SELECT_PUMP_DIV_Msk 0x7000UL 1043 #define SRSS_CLK_SELECT_PUMP_ENABLE_Pos 15UL 1044 #define SRSS_CLK_SELECT_PUMP_ENABLE_Msk 0x8000UL 1045 /* SRSS.CLK_ILO0_CONFIG */ 1046 #define SRSS_CLK_ILO0_CONFIG_ILO0_BACKUP_Pos 0UL 1047 #define SRSS_CLK_ILO0_CONFIG_ILO0_BACKUP_Msk 0x1UL 1048 #define SRSS_CLK_ILO0_CONFIG_ILO0_MON_ENABLE_Pos 30UL 1049 #define SRSS_CLK_ILO0_CONFIG_ILO0_MON_ENABLE_Msk 0x40000000UL 1050 #define SRSS_CLK_ILO0_CONFIG_ENABLE_Pos 31UL 1051 #define SRSS_CLK_ILO0_CONFIG_ENABLE_Msk 0x80000000UL 1052 /* SRSS.CLK_ILO1_CONFIG */ 1053 #define SRSS_CLK_ILO1_CONFIG_ILO1_MON_ENABLE_Pos 30UL 1054 #define SRSS_CLK_ILO1_CONFIG_ILO1_MON_ENABLE_Msk 0x40000000UL 1055 #define SRSS_CLK_ILO1_CONFIG_ENABLE_Pos 31UL 1056 #define SRSS_CLK_ILO1_CONFIG_ENABLE_Msk 0x80000000UL 1057 /* SRSS.CLK_IMO_CONFIG */ 1058 #define SRSS_CLK_IMO_CONFIG_DPSLP_ENABLE_Pos 30UL 1059 #define SRSS_CLK_IMO_CONFIG_DPSLP_ENABLE_Msk 0x40000000UL 1060 #define SRSS_CLK_IMO_CONFIG_ENABLE_Pos 31UL 1061 #define SRSS_CLK_IMO_CONFIG_ENABLE_Msk 0x80000000UL 1062 /* SRSS.CLK_ECO_CONFIG */ 1063 #define SRSS_CLK_ECO_CONFIG_AGC_EN_Pos 1UL 1064 #define SRSS_CLK_ECO_CONFIG_AGC_EN_Msk 0x2UL 1065 #define SRSS_CLK_ECO_CONFIG_ECO_DIV_DISABLE_Pos 27UL 1066 #define SRSS_CLK_ECO_CONFIG_ECO_DIV_DISABLE_Msk 0x8000000UL 1067 #define SRSS_CLK_ECO_CONFIG_ECO_DIV_ENABLE_Pos 28UL 1068 #define SRSS_CLK_ECO_CONFIG_ECO_DIV_ENABLE_Msk 0x10000000UL 1069 #define SRSS_CLK_ECO_CONFIG_ECO_EN_Pos 31UL 1070 #define SRSS_CLK_ECO_CONFIG_ECO_EN_Msk 0x80000000UL 1071 /* SRSS.CLK_ECO_PRESCALE */ 1072 #define SRSS_CLK_ECO_PRESCALE_ECO_DIV_ENABLED_Pos 0UL 1073 #define SRSS_CLK_ECO_PRESCALE_ECO_DIV_ENABLED_Msk 0x1UL 1074 #define SRSS_CLK_ECO_PRESCALE_ECO_FRAC_DIV_Pos 8UL 1075 #define SRSS_CLK_ECO_PRESCALE_ECO_FRAC_DIV_Msk 0xFF00UL 1076 #define SRSS_CLK_ECO_PRESCALE_ECO_INT_DIV_Pos 16UL 1077 #define SRSS_CLK_ECO_PRESCALE_ECO_INT_DIV_Msk 0x3FF0000UL 1078 /* SRSS.CLK_ECO_STATUS */ 1079 #define SRSS_CLK_ECO_STATUS_ECO_OK_Pos 0UL 1080 #define SRSS_CLK_ECO_STATUS_ECO_OK_Msk 0x1UL 1081 #define SRSS_CLK_ECO_STATUS_ECO_READY_Pos 1UL 1082 #define SRSS_CLK_ECO_STATUS_ECO_READY_Msk 0x2UL 1083 /* SRSS.CLK_PILO_CONFIG */ 1084 #define SRSS_CLK_PILO_CONFIG_PILO_BACKUP_Pos 0UL 1085 #define SRSS_CLK_PILO_CONFIG_PILO_BACKUP_Msk 0x1UL 1086 #define SRSS_CLK_PILO_CONFIG_PILO_TCSC_EN_Pos 16UL 1087 #define SRSS_CLK_PILO_CONFIG_PILO_TCSC_EN_Msk 0x10000UL 1088 #define SRSS_CLK_PILO_CONFIG_PILO_EN_Pos 31UL 1089 #define SRSS_CLK_PILO_CONFIG_PILO_EN_Msk 0x80000000UL 1090 /* SRSS.CLK_FLL_CONFIG */ 1091 #define SRSS_CLK_FLL_CONFIG_FLL_MULT_Pos 0UL 1092 #define SRSS_CLK_FLL_CONFIG_FLL_MULT_Msk 0x3FFFFUL 1093 #define SRSS_CLK_FLL_CONFIG_FLL_OUTPUT_DIV_Pos 24UL 1094 #define SRSS_CLK_FLL_CONFIG_FLL_OUTPUT_DIV_Msk 0x1000000UL 1095 #define SRSS_CLK_FLL_CONFIG_FLL_ENABLE_Pos 31UL 1096 #define SRSS_CLK_FLL_CONFIG_FLL_ENABLE_Msk 0x80000000UL 1097 /* SRSS.CLK_FLL_CONFIG2 */ 1098 #define SRSS_CLK_FLL_CONFIG2_FLL_REF_DIV_Pos 0UL 1099 #define SRSS_CLK_FLL_CONFIG2_FLL_REF_DIV_Msk 0x1FFFUL 1100 #define SRSS_CLK_FLL_CONFIG2_LOCK_TOL_Pos 16UL 1101 #define SRSS_CLK_FLL_CONFIG2_LOCK_TOL_Msk 0xFF0000UL 1102 #define SRSS_CLK_FLL_CONFIG2_UPDATE_TOL_Pos 24UL 1103 #define SRSS_CLK_FLL_CONFIG2_UPDATE_TOL_Msk 0xFF000000UL 1104 /* SRSS.CLK_FLL_CONFIG3 */ 1105 #define SRSS_CLK_FLL_CONFIG3_FLL_LF_IGAIN_Pos 0UL 1106 #define SRSS_CLK_FLL_CONFIG3_FLL_LF_IGAIN_Msk 0xFUL 1107 #define SRSS_CLK_FLL_CONFIG3_FLL_LF_PGAIN_Pos 4UL 1108 #define SRSS_CLK_FLL_CONFIG3_FLL_LF_PGAIN_Msk 0xF0UL 1109 #define SRSS_CLK_FLL_CONFIG3_SETTLING_COUNT_Pos 8UL 1110 #define SRSS_CLK_FLL_CONFIG3_SETTLING_COUNT_Msk 0x1FFF00UL 1111 #define SRSS_CLK_FLL_CONFIG3_BYPASS_SEL_Pos 28UL 1112 #define SRSS_CLK_FLL_CONFIG3_BYPASS_SEL_Msk 0x30000000UL 1113 /* SRSS.CLK_FLL_CONFIG4 */ 1114 #define SRSS_CLK_FLL_CONFIG4_CCO_LIMIT_Pos 0UL 1115 #define SRSS_CLK_FLL_CONFIG4_CCO_LIMIT_Msk 0xFFUL 1116 #define SRSS_CLK_FLL_CONFIG4_CCO_RANGE_Pos 8UL 1117 #define SRSS_CLK_FLL_CONFIG4_CCO_RANGE_Msk 0x700UL 1118 #define SRSS_CLK_FLL_CONFIG4_CCO_FREQ_Pos 16UL 1119 #define SRSS_CLK_FLL_CONFIG4_CCO_FREQ_Msk 0x1FF0000UL 1120 #define SRSS_CLK_FLL_CONFIG4_CCO_HW_UPDATE_DIS_Pos 30UL 1121 #define SRSS_CLK_FLL_CONFIG4_CCO_HW_UPDATE_DIS_Msk 0x40000000UL 1122 #define SRSS_CLK_FLL_CONFIG4_CCO_ENABLE_Pos 31UL 1123 #define SRSS_CLK_FLL_CONFIG4_CCO_ENABLE_Msk 0x80000000UL 1124 /* SRSS.CLK_FLL_STATUS */ 1125 #define SRSS_CLK_FLL_STATUS_LOCKED_Pos 0UL 1126 #define SRSS_CLK_FLL_STATUS_LOCKED_Msk 0x1UL 1127 #define SRSS_CLK_FLL_STATUS_UNLOCK_OCCURRED_Pos 1UL 1128 #define SRSS_CLK_FLL_STATUS_UNLOCK_OCCURRED_Msk 0x2UL 1129 #define SRSS_CLK_FLL_STATUS_CCO_READY_Pos 2UL 1130 #define SRSS_CLK_FLL_STATUS_CCO_READY_Msk 0x4UL 1131 /* SRSS.CLK_ECO_CONFIG2 */ 1132 #define SRSS_CLK_ECO_CONFIG2_WDTRIM_Pos 0UL 1133 #define SRSS_CLK_ECO_CONFIG2_WDTRIM_Msk 0x7UL 1134 #define SRSS_CLK_ECO_CONFIG2_ATRIM_Pos 4UL 1135 #define SRSS_CLK_ECO_CONFIG2_ATRIM_Msk 0xF0UL 1136 #define SRSS_CLK_ECO_CONFIG2_FTRIM_Pos 8UL 1137 #define SRSS_CLK_ECO_CONFIG2_FTRIM_Msk 0x300UL 1138 #define SRSS_CLK_ECO_CONFIG2_RTRIM_Pos 10UL 1139 #define SRSS_CLK_ECO_CONFIG2_RTRIM_Msk 0xC00UL 1140 #define SRSS_CLK_ECO_CONFIG2_GTRIM_Pos 12UL 1141 #define SRSS_CLK_ECO_CONFIG2_GTRIM_Msk 0x7000UL 1142 /* SRSS.CLK_ILO_CONFIG */ 1143 #define SRSS_CLK_ILO_CONFIG_ILO_BACKUP_Pos 0UL 1144 #define SRSS_CLK_ILO_CONFIG_ILO_BACKUP_Msk 0x1UL 1145 #define SRSS_CLK_ILO_CONFIG_ENABLE_Pos 31UL 1146 #define SRSS_CLK_ILO_CONFIG_ENABLE_Msk 0x80000000UL 1147 /* SRSS.CLK_TRIM_ILO_CTL */ 1148 #define SRSS_CLK_TRIM_ILO_CTL_ILO_FTRIM_Pos 0UL 1149 #define SRSS_CLK_TRIM_ILO_CTL_ILO_FTRIM_Msk 0x3FUL 1150 /* SRSS.CLK_TRIM_ILO0_CTL */ 1151 #define SRSS_CLK_TRIM_ILO0_CTL_ILO0_FTRIM_Pos 0UL 1152 #define SRSS_CLK_TRIM_ILO0_CTL_ILO0_FTRIM_Msk 0x3FUL 1153 #define SRSS_CLK_TRIM_ILO0_CTL_ILO0_MONTRIM_Pos 8UL 1154 #define SRSS_CLK_TRIM_ILO0_CTL_ILO0_MONTRIM_Msk 0xF00UL 1155 /* SRSS.CLK_MF_SELECT */ 1156 #define SRSS_CLK_MF_SELECT_MFCLK_SEL_Pos 0UL 1157 #define SRSS_CLK_MF_SELECT_MFCLK_SEL_Msk 0x7UL 1158 #define SRSS_CLK_MF_SELECT_MFCLK_DIV_Pos 8UL 1159 #define SRSS_CLK_MF_SELECT_MFCLK_DIV_Msk 0xFF00UL 1160 #define SRSS_CLK_MF_SELECT_ENABLE_Pos 31UL 1161 #define SRSS_CLK_MF_SELECT_ENABLE_Msk 0x80000000UL 1162 /* SRSS.CLK_MFO_CONFIG */ 1163 #define SRSS_CLK_MFO_CONFIG_DPSLP_ENABLE_Pos 30UL 1164 #define SRSS_CLK_MFO_CONFIG_DPSLP_ENABLE_Msk 0x40000000UL 1165 #define SRSS_CLK_MFO_CONFIG_ENABLE_Pos 31UL 1166 #define SRSS_CLK_MFO_CONFIG_ENABLE_Msk 0x80000000UL 1167 /* SRSS.CLK_IHO_CONFIG */ 1168 #define SRSS_CLK_IHO_CONFIG_ENABLE_Pos 31UL 1169 #define SRSS_CLK_IHO_CONFIG_ENABLE_Msk 0x80000000UL 1170 /* SRSS.CLK_ALTHF_CTL */ 1171 #define SRSS_CLK_ALTHF_CTL_ALTHF_ENABLED_Pos 0UL 1172 #define SRSS_CLK_ALTHF_CTL_ALTHF_ENABLED_Msk 0x1UL 1173 #define SRSS_CLK_ALTHF_CTL_ALTHF_ENABLE_Pos 31UL 1174 #define SRSS_CLK_ALTHF_CTL_ALTHF_ENABLE_Msk 0x80000000UL 1175 /* SRSS.CLK_PLL_CONFIG */ 1176 #define SRSS_CLK_PLL_CONFIG_FEEDBACK_DIV_Pos 0UL 1177 #define SRSS_CLK_PLL_CONFIG_FEEDBACK_DIV_Msk 0x7FUL 1178 #define SRSS_CLK_PLL_CONFIG_REFERENCE_DIV_Pos 8UL 1179 #define SRSS_CLK_PLL_CONFIG_REFERENCE_DIV_Msk 0x1F00UL 1180 #define SRSS_CLK_PLL_CONFIG_OUTPUT_DIV_Pos 16UL 1181 #define SRSS_CLK_PLL_CONFIG_OUTPUT_DIV_Msk 0x1F0000UL 1182 #define SRSS_CLK_PLL_CONFIG_LOCK_DELAY_Pos 25UL 1183 #define SRSS_CLK_PLL_CONFIG_LOCK_DELAY_Msk 0x6000000UL 1184 #define SRSS_CLK_PLL_CONFIG_PLL_LF_MODE_Pos 27UL 1185 #define SRSS_CLK_PLL_CONFIG_PLL_LF_MODE_Msk 0x8000000UL 1186 #define SRSS_CLK_PLL_CONFIG_BYPASS_SEL_Pos 28UL 1187 #define SRSS_CLK_PLL_CONFIG_BYPASS_SEL_Msk 0x30000000UL 1188 #define SRSS_CLK_PLL_CONFIG_ENABLE_Pos 31UL 1189 #define SRSS_CLK_PLL_CONFIG_ENABLE_Msk 0x80000000UL 1190 /* SRSS.CLK_PLL_STATUS */ 1191 #define SRSS_CLK_PLL_STATUS_LOCKED_Pos 0UL 1192 #define SRSS_CLK_PLL_STATUS_LOCKED_Msk 0x1UL 1193 #define SRSS_CLK_PLL_STATUS_UNLOCK_OCCURRED_Pos 1UL 1194 #define SRSS_CLK_PLL_STATUS_UNLOCK_OCCURRED_Msk 0x2UL 1195 /* SRSS.CSV_REF_SEL */ 1196 #define SRSS_CSV_REF_SEL_REF_MUX_Pos 0UL 1197 #define SRSS_CSV_REF_SEL_REF_MUX_Msk 0x7UL 1198 /* SRSS.RES_CAUSE */ 1199 #define SRSS_RES_CAUSE_RESET_WDT_Pos 0UL 1200 #define SRSS_RES_CAUSE_RESET_WDT_Msk 0x1UL 1201 #define SRSS_RES_CAUSE_RESET_ACT_FAULT_Pos 1UL 1202 #define SRSS_RES_CAUSE_RESET_ACT_FAULT_Msk 0x2UL 1203 #define SRSS_RES_CAUSE_RESET_DPSLP_FAULT_Pos 2UL 1204 #define SRSS_RES_CAUSE_RESET_DPSLP_FAULT_Msk 0x4UL 1205 #define SRSS_RES_CAUSE_RESET_TC_DBGRESET_Pos 3UL 1206 #define SRSS_RES_CAUSE_RESET_TC_DBGRESET_Msk 0x8UL 1207 #define SRSS_RES_CAUSE_RESET_SOFT_Pos 4UL 1208 #define SRSS_RES_CAUSE_RESET_SOFT_Msk 0x10UL 1209 #define SRSS_RES_CAUSE_RESET_MCWDT0_Pos 5UL 1210 #define SRSS_RES_CAUSE_RESET_MCWDT0_Msk 0x20UL 1211 #define SRSS_RES_CAUSE_RESET_MCWDT1_Pos 6UL 1212 #define SRSS_RES_CAUSE_RESET_MCWDT1_Msk 0x40UL 1213 #define SRSS_RES_CAUSE_RESET_MCWDT2_Pos 7UL 1214 #define SRSS_RES_CAUSE_RESET_MCWDT2_Msk 0x80UL 1215 #define SRSS_RES_CAUSE_RESET_MCWDT3_Pos 8UL 1216 #define SRSS_RES_CAUSE_RESET_MCWDT3_Msk 0x100UL 1217 /* SRSS.RES_CAUSE2 */ 1218 #define SRSS_RES_CAUSE2_RESET_CSV_HF_Pos 0UL 1219 #define SRSS_RES_CAUSE2_RESET_CSV_HF_Msk 0xFFFFUL 1220 #define SRSS_RES_CAUSE2_RESET_CSV_REF_Pos 16UL 1221 #define SRSS_RES_CAUSE2_RESET_CSV_REF_Msk 0x10000UL 1222 /* SRSS.RES_CAUSE_EXTEND */ 1223 #define SRSS_RES_CAUSE_EXTEND_RESET_XRES_Pos 16UL 1224 #define SRSS_RES_CAUSE_EXTEND_RESET_XRES_Msk 0x10000UL 1225 #define SRSS_RES_CAUSE_EXTEND_RESET_BODVDDD_Pos 17UL 1226 #define SRSS_RES_CAUSE_EXTEND_RESET_BODVDDD_Msk 0x20000UL 1227 #define SRSS_RES_CAUSE_EXTEND_RESET_BODVDDA_Pos 18UL 1228 #define SRSS_RES_CAUSE_EXTEND_RESET_BODVDDA_Msk 0x40000UL 1229 #define SRSS_RES_CAUSE_EXTEND_RESET_BODVCCD_Pos 19UL 1230 #define SRSS_RES_CAUSE_EXTEND_RESET_BODVCCD_Msk 0x80000UL 1231 #define SRSS_RES_CAUSE_EXTEND_RESET_OVDVDDD_Pos 20UL 1232 #define SRSS_RES_CAUSE_EXTEND_RESET_OVDVDDD_Msk 0x100000UL 1233 #define SRSS_RES_CAUSE_EXTEND_RESET_OVDVDDA_Pos 21UL 1234 #define SRSS_RES_CAUSE_EXTEND_RESET_OVDVDDA_Msk 0x200000UL 1235 #define SRSS_RES_CAUSE_EXTEND_RESET_OVDVCCD_Pos 22UL 1236 #define SRSS_RES_CAUSE_EXTEND_RESET_OVDVCCD_Msk 0x400000UL 1237 #define SRSS_RES_CAUSE_EXTEND_RESET_OCD_ACT_LINREG_Pos 23UL 1238 #define SRSS_RES_CAUSE_EXTEND_RESET_OCD_ACT_LINREG_Msk 0x800000UL 1239 #define SRSS_RES_CAUSE_EXTEND_RESET_OCD_DPSLP_LINREG_Pos 24UL 1240 #define SRSS_RES_CAUSE_EXTEND_RESET_OCD_DPSLP_LINREG_Msk 0x1000000UL 1241 #define SRSS_RES_CAUSE_EXTEND_RESET_OCD_REGHC_Pos 25UL 1242 #define SRSS_RES_CAUSE_EXTEND_RESET_OCD_REGHC_Msk 0x2000000UL 1243 #define SRSS_RES_CAUSE_EXTEND_RESET_PMIC_Pos 26UL 1244 #define SRSS_RES_CAUSE_EXTEND_RESET_PMIC_Msk 0x4000000UL 1245 #define SRSS_RES_CAUSE_EXTEND_RESET_PXRES_Pos 28UL 1246 #define SRSS_RES_CAUSE_EXTEND_RESET_PXRES_Msk 0x10000000UL 1247 #define SRSS_RES_CAUSE_EXTEND_RESET_STRUCT_XRES_Pos 29UL 1248 #define SRSS_RES_CAUSE_EXTEND_RESET_STRUCT_XRES_Msk 0x20000000UL 1249 #define SRSS_RES_CAUSE_EXTEND_RESET_PORVDDD_Pos 30UL 1250 #define SRSS_RES_CAUSE_EXTEND_RESET_PORVDDD_Msk 0x40000000UL 1251 /* SRSS.RES_PXRES_CTL */ 1252 #define SRSS_RES_PXRES_CTL_PXRES_TRIGGER_Pos 0UL 1253 #define SRSS_RES_PXRES_CTL_PXRES_TRIGGER_Msk 0x1UL 1254 /* SRSS.PWR_CBUCK_CTL */ 1255 #define SRSS_PWR_CBUCK_CTL_CBUCK_VSEL_Pos 0UL 1256 #define SRSS_PWR_CBUCK_CTL_CBUCK_VSEL_Msk 0x1FUL 1257 #define SRSS_PWR_CBUCK_CTL_CBUCK_MODE_Pos 8UL 1258 #define SRSS_PWR_CBUCK_CTL_CBUCK_MODE_Msk 0x1F00UL 1259 /* SRSS.PWR_CBUCK_CTL2 */ 1260 #define SRSS_PWR_CBUCK_CTL2_CBUCK_OVERRIDE_Pos 28UL 1261 #define SRSS_PWR_CBUCK_CTL2_CBUCK_OVERRIDE_Msk 0x10000000UL 1262 #define SRSS_PWR_CBUCK_CTL2_CBUCK_PAUSE_Pos 29UL 1263 #define SRSS_PWR_CBUCK_CTL2_CBUCK_PAUSE_Msk 0x20000000UL 1264 #define SRSS_PWR_CBUCK_CTL2_CBUCK_COPY_SETTINGS_Pos 30UL 1265 #define SRSS_PWR_CBUCK_CTL2_CBUCK_COPY_SETTINGS_Msk 0x40000000UL 1266 #define SRSS_PWR_CBUCK_CTL2_CBUCK_USE_SETTINGS_Pos 31UL 1267 #define SRSS_PWR_CBUCK_CTL2_CBUCK_USE_SETTINGS_Msk 0x80000000UL 1268 /* SRSS.PWR_CBUCK_CTL3 */ 1269 #define SRSS_PWR_CBUCK_CTL3_CBUCK_INRUSH_SEL_Pos 31UL 1270 #define SRSS_PWR_CBUCK_CTL3_CBUCK_INRUSH_SEL_Msk 0x80000000UL 1271 /* SRSS.PWR_CBUCK_STATUS */ 1272 #define SRSS_PWR_CBUCK_STATUS_PMU_DONE_Pos 31UL 1273 #define SRSS_PWR_CBUCK_STATUS_PMU_DONE_Msk 0x80000000UL 1274 /* SRSS.PWR_SDR0_CTL */ 1275 #define SRSS_PWR_SDR0_CTL_SDR0_CBUCK_VSEL_Pos 0UL 1276 #define SRSS_PWR_SDR0_CTL_SDR0_CBUCK_VSEL_Msk 0x1FUL 1277 #define SRSS_PWR_SDR0_CTL_SDR0_CBUCK_MODE_Pos 5UL 1278 #define SRSS_PWR_SDR0_CTL_SDR0_CBUCK_MODE_Msk 0x3E0UL 1279 #define SRSS_PWR_SDR0_CTL_SDR0_CBUCK_DPSLP_VSEL_Pos 10UL 1280 #define SRSS_PWR_SDR0_CTL_SDR0_CBUCK_DPSLP_VSEL_Msk 0x7C00UL 1281 #define SRSS_PWR_SDR0_CTL_SDR0_CBUCK_DPSLP_MODE_Pos 15UL 1282 #define SRSS_PWR_SDR0_CTL_SDR0_CBUCK_DPSLP_MODE_Msk 0xF8000UL 1283 #define SRSS_PWR_SDR0_CTL_SDR0_VSEL_Pos 20UL 1284 #define SRSS_PWR_SDR0_CTL_SDR0_VSEL_Msk 0xF00000UL 1285 #define SRSS_PWR_SDR0_CTL_SDR0_DPSLP_VSEL_Pos 26UL 1286 #define SRSS_PWR_SDR0_CTL_SDR0_DPSLP_VSEL_Msk 0x3C000000UL 1287 #define SRSS_PWR_SDR0_CTL_SDR0_ALLOW_BYPASS_Pos 31UL 1288 #define SRSS_PWR_SDR0_CTL_SDR0_ALLOW_BYPASS_Msk 0x80000000UL 1289 /* SRSS.PWR_SDR1_CTL */ 1290 #define SRSS_PWR_SDR1_CTL_SDR1_CBUCK_VSEL_Pos 0UL 1291 #define SRSS_PWR_SDR1_CTL_SDR1_CBUCK_VSEL_Msk 0x1FUL 1292 #define SRSS_PWR_SDR1_CTL_SDR1_CBUCK_MODE_Pos 8UL 1293 #define SRSS_PWR_SDR1_CTL_SDR1_CBUCK_MODE_Msk 0x1F00UL 1294 #define SRSS_PWR_SDR1_CTL_SDR1_VSEL_Pos 16UL 1295 #define SRSS_PWR_SDR1_CTL_SDR1_VSEL_Msk 0xF0000UL 1296 #define SRSS_PWR_SDR1_CTL_SDR1_HW_SEL_Pos 30UL 1297 #define SRSS_PWR_SDR1_CTL_SDR1_HW_SEL_Msk 0x40000000UL 1298 #define SRSS_PWR_SDR1_CTL_SDR1_ENABLE_Pos 31UL 1299 #define SRSS_PWR_SDR1_CTL_SDR1_ENABLE_Msk 0x80000000UL 1300 /* SRSS.PWR_HVLDO0_CTL */ 1301 #define SRSS_PWR_HVLDO0_CTL_HVLDO0_VSEL_Pos 0UL 1302 #define SRSS_PWR_HVLDO0_CTL_HVLDO0_VSEL_Msk 0xFUL 1303 #define SRSS_PWR_HVLDO0_CTL_HVLDO0_HW_SEL_Pos 30UL 1304 #define SRSS_PWR_HVLDO0_CTL_HVLDO0_HW_SEL_Msk 0x40000000UL 1305 #define SRSS_PWR_HVLDO0_CTL_HVLDO0_ENABLE_Pos 31UL 1306 #define SRSS_PWR_HVLDO0_CTL_HVLDO0_ENABLE_Msk 0x80000000UL 1307 /* SRSS.TST_XRES_SECURE */ 1308 #define SRSS_TST_XRES_SECURE_DATA8_Pos 0UL 1309 #define SRSS_TST_XRES_SECURE_DATA8_Msk 0xFFUL 1310 #define SRSS_TST_XRES_SECURE_FW_WR_Pos 8UL 1311 #define SRSS_TST_XRES_SECURE_FW_WR_Msk 0xF00UL 1312 #define SRSS_TST_XRES_SECURE_SECURE_WR_Pos 16UL 1313 #define SRSS_TST_XRES_SECURE_SECURE_WR_Msk 0xF0000UL 1314 #define SRSS_TST_XRES_SECURE_FW_KEY_OK_Pos 29UL 1315 #define SRSS_TST_XRES_SECURE_FW_KEY_OK_Msk 0x20000000UL 1316 #define SRSS_TST_XRES_SECURE_SECURE_KEY_OK_Pos 30UL 1317 #define SRSS_TST_XRES_SECURE_SECURE_KEY_OK_Msk 0x40000000UL 1318 #define SRSS_TST_XRES_SECURE_SECURE_DISABLE_Pos 31UL 1319 #define SRSS_TST_XRES_SECURE_SECURE_DISABLE_Msk 0x80000000UL 1320 /* SRSS.PWR_TRIM_CBUCK_CTL */ 1321 #define SRSS_PWR_TRIM_CBUCK_CTL_CBUCK_DPSLP_VSEL_Pos 0UL 1322 #define SRSS_PWR_TRIM_CBUCK_CTL_CBUCK_DPSLP_VSEL_Msk 0x1FUL 1323 #define SRSS_PWR_TRIM_CBUCK_CTL_CBUCK_DPSLP_MODE_Pos 8UL 1324 #define SRSS_PWR_TRIM_CBUCK_CTL_CBUCK_DPSLP_MODE_Msk 0x1F00UL 1325 /* SRSS.PWR_TRIM_PWRSYS_CTL */ 1326 #define SRSS_PWR_TRIM_PWRSYS_CTL_ACT_REG_TRIM_Pos 0UL 1327 #define SRSS_PWR_TRIM_PWRSYS_CTL_ACT_REG_TRIM_Msk 0x1FUL 1328 #define SRSS_PWR_TRIM_PWRSYS_CTL_ACT_REG_BOOST_Pos 30UL 1329 #define SRSS_PWR_TRIM_PWRSYS_CTL_ACT_REG_BOOST_Msk 0xC0000000UL 1330 /* SRSS.PWR_TRIM_PWRSYS_CTL2 */ 1331 #define SRSS_PWR_TRIM_PWRSYS_CTL2_DPSLP_REG_TRIM_Pos 8UL 1332 #define SRSS_PWR_TRIM_PWRSYS_CTL2_DPSLP_REG_TRIM_Msk 0x700UL 1333 #define SRSS_PWR_TRIM_PWRSYS_CTL2_RET_REG_TRIM_Pos 12UL 1334 #define SRSS_PWR_TRIM_PWRSYS_CTL2_RET_REG_TRIM_Msk 0x7000UL 1335 #define SRSS_PWR_TRIM_PWRSYS_CTL2_NWELL_REG_TRIM_Pos 16UL 1336 #define SRSS_PWR_TRIM_PWRSYS_CTL2_NWELL_REG_TRIM_Msk 0x70000UL 1337 #define SRSS_PWR_TRIM_PWRSYS_CTL2_DPSLP_REG_ACT_TRIM_Pos 20UL 1338 #define SRSS_PWR_TRIM_PWRSYS_CTL2_DPSLP_REG_ACT_TRIM_Msk 0x700000UL 1339 #define SRSS_PWR_TRIM_PWRSYS_CTL2_RET_REG_ACT_TRIM_Pos 24UL 1340 #define SRSS_PWR_TRIM_PWRSYS_CTL2_RET_REG_ACT_TRIM_Msk 0x7000000UL 1341 /* SRSS.CLK_TRIM_ECO_CTL */ 1342 #define SRSS_CLK_TRIM_ECO_CTL_ITRIM_Pos 16UL 1343 #define SRSS_CLK_TRIM_ECO_CTL_ITRIM_Msk 0x3F0000UL 1344 /* SRSS.CLK_TRIM_ILO1_CTL */ 1345 #define SRSS_CLK_TRIM_ILO1_CTL_ILO1_FTRIM_Pos 0UL 1346 #define SRSS_CLK_TRIM_ILO1_CTL_ILO1_FTRIM_Msk 0x3FUL 1347 #define SRSS_CLK_TRIM_ILO1_CTL_ILO1_MONTRIM_Pos 8UL 1348 #define SRSS_CLK_TRIM_ILO1_CTL_ILO1_MONTRIM_Msk 0xF00UL 1349 /* SRSS.WDT_CTL */ 1350 #define SRSS_WDT_CTL_WDT_EN_Pos 0UL 1351 #define SRSS_WDT_CTL_WDT_EN_Msk 0x1UL 1352 #define SRSS_WDT_CTL_WDT_CLK_SEL_Pos 4UL 1353 #define SRSS_WDT_CTL_WDT_CLK_SEL_Msk 0x30UL 1354 #define SRSS_WDT_CTL_WDT_LOCK_Pos 30UL 1355 #define SRSS_WDT_CTL_WDT_LOCK_Msk 0xC0000000UL 1356 /* SRSS.WDT_CNT */ 1357 #define SRSS_WDT_CNT_COUNTER_Pos 0UL 1358 #define SRSS_WDT_CNT_COUNTER_Msk 0xFFFFFFFFUL 1359 /* SRSS.WDT_MATCH */ 1360 #define SRSS_WDT_MATCH_MATCH_Pos 0UL 1361 #define SRSS_WDT_MATCH_MATCH_Msk 0xFFFFFFFFUL 1362 /* SRSS.WDT_MATCH2 */ 1363 #define SRSS_WDT_MATCH2_IGNORE_BITS_ABOVE_Pos 0UL 1364 #define SRSS_WDT_MATCH2_IGNORE_BITS_ABOVE_Msk 0x1FUL 1365 1366 1367 #endif /* _CYIP_SRSS_H_ */ 1368 1369 1370 /* [] END OF FILE */ 1371
