1 // Copyright 2021 Espressif Systems (Shanghai) PTE LTD 2 // 3 // Licensed under the Apache License, Version 2.0 (the "License"); 4 // you may not use this file except in compliance with the License. 5 // You may obtain a copy of the License at 6 // 7 // http://www.apache.org/licenses/LICENSE-2.0 8 // 9 // Unless required by applicable law or agreed to in writing, software 10 // distributed under the License is distributed on an "AS IS" BASIS, 11 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 // See the License for the specific language governing permissions and 13 // limitations under the License. 14 15 #pragma once 16 17 //+-----------------------------------------------Terminology---------------------------------------------+ 18 //| | 19 //| CPU Reset: Reset CPU core only, once reset done, CPU will execute from reset vector | 20 //| | 21 //| Core Reset: Reset the whole digital system except RTC sub-system | 22 //| | 23 //| System Reset: Reset the whole digital system, including RTC sub-system | 24 //| | 25 //| Chip Reset: Reset the whole chip, including the analog part | 26 //| | 27 //+-------------------------------------------------------------------------------------------------------+ 28 29 #ifdef __cplusplus 30 extern "C" { 31 #endif 32 33 /** 34 * @brief Naming conventions: RESET_REASON_{reset level}_{reset reason} 35 * @note refer to TRM: <Reset and Clock> chapter 36 */ 37 typedef enum { 38 RESET_REASON_CHIP_POWER_ON = 0x01, // Power on reset 39 RESET_REASON_CHIP_BROWN_OUT = 0x01, // VDD voltage is not stable and resets the chip 40 RESET_REASON_CHIP_SUPER_WDT = 0x01, // Super watch dog resets the chip 41 RESET_REASON_CORE_SW = 0x03, // Software resets the digital core by RTC_CNTL_SW_SYS_RST 42 RESET_REASON_CORE_DEEP_SLEEP = 0x05, // Deep sleep reset the digital core 43 RESET_REASON_CORE_MWDT0 = 0x07, // Main watch dog 0 resets digital core 44 RESET_REASON_CORE_MWDT1 = 0x08, // Main watch dog 1 resets digital core 45 RESET_REASON_CORE_RTC_WDT = 0x09, // RTC watch dog resets digital core 46 RESET_REASON_CPU0_MWDT0 = 0x0B, // Main watch dog 0 resets CPU 0 47 RESET_REASON_CPU1_MWDT0 = 0x0B, // Main watch dog 0 resets CPU 1 48 RESET_REASON_CPU0_SW = 0x0C, // Software resets CPU 0 by RTC_CNTL_SW_PROCPU_RST 49 RESET_REASON_CPU1_SW = 0x0C, // Software resets CPU 1 by RTC_CNTL_SW_APPCPU_RST 50 RESET_REASON_CPU0_RTC_WDT = 0x0D, // RTC watch dog resets CPU 0 51 RESET_REASON_CPU1_RTC_WDT = 0x0D, // RTC watch dog resets CPU 1 52 RESET_REASON_SYS_BROWN_OUT = 0x0F, // VDD voltage is not stable and resets the digital core 53 RESET_REASON_SYS_RTC_WDT = 0x10, // RTC watch dog resets digital core and rtc module 54 RESET_REASON_CPU0_MWDT1 = 0x11, // Main watch dog 1 resets CPU 0 55 RESET_REASON_CPU1_MWDT1 = 0x11, // Main watch dog 1 resets CPU 1 56 RESET_REASON_SYS_SUPER_WDT = 0x12, // Super watch dog resets the digital core and rtc module 57 RESET_REASON_SYS_CLK_GLITCH = 0x13, // Glitch on clock resets the digital core and rtc module 58 RESET_REASON_CORE_EFUSE_CRC = 0x14, // eFuse CRC error resets the digital core 59 RESET_REASON_CORE_USB_UART = 0x15, // USB UART resets the digital core 60 RESET_REASON_CORE_USB_JTAG = 0x16, // USB JTAG resets the digital core 61 RESET_REASON_CORE_PWR_GLITCH = 0x17, // Glitch on power resets the digital core 62 } soc_reset_reason_t; 63 64 #ifdef __cplusplus 65 } 66 #endif 67
