1 /**************************************************************************//** 2 * @file pdma_reg.h 3 * @version V1.00 4 * @brief PDMA register definition header file 5 * 6 * @copyright SPDX-License-Identifier: Apache-2.0 7 * @copyright Copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. 8 *****************************************************************************/ 9 #ifndef __PDMA_REG_H__ 10 #define __PDMA_REG_H__ 11 12 /** @addtogroup REGISTER Control Register 13 14 @{ 15 16 */ 17 18 /*---------------------- Peripheral Direct Memory Access Controller -------------------------*/ 19 /** 20 @addtogroup PDMA Peripheral Direct Memory Access Controller(PDMA) 21 Memory Mapped Structure for PDMA Controller 22 @{ 23 */ 24 25 26 27 typedef struct 28 { 29 /** 30 * @var DSCT_T::CTL 31 * Offset: 0x00/0x10/0x20/0x30/0x40/0x50/0x60/0x70 Descriptor Table Control Register of PDMA Channel 0~7 32 * --------------------------------------------------------------------------------------------------- 33 * |Bits |Field |Descriptions 34 * | :----: | :----: | :---- | 35 * |[1:0] |OPMODE |PDMA Operation Mode Selection 36 * | | |00 = Idle state: Channel is stopped or this table is complete, when PDMA finish channel table task, OPMODE will be cleared to idle state automatically. 37 * | | |01 = Basic mode: The descriptor table only has one task 38 * | | |When this task is finished, the TDIF(PDMA_INTSTS[1]) will be asserted. 39 * | | |10 = Scatter-Gather mode: When operating in this mode, user must give the first descriptor table address in PDMA_DSCT_FIRST register; PDMA controller will ignore this task, then load the next task to execute. 40 * | | |11 = Reserved. 41 * | | |Note: Before filling transfer task in the Descriptor Table, user must check if the descriptor table is complete. 42 * |[2] |TXTYPE |Transfer Type 43 * | | |0 = Burst transfer type. 44 * | | |1 = Single transfer type. 45 * |[6:4] |BURSIZE |Burst Size 46 * | | |This field is used for peripheral to determine the burst size or used for determine the re-arbitration size. 47 * | | |000 = 128 Transfers. 48 * | | |001 = 64 Transfers. 49 * | | |010 = 32 Transfers. 50 * | | |011 = 16 Transfers. 51 * | | |100 = 8 Transfers. 52 * | | |101 = 4 Transfers. 53 * | | |110 = 2 Transfers. 54 * | | |111 = 1 Transfers. 55 * | | |Note: This field is only useful in burst transfer type. 56 * |[7] |TBINTDIS |Table Interrupt Disable Bit 57 * | | |This field can be used to decide whether to enable table interrupt or not 58 * | | |If the TBINTDIS bit is enabled when PDMA controller finishes transfer task, it will not generates transfer done interrupt. 59 * | | |0 = Table interrupt Enabled. 60 * | | |1 = Table interrupt Disabled. 61 * | | |Note: If this bit set to 1, the TEMPTYF will not be set. 62 * |[9:8] |SAINC |Source Address Increment 63 * | | |This field is used to set the source address increment size. 64 * | | |11 = No increment (fixed address). 65 * | | |Others = Increment and size is depended on TXWIDTH selection. 66 * |[11:10] |DAINC |Destination Address Increment 67 * | | |This field is used to set the destination address increment size. 68 * | | |11 = No increment (fixed address). 69 * | | |Others = Increment and size is depended on TXWIDTH selection. 70 * |[13:12] |TXWIDTH |Transfer Width Selection 71 * | | |This field is used for transfer width. 72 * | | |00 = One byte (8 bit) is transferred for every operation. 73 * | | |01 = One half-word (16 bit) is transferred for every operation. 74 * | | |10 = One word (32-bit) is transferred for every operation. 75 * | | |11 = Reserved. 76 * | | |Note: The PDMA transfer source address (PDMA_DSCT_SA) and PDMA transfer destination address (PDMA_DSCT_DA) should be alignment under the TXWIDTH selection 77 * | | |For example, if source address is 0x2000_0202, but TXWIDTH is word transfer, the source address is not word alignment 78 * | | |The source address is aligned when TXWIDTH is byte or half-word transfer. 79 * |[14] |TXACK |Transfer Acknowledge Selection 80 * | | |0 = transfer ack when transfer done. 81 * | | |1 = transfer ack when PDMA get transfer data. 82 * |[15] |STRIDEEN |Stride Mode Enable Bit 83 * | | |0 = Stride transfer mode Disabled. 84 * | | |1 = Stride transfer mode Enabled. 85 * |[31:16] |TXCNT |Transfer Count 86 * | | |The TXCNT represents the required number of PDMA transfer, the real transfer count is (TXCNT + 1); The maximum transfer count is 65536, every transfer may be byte, half-word or word that is dependent on TXWIDTH field. 87 * | | |Note: When PDMA finish each transfer data, this field will be decrease immediately. 88 * @var DSCT_T::SA 89 * Offset: 0x04/0x14/0x24/0x34/0x44/0x54/0x64/0x74 Source Address Register of PDMA Channel 0~7 90 * --------------------------------------------------------------------------------------------------- 91 * |Bits |Field |Descriptions 92 * | :----: | :----: | :---- | 93 * |[31:0] |SA |PDMA Transfer Source Address Register 94 * | | |This field indicates a 32-bit source address of PDMA controller. 95 * | | |Note: The PDMA transfer source address should be aligned with the TXWIDTH(PDMA_DSCTn_CTL[13:12], n=0,1..7) selection. 96 * @var DSCT_T::DA 97 * Offset: 0x08/0x18/0x28/0x38/0x48/0x58/0x68/0x78 Destination Address Register of PDMA Channel 0~7 98 * --------------------------------------------------------------------------------------------------- 99 * |Bits |Field |Descriptions 100 * | :----: | :----: | :---- | 101 * |[31:0] |DA |PDMA Transfer Destination Address Register 102 * | | |This field indicates a 32-bit destination address of PDMA controller. 103 * | | |Note: The PDMA transfer destination address should be aligned with the TXWIDTH(PDMA_DSCTn_CTL[13:12], n=0,1..7) selection. 104 * @var DSCT_T::NEXT 105 * Offset: 0x0C/0x1C/0x2C/0x3C/0x4C/0x5C/0x6C/0x7C First Scatter-Gather Descriptor Table Offset of PDMA Channel 0~7 106 * --------------------------------------------------------------------------------------------------- 107 * |Bits |Field |Descriptions 108 * | :----: | :----: | :---- | 109 * |[15:0] |FIRST |PDMA First Descriptor Table Offset 110 * | | |This field indicates the offset of the first descriptor table address in system memory. 111 * | | |Write Operation: 112 * | | |If the system memory based address is 0x2000_0000 (PDMA_SCATBA), and the first descriptor table is start from 0x2000_0100, then this field must fill in 0x0100. 113 * | | |Read Operation: 114 * | | |When operating in scatter-gather mode, the last two bits FIRST[1:0] will become reserved. 115 * | | |Note1: The first descriptor table address must be word boundary. 116 * | | |Note2: Before filled transfer task in the descriptor table, user must check if the descriptor table is complete. 117 * |[31:16] |NEXT |PDMA Next Descriptor Table Offset 118 * | | |This field indicates the offset of next descriptor table address in system memory. 119 * | | |Note: write operation is useless in this field. 120 */ 121 122 __IO uint32_t CTL; /*!< [0x00/0x10/0x20/0x30/0x40/0x50/0x60/0x70] Descriptor Table Control Register of PDMA Channel 0~7 */ 123 __IO uint32_t SA; /*!< [0x04/0x14/0x24/0x34/0x44/0x54/0x64/0x74] Source Address Register of PDMA Channel 0~7 */ 124 __IO uint32_t DA; /*!< [0x08/0x18/0x28/0x38/0x48/0x58/0x68/0x78] Destination Address Register of PDMA Channel 0~7 */ 125 __IO uint32_t NEXT; /*!< [0x0C/0x1C/0x2C/0x3C/0x4C/0x5C/0x6C/0x7C]Next Scatter-Gather Descriptor Table Offset */ 126 127 } DSCT_T; 128 129 typedef struct 130 { 131 /** 132 * @var STRIDE_T::STCR 133 * Offset: 0x500/0x508/0x510/0x518/0x520/0x528 Stride Transfer Count Register of PDMA Channel 0~5 134 * --------------------------------------------------------------------------------------------------- 135 * |Bits |Field |Descriptions 136 * | :----: | :----: | :---- | 137 * |[15:0] |STC |PDMA Stride Transfer Count 138 * | | |The 16-bit register defines the stride transfer count of each row. 139 * @var STRIDE_T::ASOCR 140 * Offset: 0x504/0x50C/0x514/0x51C/0x524/0x52C Address Stride Offset Register of PDMA Channel 0~5 141 * --------------------------------------------------------------------------------------------------- 142 * |Bits |Field |Descriptions 143 * | :----: | :----: | :---- | 144 * |[15:0] |SASOL |VDMA Source Address Stride Offset Length 145 * | | |The 16-bit register defines the source address stride transfer offset count of each row. 146 * |[31:16] |DASOL |VDMA Destination Address Stride Offset Length 147 * | | |The 16-bit register defines the destination address stride transfer offset count of each row. 148 */ 149 __IO uint32_t STCR; /*!< [0x0500/0x508/0x510/0x518/0x520/0x528] Stride Transfer Count Register of PDMA Channel 0~7 */ 150 __IO uint32_t ASOCR; /*!< [0x0504/0x50C/0x514/0x51C/0x524/0x52C] Address Stride Offset Register of PDMA Channel 0 */ 151 } STRIDE_T; 152 153 typedef struct 154 { 155 /** 156 * @var REPEAT_T::AICTL 157 * Offset: 0x600 Address Interval Control Register of PDMA Channel n 158 * --------------------------------------------------------------------------------------------------- 159 * |Bits |Field |Descriptions 160 * | :----: | :----: | :---- | 161 * |[15:0] |SAICNT |PDMA Source Address Interval Count 162 * | | |The 16-bit register defines the source address interval count of each row. 163 * |[31:16] |DAICNT |PDMA Destination Address Interval Count 164 * | | |The 16-bit register defines the destination address interval count of each row. 165 * @var REPEAT_T::RCNT 166 * Offset: 0x604 Repeat Count Register of PDMA Channe n 167 * --------------------------------------------------------------------------------------------------- 168 * |Bits |Field |Descriptions 169 * | :----: | :----: | :---- | 170 * |[15:0] |RCNT |PDMA Repeat Count 171 * | | |The 16-bit register defines the repeat times of block transfer. 172 */ 173 __IO uint32_t AICTL; /*!< [0x0600] Address Interval Control Register of PDMA Channel 0 */ 174 __IO uint32_t RCNT; /*!< [0x0604] Repeat Count Register of PDMA Channel 0 */ 175 } REPEAT_T; 176 177 typedef struct 178 { 179 180 181 /** 182 * @var PDMA_T::CURSCAT 183 * Offset: 0x80/0x84/0x88/0x8C/0x90/0x94/0x98/0x9C Current Scatter-Gather Descriptor Table Address of PDMA Channel 0~7 184 * --------------------------------------------------------------------------------------------------- 185 * |Bits |Field |Descriptions 186 * | :----: | :----: | :---- | 187 * |[31:0] |CURADDR |PDMA Current Description Address Register (Read Only) 188 * | | |This field indicates a 32-bit current external description address of PDMA controller. 189 * | | |Note: This field is read only and only used for Scatter-Gather mode to indicate the current external description address. 190 * @var PDMA_T::CHCTL 191 * Offset: 0x400 PDMA Channel Control Register 192 * --------------------------------------------------------------------------------------------------- 193 * |Bits |Field |Descriptions 194 * | :----: | :----: | :---- | 195 * |[15:0] |CHENn |PDMA Channel Enable Bit 196 * | | |Set this bit to 1 to enable PDMAn operation. Channel cannot be active if it is not set as enabled. 197 * | | |0 = PDMA channel [n] Disabled. 198 * | | |1 = PDMA channel [n] Enabled. 199 * | | |Note: Set corresponding bit of PDMA_PAUSE or PDMA_CHRST register will also clear this bit. 200 * @var PDMA_T::PAUSE 201 * Offset: 0x404 PDMA Transfer Pause Control Register 202 * --------------------------------------------------------------------------------------------------- 203 * |Bits |Field |Descriptions 204 * | :----: | :----: | :---- | 205 * |[15:0] |PAUSEn |PDMA Transfer Pause Control Register (Write Only) 206 * | | |User can set PAUSEn bit field to pause the PDMA transfer 207 * | | |When user sets PAUSEn bit, the PDMA controller will pause the on-going transfer, then clear the channel enable bit CHEN(PDMA_CHCTL [n], n=0,1..7) and clear request active flag 208 * | | |If re-enable the paused channel again, the remaining transfers will be processed. 209 * | | |0 = No effect. 210 * | | |1 = Pause PDMA channel n transfer. 211 * @var PDMA_T::SWREQ 212 * Offset: 0x408 PDMA Software Request Register 213 * --------------------------------------------------------------------------------------------------- 214 * |Bits |Field |Descriptions 215 * | :----: | :----: | :---- | 216 * |[15:0] |SWREQn |PDMA Software Request Register (Write Only) 217 * | | |Set this bit to 1 to generate a software request to PDMA [n]. 218 * | | |0 = No effect. 219 * | | |1 = Generate a software request. 220 * | | |Note1: User can read PDMA_TRGSTS register to know which channel is on active 221 * | | |Active flag may be triggered by software request or peripheral request. 222 * | | |Note2: If user does not enable corresponding PDMA channel, the software request will be ignored. 223 * @var PDMA_T::TRGSTS 224 * Offset: 0x40C PDMA Channel Request Status Register 225 * --------------------------------------------------------------------------------------------------- 226 * |Bits |Field |Descriptions 227 * | :----: | :----: | :---- | 228 * |[15:0] |REQSTSn |PDMA Channel Request Status (Read Only) 229 * | | |This flag indicates whether channel[n] have a request or not, no matter request from software or peripheral 230 * | | |When PDMA controller finishes channel transfer, this bit will be cleared automatically. 231 * | | |0 = PDMA Channel n has no request. 232 * | | |1 = PDMA Channel n has a request. 233 * | | |Note: If user pauses or resets each PDMA transfer by setting PDMA_PAUSE or PDMA_CHRST register respectively, this bit will be cleared automatically after finishing current transfer. 234 * @var PDMA_T::PRISET 235 * Offset: 0x410 PDMA Fixed Priority Setting Register 236 * --------------------------------------------------------------------------------------------------- 237 * |Bits |Field |Descriptions 238 * | :----: | :----: | :---- | 239 * |[15:0] |FPRISETn |PDMA Fixed Priority Setting Register 240 * | | |Set this bit to 1 to enable fixed priority level. 241 * | | |Write Operation: 242 * | | |0 = No effect. 243 * | | |1 = Set PDMA channel [n] to fixed priority channel. 244 * | | |Read Operation: 245 * | | |0 = Corresponding PDMA channel is round-robin priority. 246 * | | |1 = Corresponding PDMA channel is fixed priority. 247 * | | |Note: This field only set to fixed priority, clear fixed priority use PDMA_PRICLR register. 248 * @var PDMA_T::PRICLR 249 * Offset: 0x414 PDMA Fixed Priority Clear Register 250 * --------------------------------------------------------------------------------------------------- 251 * |Bits |Field |Descriptions 252 * | :----: | :----: | :---- | 253 * |[15:0] |FPRICLRn |PDMA Fixed Priority Clear Register (Write Only) 254 * | | |Set this bit to 1 to clear fixed priority level. 255 * | | |0 = No effect. 256 * | | |1 = Clear PDMA channel [n] fixed priority setting. 257 * | | |Note: User can read PDMA_PRISET register to know the channel priority. 258 * @var PDMA_T::INTEN 259 * Offset: 0x418 PDMA Interrupt Enable Register 260 * --------------------------------------------------------------------------------------------------- 261 * |Bits |Field |Descriptions 262 * | :----: | :----: | :---- | 263 * |[15:0] |INTENn |PDMA Interrupt Enable Register 264 * | | |This field is used for enabling PDMA channel[n] interrupt. 265 * | | |0 = PDMA channel n interrupt Disabled. 266 * | | |1 = PDMA channel n interrupt Enabled. 267 * @var PDMA_T::INTSTS 268 * Offset: 0x41C PDMA Interrupt Status Register 269 * --------------------------------------------------------------------------------------------------- 270 * |Bits |Field |Descriptions 271 * | :----: | :----: | :---- | 272 * |[0] |ABTIF |PDMA Read/Write Target Abort Interrupt Flag (Read Only) 273 * | | |This bit indicates that PDMA has target abort error; Software can read PDMA_ABTSTS register to find which channel has target abort error. 274 * | | |0 = No AHB bus ERROR response received. 275 * | | |1 = AHB bus ERROR response received. 276 * |[1] |TDIF |Transfer Done Interrupt Flag (Read Only) 277 * | | |This bit indicates that PDMA controller has finished transmission; User can read PDMA_TDSTS register to indicate which channel finished transfer. 278 * | | |0 = Not finished yet. 279 * | | |1 = PDMA channel has finished transmission. 280 * |[2] |ALIGNF |Transfer Alignment Interrupt Flag (Read Only) 281 * | | |0 = PDMA channel source address and destination address both follow transfer width setting. 282 * | | |1 = PDMA channel source address or destination address is not follow transfer width setting. 283 * |[8] |REQTOF0 |Request Time-out Flag for Channel 0 284 * | | |This flag indicates that PDMA controller has waited peripheral request for a period defined by PDMA_TOC0, user can write 1 to clear these bits. 285 * | | |0 = No request time-out. 286 * | | |1 = Peripheral request time-out. 287 * |[9] |REQTOF1 |Request Time-out Flag for Channel 1 288 * | | |This flag indicates that PDMA controller has waited peripheral request for a period defined by PDMA_TOC1, user can write 1 to clear these bits. 289 * | | |0 = No request time-out. 290 * | | |1 = Peripheral request time-out. 291 * @var PDMA_T::ABTSTS 292 * Offset: 0x420 PDMA Channel Read/Write Target Abort Flag Register 293 * --------------------------------------------------------------------------------------------------- 294 * |Bits |Field |Descriptions 295 * | :----: | :----: | :---- | 296 * |[15:0] |ABTIFn |PDMA Read/Write Target Abort Interrupt Status Flag 297 * | | |This bit indicates which PDMA controller has target abort error; User can write 1 to clear these bits. 298 * | | |0 = No AHB bus ERROR response received when channel n transfer. 299 * | | |1 = AHB bus ERROR response received when channel n transfer. 300 * @var PDMA_T::TDSTS 301 * Offset: 0x424 PDMA Channel Transfer Done Flag Register 302 * --------------------------------------------------------------------------------------------------- 303 * |Bits |Field |Descriptions 304 * | :----: | :----: | :---- | 305 * |[15:0] |TDIFn |Transfer Done Flag Register 306 * | | |This bit indicates whether PDMA controller channel transfer has been finished or not, user can write 1 to clear these bits. 307 * | | |0 = PDMA channel transfer has not finished. 308 * | | |1 = PDMA channel has finished transmission. 309 * @var PDMA_T::ALIGN 310 * Offset: 0x428 PDMA Transfer Alignment Status Register 311 * --------------------------------------------------------------------------------------------------- 312 * |Bits |Field |Descriptions 313 * | :----: | :----: | :---- | 314 * |[15:0] |ALIGNn |Transfer Alignment Flag Register 315 * | | |0 = PDMA channel source address and destination address both follow transfer width setting. 316 * | | |1 = PDMA channel source address or destination address is not follow transfer width setting. 317 * @var PDMA_T::TACTSTS 318 * Offset: 0x42C PDMA Transfer Active Flag Register 319 * --------------------------------------------------------------------------------------------------- 320 * |Bits |Field |Descriptions 321 * | :----: | :----: | :---- | 322 * |[15:0] |TXACTFn |Transfer on Active Flag Register (Read Only) 323 * | | |This bit indicates which PDMA channel is in active. 324 * | | |0 = PDMA channel is not finished. 325 * | | |1 = PDMA channel is active. 326 * @var PDMA_T::TOUTPSC 327 * Offset: 0x430 PDMA Time-out Prescaler Register 328 * --------------------------------------------------------------------------------------------------- 329 * |Bits |Field |Descriptions 330 * | :----: | :----: | :---- | 331 * |[2:0] |TOUTPSC0 |PDMA Channel 0 Time-out Clock Source Prescaler Bits 332 * | | |000 = PDMA channel 0 time-out clock source is HCLK/2^8. 333 * | | |001 = PDMA channel 0 time-out clock source is HCLK/2^9. 334 * | | |010 = PDMA channel 0 time-out clock source is HCLK/2^10. 335 * | | |011 = PDMA channel 0 time-out clock source is HCLK/2^11. 336 * | | |100 = PDMA channel 0 time-out clock source is HCLK/2^12. 337 * | | |101 = PDMA channel 0 time-out clock source is HCLK/2^13. 338 * | | |110 = PDMA channel 0 time-out clock source is HCLK/2^14. 339 * | | |111 = PDMA channel 0 time-out clock source is HCLK/2^15. 340 * |[6:4] |TOUTPSC1 |PDMA Channel 1 Time-out Clock Source Prescaler Bits 341 * | | |000 = PDMA channel 1 time-out clock source is HCLK/2^8. 342 * | | |001 = PDMA channel 1 time-out clock source is HCLK/2^9. 343 * | | |010 = PDMA channel 1 time-out clock source is HCLK/2^10. 344 * | | |011 = PDMA channel 1 time-out clock source is HCLK/2^11. 345 * | | |100 = PDMA channel 1 time-out clock source is HCLK/2^12. 346 * | | |101 = PDMA channel 1 time-out clock source is HCLK/2^13. 347 * | | |110 = PDMA channel 1 time-out clock source is HCLK/2^14. 348 * | | |111 = PDMA channel 1 time-out clock source is HCLK/2^15. 349 * @var PDMA_T::TOUTEN 350 * Offset: 0x434 PDMA Time-out Enable Register 351 * --------------------------------------------------------------------------------------------------- 352 * |Bits |Field |Descriptions 353 * | :----: | :----: | :---- | 354 * |[0] |TOUTEN0 |PDMA Channel 0 Time-out Enable Bit 355 * | | |0 = PDMA Channel 0 time-out function Disable. 356 * | | |1 = PDMA Channel 0 time-out function Enable. 357 * |[1] |TOUTEN1 |PDMA Channel 1 Time-out Enable Bit 358 * | | |0 = PDMA Channel 1 time-out function Disable. 359 * | | |1 = PDMA Channel 1 time-out function Enable. 360 * @var PDMA_T::TOUTIEN 361 * Offset: 0x438 PDMA Time-out Interrupt Enable Register 362 * --------------------------------------------------------------------------------------------------- 363 * |Bits |Field |Descriptions 364 * | :----: | :----: | :---- | 365 * |[0] |TOUTIEN0 |PDMA Channel 0 Time-out Interrupt Enable Bit 366 * | | |0 = PDMA Channel 0 time-out interrupt Disable. 367 * | | |1 = PDMA Channel 0 time-out interrupt Enable. 368 * |[1] |TOUTIEN1 |PDMA Channel 1 Time-out Interrupt Enable Bit 369 * | | |0 = PDMA Channel 1 time-out interrupt Disable. 370 * | | |1 = PDMA Channel 1 time-out interrupt Enable. 371 * @var PDMA_T::SCATBA 372 * Offset: 0x43C PDMA Scatter-Gather Descriptor Table Base Address Register 373 * --------------------------------------------------------------------------------------------------- 374 * |Bits |Field |Descriptions 375 * | :----: | :----: | :---- | 376 * |[31:16] |SCATBA |PDMA Scatter-gather Descriptor Table Address Register 377 * | | |In Scatter-Gather mode, this is the base address for calculating the next link - list address 378 * | | |The next link address equation is 379 * | | |Next Link Address = PDMA_SCATBA + PDMA_DSCT_NEXT. 380 * | | |Note: Only useful in Scatter-Gather mode. 381 * @var PDMA_T::TOC0_1 382 * Offset: 0x440 PDMA Channel 0 and Channel 1 Time-out Counter Register 383 * --------------------------------------------------------------------------------------------------- 384 * |Bits |Field |Descriptions 385 * | :----: | :----: | :---- | 386 * |[15:0] |TOC0 |Time-out Counter for Channel 0 387 * | | |This controls the period of time-out function for channel 0 388 * | | |The calculation unit is based on TOUTPSC0 (PDMA_TOUTPSC[2:0]) clock. 389 * | | |Time-out period = (Period of time-out clock) * (16-bit TOCn),n = 0,1. 390 * |[31:16] |TOC1 |Time-out Counter for Channel 1 391 * | | |This controls the period of time-out function for channel 1 392 * | | |The calculation unit is based on TOUTPSC1 (PDMA_TOUTPSC[5:3]) clock 393 * | | |The example of time-out period can refer TOC0 bit description. 394 * @var PDMA_T::CHRST 395 * Offset: 0x460 PDMA Channel Reset Control Register 396 * --------------------------------------------------------------------------------------------------- 397 * |Bits |Field |Descriptions 398 * | :----: | :----: | :---- | 399 * |[15:0] |CHnRST |Channel N Reset 400 * | | |0 = corresponding channel n not reset. 401 * | | |1 = corresponding channel n is reset. 402 * @var PDMA_T::REQSEL0_3 403 * Offset: 0x480 PDMA Channel 0 to Channel 3 Request Source Select Register 404 * --------------------------------------------------------------------------------------------------- 405 * |Bits |Field |Descriptions 406 * | :----: | :----: | :---- | 407 * |[6:0] |REQSRC0 |Channel 0 Request Source Selection 408 * | | |This filed defines which peripheral is connected to PDMA channel 0 409 * | | |User can configure the peripheral by setting REQSRC0. 410 * | | |0 = Disable PDMA. 411 * | | |1 = Reserved. 412 * | | |2 = Channel connects to USB_TX. 413 * | | |3 = Channel connects to USB_RX. 414 * | | |4 = Channel connects to UART0_TX. 415 * | | |5 = Channel connects to UART0_RX. 416 * | | |6 = Channel connects to UART1_TX. 417 * | | |7 = Channel connects to UART1_RX. 418 * | | |8 = Channel connects to UART2_TX. 419 * | | |9 = Channel connects to UART2_RX. 420 * | | |10 = Channel connects to UART3_TX. 421 * | | |11 = Channel connects to UART3_RX. 422 * | | |12 = Channel connects to UART4_TX. 423 * | | |13 = Channel connects to UART4_RX. 424 * | | |14 = Channel connects to UART5_TX. 425 * | | |15 = Channel connects to UART5_RX. 426 * | | |16 = Channel connects to USCI0_TX. 427 * | | |17 = Channel connects to USCI0_RX. 428 * | | |18 = Channel connects to USCI1_TX. 429 * | | |19 = Channel connects to USCI1_RX. 430 * | | |20 = Channel connects to QSPI0_TX. 431 * | | |21 = Channel connects to QSPI0_RX. 432 * | | |22 = Channel connects to SPI0_TX. 433 * | | |23 = Channel connects to SPI0_RX. 434 * | | |24 = Channel connects to SPI1_TX. 435 * | | |25 = Channel connects to SPI1_RX. 436 * | | |26 = Channel connects to SPI2_TX. 437 * | | |27 = Channel connects to SPI2_RX. 438 * | | |28 = Channel connects to SPI3_TX. 439 * | | |29 = Channel connects to SPI3_RX. 440 * | | |30 = Channel connects to ADC_RX. 441 * | | |32 = Channel connects to EPWM0_P1_RX. 442 * | | |33 = Channel connects to EPWM0_P2_RX. 443 * | | |34 = Channel connects to EPWM0_P3_RX. 444 * | | |35 = Channel connects to EPWM1_P1_RX. 445 * | | |36 = Channel connects to EPWM1_P2_RX. 446 * | | |37 = Channel connects to EPWM1_P3_RX. 447 * | | |38 = Channel connects to I2C0_TX. 448 * | | |39 = Channel connects to I2C0_RX. 449 * | | |40 = Channel connects to I2C1_TX. 450 * | | |41 = Channel connects to I2C1_RX. 451 * | | |42 = Channel connects to I2C2_TX. 452 * | | |43 = Channel connects to I2C2_RX. 453 * | | |44 = Channel connects to I2S0_TX. 454 * | | |45 = Channel connects to I2S0_RX. 455 * | | |46 = Channel connects to TMR0. 456 * | | |47 = Channel connects to TMR1. 457 * | | |48 = Channel connects to TMR2. 458 * | | |49 = Channel connects to TMR3. 459 * | | |50 = Channel connects to TMR4. 460 * | | |51 = Channel connects to TMR5. 461 * | | |52 = Channel connects to DAC0_TX. 462 * | | |53 = Channel connects to DAC1_TX. 463 * | | |54 = Channel connects to EPWM0_CH0_TX. 464 * | | |55 = Channel connects to EPWM0_CH1_TX. 465 * | | |56 = Channel connects to EPWM0_CH2_TX. 466 * | | |57 = Channel connects to EPWM0_CH3_TX. 467 * | | |58 = Channel connects to EPWM0_CH4_TX. 468 * | | |59 = Channel connects to EPWM0_CH5_TX. 469 * | | |60 = Channel connects to EPWM1_CH0_TX. 470 * | | |61 = Channel connects to EPWM1_CH1_TX. 471 * | | |62 = Channel connects to EPWM1_CH2_TX. 472 * | | |63 = Channel connects to EPWM1_CH3_TX. 473 * | | |64 = Channel connects to EPWM1_CH4_TX. 474 * | | |65 = Channel connects to EPWM1_CH5_TX. 475 * | | |Others = Reserved. 476 * | | |Note 1: A request source cannot assign to two channels at the same time. 477 * | | |Note 2: This field is useless when transfer between memory and memory. 478 * |[14:8] |REQSRC1 |Channel 1 Request Source Selection 479 * | | |This filed defines which peripheral is connected to PDMA channel 1 480 * | | |User can configure the peripheral setting by REQSRC1. 481 * | | |Note: The channel configuration is the same as REQSRC0 field 482 * | | |Please refer to the explanation of REQSRC0. 483 * |[22:16] |REQSRC2 |Channel 2 Request Source Selection 484 * | | |This filed defines which peripheral is connected to PDMA channel 2 485 * | | |User can configure the peripheral setting by REQSRC2. 486 * | | |Note: The channel configuration is the same as REQSRC0 field 487 * | | |Please refer to the explanation of REQSRC0. 488 * |[30:24] |REQSRC3 |Channel 3 Request Source Selection 489 * | | |This filed defines which peripheral is connected to PDMA channel 3 490 * | | |User can configure the peripheral setting by REQSRC3. 491 * | | |Note: The channel configuration is the same as REQSRC0 field 492 * | | |Please refer to the explanation of REQSRC0. 493 * @var PDMA_T::REQSEL4_7 494 * Offset: 0x484 PDMA Request Source Select Register 1 495 * --------------------------------------------------------------------------------------------------- 496 * |Bits |Field |Descriptions 497 * | :----: | :----: | :---- | 498 * |[6:0] |REQSRC4 |Channel 4 Request Source Selection 499 * | | |This filed defines which peripheral is connected to PDMA channel 4 500 * | | |User can configure the peripheral setting by REQSRC4. 501 * | | |Note: The channel configuration is the same as REQSRC0 field 502 * | | |Please refer to the explanation of REQSRC0. 503 * |[14:8] |REQSRC5 |Channel 5 Request Source Selection 504 * | | |This filed defines which peripheral is connected to PDMA channel 5 505 * | | |User can configure the peripheral setting by REQSRC5. 506 * | | |Note: The channel configuration is the same as REQSRC0 field 507 * | | |Please refer to the explanation of REQSRC0. 508 * |[22:16] |REQSRC6 |Channel 6 Request Source Selection 509 * | | |This filed defines which peripheral is connected to PDMA channel 6 510 * | | |User can configure the peripheral setting by REQSRC6. 511 * | | |Note: The channel configuration is the same as REQSRC0 field 512 * | | |Please refer to the explanation of REQSRC0. 513 * |[30:24] |REQSRC7 |Channel 7 Request Source Selection 514 * | | |This filed defines which peripheral is connected to PDMA channel 7 515 * | | |User can configure the peripheral setting by REQSRC7. 516 * | | |Note: The channel configuration is the same as REQSRC0 field 517 * | | |Please refer to the explanation of REQSRC0. 518 */ 519 520 DSCT_T DSCT[8]; /*!< [0x0000 ~ 0x007C] DMA Embedded Description Table 0~7 */ 521 __I uint32_t CURSCAT[8]; /*!< [0x0080~0x009C] Current Scatter-Gather Descriptor Table Address of PDMA Channel 0~7 */ 522 __I uint32_t RESERVE0[216]; 523 __IO uint32_t CHCTL; /*!< [0x0400] PDMA Channel Control Register */ 524 __O uint32_t PAUSE; /*!< [0x0404] PDMA Transfer Pause Control Register */ 525 __O uint32_t SWREQ; /*!< [0x0408] PDMA Software Request Register */ 526 __I uint32_t TRGSTS; /*!< [0x040c] PDMA Channel Request Status Register */ 527 __IO uint32_t PRISET; /*!< [0x0410] PDMA Fixed Priority Setting Register */ 528 __O uint32_t PRICLR; /*!< [0x0414] PDMA Fixed Priority Clear Register */ 529 __IO uint32_t INTEN; /*!< [0x0418] PDMA Interrupt Enable Register */ 530 __IO uint32_t INTSTS; /*!< [0x041c] PDMA Interrupt Status Register */ 531 __IO uint32_t ABTSTS; /*!< [0x0420] PDMA Channel Read/Write Target Abort Flag Register */ 532 __IO uint32_t TDSTS; /*!< [0x0424] PDMA Channel Transfer Done Flag Register */ 533 __IO uint32_t ALIGN; /*!< [0x0428] PDMA Transfer Alignment Status Register */ 534 __I uint32_t TACTSTS; /*!< [0x042c] PDMA Transfer Active Flag Register */ 535 __IO uint32_t TOUTPSC; /*!< [0x0430] PDMA Time-out Prescaler Register */ 536 __IO uint32_t TOUTEN; /*!< [0x0434] PDMA Time-out Enable Register */ 537 __IO uint32_t TOUTIEN; /*!< [0x0438] PDMA Time-out Interrupt Enable Register */ 538 __IO uint32_t SCATBA; /*!< [0x043c] PDMA Scatter-Gather Descriptor Table Base Address Register */ 539 __IO uint32_t TOC0_1; /*!< [0x0440] PDMA Channel 0 and Channel 1 Time-out Counter Register */ 540 __I uint32_t RESERVE1[7]; 541 __IO uint32_t CHRST; /*!< [0x0460] PDMA Channel Reset Register */ 542 __I uint32_t RESERVE2[7]; 543 __IO uint32_t REQSEL0_3; /*!< [0x0480] PDMA Channel 0 to Channel 3 Request Source Select Register */ 544 __IO uint32_t REQSEL4_7; /*!< [0x0484] PDMA Channel 4 to Channel 7 Request Source Select Register */ 545 __I uint32_t RESERVE4[30]; 546 STRIDE_T STRIDE[6]; /*!< [0x0500 ~ 0x052C] Stride function control register of PDMA Channel 0 ~ 5 */ 547 __IO uint32_t RESERVE5[52]; 548 REPEAT_T REPEAT[2]; /*!< [0x0600 ~ 0x060C] Repeat Count Function Control Register of PDMA Channel 0 ~ 1 */ 549 } PDMA_T; 550 551 552 553 554 /** 555 @addtogroup PDMA_CONST PDMA Bit Field Definition 556 Constant Definitions for PDMA Controller 557 @{ 558 */ 559 560 #define PDMA_DSCT_CTL_OPMODE_Pos (0) /*!< PDMA_T::DSCT_CTL: OPMODE Position */ 561 #define PDMA_DSCT_CTL_OPMODE_Msk (0x3ul << PDMA_DSCT_CTL_OPMODE_Pos) /*!< PDMA_T::DSCT_CTL: OPMODE Mask */ 562 563 #define PDMA_DSCT_CTL_TXTYPE_Pos (2) /*!< PDMA_T::DSCT_CTL: TXTYPE Position */ 564 #define PDMA_DSCT_CTL_TXTYPE_Msk (0x1ul << PDMA_DSCT_CTL_TXTYPE_Pos) /*!< PDMA_T::DSCT_CTL: TXTYPE Mask */ 565 566 #define PDMA_DSCT_CTL_BURSIZE_Pos (4) /*!< PDMA_T::DSCT_CTL: BURSIZE Position */ 567 #define PDMA_DSCT_CTL_BURSIZE_Msk (0x7ul << PDMA_DSCT_CTL_BURSIZE_Pos) /*!< PDMA_T::DSCT_CTL: BURSIZE Mask */ 568 569 #define PDMA_DSCT_CTL_TBINTDIS_Pos (7) /*!< PDMA_T::DSCT_CTL: TBINTDIS Position */ 570 #define PDMA_DSCT_CTL_TBINTDIS_Msk (0x1ul << PDMA_DSCT_CTL_TBINTDIS_Pos) /*!< PDMA_T::DSCT_CTL: TBINTDIS Mask */ 571 572 #define PDMA_DSCT_CTL_SAINC_Pos (8) /*!< PDMA_T::DSCT_CTL: SAINC Position */ 573 #define PDMA_DSCT_CTL_SAINC_Msk (0x3ul << PDMA_DSCT_CTL_SAINC_Pos) /*!< PDMA_T::DSCT_CTL: SAINC Mask */ 574 575 #define PDMA_DSCT_CTL_DAINC_Pos (10) /*!< PDMA_T::DSCT_CTL: DAINC Position */ 576 #define PDMA_DSCT_CTL_DAINC_Msk (0x3ul << PDMA_DSCT_CTL_DAINC_Pos) /*!< PDMA_T::DSCT_CTL: DAINC Mask */ 577 578 #define PDMA_DSCT_CTL_TXWIDTH_Pos (12) /*!< PDMA_T::DSCT_CTL: TXWIDTH Position */ 579 #define PDMA_DSCT_CTL_TXWIDTH_Msk (0x3ul << PDMA_DSCT_CTL_TXWIDTH_Pos) /*!< PDMA_T::DSCT_CTL: TXWIDTH Mask */ 580 581 #define PDMA_DSCT_CTL_TXACK_Pos (14) /*!< PDMA_T::DSCT_CTL: TXACK Position */ 582 #define PDMA_DSCT_CTL_TXACK_Msk (0x1ul << PDMA_DSCT_CTL_TXACK_Pos) /*!< PDMA_T::DSCT_CTL: TXACK Mask */ 583 584 #define PDMA_DSCT_CTL_STRIDEEN_Pos (15) /*!< PDMA_T::DSCT_CTL: STRIDEEN Position */ 585 #define PDMA_DSCT_CTL_STRIDEEN_Msk (0x1ul << PDMA_DSCT_CTL_STRIDEEN_Pos) /*!< PDMA_T::DSCT_CTL: STRIDEEN Mask */ 586 587 #define PDMA_DSCT_CTL_TXCNT_Pos (16) /*!< PDMA_T::DSCT_CTL: TXCNT Position */ 588 #define PDMA_DSCT_CTL_TXCNT_Msk (0xfffful << PDMA_DSCT_CTL_TXCNT_Pos) /*!< PDMA_T::DSCT_CTL: TXCNT Mask */ 589 590 #define PDMA_DSCT_SA_SA_Pos (0) /*!< PDMA_T::DSCT_SA: SA Position */ 591 #define PDMA_DSCT_SA_SA_Msk (0xfffffffful << PDMA_DSCT_SA_SA_Pos) /*!< PDMA_T::DSCT_SA: SA Mask */ 592 593 #define PDMA_DSCT_DA_DA_Pos (0) /*!< PDMA_T::DSCT_DA: DA Position */ 594 #define PDMA_DSCT_DA_DA_Msk (0xfffffffful << PDMA_DSCT_DA_DA_Pos) /*!< PDMA_T::DSCT_DA: DA Mask */ 595 596 #define PDMA_DSCT_NEXT_NEXT_Pos (0) /*!< PDMA_T::DSCT_NEXT: NEXT Position */ 597 #define PDMA_DSCT_NEXT_NEXT_Msk (0xfffful << PDMA_DSCT_NEXT_NEXT_Pos) /*!< PDMA_T::DSCT_NEXT: NEXT Mask */ 598 599 #define PDMA_DSCT_NEXT_EXENEXT_Pos (16) /*!< PDMA_T::DSCT_FIRST: NEXT Position */ 600 #define PDMA_DSCT_NEXT_EXENEXT_Msk (0xfffful << PDMA_DSCT_NEXT_EXENEXT_Pos) /*!< PDMA_T::DSCT_FIRST: NEXT Mask */ 601 602 #define PDMA_CURSCAT_CURADDR_Pos (0) /*!< PDMA_T::CURSCAT: CURADDR Position */ 603 #define PDMA_CURSCAT_CURADDR_Msk (0xfffffffful << PDMA_CURSCAT_CURADDR_Pos) /*!< PDMA_T::CURSCAT: CURADDR Mask */ 604 605 #define PDMA_CHCTL_CHENn_Pos (0) /*!< PDMA_T::CHCTL: CHENn Position */ 606 #define PDMA_CHCTL_CHENn_Msk (0xfffful << PDMA_CHCTL_CHENn_Pos) /*!< PDMA_T::CHCTL: CHENn Mask */ 607 608 #define PDMA_PAUSE_PAUSEn_Pos (0) /*!< PDMA_T::PAUSE: PAUSEn Position */ 609 #define PDMA_PAUSE_PAUSEn_Msk (0xfffful << PDMA_PAUSE_PAUSEn_Pos) /*!< PDMA_T::PAUSE: PAUSEn Mask */ 610 611 #define PDMA_SWREQ_SWREQn_Pos (0) /*!< PDMA_T::SWREQ: SWREQn Position */ 612 #define PDMA_SWREQ_SWREQn_Msk (0xfffful << PDMA_SWREQ_SWREQn_Pos) /*!< PDMA_T::SWREQ: SWREQn Mask */ 613 614 #define PDMA_TRGSTS_REQSTSn_Pos (0) /*!< PDMA_T::TRGSTS: REQSTSn Position */ 615 #define PDMA_TRGSTS_REQSTSn_Msk (0xfffful << PDMA_TRGSTS_REQSTSn_Pos) /*!< PDMA_T::TRGSTS: REQSTSn Mask */ 616 617 #define PDMA_PRISET_FPRISETn_Pos (0) /*!< PDMA_T::PRISET: FPRISETn Position */ 618 #define PDMA_PRISET_FPRISETn_Msk (0xfffful << PDMA_PRISET_FPRISETn_Pos) /*!< PDMA_T::PRISET: FPRISETn Mask */ 619 620 #define PDMA_PRICLR_FPRICLRn_Pos (0) /*!< PDMA_T::PRICLR: FPRICLRn Position */ 621 #define PDMA_PRICLR_FPRICLRn_Msk (0xfffful << PDMA_PRICLR_FPRICLRn_Pos) /*!< PDMA_T::PRICLR: FPRICLRn Mask */ 622 623 #define PDMA_INTEN_INTENn_Pos (0) /*!< PDMA_T::INTEN: INTENn Position */ 624 #define PDMA_INTEN_INTENn_Msk (0xfffful << PDMA_INTEN_INTENn_Pos) /*!< PDMA_T::INTEN: INTENn Mask */ 625 626 #define PDMA_INTSTS_ABTIF_Pos (0) /*!< PDMA_T::INTSTS: ABTIF Position */ 627 #define PDMA_INTSTS_ABTIF_Msk (0x1ul << PDMA_INTSTS_ABTIF_Pos) /*!< PDMA_T::INTSTS: ABTIF Mask */ 628 629 #define PDMA_INTSTS_TDIF_Pos (1) /*!< PDMA_T::INTSTS: TDIF Position */ 630 #define PDMA_INTSTS_TDIF_Msk (0x1ul << PDMA_INTSTS_TDIF_Pos) /*!< PDMA_T::INTSTS: TDIF Mask */ 631 632 #define PDMA_INTSTS_ALIGNF_Pos (2) /*!< PDMA_T::INTSTS: ALIGNF Position */ 633 #define PDMA_INTSTS_ALIGNF_Msk (0x1ul << PDMA_INTSTS_ALIGNF_Pos) /*!< PDMA_T::INTSTS: ALIGNF Mask */ 634 635 #define PDMA_INTSTS_REQTOF0_Pos (8) /*!< PDMA_T::INTSTS: REQTOF0 Position */ 636 #define PDMA_INTSTS_REQTOF0_Msk (0x1ul << PDMA_INTSTS_REQTOF0_Pos) /*!< PDMA_T::INTSTS: REQTOF0 Mask */ 637 638 #define PDMA_INTSTS_REQTOF1_Pos (9) /*!< PDMA_T::INTSTS: REQTOF1 Position */ 639 #define PDMA_INTSTS_REQTOF1_Msk (0x1ul << PDMA_INTSTS_REQTOF1_Pos) /*!< PDMA_T::INTSTS: REQTOF1 Mask */ 640 641 #define PDMA_ABTSTS_ABTIF0_Pos (0) /*!< PDMA_T::ABTSTS: ABTIF0 Position */ 642 #define PDMA_ABTSTS_ABTIF0_Msk (0x1ul << PDMA_ABTSTS_ABTIF0_Pos) /*!< PDMA_T::ABTSTS: ABTIF0 Mask */ 643 644 #define PDMA_ABTSTS_ABTIF1_Pos (1) /*!< PDMA_T::ABTSTS: ABTIF1 Position */ 645 #define PDMA_ABTSTS_ABTIF1_Msk (0x1ul << PDMA_ABTSTS_ABTIF1_Pos) /*!< PDMA_T::ABTSTS: ABTIF1 Mask */ 646 647 #define PDMA_ABTSTS_ABTIF2_Pos (2) /*!< PDMA_T::ABTSTS: ABTIF2 Position */ 648 #define PDMA_ABTSTS_ABTIF2_Msk (0x1ul << PDMA_ABTSTS_ABTIF2_Pos) /*!< PDMA_T::ABTSTS: ABTIF2 Mask */ 649 650 #define PDMA_ABTSTS_ABTIF3_Pos (3) /*!< PDMA_T::ABTSTS: ABTIF3 Position */ 651 #define PDMA_ABTSTS_ABTIF3_Msk (0x1ul << PDMA_ABTSTS_ABTIF3_Pos) /*!< PDMA_T::ABTSTS: ABTIF3 Mask */ 652 653 #define PDMA_ABTSTS_ABTIF4_Pos (4) /*!< PDMA_T::ABTSTS: ABTIF4 Position */ 654 #define PDMA_ABTSTS_ABTIF4_Msk (0x1ul << PDMA_ABTSTS_ABTIF4_Pos) /*!< PDMA_T::ABTSTS: ABTIF4 Mask */ 655 656 #define PDMA_ABTSTS_ABTIF5_Pos (5) /*!< PDMA_T::ABTSTS: ABTIF5 Position */ 657 #define PDMA_ABTSTS_ABTIF5_Msk (0x1ul << PDMA_ABTSTS_ABTIF5_Pos) /*!< PDMA_T::ABTSTS: ABTIF5 Mask */ 658 659 #define PDMA_ABTSTS_ABTIF6_Pos (6) /*!< PDMA_T::ABTSTS: ABTIF6 Position */ 660 #define PDMA_ABTSTS_ABTIF6_Msk (0x1ul << PDMA_ABTSTS_ABTIF6_Pos) /*!< PDMA_T::ABTSTS: ABTIF6 Mask */ 661 662 #define PDMA_ABTSTS_ABTIF7_Pos (7) /*!< PDMA_T::ABTSTS: ABTIF7 Position */ 663 #define PDMA_ABTSTS_ABTIF7_Msk (0x1ul << PDMA_ABTSTS_ABTIF7_Pos) /*!< PDMA_T::ABTSTS: ABTIF7 Mask */ 664 665 #define PDMA_ABTSTS_ABTIF8_Pos (8) /*!< PDMA_T::ABTSTS: ABTIF8 Position */ 666 #define PDMA_ABTSTS_ABTIF8_Msk (0x1ul << PDMA_ABTSTS_ABTIF8_Pos) /*!< PDMA_T::ABTSTS: ABTIF8 Mask */ 667 668 #define PDMA_ABTSTS_ABTIF9_Pos (9) /*!< PDMA_T::ABTSTS: ABTIF9 Position */ 669 #define PDMA_ABTSTS_ABTIF9_Msk (0x1ul << PDMA_ABTSTS_ABTIF9_Pos) /*!< PDMA_T::ABTSTS: ABTIF9 Mask */ 670 671 #define PDMA_ABTSTS_ABTIF10_Pos (10) /*!< PDMA_T::ABTSTS: ABTIF10 Position */ 672 #define PDMA_ABTSTS_ABTIF10_Msk (0x1ul << PDMA_ABTSTS_ABTIF10_Pos) /*!< PDMA_T::ABTSTS: ABTIF10 Mask */ 673 674 #define PDMA_ABTSTS_ABTIF11_Pos (11) /*!< PDMA_T::ABTSTS: ABTIF11 Position */ 675 #define PDMA_ABTSTS_ABTIF11_Msk (0x1ul << PDMA_ABTSTS_ABTIF11_Pos) /*!< PDMA_T::ABTSTS: ABTIF11 Mask */ 676 677 #define PDMA_ABTSTS_ABTIF12_Pos (12) /*!< PDMA_T::ABTSTS: ABTIF12 Position */ 678 #define PDMA_ABTSTS_ABTIF12_Msk (0x1ul << PDMA_ABTSTS_ABTIF12_Pos) /*!< PDMA_T::ABTSTS: ABTIF12 Mask */ 679 680 #define PDMA_ABTSTS_ABTIF13_Pos (13) /*!< PDMA_T::ABTSTS: ABTIF13 Position */ 681 #define PDMA_ABTSTS_ABTIF13_Msk (0x1ul << PDMA_ABTSTS_ABTIF13_Pos) /*!< PDMA_T::ABTSTS: ABTIF13 Mask */ 682 683 #define PDMA_ABTSTS_ABTIF14_Pos (14) /*!< PDMA_T::ABTSTS: ABTIF14 Position */ 684 #define PDMA_ABTSTS_ABTIF14_Msk (0x1ul << PDMA_ABTSTS_ABTIF14_Pos) /*!< PDMA_T::ABTSTS: ABTIF14 Mask */ 685 686 #define PDMA_ABTSTS_ABTIF15_Pos (15) /*!< PDMA_T::ABTSTS: ABTIF15 Position */ 687 #define PDMA_ABTSTS_ABTIF15_Msk (0x1ul << PDMA_ABTSTS_ABTIF15_Pos) /*!< PDMA_T::ABTSTS: ABTIF15 Mask */ 688 689 #define PDMA_TDSTS_TDIF0_Pos (0) /*!< PDMA_T::TDSTS: TDIF0 Position */ 690 #define PDMA_TDSTS_TDIF0_Msk (0x1ul << PDMA_TDSTS_TDIF0_Pos) /*!< PDMA_T::TDSTS: TDIF0 Mask */ 691 692 #define PDMA_TDSTS_TDIF1_Pos (1) /*!< PDMA_T::TDSTS: TDIF1 Position */ 693 #define PDMA_TDSTS_TDIF1_Msk (0x1ul << PDMA_TDSTS_TDIF1_Pos) /*!< PDMA_T::TDSTS: TDIF1 Mask */ 694 695 #define PDMA_TDSTS_TDIF2_Pos (2) /*!< PDMA_T::TDSTS: TDIF2 Position */ 696 #define PDMA_TDSTS_TDIF2_Msk (0x1ul << PDMA_TDSTS_TDIF2_Pos) /*!< PDMA_T::TDSTS: TDIF2 Mask */ 697 698 #define PDMA_TDSTS_TDIF3_Pos (3) /*!< PDMA_T::TDSTS: TDIF3 Position */ 699 #define PDMA_TDSTS_TDIF3_Msk (0x1ul << PDMA_TDSTS_TDIF3_Pos) /*!< PDMA_T::TDSTS: TDIF3 Mask */ 700 701 #define PDMA_TDSTS_TDIF4_Pos (4) /*!< PDMA_T::TDSTS: TDIF4 Position */ 702 #define PDMA_TDSTS_TDIF4_Msk (0x1ul << PDMA_TDSTS_TDIF4_Pos) /*!< PDMA_T::TDSTS: TDIF4 Mask */ 703 704 #define PDMA_TDSTS_TDIF5_Pos (5) /*!< PDMA_T::TDSTS: TDIF5 Position */ 705 #define PDMA_TDSTS_TDIF5_Msk (0x1ul << PDMA_TDSTS_TDIF5_Pos) /*!< PDMA_T::TDSTS: TDIF5 Mask */ 706 707 #define PDMA_TDSTS_TDIF6_Pos (6) /*!< PDMA_T::TDSTS: TDIF6 Position */ 708 #define PDMA_TDSTS_TDIF6_Msk (0x1ul << PDMA_TDSTS_TDIF6_Pos) /*!< PDMA_T::TDSTS: TDIF6 Mask */ 709 710 #define PDMA_TDSTS_TDIF7_Pos (7) /*!< PDMA_T::TDSTS: TDIF7 Position */ 711 #define PDMA_TDSTS_TDIF7_Msk (0x1ul << PDMA_TDSTS_TDIF7_Pos) /*!< PDMA_T::TDSTS: TDIF7 Mask */ 712 713 #define PDMA_TDSTS_TDIF8_Pos (8) /*!< PDMA_T::TDSTS: TDIF8 Position */ 714 #define PDMA_TDSTS_TDIF8_Msk (0x1ul << PDMA_TDSTS_TDIF8_Pos) /*!< PDMA_T::TDSTS: TDIF8 Mask */ 715 716 #define PDMA_TDSTS_TDIF9_Pos (9) /*!< PDMA_T::TDSTS: TDIF9 Position */ 717 #define PDMA_TDSTS_TDIF9_Msk (0x1ul << PDMA_TDSTS_TDIF9_Pos) /*!< PDMA_T::TDSTS: TDIF9 Mask */ 718 719 #define PDMA_TDSTS_TDIF10_Pos (10) /*!< PDMA_T::TDSTS: TDIF10 Position */ 720 #define PDMA_TDSTS_TDIF10_Msk (0x1ul << PDMA_TDSTS_TDIF10_Pos) /*!< PDMA_T::TDSTS: TDIF10 Mask */ 721 722 #define PDMA_TDSTS_TDIF11_Pos (11) /*!< PDMA_T::TDSTS: TDIF11 Position */ 723 #define PDMA_TDSTS_TDIF11_Msk (0x1ul << PDMA_TDSTS_TDIF11_Pos) /*!< PDMA_T::TDSTS: TDIF11 Mask */ 724 725 #define PDMA_TDSTS_TDIF12_Pos (12) /*!< PDMA_T::TDSTS: TDIF12 Position */ 726 #define PDMA_TDSTS_TDIF12_Msk (0x1ul << PDMA_TDSTS_TDIF12_Pos) /*!< PDMA_T::TDSTS: TDIF12 Mask */ 727 728 #define PDMA_TDSTS_TDIF13_Pos (13) /*!< PDMA_T::TDSTS: TDIF13 Position */ 729 #define PDMA_TDSTS_TDIF13_Msk (0x1ul << PDMA_TDSTS_TDIF13_Pos) /*!< PDMA_T::TDSTS: TDIF13 Mask */ 730 731 #define PDMA_TDSTS_TDIF14_Pos (14) /*!< PDMA_T::TDSTS: TDIF14 Position */ 732 #define PDMA_TDSTS_TDIF14_Msk (0x1ul << PDMA_TDSTS_TDIF14_Pos) /*!< PDMA_T::TDSTS: TDIF14 Mask */ 733 734 #define PDMA_TDSTS_TDIF15_Pos (15) /*!< PDMA_T::TDSTS: TDIF15 Position */ 735 #define PDMA_TDSTS_TDIF15_Msk (0x1ul << PDMA_TDSTS_TDIF15_Pos) /*!< PDMA_T::TDSTS: TDIF15 Mask */ 736 737 #define PDMA_ALIGN_ALIGNn_Pos (0) /*!< PDMA_T::ALIGN: ALIGNn Position */ 738 #define PDMA_ALIGN_ALIGNn_Msk (0xfffful << PDMA_ALIGN_ALIGNn_Pos) /*!< PDMA_T::ALIGN: ALIGNn Mask */ 739 740 #define PDMA_TACTSTS_TXACTFn_Pos (0) /*!< PDMA_T::TACTSTS: TXACTFn Position */ 741 #define PDMA_TACTSTS_TXACTFn_Msk (0xfffful << PDMA_TACTSTS_TXACTFn_Pos) /*!< PDMA_T::TACTSTS: TXACTFn Mask */ 742 743 #define PDMA_TOUTPSC_TOUTPSC0_Pos (0) /*!< PDMA_T::TOUTPSC: TOUTPSC0 Position */ 744 #define PDMA_TOUTPSC_TOUTPSC0_Msk (0x7ul << PDMA_TOUTPSC_TOUTPSC0_Pos) /*!< PDMA_T::TOUTPSC: TOUTPSC0 Mask */ 745 746 #define PDMA_TOUTPSC_TOUTPSC1_Pos (4) /*!< PDMA_T::TOUTPSC: TOUTPSC1 Position */ 747 #define PDMA_TOUTPSC_TOUTPSC1_Msk (0x7ul << PDMA_TOUTPSC_TOUTPSC1_Pos) /*!< PDMA_T::TOUTPSC: TOUTPSC1 Mask */ 748 749 #define PDMA_TOUTEN_TOUTENn_Pos (0) /*!< PDMA_T::TOUTEN: TOUTENn Position */ 750 #define PDMA_TOUTEN_TOUTENn_Msk (0x3ul << PDMA_TOUTEN_TOUTENn_Pos) /*!< PDMA_T::TOUTEN: TOUTENn Mask */ 751 752 #define PDMA_TOUTIEN_TOUTIENn_Pos (0) /*!< PDMA_T::TOUTIEN: TOUTIENn Position */ 753 #define PDMA_TOUTIEN_TOUTIENn_Msk (0x3ul << PDMA_TOUTIEN_TOUTIENn_Pos) /*!< PDMA_T::TOUTIEN: TOUTIENn Mask */ 754 755 #define PDMA_SCATBA_SCATBA_Pos (16) /*!< PDMA_T::SCATBA: SCATBA Position */ 756 #define PDMA_SCATBA_SCATBA_Msk (0xfffful << PDMA_SCATBA_SCATBA_Pos) /*!< PDMA_T::SCATBA: SCATBA Mask */ 757 758 #define PDMA_TOC0_1_TOC0_Pos (0) /*!< PDMA_T::TOC0_1: TOC0 Position */ 759 #define PDMA_TOC0_1_TOC0_Msk (0xfffful << PDMA_TOC0_1_TOC0_Pos) /*!< PDMA_T::TOC0_1: TOC0 Mask */ 760 761 #define PDMA_TOC0_1_TOC1_Pos (16) /*!< PDMA_T::TOC0_1: TOC1 Position */ 762 #define PDMA_TOC0_1_TOC1_Msk (0xfffful << PDMA_TOC0_1_TOC1_Pos) /*!< PDMA_T::TOC0_1: TOC1 Mask */ 763 764 #define PDMA_CHRST_CHnRST_Pos (0) /*!< PDMA_T::CHRST: CHnRST Position */ 765 #define PDMA_CHRST_CHnRST_Msk (0xfffful << PDMA_CHRST_CHnRST_Pos) /*!< PDMA_T::CHRST: CHnRST Mask */ 766 767 #define PDMA_REQSEL0_3_REQSRC0_Pos (0) /*!< PDMA_T::REQSEL0_3: REQSRC0 Position */ 768 #define PDMA_REQSEL0_3_REQSRC0_Msk (0x7ful << PDMA_REQSEL0_3_REQSRC0_Pos) /*!< PDMA_T::REQSEL0_3: REQSRC0 Mask */ 769 770 #define PDMA_REQSEL0_3_REQSRC1_Pos (8) /*!< PDMA_T::REQSEL0_3: REQSRC1 Position */ 771 #define PDMA_REQSEL0_3_REQSRC1_Msk (0x7ful << PDMA_REQSEL0_3_REQSRC1_Pos) /*!< PDMA_T::REQSEL0_3: REQSRC1 Mask */ 772 773 #define PDMA_REQSEL0_3_REQSRC2_Pos (16) /*!< PDMA_T::REQSEL0_3: REQSRC2 Position */ 774 #define PDMA_REQSEL0_3_REQSRC2_Msk (0x7ful << PDMA_REQSEL0_3_REQSRC2_Pos) /*!< PDMA_T::REQSEL0_3: REQSRC2 Mask */ 775 776 #define PDMA_REQSEL0_3_REQSRC3_Pos (24) /*!< PDMA_T::REQSEL0_3: REQSRC3 Position */ 777 #define PDMA_REQSEL0_3_REQSRC3_Msk (0x7ful << PDMA_REQSEL0_3_REQSRC3_Pos) /*!< PDMA_T::REQSEL0_3: REQSRC3 Mask */ 778 779 #define PDMA_REQSEL4_7_REQSRC4_Pos (0) /*!< PDMA_T::REQSEL4_7: REQSRC4 Position */ 780 #define PDMA_REQSEL4_7_REQSRC4_Msk (0x7ful << PDMA_REQSEL4_7_REQSRC4_Pos) /*!< PDMA_T::REQSEL4_7: REQSRC4 Mask */ 781 782 #define PDMA_REQSEL4_7_REQSRC5_Pos (8) /*!< PDMA_T::REQSEL4_7: REQSRC5 Position */ 783 #define PDMA_REQSEL4_7_REQSRC5_Msk (0x7ful << PDMA_REQSEL4_7_REQSRC5_Pos) /*!< PDMA_T::REQSEL4_7: REQSRC5 Mask */ 784 785 #define PDMA_REQSEL4_7_REQSRC6_Pos (16) /*!< PDMA_T::REQSEL4_7: REQSRC6 Position */ 786 #define PDMA_REQSEL4_7_REQSRC6_Msk (0x7ful << PDMA_REQSEL4_7_REQSRC6_Pos) /*!< PDMA_T::REQSEL4_7: REQSRC6 Mask */ 787 788 #define PDMA_REQSEL4_7_REQSRC7_Pos (24) /*!< PDMA_T::REQSEL4_7: REQSRC7 Position */ 789 #define PDMA_REQSEL4_7_REQSRC7_Msk (0x7ful << PDMA_REQSEL4_7_REQSRC7_Pos) /*!< PDMA_T::REQSEL4_7: REQSRC7 Mask */ 790 791 #define PDMA_STCRn_STC_Pos (0) /*!< PDMA_T::STCRn: STC Position */ 792 #define PDMA_STCRn_STC_Msk (0xfffful << PDMA_STCRn_STC_Pos) /*!< PDMA_T::STCRn: STC Mask */ 793 794 #define PDMA_ASOCRn_SASOL_Pos (0) /*!< PDMA_T::ASOCRn: SASOL Position */ 795 #define PDMA_ASOCRn_SASOL_Msk (0xfffful << PDMA_ASOCRn_SASOL_Pos) /*!< PDMA_T::ASOCRn: SASOL Mask */ 796 797 #define PDMA_ASOCRn_DASOL_Pos (16) /*!< PDMA_T::ASOCRn: DASOL Position */ 798 #define PDMA_ASOCRn_DASOL_Msk (0xfffful << PDMA_ASOCRn_DASOL_Pos) /*!< PDMA_T::ASOCRn: DASOL Mask */ 799 800 #define PDMA_AICTLn_SAICNT_Pos (0) /*!< PDMA_T::AICTLn: SAICNT Position */ 801 #define PDMA_AICTLn_SAICNT_Msk (0xfffful << PDMA_ASOCRn_SASOL_Pos) /*!< PDMA_T::AICTLn: SAICNT Mask */ 802 803 #define PDMA_AICTLn_DAICNT_Pos (16) /*!< PDMA_T::AICTLn: DAICNT Position */ 804 #define PDMA_AICTLn_DAICNT_Msk (0xfffful << PDMA_ASOCRn_DASOL_Pos) /*!< PDMA_T::AICTLn: DAICNT Mask */ 805 806 #define PDMA_RCNTn_RCNT_Pos (0) /*!< PDMA_T::RCNTn: RCNT Position */ 807 #define PDMA_RCNTn_RCNT_Msk (0xfffful << PDMA_STCRn_RCNT_Pos) /*!< PDMA_T::RCNTn: RCNT Mask */ 808 809 /**@}*/ /* PDMA_CONST */ 810 /**@}*/ /* end of PDMA register group */ 811 /**@}*/ /* end of REGISTER group */ 812 813 814 #endif /* __PDMA_REG_H__ */ 815
