1 /**************************************************************************//** 2 * @file keystore_reg.h 3 * @version V1.00 4 * @brief Key store register definition header file 5 * 6 * @copyright SPDX-License-Identifier: Apache-2.0 7 * @copyright Copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. 8 *****************************************************************************/ 9 #ifndef __KEYSTORE_REG_H__ 10 #define __KEYSTORE_REG_H__ 11 12 13 /** @addtogroup REGISTER Control Register 14 15 @{ 16 17 */ 18 19 20 /*---------------------- Key Store -------------------------*/ 21 /** 22 @addtogroup KS Key Store (KS) 23 Memory Mapped Structure for KS Controller 24 @{ */ 25 26 typedef struct 27 { 28 29 30 /** 31 * @var KS_T::CTL 32 * Offset: 0x00 Key Store Control Register 33 * --------------------------------------------------------------------------------------------------- 34 * |Bits |Field |Descriptions 35 * | :----: | :----: | :---- | 36 * |[0] |START |Key Store Start Control Bit 37 * | | |0 = No operation. 38 * | | |1 = Start the operation. 39 * |[3:1] |OPMODE |Key Store Operation Mode 40 * | | |000 = Read operation. 41 * | | |001 = Create operation. 42 * | | |010 = Erase one key operation (only for key is in SRAM and OTP). 43 * | | |011 = Erase all keys operation (only for SRAM and Flash). 44 * | | |100 = Revoke key operation. 45 * | | |101 = Data Remanence prevention operation (only for SRAM). 46 * | | |111 = Lock operation (only for OTP). 47 * | | |Others = reserved. 48 * |[7] |CONT |Read/Write Key Continue Bit 49 * | | |0 = Read/Write key operation is not continuous to previous operation. 50 * | | |1 = Read/Write key operation is continuous to previous operation. 51 * |[8] |INIT |Key Store Initialization 52 * | | |User should to check BUSY(KS_STS[2]) is 0, and then write 1 to this bit and START(KS_CTL[0[), the Key Store will start to be initializationed. 53 * | | |After Key Store is initialized, INIT will be cleared. 54 * | | |Note: Before executing INIT, user must to checks KS(SYS_SRAMPC1) is 00. 55 * |[15] |IEN |Key Store Interrupt Enable Bit 56 * | | |0 = Key Store Interrupt Disabled. 57 * | | |1 = Key Store Interrupt Enabled. 58 * @var KS_T::METADATA 59 * Offset: 0x04 Key Store Metadata Register 60 * --------------------------------------------------------------------------------------------------- 61 * |Bits |Field |Descriptions 62 * | :----: | :----: | :---- | 63 * |[0] |SEC |Secure Key Selection Bit 64 * | | |0 = Set key as the non-secure key. 65 * | | |1 = Set key as the secure key. 66 * |[1] |PRIV |Privilege Key Selection Bit 67 * | | |0 = Set key as the non-privilege key. 68 * | | |1 = Set key as the privilege key. 69 * |[2] |READABLE |Key Readable Control Bit 70 * | | |0 = key is un-readable. 71 * | | |1 = key is readable. 72 * |[4] |BS |Booting State Selection Bit 73 * | | |0 = Set key used at all state. 74 * | | |1 = Set key used at boot loader state 1 (BL1 state). 75 * |[12:8] |SIZE |Key Size Selection Bits 76 * | | |00000 = 128 bits. 77 * | | |00001 = 163 bits. 78 * | | |00010 = 192 bits. 79 * | | |00011 = 224 bits. 80 * | | |00100 = 233 bits. 81 * | | |00101 = 255 bits. 82 * | | |00110 = 256 bits. 83 * | | |00111 = 283 bits. 84 * | | |01000 = 384 bits. 85 * | | |01001 = 409 bits. 86 * | | |01010 = 512 bits. 87 * | | |01011 = 521 bits. 88 * | | |01100 = 571 bits. 89 * | | |10000 = 1024 bits. 90 * | | |10001 = 1536 bits. 91 * | | |10010 = 2048 bits. 92 * | | |10011 = 3072 bits. 93 * | | |10100 = 4096 bits. 94 * | | |Others = reserved. 95 * |[18:16] |OWNER |Key Owner Selection Bits 96 * | | |000 = AES 97 * | | |001 = HMAC 98 * | | |010 = RSA exponent blind key for SCAP(CRYPTO_RSA_CTL[8]) = 1 and CRT(CRYPTO_RSA_CTL[2]) = 0 99 * | | |011 = RSA middle data, p, q and private key. 100 * | | |100 = ECC. 101 * | | |101 = CPU. 102 * | | |Others = reserved. 103 * |[25:20] |NUMBER |Key Number 104 * | | |Before read or erase one key operation starts, user should write the key number to be operated 105 * | | |When create operation is finished, user can read these bits to get its key number. 106 * |[31:30] |DST |Key Location Selection Bits 107 * | | |00 = Key is in SRAM. 108 * | | |01 = Key is in Flash. 109 * | | |10 = Key is in OTP. 110 * | | |Others = reserved. 111 * @var KS_T::STS 112 * Offset: 0x08 Key Store Status Register 113 * --------------------------------------------------------------------------------------------------- 114 * |Bits |Field |Descriptions 115 * | :----: | :----: | :---- | 116 * |[0] |IF |Key Store Finish Interrupt Flag 117 * | | |This bit is cleared by writing 1 and it has no effect by writing 0. 118 * | | |0 = No Key Store interrupt. 119 * | | |1 = Key Store operation done interrupt. 120 * |[1] |EIF |Key Store Error Flag 121 * | | |This bit is cleared by writing 1 and it has no effect by writing 0. 122 * | | |0 = No Key Store error. 123 * | | |1 = Key Store error interrupt. 124 * |[2] |BUSY |Key Store Busy Flag (read only) 125 * | | |0 = Key Store is idle or finished. 126 * | | |1 = Key Store is busy. 127 * |[3] |SRAMFULL |Key Storage at SRAM Full Status Bit (read only) 128 * | | |0 = Key Storage at SRAM is not full. 129 * | | |1 = Key Storage at SRAM is full. 130 * |[4] |FLASHFULL |Key Storage at Flash Full Status Bit (read only) 131 * | | |0 = Key Storage at Flash is not full. 132 * | | |1 = Key Storage at Flash is full. 133 * |[7] |INITDONE |Key Store Initialization Done Status (read only) 134 * | | |0 = Key Store is un-initialized. 135 * | | |1 = Key Store is initialized. 136 * |[8] |RAMINV |Key Store SRAM Invert Status (read only) 137 * | | |0 = Key Store key in SRAM is normal. 138 * | | |1 = Key Store key in SRAM is inverted. 139 * @var KS_T::REMAIN 140 * Offset: 0x0C Key Store Remaining Space Register 141 * --------------------------------------------------------------------------------------------------- 142 * |Bits |Field |Descriptions 143 * | :----: | :----: | :---- | 144 * |[12:0] |RRMNG |Key Store SRAM Remaining Space 145 * | | |The RRMNG shows the remaining byte count space for SRAM. 146 * |[28:16] |FRMNG |Key Store Flash Remaining Space 147 * | | |The FRMNG shows the remaining byte count space for Flash. 148 * @var KS_T::KEY0 149 * Offset: 0x20 Key Store Entry Key Word 0 Register 150 * --------------------------------------------------------------------------------------------------- 151 * |Bits |Field |Descriptions 152 * | :----: | :----: | :---- | 153 * |[31:0] |KEY |Key Data 154 * | | |The register will be cleared if the Key Store executes the write operation or CPU completes the reading key. 155 * @var KS_T::KEY1 156 * Offset: 0x24 Key Store Entry Key Word 1 Register 157 * --------------------------------------------------------------------------------------------------- 158 * |Bits |Field |Descriptions 159 * | :----: | :----: | :---- | 160 * |[31:0] |KEY |Key Data 161 * | | |The register will be cleared if the Key Store executes the write operation or CPU completes the reading key. 162 * @var KS_T::KEY2 163 * Offset: 0x28 Key Store Entry Key Word 2 Register 164 * --------------------------------------------------------------------------------------------------- 165 * |Bits |Field |Descriptions 166 * | :----: | :----: | :---- | 167 * |[31:0] |KEY |Key Data 168 * | | |The register will be cleared if the Key Store executes the write operation or CPU completes the reading key. 169 * @var KS_T::KEY3 170 * Offset: 0x2C Key Store Entry Key Word 3 Register 171 * --------------------------------------------------------------------------------------------------- 172 * |Bits |Field |Descriptions 173 * | :----: | :----: | :---- | 174 * |[31:0] |KEY |Key Data 175 * | | |The register will be cleared if the Key Store executes the write operation or CPU completes the reading key. 176 * @var KS_T::KEY4 177 * Offset: 0x30 Key Store Entry Key Word 4 Register 178 * --------------------------------------------------------------------------------------------------- 179 * |Bits |Field |Descriptions 180 * | :----: | :----: | :---- | 181 * |[31:0] |KEY |Key Data 182 * | | |The register will be cleared if the Key Store executes the write operation or CPU completes the reading key. 183 * @var KS_T::KEY5 184 * Offset: 0x34 Key Store Entry Key Word 5 Register 185 * --------------------------------------------------------------------------------------------------- 186 * |Bits |Field |Descriptions 187 * | :----: | :----: | :---- | 188 * |[31:0] |KEY |Key Data 189 * | | |The register will be cleared if the Key Store executes the write operation or CPU completes the reading key. 190 * @var KS_T::KEY6 191 * Offset: 0x38 Key Store Entry Key Word 6 Register 192 * --------------------------------------------------------------------------------------------------- 193 * |Bits |Field |Descriptions 194 * | :----: | :----: | :---- | 195 * |[31:0] |KEY |Key Data 196 * | | |The register will be cleared if the Key Store executes the write operation or CPU completes the reading key. 197 * @var KS_T::KEY7 198 * Offset: 0x3C Key Store Entry Key Word 7 Register 199 * --------------------------------------------------------------------------------------------------- 200 * |Bits |Field |Descriptions 201 * | :----: | :----: | :---- | 202 * |[31:0] |KEY |Key Data 203 * | | |The register will be cleared if the Key Store executes the write operation or CPU completes the reading key. 204 * @var KS_T::OTPSTS 205 * Offset: 0x40 Key Store OTP Keys Status Register 206 * --------------------------------------------------------------------------------------------------- 207 * |Bits |Field |Descriptions 208 * | :----: | :----: | :---- | 209 * |[0] |KEY0 |OTP Key 0 Used Status 210 * | | |0 = OTP key 0 is unused. 211 * | | |1 = OTP key 0 is used. 212 * | | |Note: If chip is in RMA stage, this bit will set to 1 and key is revoked after initialization if key is existed.Note: If chip is changed to RMA stage, the existing key will be revoked after initialization. 213 * |[1] |KEY1 |OTP Key 1 Used Status 214 * | | |0 = OTP key 1 is unused. 215 * | | |1 = OTP key 1 is used. 216 * | | |Note: If chip is in RMA stage, this bit will set to 1 and key is revoked after initialization if key is existed.Note: If chip is changed to RMA stage, the existing key will be revoked after initialization. 217 * |[2] |KEY2 |OTP Key 2 Used Status 218 * | | |0 = OTP key 2 is unused. 219 * | | |1 = OTP key 2 is used. 220 * | | |Note: If chip is in RMA stage, this bit will set to 1 and key is revoked after initialization if key is existed.Note: If chip is changed to RMA stage, the existing key will be revoked after initialization. 221 * |[3] |KEY3 |OTP Key 3 Used Status 222 * | | |0 = OTP key 3 is unused. 223 * | | |1 = OTP key 3 is used. 224 * | | |Note: If chip is in RMA stage, this bit will set to 1 and key is revoked after initialization if key is existed.Note: If chip is changed to RMA stage, the existing key will be revoked after initialization. 225 * |[4] |KEY4 |OTP Key 4 Used Status 226 * | | |0 = OTP key 4 is unused. 227 * | | |1 = OTP key 4 is used. 228 * | | |Note: If chip is in RMA stage, this bit will set to 1 and key is revoked after initialization if key is existed.Note: If chip is changed to RMA stage, existing key will be revoked after initialization. 229 * |[5] |KEY5 |OTP Key 5 Used Status 230 * | | |0 = OTP key 5 is unused. 231 * | | |1 = OTP key 5 is used. 232 * | | |Note: If chip is in RMA stage, this bit will set to 1 and key is revoked after initialization if key is existed.Note: If chip is changed to RMA stage, the existing key will be revoked after initialization. 233 * |[6] |KEY6 |OTP Key 6 Used Status 234 * | | |0 = OTP key 6 is unused. 235 * | | |1 = OTP key 6 is used. 236 * | | |Note: If chip is in RMA stage, this bit will set to 1 and key is revoked after initialization if key is existed.Note: If chip is changed to RMA stage, the existing key will be revoked after initialization. 237 * |[7] |KEY7 |OTP Key 7 Used Status 238 * | | |0 = OTP key 7 is unused. 239 * | | |1 = OTP key 7 is used. 240 * | | |Note: If chip is inchanged to RMA stage, this bit will set to 1 and key is revoked after initialization if key is existedthe existing key will be revoked after initialization. 241 * @var KS_T::REMKCNT 242 * Offset: 0x44 Key Store Remaining Key Count Register 243 * --------------------------------------------------------------------------------------------------- 244 * |Bits |Field |Descriptions 245 * | :----: | :----: | :---- | 246 * |[5:0] |RRMKCNT |Key Store SRAM Remaining Key Count 247 * | | |The RRMKCNT shows the remaining key count for SRAM. 248 * |[21:16] |FRMKCNT |Key Store Flash Remaining Key Count 249 * | | |The FRMKCNT shows the remaining key count for Flash. 250 * @var KS_T::VERSION 251 * Offset: 0xFFC Key Store RTL Design Version Register 252 * --------------------------------------------------------------------------------------------------- 253 * |Bits |Field |Descriptions 254 * | :----: | :----: | :---- | 255 * |[15:0] |MINOR |RTL Design Minor Version Number 256 * | | |Minor version number is dependent on moduleu2019s ECO version control. 257 * | | |0x0000 (Current Minor Version Number) 258 * |[23:16] |SUB |RTL Design Sub Version Number 259 * | | |Sub version number is correlated to moduleu2019s key feature. 260 * | | |0x01 (Current Sub Version Number) 261 * |[31:24] |MAJOR |RTL Design Major Version Number 262 * | | |Major version number is correlated to Product Line. 263 * | | |0x021 (Current Major Version Number) 264 */ 265 __IO uint32_t CTL; /*!< [0x0000] Key Store Control Register */ 266 __IO uint32_t METADATA; /*!< [0x0004] Key Store Metadata Register */ 267 __IO uint32_t STS; /*!< [0x0008] Key Store Status Register */ 268 __I uint32_t REMAIN; /*!< [0x000c] Key Store Remaining Space Register */ 269 __I uint32_t RESERVE0[4]; 270 __IO uint32_t KEY[8]; /*!< [0x0020-0x003c] Key Store Entry Key Word 0 Register */ 271 __I uint32_t OTPSTS; /*!< [0x0040] Key Store OTP Keys Status Register */ 272 __I uint32_t REMKCNT; /*!< [0x0044] Key Store Remaining Key Count Register */ 273 __I uint32_t RESERVE1[1005]; 274 __I uint32_t VERSION; /*!< [0x0ffc] Key Store RTL Design Version Register */ 275 276 } KS_T; 277 278 /** 279 @addtogroup KS_CONST KS Bit Field Definition 280 Constant Definitions for KS Controller 281 @{ */ 282 283 #define KS_CTL_START_Pos (0) /*!< KS_T::CTL: START Position */ 284 #define KS_CTL_START_Msk (0x1ul << KS_CTL_START_Pos) /*!< KS_T::CTL: START Mask */ 285 286 #define KS_CTL_OPMODE_Pos (1) /*!< KS_T::CTL: OPMODE Position */ 287 #define KS_CTL_OPMODE_Msk (0x7ul << KS_CTL_OPMODE_Pos) /*!< KS_T::CTL: OPMODE Mask */ 288 289 #define KS_CTL_CONT_Pos (7) /*!< KS_T::CTL: CONT Position */ 290 #define KS_CTL_CONT_Msk (0x1ul << KS_CTL_CONT_Pos) /*!< KS_T::CTL: CONT Mask */ 291 292 #define KS_CTL_INIT_Pos (8) /*!< KS_T::CTL: INIT Position */ 293 #define KS_CTL_INIT_Msk (0x1ul << KS_CTL_INIT_Pos) /*!< KS_T::CTL: INIT Mask */ 294 295 #define KS_CTL_IEN_Pos (15) /*!< KS_T::CTL: IEN Position */ 296 #define KS_CTL_IEN_Msk (0x1ul << KS_CTL_IEN_Pos) /*!< KS_T::CTL: IEN Mask */ 297 298 #define KS_METADATA_SEC_Pos (0) /*!< KS_T::METADATA: SEC Position */ 299 #define KS_METADATA_SEC_Msk (0x1ul << KS_METADATA_SEC_Pos) /*!< KS_T::METADATA: SEC Mask */ 300 301 #define KS_METADATA_PRIV_Pos (1) /*!< KS_T::METADATA: PRIV Position */ 302 #define KS_METADATA_PRIV_Msk (0x1ul << KS_METADATA_PRIV_Pos) /*!< KS_T::METADATA: PRIV Mask */ 303 304 #define KS_METADATA_READABLE_Pos (2) /*!< KS_T::METADATA: READABLE Position */ 305 #define KS_METADATA_READABLE_Msk (0x1ul << KS_METADATA_READABLE_Pos) /*!< KS_T::METADATA: READABLE Mask */ 306 307 #define KS_METADATA_BS_Pos (4) /*!< KS_T::METADATA: BS Position */ 308 #define KS_METADATA_BS_Msk (0x1ul << KS_METADATA_BS_Pos) /*!< KS_T::METADATA: BS Mask */ 309 310 #define KS_METADATA_SIZE_Pos (8) /*!< KS_T::METADATA: SIZE Position */ 311 #define KS_METADATA_SIZE_Msk (0x1ful << KS_METADATA_SIZE_Pos) /*!< KS_T::METADATA: SIZE Mask */ 312 313 #define KS_METADATA_OWNER_Pos (16) /*!< KS_T::METADATA: OWNER Position */ 314 #define KS_METADATA_OWNER_Msk (0x7ul << KS_METADATA_OWNER_Pos) /*!< KS_T::METADATA: OWNER Mask */ 315 316 #define KS_METADATA_NUMBER_Pos (20) /*!< KS_T::METADATA: NUMBER Position */ 317 #define KS_METADATA_NUMBER_Msk (0x3ful << KS_METADATA_NUMBER_Pos) /*!< KS_T::METADATA: NUMBER Mask */ 318 319 #define KS_METADATA_DST_Pos (30) /*!< KS_T::METADATA: DST Position */ 320 #define KS_METADATA_DST_Msk (0x3ul << KS_METADATA_DST_Pos) /*!< KS_T::METADATA: DST Mask */ 321 322 #define KS_STS_IF_Pos (0) /*!< KS_T::STS: IF Position */ 323 #define KS_STS_IF_Msk (0x1ul << KS_STS_IF_Pos) /*!< KS_T::STS: IF Mask */ 324 325 #define KS_STS_EIF_Pos (1) /*!< KS_T::STS: EIF Position */ 326 #define KS_STS_EIF_Msk (0x1ul << KS_STS_EIF_Pos) /*!< KS_T::STS: EIF Mask */ 327 328 #define KS_STS_BUSY_Pos (2) /*!< KS_T::STS: BUSY Position */ 329 #define KS_STS_BUSY_Msk (0x1ul << KS_STS_BUSY_Pos) /*!< KS_T::STS: BUSY Mask */ 330 331 #define KS_STS_SRAMFULL_Pos (3) /*!< KS_T::STS: SRAMFULL Position */ 332 #define KS_STS_SRAMFULL_Msk (0x1ul << KS_STS_SRAMFULL_Pos) /*!< KS_T::STS: SRAMFULL Mask */ 333 334 #define KS_STS_FLASHFULL_Pos (4) /*!< KS_T::STS: FLASHFULL Position */ 335 #define KS_STS_FLASHFULL_Msk (0x1ul << KS_STS_FLASHFULL_Pos) /*!< KS_T::STS: FLASHFULL Mask */ 336 337 #define KS_STS_INITDONE_Pos (7) /*!< KS_T::STS: INITDONE Position */ 338 #define KS_STS_INITDONE_Msk (0x1ul << KS_STS_INITDONE_Pos) /*!< KS_T::STS: INITDONE Mask */ 339 340 #define KS_STS_RAMINV_Pos (8) /*!< KS_T::STS: RAMINV Position */ 341 #define KS_STS_RAMINV_Msk (0x1ul << KS_STS_RAMINV_Pos) /*!< KS_T::STS: RAMINV Mask */ 342 343 #define KS_STS_KRVKF_Pos (9) /*!< KS_T::STS: KRVKF Position */ 344 #define KS_STS_KRVKF_Msk (0x1ul << KS_STS_KRVKF_Pos) /*!< KS_T::STS: KRVKF Mask */ 345 346 #define KS_REMAIN_RRMNG_Pos (0) /*!< KS_T::REMAIN: RRMNG Position */ 347 #define KS_REMAIN_RRMNG_Msk (0x1ffful << KS_REMAIN_RRMNG_Pos) /*!< KS_T::REMAIN: RRMNG Mask */ 348 349 #define KS_REMAIN_FRMNG_Pos (16) /*!< KS_T::REMAIN: FRMNG Position */ 350 #define KS_REMAIN_FRMNG_Msk (0x1ffful << KS_REMAIN_FRMNG_Pos) /*!< KS_T::REMAIN: FRMNG Mask */ 351 352 #define KS_KEY_KEY_Pos (0) /*!< KS_T::KEY: KEY Position */ 353 #define KS_KEY_KEY_Msk (0xfffffffful << KS_KEY0_KEY_Pos) /*!< KS_T::KEY: KEY Mask */ 354 355 #define KS_OTPSTS_KEY0_Pos (0) /*!< KS_T::OTPSTS: KEY0 Position */ 356 #define KS_OTPSTS_KEY0_Msk (0x1ul << KS_OTPSTS_KEY0_Pos) /*!< KS_T::OTPSTS: KEY0 Mask */ 357 358 #define KS_OTPSTS_KEY1_Pos (1) /*!< KS_T::OTPSTS: KEY1 Position */ 359 #define KS_OTPSTS_KEY1_Msk (0x1ul << KS_OTPSTS_KEY1_Pos) /*!< KS_T::OTPSTS: KEY1 Mask */ 360 361 #define KS_OTPSTS_KEY2_Pos (2) /*!< KS_T::OTPSTS: KEY2 Position */ 362 #define KS_OTPSTS_KEY2_Msk (0x1ul << KS_OTPSTS_KEY2_Pos) /*!< KS_T::OTPSTS: KEY2 Mask */ 363 364 #define KS_OTPSTS_KEY3_Pos (3) /*!< KS_T::OTPSTS: KEY3 Position */ 365 #define KS_OTPSTS_KEY3_Msk (0x1ul << KS_OTPSTS_KEY3_Pos) /*!< KS_T::OTPSTS: KEY3 Mask */ 366 367 #define KS_OTPSTS_KEY4_Pos (4) /*!< KS_T::OTPSTS: KEY4 Position */ 368 #define KS_OTPSTS_KEY4_Msk (0x1ul << KS_OTPSTS_KEY4_Pos) /*!< KS_T::OTPSTS: KEY4 Mask */ 369 370 #define KS_OTPSTS_KEY5_Pos (5) /*!< KS_T::OTPSTS: KEY5 Position */ 371 #define KS_OTPSTS_KEY5_Msk (0x1ul << KS_OTPSTS_KEY5_Pos) /*!< KS_T::OTPSTS: KEY5 Mask */ 372 373 #define KS_OTPSTS_KEY6_Pos (6) /*!< KS_T::OTPSTS: KEY6 Position */ 374 #define KS_OTPSTS_KEY6_Msk (0x1ul << KS_OTPSTS_KEY6_Pos) /*!< KS_T::OTPSTS: KEY6 Mask */ 375 376 #define KS_OTPSTS_KEY7_Pos (7) /*!< KS_T::OTPSTS: KEY7 Position */ 377 #define KS_OTPSTS_KEY7_Msk (0x1ul << KS_OTPSTS_KEY7_Pos) /*!< KS_T::OTPSTS: KEY7 Mask */ 378 379 #define KS_REMKCNT_RRMKCNT_Pos (0) /*!< KS_T::REMKCNT: RRMKCNT Position */ 380 #define KS_REMKCNT_RRMKCNT_Msk (0x3ful << KS_REMKCNT_RRMKCNT_Pos) /*!< KS_T::REMKCNT: RRMKCNT Mask */ 381 382 #define KS_REMKCNT_FRMKCNT_Pos (16) /*!< KS_T::REMKCNT: FRMKCNT Position */ 383 #define KS_REMKCNT_FRMKCNT_Msk (0x3ful << KS_REMKCNT_FRMKCNT_Pos) /*!< KS_T::REMKCNT: FRMKCNT Mask */ 384 385 #define KS_VERSION_MINOR_Pos (0) /*!< KS_T::VERSION: MINOR Position */ 386 #define KS_VERSION_MINOR_Msk (0xfffful << KS_VERSION_MINOR_Pos) /*!< KS_T::VERSION: MINOR Mask */ 387 388 #define KS_VERSION_SUB_Pos (16) /*!< KS_T::VERSION: SUB Position */ 389 #define KS_VERSION_SUB_Msk (0xfful << KS_VERSION_SUB_Pos) /*!< KS_T::VERSION: SUB Mask */ 390 391 #define KS_VERSION_MAJOR_Pos (24) /*!< KS_T::VERSION: MAJOR Position */ 392 #define KS_VERSION_MAJOR_Msk (0xfful << KS_VERSION_MAJOR_Pos) /*!< KS_T::VERSION: MAJOR Mask */ 393 394 /**@}*/ /* KS_CONST */ 395 /**@}*/ /* end of KS register group */ 396 /**@}*/ /* end of REGISTER group */ 397 398 #endif /* __KEYSTORE_REG_H__ */ 399
