1 /* 2 * SPDX-FileCopyrightText: 2016-2022 Espressif Systems (Shanghai) CO LTD 3 * 4 * SPDX-License-Identifier: GPL-2.0-or-later 5 */ 6 7 /* SoC-level support for ESP8266/ESP32. 8 * 9 * Provide a unified register-level interface. 10 * 11 * This is the same information provided in the register headers 12 * of ESP8266 Non-OS SDK and ESP-IDF soc component, however 13 * only values that are needed for the flasher stub are included here. 14 * 15 */ 16 #pragma once 17 18 #include <stdint.h> 19 #include <stdbool.h> 20 #include <stddef.h> 21 22 #define READ_REG(REG) (*((volatile uint32_t *)(REG))) 23 #define WRITE_REG(REG, VAL) *((volatile uint32_t *)(REG)) = (VAL) 24 #define REG_SET_MASK(reg, mask) WRITE_REG((reg), (READ_REG(reg)|(mask))) 25 #define REG_CLR_MASK(reg, mask) WRITE_REG((reg), (READ_REG(reg)&(~(mask)))) 26 27 #define ESP32_OR_LATER !(ESP8266) 28 #define ESP32S2_OR_LATER !(ESP8266 || ESP32) 29 #define ESP32S3_OR_LATER !(ESP8266 || ESP32 || ESP32S2) 30 31 /********************************************************** 32 * Per-SOC capabilities 33 */ 34 #ifdef ESP32S2 35 #define WITH_USB_OTG 1 36 #endif // ESP32S2 37 38 #ifdef ESP32C3 39 #define WITH_USB_JTAG_SERIAL 1 40 #define IS_RISCV 1 41 #endif // ESP32C3 42 43 #ifdef ESP32S3 44 #define WITH_USB_JTAG_SERIAL 1 45 #define WITH_USB_OTG 1 46 #endif // ESP32S3 47 48 #ifdef ESP32C6 49 #define WITH_USB_JTAG_SERIAL 1 50 #define IS_RISCV 1 51 #endif // ESP32C6 52 53 #ifdef ESP32H2 54 #define WITH_USB_JTAG_SERIAL 1 55 #define IS_RISCV 1 56 #endif // ESP32H2 57 58 // Increase CPU freq to speed up read/write operations over USB 59 #define USE_MAX_CPU_FREQ (WITH_USB_JTAG_SERIAL || WITH_USB_OTG) 60 61 /********************************************************** 62 * Per-SOC based peripheral register base addresses 63 */ 64 #ifdef ESP8266 65 #define UART_BASE_REG 0x60000000 /* UART0 */ 66 #define SPI_BASE_REG 0x60000200 /* SPI peripheral 0 */ 67 #endif 68 69 #ifdef ESP32 70 #define UART_BASE_REG 0x3ff40000 /* UART0 */ 71 #define SPI_BASE_REG 0x3ff42000 /* SPI peripheral 1, used for SPI flash */ 72 #define SPI0_BASE_REG 0x3ff43000 /* SPI peripheral 0, inner state machine */ 73 #define GPIO_BASE_REG 0x3ff44000 /* GPIO */ 74 #endif 75 76 #ifdef ESP32S2 77 #define UART_BASE_REG 0x60000000 /* UART0 */ 78 #define SPI_BASE_REG 0x3f402000 /* SPI peripheral 1, used for SPI flash */ 79 #define SPI0_BASE_REG 0x3f403000 /* SPI peripheral 0, inner state machine */ 80 #define GPIO_BASE_REG 0x3f404000 81 #define USB_BASE_REG 0x60080000 82 #define RTCCNTL_BASE_REG 0x3f408000 83 #define SYSTEM_BASE_REG 0x3F4C0000 84 #endif 85 86 #ifdef ESP32S3 87 #define UART_BASE_REG 0x60000000 /* UART0 */ 88 #define SPI_BASE_REG 0x60002000 /* SPI peripheral 1, used for SPI flash */ 89 #define SPI0_BASE_REG 0x60003000 /* SPI peripheral 0, inner state machine */ 90 #define GPIO_BASE_REG 0x60004000 /* GPIO */ 91 #define USB_BASE_REG 0x60080000 92 #define RTCCNTL_BASE_REG 0x60008000 /* RTC Control */ 93 #define USB_DEVICE_BASE_REG 0x60038000 94 #define SYSTEM_BASE_REG 0x600C0000 95 #endif 96 97 #ifdef ESP32C3 98 #define UART_BASE_REG 0x60000000 /* UART0 */ 99 #define SPI_BASE_REG 0x60002000 /* SPI peripheral 1, used for SPI flash */ 100 #define SPI0_BASE_REG 0x60003000 /* SPI peripheral 0, inner state machine */ 101 #define GPIO_BASE_REG 0x60004000 102 #define RTCCNTL_BASE_REG 0x60008000 /* RTC Control */ 103 #define USB_DEVICE_BASE_REG 0x60043000 104 #define SYSTEM_BASE_REG 0x600C0000 105 #endif 106 107 #ifdef ESP32C6BETA 108 #define UART_BASE_REG 0x60000000 /* UART0 */ 109 #define SPI_BASE_REG 0x60002000 /* SPI peripheral 1, used for SPI flash */ 110 #define SPI0_BASE_REG 0x60003000 /* SPI peripheral 0, inner state machine */ 111 #define GPIO_BASE_REG 0x60004000 112 #endif 113 114 #ifdef ESP32H2BETA1 115 #define UART_BASE_REG 0x60000000 /* UART0 */ 116 #define SPI_BASE_REG 0x60002000 /* SPI peripheral 1, used for SPI flash */ 117 #define SPI0_BASE_REG 0x60003000 /* SPI peripheral 0, inner state machine */ 118 #define GPIO_BASE_REG 0x60004000 119 #define RTCCNTL_BASE_REG 0x60008000 120 #endif 121 122 #ifdef ESP32H2BETA2 123 #define UART_BASE_REG 0x60000000 /* UART0 */ 124 #define SPI_BASE_REG 0x60002000 /* SPI peripheral 1, used for SPI flash */ 125 #define SPI0_BASE_REG 0x60003000 /* SPI peripheral 0, inner state machine */ 126 #define GPIO_BASE_REG 0x60004000 127 #endif 128 129 #ifdef ESP32C2 130 #define UART_BASE_REG 0x60000000 /* UART0 */ 131 #define SPI_BASE_REG 0x60002000 /* SPI peripheral 1, used for SPI flash */ 132 #define SPI0_BASE_REG 0x60003000 /* SPI peripheral 0, inner state machine */ 133 #define GPIO_BASE_REG 0x60004000 134 #endif 135 136 #ifdef ESP32C6 137 #define UART_BASE_REG 0x60000000 /* UART0 */ 138 #define SPI_BASE_REG 0x60003000 /* SPI peripheral 1, used for SPI flash */ 139 #define SPI0_BASE_REG 0x60002000 /* SPI peripheral 0, inner state machine */ 140 #define GPIO_BASE_REG 0x60091000 141 #define USB_DEVICE_BASE_REG 0x6000F000 142 #define DR_REG_PCR_BASE 0x60096000 143 #define DR_REG_LP_WDT_BASE 0x600B1C00 144 #endif 145 146 #ifdef ESP32H2 147 #define UART_BASE_REG 0x60000000 /* UART0 */ 148 #define SPI_BASE_REG 0x60003000 /* SPI peripheral 1, used for SPI flash */ 149 #define SPI0_BASE_REG 0x60002000 /* SPI peripheral 0, inner state machine */ 150 #define GPIO_BASE_REG 0x60091000 151 #define USB_DEVICE_BASE_REG 0x6000F000 152 #define DR_REG_PCR_BASE 0x60096000 153 #define DR_REG_LP_WDT_BASE 0x600B1C00 154 #endif 155 156 /********************************************************** 157 * UART peripheral 158 * 159 * The features we use are basically the same on all chips 160 * 161 * Only UART0 is used 162 */ 163 #define UART_CLKDIV_REG(X) (UART_BASE_REG + 0x14) 164 #define UART_CLKDIV_M (0x000FFFFF) 165 166 #if ESP32_OR_LATER 167 #define UART_CLKDIV_FRAG_S 20 168 #define UART_CLKDIV_FRAG_V 0xF 169 #endif 170 171 #define UART_FIFO(X) (UART_BASE_REG + 0x00) 172 #define UART_INT_ST(X) (UART_BASE_REG + 0x08) 173 #define UART_INT_ENA(X) (UART_BASE_REG + 0x0C) 174 #define UART_INT_CLR(X) (UART_BASE_REG + 0x10) 175 #define UART_STATUS(X) (UART_BASE_REG + 0x1C) 176 177 #if ESP32S2_OR_LATER && !ESP32C6 && !ESP32H2 178 #define UART_RXFIFO_CNT_M 0x3FF 179 #else 180 #define UART_RXFIFO_CNT_M 0xFF 181 #endif 182 183 #define UART_RXFIFO_FULL_INT_ENA (1<<0) 184 #define UART_RXFIFO_TOUT_INT_ENA (1<<8) 185 186 #define ETS_UART0_INUM 5 187 188 189 /********************************************************** 190 * SPI peripheral 191 * 192 * The features we use are mostly the same on all chips 193 * except for W0 base address & option for 2-byte status command 194 * 195 * Only one SPI peripheral is used (0 on ESP8266, 1 on ESP32). 196 * On ESP32S2 && ESP32S3 this is called SPI_MEM_xxx index 1 197 */ 198 #define SPI_CMD_REG (SPI_BASE_REG + 0x00) 199 #define SPI_FLASH_WREN (1<<30) 200 #define SPI_FLASH_RDSR (1<<27) 201 #define SPI_FLASH_SE (1<<24) 202 #define SPI_FLASH_BE (1<<23) 203 204 #define SPI_ADDR_REG (SPI_BASE_REG + 0x04) 205 206 #define SPI_CTRL_REG (SPI_BASE_REG + 0x08) 207 #if ESP32_OR_LATER 208 #define SPI_WRSR_2B (1<<22) 209 #endif 210 211 #if ESP32S2_OR_LATER 212 #define SPI_RD_STATUS_REG (SPI_BASE_REG + 0x2C) 213 #else 214 #define SPI_RD_STATUS_REG (SPI_BASE_REG + 0x10) 215 #endif 216 217 #ifdef ESP8266 218 #define SPI_W0_REG (SPI_BASE_REG + 0x40) 219 #endif 220 #ifdef ESP32 221 #define SPI_W0_REG (SPI_BASE_REG + 0x80) 222 #endif 223 #if ESP32S2_OR_LATER 224 #define SPI_W0_REG (SPI_BASE_REG + 0x58) 225 #endif 226 227 #if ESP32S2_OR_LATER 228 #define SPI_EXT2_REG (SPI_BASE_REG + 0x54) /* renamed SPI_MEM_FSM_REG */ 229 #else 230 #define SPI_EXT2_REG (SPI_BASE_REG + 0xF8) 231 #endif 232 233 #define SPI_ST 0x7 /* done state value */ 234 235 #ifdef ESP32 236 /* On ESP32 & newer the SPI peripherals are layered 237 * flash, this lets us check the state of the internal 238 * state machine under the SPI flash controller 239 */ 240 #define SPI0_EXT2_REG (SPI0_BASE_REG + 0xF8) 241 #endif 242 #if ESP32S2_OR_LATER 243 #define SPI0_EXT2_REG (SPI0_BASE_REG + 0x54) 244 #endif 245 246 /********************************************************** 247 * GPIO peripheral 248 * 249 * We only need to read the strapping register on ESP32 or later 250 */ 251 #define GPIO_STRAP_REG (GPIO_BASE_REG + 0x38) 252 253 /********************************************************** 254 * USB peripheral 255 */ 256 257 #ifdef ESP32S2 258 #define UART_USB_OTG 2 259 260 #define ETS_USB_INTR_SOURCE 48 261 #define ETS_USB_INUM 9 /* arbitrary level 1 level interrupt */ 262 #endif // ESP32S2 263 264 #ifdef ESP32C3 265 #define UART_USB_JTAG_SERIAL 3 266 267 #define DR_REG_INTERRUPT_CORE0_BASE 0x600c2000 268 #define INTERRUPT_CORE0_USB_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x068) /* USB-JTAG-Serial */ 269 270 #define ETS_USB_INUM 17 /* arbitrary level 1 level interrupt */ 271 #endif // ESP32C3 272 273 #ifdef ESP32S3 274 #define UART_USB_OTG 3 275 #define UART_USB_JTAG_SERIAL 4 276 277 #define DR_REG_INTERRUPT_CORE0_BASE 0x600c2000 278 #define INTERRUPT_CORE0_USB_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x098) /* DWC-OTG */ 279 #define INTERRUPT_CORE0_USB_DEVICE_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x180) /* USB-JTAG-Serial */ 280 281 #define ETS_USB_INUM 17 /* arbitrary level 1 level interrupt */ 282 #endif // ESP32S3 283 284 #ifdef ESP32C6 285 #define UART_USB_JTAG_SERIAL 3 286 287 #define DR_REG_INTERRUPT_MATRIX_BASE 0x60010000 288 #define INTERRUPT_CORE0_USB_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xC0) /* USB-JTAG-Serial, INTMTX_CORE0_USB_INTR_MAP_REG */ 289 290 #define ETS_USB_INUM 17 /* arbitrary level 1 level interrupt */ 291 #endif // ESP32C6 292 293 #ifdef ESP32H2 294 #define UART_USB_JTAG_SERIAL 3 295 296 #define DR_REG_INTERRUPT_MATRIX_BASE 0x60010000 297 #define INTERRUPT_CORE0_USB_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x94) /* USB-JTAG-Serial, INTMTX_CORE0_USB_INTR_MAP_REG */ 298 299 #define ETS_USB_INUM 17 /* arbitrary level 1 level interrupt */ 300 #endif // ESP32H2 301 302 #ifdef WITH_USB_JTAG_SERIAL 303 #define USB_DEVICE_INT_ENA_REG (USB_DEVICE_BASE_REG + 0x010) 304 #define USB_DEVICE_INT_CLR_REG (USB_DEVICE_BASE_REG + 0x014) 305 #define USB_DEVICE_EP1_CONF_REG (USB_DEVICE_BASE_REG + 0x004) 306 #define USB_DEVICE_EP1_REG (USB_DEVICE_BASE_REG + 0x000) 307 #define USB_DEVICE_SERIAL_OUT_RECV_PKT_INT_CLR (1<<2) 308 #define USB_DEVICE_SERIAL_OUT_EP_DATA_AVAIL (1<<2) 309 #define USB_DEVICE_SERIAL_OUT_RECV_PKT_INT_ENA (1<<2) 310 #endif // WITH_USB_JTAG_SERIAL 311 312 #define USB_GAHBCFG_REG (USB_BASE_REG + 0x8) 313 #define USB_GLBLLNTRMSK (1 << 0) 314 315 316 /********************************************************** 317 * RTC_CNTL peripheral 318 */ 319 320 #ifdef ESP32S2 321 #define RTC_CNTL_OPTION1_REG (RTCCNTL_BASE_REG + 0x0128) 322 #endif 323 324 #ifdef ESP32S3 325 #define RTC_CNTL_OPTION1_REG (RTCCNTL_BASE_REG + 0x012C) 326 #define RTC_CNTL_WDTCONFIG0_REG (RTCCNTL_BASE_REG + 0x0090) // RTC_CNTL_RTC_WDTCONFIG0_REG 327 #define RTC_CNTL_WDTWPROTECT_REG (RTCCNTL_BASE_REG + 0x00B0) // RTC_CNTL_RTC_WDTWPROTECT_REG 328 #endif 329 330 #ifdef ESP32C3 331 #define RTC_CNTL_WDTCONFIG0_REG (RTCCNTL_BASE_REG + 0x0090) 332 #define RTC_CNTL_WDTWPROTECT_REG (RTCCNTL_BASE_REG + 0x00A8) 333 #endif 334 335 #ifdef ESP32C6 336 #define RTC_CNTL_WDTCONFIG0_REG (DR_REG_LP_WDT_BASE + 0x0) // LP_WDT_RWDT_CONFIG0_REG 337 #define RTC_CNTL_WDTWPROTECT_REG (DR_REG_LP_WDT_BASE + 0x0018) // LP_WDT_RWDT_WPROTECT_REG 338 #endif 339 340 #ifdef ESP32H2 341 #define RTC_CNTL_WDTCONFIG0_REG (DR_REG_LP_WDT_BASE + 0x0) // LP_WDT_RWDT_CONFIG0_REG 342 #define RTC_CNTL_WDTWPROTECT_REG (DR_REG_LP_WDT_BASE + 0x0018) // LP_WDT_RWDT_WPROTECT_REG 343 #endif 344 345 #define RTC_CNTL_WDT_WKEY 0x50D83AA1 346 #define RTC_CNTL_FORCE_DOWNLOAD_BOOT (1 << 0) 347 348 /********************************************************** 349 * SYSTEM registers 350 */ 351 352 #ifdef ESP32S3 353 #define SYSTEM_CPU_PER_CONF_REG (SYSTEM_BASE_REG + 0x010) 354 #define SYSTEM_CPUPERIOD_SEL_M ((SYSTEM_CPUPERIOD_SEL_V)<<(SYSTEM_CPUPERIOD_SEL_S)) 355 #define SYSTEM_CPUPERIOD_SEL_V 0x3 356 #define SYSTEM_CPUPERIOD_SEL_S 0 357 #define SYSTEM_CPUPERIOD_MAX 2 // CPU_CLK frequency is 240 MHz 358 359 #define SYSTEM_SYSCLK_CONF_REG (SYSTEM_BASE_REG + 0x060) 360 #define SYSTEM_SOC_CLK_SEL_M ((SYSTEM_SOC_CLK_SEL_V)<<(SYSTEM_SOC_CLK_SEL_S)) 361 #define SYSTEM_SOC_CLK_SEL_V 0x3 362 #define SYSTEM_SOC_CLK_SEL_S 10 363 #define SYSTEM_SOC_CLK_MAX 1 364 #endif // ESP32S3 365 366 #ifdef ESP32C3 367 #define SYSTEM_CPU_PER_CONF_REG (SYSTEM_BASE_REG + 0x008) 368 #define SYSTEM_CPUPERIOD_SEL_M ((SYSTEM_CPUPERIOD_SEL_V)<<(SYSTEM_CPUPERIOD_SEL_S)) 369 #define SYSTEM_CPUPERIOD_SEL_V 0x3 370 #define SYSTEM_CPUPERIOD_SEL_S 0 371 #define SYSTEM_CPUPERIOD_MAX 1 // CPU_CLK frequency is 160 MHz 372 373 #define SYSTEM_SYSCLK_CONF_REG (SYSTEM_BASE_REG + 0x058) 374 #define SYSTEM_SOC_CLK_SEL_M ((SYSTEM_SOC_CLK_SEL_V)<<(SYSTEM_SOC_CLK_SEL_S)) 375 #define SYSTEM_SOC_CLK_SEL_V 0x3 376 #define SYSTEM_SOC_CLK_SEL_S 10 377 #define SYSTEM_SOC_CLK_MAX 1 378 #endif // ESP32C3 379 380 #ifdef ESP32S2 381 #define SYSTEM_CPU_PER_CONF_REG (SYSTEM_BASE_REG + 0x018) 382 #define SYSTEM_CPUPERIOD_SEL_M ((SYSTEM_CPUPERIOD_SEL_V)<<(SYSTEM_CPUPERIOD_SEL_S)) 383 #define SYSTEM_CPUPERIOD_SEL_V 0x3 384 #define SYSTEM_CPUPERIOD_SEL_S 0 385 #define SYSTEM_CPUPERIOD_MAX 2 // CPU_CLK frequency is 240 MHz 386 387 #define SYSTEM_SYSCLK_CONF_REG (SYSTEM_BASE_REG + 0x08C) 388 #define SYSTEM_SOC_CLK_SEL_M ((SYSTEM_SOC_CLK_SEL_V)<<(SYSTEM_SOC_CLK_SEL_S)) 389 #define SYSTEM_SOC_CLK_SEL_V 0x3 390 #define SYSTEM_SOC_CLK_SEL_S 10 391 #define SYSTEM_SOC_CLK_MAX 1 392 #endif // ESP32S2 393 394 #ifdef ESP32C6 395 #define PCR_SYSCLK_CONF_REG (DR_REG_PCR_BASE + 0x110) 396 #define PCR_SOC_CLK_SEL_M ((PCR_SOC_CLK_SEL_V)<<(PCR_SOC_CLK_SEL_S)) 397 #define PCR_SOC_CLK_SEL_V 0x3 398 #define PCR_SOC_CLK_SEL_S 16 399 #define PCR_SOC_CLK_MAX 1 // CPU_CLK frequency is 160 MHz (source is PLL_CLK) 400 #endif // ESP32C6 401 402 #ifdef ESP32H2 403 #define PCR_SYSCLK_CONF_REG (DR_REG_PCR_BASE + 0x10c) 404 #define PCR_SOC_CLK_SEL_M ((PCR_SOC_CLK_SEL_V)<<(PCR_SOC_CLK_SEL_S)) 405 #define PCR_SOC_CLK_SEL_V 0x3 406 #define PCR_SOC_CLK_SEL_S 16 407 #define PCR_SOC_CLK_MAX 1 // CPU_CLK frequency is 160 MHz (source is PLL_CLK) 408 #endif // ESP32C6 409 410 /********************************************************** 411 * Per-SOC security info buffer size 412 */ 413 414 #ifdef ESP32S2 415 #define SECURITY_INFO_BYTES 12 /* doesn't include chip_id and api_version */ 416 #endif // ESP32S2 417 418 #if ESP32S3_OR_LATER 419 #define SECURITY_INFO_BYTES 20 420 #endif // ESP32S3_OR_LATER 421
