1 /** @file mlan_sdio_defs.h 2 * 3 * @brief This file contains definitions for SDIO interface. 4 * 5 * Copyright 2022-2024 NXP 6 * 7 * SPDX-License-Identifier: BSD-3-Clause 8 * 9 */ 10 /**************************************************** 11 Change log: 12 ****************************************************/ 13 14 #ifndef _MLAN_SDIO_DEFS_H 15 #define _MLAN_SDIO_DEFS_H 16 17 #include <wifi_config_default.h> 18 19 /** Block mode */ 20 #define BLOCK_MODE 1 21 /** Fixed address mode */ 22 #define FIXED_ADDRESS 0 23 24 /* Host Control Registers */ 25 /** Host Control Registers : Host to Card Event */ 26 #define HOST_TO_CARD_EVENT_REG 0x00 27 /** Host Control Registers : Host terminates Command 53 */ 28 #define HOST_TERM_CMD53 (0x1U << 2) 29 /** Host Control Registers : Host without Command 53 finish host */ 30 #define HOST_WO_CMD53_FINISH_HOST (0x1U << 2) 31 /** Host Control Registers : Host power up */ 32 #define HOST_POWER_UP (0x1U << 1) 33 /** Host Control Registers : Host power down */ 34 #define HOST_POWER_DOWN (0x1U << 0) 35 36 #if defined(SD8801) 37 /** Host Control Registers : Host interrupt RSR */ 38 #define HOST_INT_RSR_REG 0x01 39 #define HOST_INT_RSR_MASK 0x3F 40 /** Host Control Registers : Host interrupt mask */ 41 #define HOST_INT_MASK_REG 0x02 42 #elif defined(SD8978) || defined(SD8987) || defined(SD8997) || defined(SD9097) || defined(SD9098) || defined(SD9177) 43 /** Host Control Registers : Host interrupt RSR */ 44 #define HOST_INT_RSR_REG 0x04 45 #define HOST_INT_RSR_MASK 0xFF 46 /** Host Control Registers : Host interrupt mask */ 47 #define HOST_INT_MASK_REG 0x08 48 #endif 49 50 /** Host Control Registers : Upload host interrupt RSR */ 51 #define UP_LD_HOST_INT_RSR (0x1U) 52 /** Host Control Registers : Upload host interrupt mask */ 53 #define UP_LD_HOST_INT_MASK (0x1U) 54 /** Host Control Registers : Download host interrupt mask */ 55 #define DN_LD_HOST_INT_MASK (0x2U) 56 57 #if defined(SD8978) || defined(SD8987) || defined(SD8997) || defined(SD9097) || defined(SD9098) || defined(SD9177) 58 /** Host Control Registers : Cmd port upload interrupt mask */ 59 #define CMD_PORT_UPLD_INT_MASK (0x1U << 6) 60 /** Host Control Registers : Cmd port download interrupt mask */ 61 #define CMD_PORT_DNLD_INT_MASK (0x1U << 7) 62 /** Enable Host interrupt mask */ 63 #define HIM_ENABLE (UP_LD_HOST_INT_MASK | DN_LD_HOST_INT_MASK | CMD_PORT_UPLD_INT_MASK | CMD_PORT_DNLD_INT_MASK) 64 #elif defined(SD8801) 65 /** Enable Host interrupt mask */ 66 #define HIM_ENABLE (UP_LD_HOST_INT_MASK | DN_LD_HOST_INT_MASK) 67 #endif 68 69 /** Disable Host interrupt mask */ 70 #define HIM_DISABLE 0xff 71 72 #if defined(SD8978) || defined(SD8987) || defined(SD8997) || defined(SD9097) || defined(SD9098) || defined(SD9177) 73 /** Host Control Registers : Host interrupt status */ 74 #define HOST_INT_STATUS_REG 0x0C 75 /** Host Control Registers : Upload command port host interrupt status */ 76 #define UP_LD_CMD_PORT_HOST_INT_STATUS (0x40U) 77 /** Host Control Registers : Download command port host interrupt status */ 78 #define DN_LD_CMD_PORT_HOST_INT_STATUS (0x80U) 79 #elif defined(SD8801) 80 #define HOST_INT_STATUS_REG 0x03 81 #endif 82 83 /** Host Control Registers : Upload host interrupt status */ 84 #define UP_LD_HOST_INT_STATUS (0x1U) 85 /** Host Control Registers : Download host interrupt status */ 86 #define DN_LD_HOST_INT_STATUS (0x2U) 87 88 #define WLAN_VALUE1 0x80002080U 89 /** Port for registers */ 90 #define REG_PORT 0U 91 92 #if defined(SD8978) || defined(SD8987) || defined(SD8997) || defined(SD9097) || defined(SD9098) || defined(SD9177) 93 /** Port for memory */ 94 #define MEM_PORT 0x10000 95 /** LSB of read bitmap */ 96 #define RD_BITMAP_L 0x10 97 /** MSB of read bitmap */ 98 #define RD_BITMAP_U 0x11 99 /** LSB of read bitmap second word */ 100 #define RD_BITMAP_1L 0x12 101 /** MSB of read bitmap second word */ 102 #define RD_BITMAP_1U 0x13 103 /** LSB of write bitmap */ 104 #define WR_BITMAP_L 0x14 105 /** MSB of write bitmap */ 106 #define WR_BITMAP_U 0x15 107 /** LSB of write bitmap second word */ 108 #define WR_BITMAP_1L 0x16 109 /** MSB of write bitmap second word */ 110 #define WR_BITMAP_1U 0x17 111 /** LSB of read length for port 0 */ 112 #define RD_LEN_P0_L 0x18 113 /** MSB of read length for port 0 */ 114 #define RD_LEN_P0_U 0x19 115 #elif defined(SD8801) 116 /** LSB of read bitmap */ 117 #define RD_BITMAP_L 0x04 118 /** MSB of read bitmap */ 119 #define RD_BITMAP_U 0x05 120 /** LSB of write bitmap */ 121 #define WR_BITMAP_L 0x06 122 /** MSB of write bitmap */ 123 #define WR_BITMAP_U 0x07 124 /** LSB of read length for port 0 */ 125 #define RD_LEN_P0_L 0x08 126 /** MSB of read length for port 0 */ 127 #define RD_LEN_P0_U 0x09 128 #endif 129 130 #if defined(SD8978) || defined(SD8987) || defined(SD8997) || defined(SD9097) || defined(SD9098) || defined(SD9177) 131 /* Card Control Registers : Command port read length 0 */ 132 #define CMD_RD_LEN_0 0xC0 133 /* Card Control Registers : Command port read length 1 */ 134 #define CMD_RD_LEN_1 0xC1 135 /* Card Control Registers : Command port read length 2 (reserved) */ 136 #define CMD_RD_LEN_2 0xC2 137 /* Card Control Registers : Command port read length 3 */ 138 #define CMD_RD_LEN_3 0xC3 139 /* Card Control Registers : Command port configuration 0 */ 140 #define CMD_CONFIG_0 0xC4 141 #define CMD_PORT_RD_LEN_EN (0x1U << 2) 142 /* Card Control Registers : Command port configuration 1 */ 143 #define CMD_CONFIG_1 0xC5 144 /* Card Control Registers : cmd port auto enable */ 145 #define CMD_PORT_AUTO_EN (0x1U << 0) 146 /* Card Control Registers : Command port configuration 2 (reserved) */ 147 #define CMD_CONFIG_2 0xC6 148 /* Card Control Registers : Command port configuration 3 (reserved) */ 149 #define CMD_CONFIG_3 0xC7 150 151 /* Command port */ 152 #define CMD_PORT_SLCT 0x8000U 153 /** Data port mask */ 154 #define DATA_PORT_MASK 0xffffffffU 155 #endif /* SD8987 SD8997 SD9097 SD9098 SD9177*/ 156 157 #if defined(SD8801) 158 /** Ctrl port */ 159 #define CTRL_PORT 0 160 /** Ctrl port mask */ 161 #define CTRL_PORT_MASK 0x0001 162 /** Data port mask */ 163 #define DATA_PORT_MASK 0xfffe 164 #endif /* SD8801 */ 165 /** Ctrl port mask */ 166 // #define CTRL_PORT_MASK 0x00000001 167 /** Data port mask */ 168 // #define DATA_PORT_MASK 0xfffffffe 169 /** Misc. Config Register : Auto Re-enable interrupts */ 170 #define AUTO_RE_ENABLE_INT (0x1U << 4) 171 172 #if defined(SD8801) 173 /** Host Control Registers : Host transfer status */ 174 #define HOST_RESTART_REG 0x28 175 #elif defined(SD8978) || defined(SD8987) || defined(SD8997) || defined(SD9097) || defined(SD9098) || defined(SD9177) 176 /** Host Control Registers : Host transfer status */ 177 #define HOST_RESTART_REG 0x58 178 #endif 179 180 /** Host Control Registers : Download CRC error */ 181 #define DN_LD_CRC_ERR (0x1U << 2) 182 /** Host Control Registers : Upload restart */ 183 #define UP_LD_RESTART (0x1U << 1) 184 /** Host Control Registers : Download restart */ 185 #define DN_LD_RESTART (0x1U << 0) 186 187 /* Card Control Registers */ 188 #if defined(SD8978) || defined(SD8987) || defined(SD8997) || defined(SD9097) || defined(SD9098) || defined(SD9177) 189 /** Card Control Registers : Card to host event */ 190 #define CARD_TO_HOST_EVENT_REG 0x5C 191 /** Card Control Registers : Command port upload ready */ 192 #define UP_LD_CP_RDY (0x1U << 6) 193 /** Card Control Registers : Command port download ready */ 194 #define DN_LD_CP_RDY (0x1U << 7) 195 #endif /* SD8987 SD8997 SD9097 SD9098 SD9177 */ 196 197 #if defined(SD8801) 198 /** Card Control Registers : Card to host event */ 199 #define CARD_TO_HOST_EVENT_REG 0x30 200 #endif /* SD8801 */ 201 202 /** Card Control Registers : Card I/O ready */ 203 #define CARD_IO_READY (0x1U << 3) 204 /** Card Control Registers : CIS card ready */ 205 #define CIS_CARD_RDY (0x1U << 2) 206 /** Card Control Registers : Upload card ready */ 207 #define UP_LD_CARD_RDY (0x1U << 1) 208 /** Card Control Registers : Download card ready */ 209 #define DN_LD_CARD_RDY (0x1U << 0) 210 211 #if defined(SD8801) 212 /** Card Control Registers : Host interrupt mask register */ 213 #define HOST_INTERRUPT_MASK_REG 0x34 214 #elif defined(SD8978) || defined(SD8987) || defined(SD8997) || defined(SD9097) || defined(SD9098) || defined(SD9177) 215 /** Card Control Registers : Host interrupt mask register */ 216 #define HOST_INTERRUPT_MASK_REG 0x60 217 #endif 218 219 /** Card Control Registers : Host power interrupt mask */ 220 #define HOST_POWER_INT_MASK (0x1U << 3) 221 /** Card Control Registers : Abort card interrupt mask */ 222 #define ABORT_CARD_INT_MASK (0x1U << 2) 223 /** Card Control Registers : Upload card interrupt mask */ 224 #define UP_LD_CARD_INT_MASK (0x1U << 1) 225 /** Card Control Registers : Download card interrupt mask */ 226 #define DN_LD_CARD_INT_MASK (0x1U << 0) 227 228 #if defined(SD8801) 229 /** Card Control Registers : Card interrupt status register */ 230 #define CARD_INTERRUPT_STATUS_REG 0x38 231 #elif defined(SD8978) || defined(SD8987) || defined(SD8997) || defined(SD9097) || defined(SD9098) || defined(SD9177) 232 /** Card Control Registers : Card interrupt status register */ 233 #define CARD_INTERRUPT_STATUS_REG 0x64 234 #endif 235 236 /** Card Control Registers : Power up interrupt */ 237 #define POWER_UP_INT (0x1U << 4) 238 /** Card Control Registers : Power down interrupt */ 239 #define POWER_DOWN_INT (0x1U << 3) 240 241 #if defined(SD8801) 242 /** Card Control Registers : Card interrupt RSR register */ 243 #define CARD_INTERRUPT_RSR_REG 0x3c 244 #elif defined(SD8978) || defined(SD8987) || defined(SD8997) || defined(SD9097) || defined(SD9098) || defined(SD9177) 245 /** Card Control Registers : Card interrupt RSR register */ 246 #define CARD_INTERRUPT_RSR_REG 0x68 247 #endif 248 249 /** Card Control Registers : Power up RSR */ 250 #define POWER_UP_RSR (0x1U << 4) 251 /** Card Control Registers : Power down RSR */ 252 #define POWER_DOWN_RSR (0x1U << 3) 253 254 #if defined(SD8978) || defined(SD8987) || defined(SD8997) || defined(SD9097) || defined(SD9098) || defined(SD9177) 255 /** Card Control Registers : SQ Read base address 0 register */ 256 #define READ_BASE_0_REG 0xf8 257 /** Card Control Registers : SQ Read base address 1 register */ 258 #define READ_BASE_1_REG 0xf9 259 /** Enable GPIO-1 as a duplicated signal of interrupt as appear of SDIO_DAT1*/ 260 #define ENABLE_GPIO_1_INT_MODE 0x88 261 /** Scratch reg 3 2 : Configure GPIO-1 INT*/ 262 #define SCRATCH_REG_32 0xEE 263 #elif defined(SD8801) 264 /** Card Control Registers : SQ Read base address 0 register */ 265 #define READ_BASE_0_REG 0x40 266 /** Card Control Registers : SQ Read base address 1 register */ 267 #define READ_BASE_1_REG 0x41 268 #endif 269 270 #if defined(SD8978) || defined(SD8987) || defined(SD8997) || defined(SD9097) || defined(SD9098) || defined(SD9177) 271 /** Card Control Registers : Card revision register */ 272 #define CARD_REVISION_REG 0xC8 273 274 /** Firmware status 0 register (SCRATCH0_0) */ 275 #define CARD_FW_STATUS0_REG 0xe8 276 /** Firmware status 1 register (SCRATCH0_1) */ 277 #define CARD_FW_STATUS1_REG 0xe9 278 /** Rx length register (SCRATCH0_2) */ 279 #define CARD_RX_LEN_REG 0xea 280 /** Rx unit register (SCRATCH0_3) */ 281 #define CARD_RX_UNIT_REG 0xeb 282 283 #if (CONFIG_WIFI_IND_DNLD) 284 #if defined(SD8978) || defined(SD8987) || defined(SD9177) 285 /** Firmware reset register */ 286 #define CARD_FW_RESET_REG 0xEE 287 /** Firmware reset val */ 288 #define CARD_FW_RESET_VAL 0x99 289 #endif 290 #endif 291 292 /** Card Control Registers : Card OCR 0 register */ 293 #define CARD_OCR_0_REG 0xD4 294 /** Card Control Registers : Card OCR 1 register */ 295 #define CARD_OCR_1_REG 0xD5 296 /** Card Control Registers : Card OCR 3 register */ 297 #define CARD_OCR_3_REG 0xD6 298 /** Card Control Registers : Card config register */ 299 #define CARD_CONFIG_REG 0xD7 300 /** Card Control Registers : Miscellaneous Configuration Register */ 301 #define CARD_MISC_CFG_REG 0xD8 302 303 /** Card Control Registers : sdio new mode register 1 */ 304 #define CARD_CONFIG_2_1_REG 0xD9 305 /** Card Control Registers : cmd53 new mode */ 306 #define CMD53_NEW_MODE (0x1U << 0) 307 /** Card Control Registers : cmd53 tx len format 1 (0x10) */ 308 #define CMD53_TX_LEN_FORMAT_1 (0x1U << 4) 309 /** Card Control Registers : cmd53 tx len format 2 (0x20)*/ 310 #define CMD53_TX_LEN_FORMAT_2 (0x1U << 5) 311 /** Card Control Registers : cmd53 rx len format 1 (0x40) */ 312 #define CMD53_RX_LEN_FORMAT_1 (0x1U << 6) 313 /** Card Control Registers : cmd53 rx len format 2 (0x80)*/ 314 #define CMD53_RX_LEN_FORMAT_2 (0x1U << 7) 315 316 /** Card Control Registers : sdio new mode register 2 */ 317 #define CARD_CONFIG_2_2_REG 0xDA 318 /** Card Control Registers : test data out (0x01) */ 319 #define TEST_DATA_OUT_1 (0x1U << 0) 320 /** Card Control Registers : test data out (0x02) */ 321 #define TEST_DATA_OUT_2 (0x1U << 1) 322 /** Card Control Registers : test data out (0x04) */ 323 #define TEST_DATA_OUT_3 (0x1U << 2) 324 /** Card Control Registers : test data out (0x08) */ 325 #define TEST_DATA_OUT_4 (0x1U << 3) 326 /** Card Control Registers : test cmd out (0x10) */ 327 #define TEST_CMD_OUT (0x1U << 4) 328 329 /** Card Control Registers : sdio new mode register 3 */ 330 #define CARD_CONFIG_2_3_REG 0xDB 331 /** Card Control Registers : test data enable (0x01) */ 332 #define TEST_DATA_EN_1 (0x1U << 0) 333 /** Card Control Registers : test data enable (0x02) */ 334 #define TEST_DATA_EN_2 (0x1U << 1) 335 /** Card Control Registers : test data enable (0x04) */ 336 #define TEST_DATA_EN_3 (0x1U << 2) 337 /** Card Control Registers : test data enable (0x08) */ 338 #define TEST_DATA_EN_4 (0x1U << 3) 339 /** Card Control Registers : test cmd enable (0x10) */ 340 #define TEST_CMD_EN (0x1U << 4) 341 /** Card Control Registers : test mode (0x20) */ 342 #define TEST_MODE (0x1U << 5) 343 #elif defined(SD8801) 344 /** Card Control Registers : Card revision register */ 345 #define CARD_REVISION_REG 0x5c 346 347 /** Firmware status 0 register (SCRATCH0_0) */ 348 #define CARD_FW_STATUS0_REG 0x60 349 /** Firmware status 1 register (SCRATCH0_1) */ 350 #define CARD_FW_STATUS1_REG 0x61 351 /** Rx length register (SCRATCH0_2) */ 352 #define CARD_RX_LEN_REG 0x62 353 /** Rx unit register (SCRATCH0_3) */ 354 #define CARD_RX_UNIT_REG 0x63 355 356 #if (CONFIG_WIFI_IND_DNLD) 357 /** Firmware reset register */ 358 #define CARD_FW_RESET_REG 0x64 359 /** Firmware reset register */ 360 #define CARD_FW_RESET_VAL 0x00 361 #endif 362 363 /** Card Control Registers : Card OCR 0 register */ 364 #define CARD_OCR_0_REG 0x68 365 /** Card Control Registers : Card OCR 1 register */ 366 #define CARD_OCR_1_REG 0x69 367 /** Card Control Registers : Card OCR 3 register */ 368 #define CARD_OCR_3_REG 0x6A 369 /** Card Control Registers : Card config register */ 370 #define CARD_CONFIG_REG 0x6B 371 /** Card Control Registers : Miscellaneous Configuration Register */ 372 #define CARD_MISC_CFG_REG 0x6C 373 #endif 374 375 #if defined(SD8978) || defined(SD8987) || defined(SD8997) || defined(SD9097) || defined(SD9098) || defined(SD9177) 376 /** Card Control Registers : Debug 0 register */ 377 #define DEBUG_0_REG 0xDC 378 /** Card Control Registers : SD test BUS 0 */ 379 #define SD_TESTBUS0 (0x1U) 380 /** Card Control Registers : Debug 1 register */ 381 #define DEBUG_1_REG 0xDD 382 /** Card Control Registers : SD test BUS 1 */ 383 #define SD_TESTBUS1 (0x1U) 384 /** Card Control Registers : Debug 2 register */ 385 #define DEBUG_2_REG 0xDE 386 /** Card Control Registers : SD test BUS 2 */ 387 #define SD_TESTBUS2 (0x1U) 388 /** Card Control Registers : Debug 3 register */ 389 #define DEBUG_3_REG 0xDF 390 /** Card Control Registers : SD test BUS 3 */ 391 #define SD_TESTBUS3 (0x1U) 392 393 /** Host Control Registers : I/O port 0 */ 394 #define IO_PORT_0_REG 0xE4 395 /** Host Control Registers : I/O port 1 */ 396 #define IO_PORT_1_REG 0xE5 397 /** Host Control Registers : I/O port 2 */ 398 #define IO_PORT_2_REG 0xE6 399 #elif defined(SD8801) 400 /** Card Control Registers : Debug 0 register */ 401 #define DEBUG_0_REG 0x70 402 /** Card Control Registers : SD test BUS 0 */ 403 #define SD_TESTBUS0 (0x1U) 404 /** Card Control Registers : Debug 1 register */ 405 #define DEBUG_1_REG 0x71 406 /** Card Control Registers : SD test BUS 1 */ 407 #define SD_TESTBUS1 (0x1U) 408 /** Card Control Registers : Debug 2 register */ 409 #define DEBUG_2_REG 0x72 410 /** Card Control Registers : SD test BUS 2 */ 411 #define SD_TESTBUS2 (0x1U) 412 /** Card Control Registers : Debug 3 register */ 413 #define DEBUG_3_REG 0x73 414 /** Card Control Registers : SD test BUS 3 */ 415 #define SD_TESTBUS3 (0x1U) 416 417 /** Host Control Registers : I/O port 0 */ 418 #define IO_PORT_0_REG 0x78 419 /** Host Control Registers : I/O port 1 */ 420 #define IO_PORT_1_REG 0x79 421 /** Host Control Registers : I/O port 2 */ 422 #define IO_PORT_2_REG 0x7A 423 #endif 424 425 #endif /* _MLAN_SDIO_DEFS_H */ 426
