1 /* STELLARIS Ethernet Controller 2 * 3 * Copyright (c) 2018 Zilogic Systems 4 * 5 * SPDX-License-Identifier: Apache-2.0 6 */ 7 8 #ifndef ETH_STELLARIS_PRIV_H_ 9 #define ETH_STELLARIS_PRIV_H_ 10 11 #define DEV_DATA(dev) \ 12 ((struct eth_stellaris_runtime *)(dev)->data) 13 #define DEV_CFG(dev) \ 14 ((const struct eth_stellaris_config *const)(dev)->config) 15 /* 16 * Register mapping 17 */ 18 /* Registers for ethernet system, mac_base + offset */ 19 #define REG_MACRIS ((DEV_CFG(dev)->mac_base) + 0x000) 20 #define REG_MACIM ((DEV_CFG(dev)->mac_base) + 0x004) 21 #define REG_MACRCTL ((DEV_CFG(dev)->mac_base) + 0x008) 22 #define REG_MACTCTL ((DEV_CFG(dev)->mac_base) + 0x00C) 23 #define REG_MACDATA ((DEV_CFG(dev)->mac_base) + 0x010) 24 #define REG_MACIA0 ((DEV_CFG(dev)->mac_base) + 0x014) 25 #define REG_MACIA1 ((DEV_CFG(dev)->mac_base) + 0x018) 26 #define REG_MACNP ((DEV_CFG(dev)->mac_base) + 0x034) 27 #define REG_MACTR ((DEV_CFG(dev)->mac_base) + 0x038) 28 29 /* ETH MAC Receive Control bit fields set value */ 30 #define BIT_MACRCTL_RSTFIFO 0x10 31 #define BIT_MACRCTL_BADCRC 0x8 32 #define BIT_MACRCTL_RXEN 0x1 33 #define BIT_MACRCTL_PRMS 0x4 34 35 /* ETH MAC Transmit Control bit fields set value */ 36 #define BIT_MACTCTL_DUPLEX 0x10 37 #define BIT_MACTCTL_CRC 0x4 38 #define BIT_MACTCTL_PADEN 0x2 39 #define BIT_MACTCTL_TXEN 0x1 40 41 /* ETH MAC Txn req bit fields set value */ 42 #define BIT_MACTR_NEWTX 0x1 43 44 /* Ethernet MAC RAW Interrupt Status/Ack bit set values */ 45 #define BIT_MACRIS_RXINT 0x1 46 #define BIT_MACRIS_TXER 0x2 47 #define BIT_MACRIS_TXEMP 0x4 48 #define BIT_MACRIS_FOV 0x8 49 #define BIT_MACRIS_RXER 0x10 50 51 struct eth_stellaris_runtime { 52 struct net_if *iface; 53 uint8_t mac_addr[6]; 54 struct k_sem tx_sem; 55 bool tx_err; 56 uint32_t tx_word; 57 int tx_pos; 58 #if defined(CONFIG_NET_STATISTICS_ETHERNET) 59 struct net_stats_eth stats; 60 #endif 61 }; 62 63 typedef void (*eth_stellaris_config_irq_t)(const struct device *dev); 64 65 struct eth_stellaris_config { 66 uint32_t mac_base; 67 uint32_t sys_ctrl_base; 68 uint32_t irq_num; 69 eth_stellaris_config_irq_t config_func; 70 }; 71 72 #endif /* ETH_STELLARIS_PRIV_H_ */ 73
