1 //***************************************************************************** 2 // 3 // am_reg_base_addresses.h 4 //! @file am_reg_base_addresses.h 5 //! 6 //! @brief Register defines for all module base addresses 7 // 8 //***************************************************************************** 9 10 //***************************************************************************** 11 // 12 // Copyright (c) 2023, Ambiq Micro, Inc. 13 // All rights reserved. 14 // 15 // Redistribution and use in source and binary forms, with or without 16 // modification, are permitted provided that the following conditions are met: 17 // 18 // 1. Redistributions of source code must retain the above copyright notice, 19 // this list of conditions and the following disclaimer. 20 // 21 // 2. Redistributions in binary form must reproduce the above copyright 22 // notice, this list of conditions and the following disclaimer in the 23 // documentation and/or other materials provided with the distribution. 24 // 25 // 3. Neither the name of the copyright holder nor the names of its 26 // contributors may be used to endorse or promote products derived from this 27 // software without specific prior written permission. 28 // 29 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 30 // AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 31 // IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 32 // ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 33 // LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 34 // CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 35 // SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 36 // INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 37 // CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 38 // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 39 // POSSIBILITY OF SUCH DAMAGE. 40 // 41 // This is part of revision release_sdk_4_4_0-3c5977e664 of the AmbiqSuite Development Package. 42 // 43 //***************************************************************************** 44 #ifndef AM_REG_BASE_ADDRESSES_H 45 #define AM_REG_BASE_ADDRESSES_H 46 47 #include "stdint.h" 48 49 // 50 // ARM standard register space (needed for macros) 51 // 52 #define REG_ITM_BASEADDR (0x00000000UL) 53 #define REG_JEDEC_BASEADDR (0x00000000UL) 54 #define REG_NVIC_BASEADDR (0x00000000UL) 55 #define REG_SYSCTRL_BASEADDR (0x00000000UL) 56 #define REG_SYSTICK_BASEADDR (0x00000000UL) 57 #define REG_TPIU_BASEADDR (0x00000000UL) 58 59 // 60 // Peripheral register space 61 // 62 #define REG_ADC_BASEADDR (0x40038000UL) 63 #define REG_APBDMA_BASEADDR (0x51000000UL) 64 #define REG_AUDADC_BASEADDR (0x40210000UL) 65 #define REG_CLKGEN_BASEADDR (0x40004000UL) 66 #define REG_CPU_BASEADDR (0x48000000UL) 67 #define REG_DC_BASEADDR (0x400A0000UL) 68 #define REG_DSI_BASEADDR (0x400A8000UL) 69 #define REG_DSP_BASEADDR (0x40100000UL) 70 #define REG_DSPI2S_BASEADDR (0x50428000UL) 71 #define REG_DSPTIMER_BASEADDR (0x40087000UL) 72 #define REG_FPIO_BASEADDR (0x40010800UL) 73 #define REG_GPIO_BASEADDR (0x40010000UL) 74 #define REG_GPU_BASEADDR (0x40090000UL) 75 #define REG_IOM_BASEADDR (0x40050000UL) 76 #define REG_IOSLAVE_BASEADDR (0x40034000UL) 77 #define REG_MCUCTRL_BASEADDR (0x40020000UL) 78 #define REG_MRAM_BASEADDR (0x40014000UL) 79 #define REG_MSPI_BASEADDR (0x40060000UL) 80 #define REG_PDM_BASEADDR (0x50401000UL) 81 #define REG_PWRCTRL_BASEADDR (0x40021000UL) 82 #define REG_RSTGEN_BASEADDR (0x40000000UL) 83 #define REG_RTC_BASEADDR (0x40004800UL) 84 #define REG_SECURITY_BASEADDR (0x40030000UL) 85 #define REG_STIMER_BASEADDR (0x40008800UL) 86 #define REG_TIMER_BASEADDR (0x40008000UL) 87 #define REG_UART_BASEADDR (0x4001C000UL) 88 #define REG_VCOMP_BASEADDR (0x4000C000UL) 89 #define REG_WDT_BASEADDR (0x40024000UL) 90 91 // **************************************************************************** 92 // RAM Memory Map: 93 // TCM: 384KB 0x10000000 - 0x1005FFFF 94 // Shared System SRAM (SSRAM): 1024KB 0x10060000 - 0x1015FFFF 95 // Extended RAM: 384KB 0x10160000 - 0x101BFFFF 96 // Shared System SRAM (SSRAM): 1024KB 0x101C0000 - 0x102BFFFF 97 // **************************************************************************** 98 // 99 // TCM address space 100 // 101 #define SRAM_BASEADDR (0x10000000UL) 102 #define TCM_BASEADDR SRAM_BASEADDR 103 #define TCM_MAX_SIZE (384UL * 1024UL) 104 105 // 106 // The two non-contiguous SSRAM spaces are referred to as SSRAM0 and SSRAM1. 107 // SSRAM0 address space. 108 // 109 #define SSRAM0_BASEADDR (SRAM_BASEADDR + TCM_MAX_SIZE) 110 #define SSRAM0_MAX_SIZE (1024UL * 1024UL) 111 112 // 113 // Extended RAM address space. 114 // DSP0 layout is exactly as Apollo4b. DSP1RAMs were replaced in Apollo4p with SSRAM1. 115 // 116 #define EXTRAM_BASEADDR (SSRAM0_BASEADDR + SSRAM0_MAX_SIZE) 117 #define DSP0IRAM_BASEADDR EXTRAM_BASEADDR 118 #define DSP0IRAM_MAX_SIZE (128UL * 1024UL) 119 #define DSP0DRAM_BASEADDR (DSP0IRAM_BASEADDR + DSP0IRAM_MAX_SIZE) 120 #define DSP0DRAM_MAX_SIZE (256UL * 1024UL) 121 #define EXTRAM_MAX_SIZE (DSP0IRAM_MAX_SIZE + DSP0DRAM_MAX_SIZE) 122 123 // 124 // SSRAM1 address space 125 // 126 #define SSRAM1_BASEADDR (EXTRAM_BASEADDR + EXTRAM_MAX_SIZE) 127 #define SSRAM1_MAX_SIZE (1024UL * 1024UL) 128 129 // 130 // RAM sizes. 131 // NONTCM_MAX_SIZE is the total of contiguous RAM after TCM (mix of SSRAM and Extended) 132 // SSRAM_MAX_SIZE is the total of Shared System RAM, but is not necessarily contiguous. 133 // RAM_TOTAL_SIZE is the grand total of all contiguous RAM. 134 // 135 #define SSRAM_MAX_SIZE (SSRAM0_MAX_SIZE + SSRAM1_MAX_SIZE) 136 #define NONTCM_MAX_SIZE (EXTRAM_MAX_SIZE + SSRAM_MAX_SIZE) 137 #define RAM_TOTAL_SIZE (TCM_MAX_SIZE + NONTCM_MAX_SIZE) 138 139 // **************************************************************************** 140 // MRAM Address Space 141 // **************************************************************************** 142 #define MRAM_BASEADDR (0x00000000UL) 143 #define MRAM_MAX_SIZE (2048UL * 1024UL) 144 145 // 146 // MSPI Aperature address ranges 147 // 148 #define MSPI0_APERTURE_START_ADDR (0x14000000UL) 149 #define MSPI0_APERTURE_END_ADDR (0x18000000UL) 150 #define MSPI1_APERTURE_START_ADDR (0x18000000UL) 151 #define MSPI1_APERTURE_END_ADDR (0x1C000000UL) 152 #define MSPI2_APERTURE_START_ADDR (0x1C000000UL) 153 #define MSPI2_APERTURE_END_ADDR (0x20000000UL) 154 155 156 #endif // AM_REG_BASE_ADDRESSES_H 157 158
