| /trusted-firmware-a-latest/drivers/arm/gic/v3/ |
| D | gicv3_private.h | 29 #define BIT_NUM(REG, id) \ argument
38 #define GICD_OFFSET_8(REG, id) \ argument
43 #define GICD_OFFSET(REG, id) \ argument
49 #define GICD_OFFSET_64(REG, id) \ argument
56 #define GICD_OFFSET_8(REG, id) \ argument
59 #define GICD_OFFSET(REG, id) \ argument
62 #define GICD_OFFSET_64(REG, id) \ argument
70 #define GICD_READ(REG, base, id) \ argument
73 #define GICD_READ_64(REG, base, id) \ argument
76 #define GICD_WRITE_8(REG, base, id, val) \ argument
[all …]
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| D | gicv3_main.c | 51 #define RESTORE_GICD_REGS(base, ctx, intr_num, reg, REG) \ argument
61 #define SAVE_GICD_REGS(base, ctx, intr_num, reg, REG) \ argument
71 #define RESTORE_GICD_EREGS(base, ctx, intr_num, reg, REG) \ argument
82 #define SAVE_GICD_EREGS(base, ctx, intr_num, reg, REG) \ argument
92 #define SAVE_GICD_EREGS(base, ctx, intr_num, reg, REG) argument
93 #define RESTORE_GICD_EREGS(base, ctx, intr_num, reg, REG) argument
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| /trusted-firmware-a-latest/plat/mediatek/mt8195/drivers/apusys/ |
| D | apupwr_clkctl_def.h | 71 #define apupwr_writel(VAL, REG) mmio_write_32((uintptr_t)REG, VAL) argument
72 #define apupwr_writel_relax(VAL, REG) mmio_write_32_relax((uintptr_t)REG, VAL) argument
73 #define apupwr_readl(REG) mmio_read_32((uintptr_t)REG) argument
74 #define apupwr_clrbits(VAL, REG) mmio_clrbits_32((uintptr_t)REG, VAL) argument
75 #define apupwr_setbits(VAL, REG) mmio_setbits_32((uintptr_t)REG, VAL) argument
76 #define apupwr_clrsetbits(CLR_VAL, SET_VAL, REG) \ argument
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| /trusted-firmware-a-latest/plat/mediatek/mt8192/drivers/apusys/ |
| D | mtk_apusys_apc_def.h | 85 #define apuapc_writel(VAL, REG) mmio_write_32((uintptr_t)REG, VAL) argument
86 #define apuapc_readl(REG) mmio_read_32((uintptr_t)REG) argument
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| /trusted-firmware-a-latest/plat/mediatek/mt8192/drivers/devapc/ |
| D | devapc.h | 173 #define devapc_writel(VAL, REG) mmio_write_32((uintptr_t)REG, VAL) argument
174 #define devapc_readl(REG) mmio_read_32((uintptr_t)REG) argument
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