1 /*
2 * Copyright 2021 Basalte bv
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7 #define DT_DRV_COMPAT nxp_imx_flexspi_hyperram
8
9 #include <logging/log.h>
10 #include <sys/util.h>
11
12 #include "memc_mcux_flexspi.h"
13
14
15 /*
16 * NOTE: If CONFIG_FLASH_MCUX_FLEXSPI_XIP is selected, Any external functions
17 * called while interacting with the flexspi MUST be relocated to SRAM or ITCM
18 * at runtime, so that the chip does not access the flexspi to read program
19 * instructions while it is being written to
20 */
21 #if defined(CONFIG_FLASH_MCUX_FLEXSPI_XIP) && (CONFIG_MEMC_LOG_LEVEL > 0)
22 #warning "Enabling memc driver logging and XIP mode simultaneously can cause \
23 read-while-write hazards. This configuration is not recommended."
24 #endif
25
26 LOG_MODULE_REGISTER(memc_flexspi, CONFIG_MEMC_LOG_LEVEL);
27
28 enum {
29 READ_DATA,
30 WRITE_DATA,
31 READ_REG,
32 WRITE_REG,
33 };
34
35 struct memc_flexspi_hyperram_config {
36 char *controller_label;
37 flexspi_port_t port;
38 flexspi_device_config_t config;
39 };
40
41 struct memc_flexspi_hyperram_data {
42 const struct device *controller;
43 };
44
45 static const uint32_t memc_flexspi_hyperram_lut[][4] = {
46 /* Read Data */
47 [READ_DATA] = {
48 FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0xA0,
49 kFLEXSPI_Command_RADDR_DDR, kFLEXSPI_8PAD, 0x18),
50 FLEXSPI_LUT_SEQ(kFLEXSPI_Command_CADDR_DDR, kFLEXSPI_8PAD, 0x10,
51 kFLEXSPI_Command_DUMMY_RWDS_DDR, kFLEXSPI_8PAD, 0x06),
52 FLEXSPI_LUT_SEQ(kFLEXSPI_Command_READ_DDR, kFLEXSPI_8PAD, 0x04,
53 kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0x00),
54 },
55
56 /* Write Data */
57 [WRITE_DATA] = {
58 FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x20,
59 kFLEXSPI_Command_RADDR_DDR, kFLEXSPI_8PAD, 0x18),
60 FLEXSPI_LUT_SEQ(kFLEXSPI_Command_CADDR_DDR, kFLEXSPI_8PAD, 0x10,
61 kFLEXSPI_Command_DUMMY_RWDS_DDR, kFLEXSPI_8PAD, 0x06),
62 FLEXSPI_LUT_SEQ(kFLEXSPI_Command_WRITE_DDR, kFLEXSPI_8PAD, 0x04,
63 kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0x00),
64 },
65
66 /* Read Register */
67 [READ_REG] = {
68 FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0xE0,
69 kFLEXSPI_Command_RADDR_DDR, kFLEXSPI_8PAD, 0x18),
70 FLEXSPI_LUT_SEQ(kFLEXSPI_Command_CADDR_DDR, kFLEXSPI_8PAD, 0x10,
71 kFLEXSPI_Command_DUMMY_RWDS_DDR, kFLEXSPI_8PAD, 0x06),
72 FLEXSPI_LUT_SEQ(kFLEXSPI_Command_READ_DDR, kFLEXSPI_8PAD, 0x04,
73 kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0x00),
74 },
75
76 /* Write Register */
77 [WRITE_REG] = {
78 FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x60,
79 kFLEXSPI_Command_RADDR_DDR, kFLEXSPI_8PAD, 0x18),
80 FLEXSPI_LUT_SEQ(kFLEXSPI_Command_CADDR_DDR, kFLEXSPI_8PAD, 0x10,
81 kFLEXSPI_Command_DUMMY_RWDS_DDR, kFLEXSPI_8PAD, 0x06),
82 FLEXSPI_LUT_SEQ(kFLEXSPI_Command_WRITE_DDR, kFLEXSPI_8PAD, 0x04,
83 kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0x00),
84 },
85 };
86
memc_flexspi_hyperram_get_vendor_id(const struct device * dev,uint16_t * vendor_id)87 static int memc_flexspi_hyperram_get_vendor_id(const struct device *dev,
88 uint16_t *vendor_id)
89 {
90 const struct memc_flexspi_hyperram_config *config = dev->config;
91 struct memc_flexspi_hyperram_data *data = dev->data;
92 uint32_t buffer = 0;
93 int ret;
94
95 flexspi_transfer_t transfer = {
96 .deviceAddress = 0,
97 .port = config->port,
98 .cmdType = kFLEXSPI_Read,
99 .SeqNumber = 1,
100 .seqIndex = READ_REG,
101 .data = &buffer,
102 .dataSize = 4,
103 };
104
105 LOG_DBG("Reading id");
106
107 ret = memc_flexspi_transfer(data->controller, &transfer);
108 *vendor_id = buffer & 0xffff;
109
110 return ret;
111 }
112
memc_flexspi_hyperram_init(const struct device * dev)113 static int memc_flexspi_hyperram_init(const struct device *dev)
114 {
115 const struct memc_flexspi_hyperram_config *config = dev->config;
116 struct memc_flexspi_hyperram_data *data = dev->data;
117 uint16_t vendor_id;
118
119 data->controller = device_get_binding(config->controller_label);
120 if (data->controller == NULL) {
121 LOG_ERR("Could not find controller");
122 return -EINVAL;
123 }
124
125 if (memc_flexspi_set_device_config(data->controller, &config->config,
126 config->port)) {
127 LOG_ERR("Could not set device configuration");
128 return -EINVAL;
129 }
130
131 if (memc_flexspi_update_lut(data->controller, 0,
132 (const uint32_t *) memc_flexspi_hyperram_lut,
133 sizeof(memc_flexspi_hyperram_lut) / 4)) {
134 LOG_ERR("Could not update lut");
135 return -EINVAL;
136 }
137
138 memc_flexspi_reset(data->controller);
139
140 if (memc_flexspi_hyperram_get_vendor_id(dev, &vendor_id)) {
141 LOG_ERR("Could not read vendor id");
142 return -EIO;
143 }
144 LOG_DBG("Vendor id: 0x%0x", vendor_id);
145
146 return 0;
147 }
148
149 #define CONCAT3(x, y, z) x ## y ## z
150
151 #define CS_INTERVAL_UNIT(unit) \
152 CONCAT3(kFLEXSPI_CsIntervalUnit, unit, SckCycle)
153
154 #define AHB_WRITE_WAIT_UNIT(unit) \
155 CONCAT3(kFLEXSPI_AhbWriteWaitUnit, unit, AhbCycle)
156
157 #define MEMC_FLEXSPI_DEVICE_CONFIG(n) \
158 { \
159 .flexspiRootClk = MHZ(332), \
160 .isSck2Enabled = false, \
161 .flashSize = DT_INST_PROP(n, size) / 8 / KB(1), \
162 .CSIntervalUnit = \
163 CS_INTERVAL_UNIT( \
164 DT_INST_PROP(n, cs_interval_unit)), \
165 .CSInterval = DT_INST_PROP(n, cs_interval), \
166 .CSHoldTime = DT_INST_PROP(n, cs_hold_time), \
167 .CSSetupTime = DT_INST_PROP(n, cs_setup_time), \
168 .dataValidTime = DT_INST_PROP(n, data_valid_time), \
169 .columnspace = DT_INST_PROP(n, column_space), \
170 .enableWordAddress = DT_INST_PROP(n, word_addressable), \
171 .AWRSeqIndex = WRITE_DATA, \
172 .AWRSeqNumber = 1, \
173 .ARDSeqIndex = READ_DATA, \
174 .ARDSeqNumber = 1, \
175 .AHBWriteWaitUnit = \
176 AHB_WRITE_WAIT_UNIT( \
177 DT_INST_PROP(n, ahb_write_wait_unit)), \
178 .AHBWriteWaitInterval = \
179 DT_INST_PROP(n, ahb_write_wait_interval), \
180 .enableWriteMask = true, \
181 } \
182
183 #define MEMC_FLEXSPI_HYPERRAM(n) \
184 static const struct memc_flexspi_hyperram_config \
185 memc_flexspi_hyperram_config_##n = { \
186 .controller_label = DT_INST_BUS_LABEL(n), \
187 .port = DT_INST_REG_ADDR(n), \
188 .config = MEMC_FLEXSPI_DEVICE_CONFIG(n), \
189 }; \
190 \
191 static struct memc_flexspi_hyperram_data \
192 memc_flexspi_hyperram_data_##n; \
193 \
194 DEVICE_DT_INST_DEFINE(n, \
195 memc_flexspi_hyperram_init, \
196 NULL, \
197 &memc_flexspi_hyperram_data_##n, \
198 &memc_flexspi_hyperram_config_##n, \
199 POST_KERNEL, \
200 CONFIG_KERNEL_INIT_PRIORITY_DEVICE, \
201 NULL);
202
203 DT_INST_FOREACH_STATUS_OKAY(MEMC_FLEXSPI_HYPERRAM)
204
