1 /* 2 * Copyright (c) 2001-2019, Arm Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 8 #ifndef __TST_HW_ACCESS_H__ 9 #define __TST_HW_ACCESS_H__ 10 11 #include <stdint.h> 12 13 extern unsigned long g_testHwRegBaseAddr; 14 extern unsigned long g_testHwReeRegBaseAddr; 15 extern unsigned long g_testHwEnvBaseAddr; 16 17 /* rotate 32-bits word by 16 bits */ 18 #define ROT32(x) ( (x) >> 16 | (x) << 16 ) 19 20 /* inverse the bytes order in a word */ 21 #define REVERSE32(x) ( ((ROT32((x)) & 0xff00ff00UL) >> 8) | ((ROT32((x)) & 0x00ff00ffUL) << 8) ) 22 23 #ifndef BIG__ENDIAN 24 /* define word endiannes*/ 25 #define SET_WORD_ENDIANESS 26 #else 27 #define SET_WORD_ENDIANESS(val) REVERSE32(val) 28 #endif 29 30 31 #define SESSION_KEY_LEN_IN_BYTES 16 32 33 /* LCS */ 34 #define TESTS_LCS_CM 0x0 35 #define TESTS_LCS_DM 0x1 36 #define TESTS_LCS_SEC_DISABLED 0x3 37 #define TESTS_LCS_SEC_ENABLED 0x5 38 #define TESTS_LCS_RMA 0x7 39 40 /* errors */ 41 #define TEST_OK 0 42 #define TEST_BURN_OTP_ERR 1 43 #define TEST_BURN_OTP_KDR_ERR 2 44 #define TEST_BURN_OTP_SCP_ERR 3 45 #define TEST_BURN_OTP_LCS_ERR 4 46 #define TEST_INVALID_PARAM_ERR 5 47 48 49 /* OTP memeory mapping */ 50 51 #define ENV_OTP_START_OFFSET 0x800UL 52 #define TEST_OTP_SIZE_IN_WORDS 0x25 53 54 #define OTP_KRD_START_WORD_OFFSET 0x00 55 #define OTP_KRD_SIZE_IN_WORDS 0x08 56 #define OTP_KRD_SIZE_IN_BYTES (OTP_KRD_SIZE_IN_WORDS * sizeof(uint32_t)) 57 #define OTP_SCP_START_WORD_OFFSET 0x08 58 #define OTP_SCP_SIZE_IN_WORDS 0x02 59 60 #define OTP_MANUFACTOR_FLAG_START_WORD_OFFSET 0x0A 61 #define OTP_MANUFACTOR_FLAG_SIZE_IN_WORDS 0x01 62 #define OTP_MANUFACTOR_FLAG_KDR_ZEROS_BIT_OFFSET 0x00 63 #define OTP_MANUFACTOR_FLAG_KDR_ZEROS_NUM_BITS 0x08 64 #define OTP_MANUFACTOR_FLAG_SCP_ZEROS_BIT_OFFSET 0x08 65 #define OTP_MANUFACTOR_FLAG_SCP_ZEROS_NUM_BITS 0x07 66 #define OTP_MANUFACTOR_FLAG_SEC_EN_BIT_OFFSET 0x10 67 #define OTP_MANUFACTOR_FLAG_SEC_EN_NUM_BITS 0x04 68 #define OTP_MANUFACTOR_FLAG_SEC_ENABLE 0x3 69 #define OTP_MANUFACTOR_FLAG_SEC_DISABLE 0xC 70 71 72 #define OTP_DM_DEF_START_WORD_OFFSET 0x0B 73 #define OTP_DM_DEF_SIZE_IN_WORDS 0x02 74 #define OTP_DM_DEF_HBK0_ZEROS_BIT_OFFSET 0x00 75 #define OTP_DM_DEF_HBK0_ZEROS_NUM_BITS 0x08 76 #define OTP_DM_DEF_HBK1_ZEROS_BIT_OFFSET 0x08 77 #define OTP_DM_DEF_HBK1_ZEROS_NUM_BITS 0x08 78 79 #define OTP_KCE_START_WORD_OFFSET 0x0C 80 #define OTP_KCE_SIZE_IN_WORDS 0x04 81 #define OTP_HBK0_START_WORD_OFFSET 0x10 82 #define OTP_HBK0_SIZE_IN_WORDS 0x04 83 #define OTP_HBK1_START_WORD_OFFSET 0x14 84 #define OTP_HBK1_SIZE_IN_WORDS 0x04 85 #define OTP_SB_VER_START_WORD_OFFSET 0x18 86 #define OTP_SB_VER_SIZE_IN_WORDS 0x01 87 88 89 #define AIB_ADDR_REG_READ_ACCESS_BIT_SHIFT 0x10UL 90 #define AIB_ADDR_REG_WRITE_ACCESS_BIT_SHIFT 0x11UL 91 92 #define OTP_BASE_ADDR 0x00 93 #define OTP_WRITE_ADDR (0x1 << AIB_ADDR_REG_WRITE_ACCESS_BIT_SHIFT) 94 #define OTP_READ_ADDR (0x1 << AIB_ADDR_REG_READ_ACCESS_BIT_SHIFT) 95 96 #ifdef BIG__ENDIAN 97 #define TEST_CONVERT_BYTE_ARR_TO_WORD(inPtr, outWord) {\ 98 outWord = (*inPtr<<24);\ 99 outWord |= (*(inPtr+1)<<16);\ 100 outWord |= (*(inPtr+2)<<8);\ 101 outWord |= (*(inPtr+3));\ 102 } 103 #else 104 #define TEST_CONVERT_BYTE_ARR_TO_WORD(inPtr, outWord) {\ 105 outWord = (*(inPtr+3))<<24;\ 106 outWord |= (*(inPtr+2))<<16;\ 107 outWord |= (*(inPtr+1))<<8;\ 108 outWord |= (*inPtr);\ 109 } 110 #endif 111 112 113 #define TEST_CALC_BUFF_ZEROS(wordBuf, buffWordSize, zeros) {\ 114 int i = 0;\ 115 int j = 0;\ 116 int mask = 0;\ 117 zeros = 0;\ 118 for (i = 0; i< buffWordSize; i++) {\ 119 for (j = 0; j<32; j++) {\ 120 mask = 0x1;\ 121 if (!(*(wordBuf+i) & (mask << j))) {\ 122 zeros++;\ 123 }\ 124 }\ 125 }\ 126 } 127 128 129 #define READ_REG(offset) \ 130 *(volatile uint32_t *)(g_testHwRegBaseAddr + (offset)) 131 132 #define WRITE_REG(offset, val) { \ 133 volatile uint32_t ii1; \ 134 (*(volatile uint32_t *)(g_testHwRegBaseAddr + (offset))) = (uint32_t)(val); \ 135 for(ii1=0; ii1<500; ii1++); \ 136 } 137 138 139 #define READ_REE_REG(offset) \ 140 (*(volatile uint32_t *)(g_testHwReeRegBaseAddr + (offset))); 141 142 #define WRITE_REE_REG(offset, val) { \ 143 volatile uint32_t ii1; \ 144 (*(volatile uint32_t *)(g_testHwReeRegBaseAddr + (offset))) = (uint32_t)(val); \ 145 for(ii1=0; ii1<500; ii1++); \ 146 } 147 148 149 #define GET_LCS(val) {\ 150 do {\ 151 val = READ_REG(DX_LCS_IS_VALID_REG_OFFSET);\ 152 }while( !(val & 0x1));\ 153 val = READ_REG(DX_LCS_REG_REG_OFFSET);\ 154 val &= 0xFF;\ 155 } 156 157 #define WRITE_ENV(offset, val) { \ 158 volatile uint32_t ii1; \ 159 (*(volatile uint32_t *)(g_testHwEnvBaseAddr + (offset))) = (uint32_t)(val); \ 160 for(ii1=0; ii1<500; ii1++);\ 161 } 162 163 #define READ_ENV(offset) \ 164 *(volatile uint32_t *)(g_testHwEnvBaseAddr + (offset)) 165 166 167 #define WRITE_OTP(wordOffset, val) { \ 168 volatile uint32_t ii1; \ 169 (*(volatile uint32_t *)(g_testHwEnvBaseAddr + ENV_OTP_START_OFFSET+ ((wordOffset)*sizeof(uint32_t)))) = (uint32_t)(val); \ 170 for(ii1=0; ii1<500; ii1++);\ 171 } 172 173 #define READ_OTP(wordOffset) \ 174 (*(volatile uint32_t *)(g_testHwEnvBaseAddr + ENV_OTP_START_OFFSET+ ((wordOffset)*sizeof(uint32_t)))) 175 176 177 178 /* Poll on the AIB bit */ 179 #define WAIT_ON_AIB_PROG_COMP_BIT() \ 180 do {\ 181 int regVal;\ 182 do {\ 183 regVal = READ_REG(DX_AIB_FUSE_PROG_COMPLETED_REG_OFFSET);\ 184 }while( !(regVal & 0x1 ));\ 185 }while(0) 186 187 /* Poll on the AIB acknowledge bit */ 188 #define WAIT_ON_AIB_ACK_BIT() \ 189 do {\ 190 int regVal;\ 191 do {\ 192 regVal = READ_REG(DX_AIB_FUSE_ACK_REG_OFFSET);\ 193 }while( !(regVal & 0x1));\ 194 }while(0) 195 196 #define WRITE_AIB(addr, val) { \ 197 WRITE_REG(DX_HOST_AIB_WDATA_REG_REG_OFFSET, val);\ 198 WRITE_REG(DX_HOST_AIB_ADDR_REG_REG_OFFSET, (OTP_BASE_ADDR|OTP_WRITE_ADDR)+addr);\ 199 WAIT_ON_AIB_ACK_BIT();\ 200 WAIT_ON_AIB_PROG_COMP_BIT();\ 201 } 202 203 #define READ_AIB(addr, val) { \ 204 WRITE_REG(DX_HOST_AIB_ADDR_REG_REG_OFFSET, (OTP_BASE_ADDR|OTP_READ_ADDR)+addr); \ 205 WAIT_ON_AIB_ACK_BIT(); \ 206 val = READ_REG(DX_HOST_AIB_RDATA_REG_REG_OFFSET); \ 207 } 208 209 typedef enum otpHbkTypes_t{ 210 TEST_OTP_HBK0_TYPE = 1, //HBK0 211 TEST_OTP_HBK1_TYPE = 2, //HBK1 212 TEST_OTP_HBK_256_TYPE = 4, //HBK 213 }OtpHbkTypes_t; 214 215 216 /******************************/ 217 /* function declaration */ 218 /*****************************/ 219 220 unsigned int testBurnOtp(unsigned int *otp, unsigned int nextLcs); 221 unsigned int testClearOtp(void); 222 int testReadKdrZeros(void); 223 224 void performPowerOnReset(void); 225 void performColdReset(void); 226 void performWarmReset(void); 227 unsigned int testCheckLcs(unsigned int nextLcs); 228 229 unsigned int testSetKdrInOtpBuff(unsigned int *otp, unsigned char *kdrBuff); 230 unsigned int testSetScpInOtpBuff(unsigned int *otp, unsigned char *scpBuff); 231 unsigned int testSetHbkInOtpBuff(unsigned int *otp, unsigned char *hbkBuff, OtpHbkTypes_t type); 232 unsigned int testSetSecureInOtpBuff(unsigned int *otp, unsigned char enFlag); 233 unsigned int testReadOtp(unsigned int offset, unsigned int size, uint32_t *buff); 234 235 #endif //__TST_HW_ACCESS_H__ 236
