1 /**************************************************************************//** 2 * @file epwm_reg.h 3 * @version V1.00 4 * @brief EPWM register definition header file 5 * 6 * SPDX-License-Identifier: Apache-2.0 7 * @copyright (C) 2021 Nuvoton Technology Corp. All rights reserved. 8 *****************************************************************************/ 9 #ifndef __EPWM_REG_H__ 10 #define __EPWM_REG_H__ 11 12 #if defined ( __CC_ARM ) 13 #pragma anon_unions 14 #endif 15 16 /** 17 @addtogroup REGISTER Control Register 18 @{ 19 */ 20 21 /** 22 @addtogroup EPWM Pulse Width Modulation Controller (EPWM) 23 Memory Mapped Structure for EPWM Controller 24 @{ */ 25 26 typedef struct 27 { 28 /** 29 * @var ECAPDAT_T::RCAPDAT 30 * Offset: 0x20C EPWM Rising Capture Data Register 0~5 31 * --------------------------------------------------------------------------------------------------- 32 * |Bits |Field |Descriptions 33 * | :----: | :----: | :---- | 34 * |[15:0] |RCAPDAT |EPWM Rising Capture Data (Read Only) 35 * | | |When rising capture condition happened, the EPWM counter value will be saved in this register. 36 * @var ECAPDAT_T::FCAPDAT 37 * Offset: 0x210 EPWM Falling Capture Data Register 0~5 38 * --------------------------------------------------------------------------------------------------- 39 * |Bits |Field |Descriptions 40 * | :----: | :----: | :---- | 41 * |[15:0] |FCAPDAT |EPWM Falling Capture Data (Read Only) 42 * | | |When falling capture condition happened, the EPWM counter value will be saved in this register. 43 */ 44 __IO uint32_t RCAPDAT; /*!< [0x20C/0x214/0x21C/0x224/0x22C/0x234] EPWM Rising Capture Data Register 0~5 */ 45 __IO uint32_t FCAPDAT; /*!< [0x210/0x218/0x220/0x228/0x230/0x238] EPWM Falling Capture Data Register 0~5 */ 46 } ECAPDAT_T; 47 48 typedef struct 49 { 50 51 52 /** 53 * @var EPWM_T::CTL0 54 * Offset: 0x00 EPWM Control Register 0 55 * --------------------------------------------------------------------------------------------------- 56 * |Bits |Field |Descriptions 57 * | :----: | :----: | :---- | 58 * |[0] |CTRLD0 |Center Re-load 59 * | | |In up-down counter type, PERIOD will load to PBUF at the end point of each period 60 * | | |CMP will load to CMPBUF at the center point of a period 61 * |[1] |CTRLD1 |Center Re-load 62 * | | |In up-down counter type, PERIOD will load to PBUF at the end point of each period 63 * | | |CMP will load to CMPBUF at the center point of a period 64 * |[2] |CTRLD2 |Center Re-load 65 * | | |In up-down counter type, PERIOD will load to PBUF at the end point of each period 66 * | | |CMP will load to CMPBUF at the center point of a period 67 * |[3] |CTRLD3 |Center Re-load 68 * | | |In up-down counter type, PERIOD will load to PBUF at the end point of each period 69 * | | |CMP will load to CMPBUF at the center point of a period 70 * |[4] |CTRLD4 |Center Re-load 71 * | | |In up-down counter type, PERIOD will load to PBUF at the end point of each period 72 * | | |CMP will load to CMPBUF at the center point of a period 73 * |[5] |CTRLD5 |Center Re-load 74 * | | |In up-down counter type, PERIOD will load to PBUF at the end point of each period 75 * | | |CMP will load to CMPBUF at the center point of a period 76 * |[8] |WINLDEN0 |Window Load Enable Bits 77 * | | |0 = PERIOD will load to PBUF at the end point of each period 78 * | | |CMP will load to CMPBUF at the end point or center point of each period by setting CTRLD bit. 79 * | | |1 = PERIOD will load to PBUF at the end point of each period 80 * | | |CMP will load to CMPBUF at the end point of each period when valid reload window is set 81 * | | |The valid reload window is set by software write 1 to EPWM_LOAD register and cleared by hardware after load success. 82 * |[9] |WINLDEN1 |Window Load Enable Bits 83 * | | |0 = PERIOD will load to PBUF at the end point of each period 84 * | | |CMP will load to CMPBUF at the end point or center point of each period by setting CTRLD bit. 85 * | | |1 = PERIOD will load to PBUF at the end point of each period 86 * | | |CMP will load to CMPBUF at the end point of each period when valid reload window is set 87 * | | |The valid reload window is set by software write 1 to EPWM_LOAD register and cleared by hardware after load success. 88 * |[10] |WINLDEN2 |Window Load Enable Bits 89 * | | |0 = PERIOD will load to PBUF at the end point of each period 90 * | | |CMP will load to CMPBUF at the end point or center point of each period by setting CTRLD bit. 91 * | | |1 = PERIOD will load to PBUF at the end point of each period 92 * | | |CMP will load to CMPBUF at the end point of each period when valid reload window is set 93 * | | |The valid reload window is set by software write 1 to EPWM_LOAD register and cleared by hardware after load success. 94 * |[11] |WINLDEN3 |Window Load Enable Bits 95 * | | |0 = PERIOD will load to PBUF at the end point of each period 96 * | | |CMP will load to CMPBUF at the end point or center point of each period by setting CTRLD bit. 97 * | | |1 = PERIOD will load to PBUF at the end point of each period 98 * | | |CMP will load to CMPBUF at the end point of each period when valid reload window is set 99 * | | |The valid reload window is set by software write 1 to EPWM_LOAD register and cleared by hardware after load success. 100 * |[12] |WINLDEN4 |Window Load Enable Bits 101 * | | |0 = PERIOD will load to PBUF at the end point of each period 102 * | | |CMP will load to CMPBUF at the end point or center point of each period by setting CTRLD bit. 103 * | | |1 = PERIOD will load to PBUF at the end point of each period 104 * | | |CMP will load to CMPBUF at the end point of each period when valid reload window is set 105 * | | |The valid reload window is set by software write 1 to EPWM_LOAD register and cleared by hardware after load success. 106 * |[13] |WINLDEN5 |Window Load Enable Bits 107 * | | |0 = PERIOD will load to PBUF at the end point of each period 108 * | | |CMP will load to CMPBUF at the end point or center point of each period by setting CTRLD bit. 109 * | | |1 = PERIOD will load to PBUF at the end point of each period 110 * | | |CMP will load to CMPBUF at the end point of each period when valid reload window is set 111 * | | |The valid reload window is set by software write 1 to EPWM_LOAD register and cleared by hardware after load success. 112 * |[16] |IMMLDEN0 |Immediately Load Enable Bits 113 * | | |0 = PERIOD will load to PBUF at the end point of each period 114 * | | |CMP will load to CMPBUF at the end point or center point of each period by setting CTRLD bit. 115 * | | |1 = PERIOD/CMP will load to PBUF and CMPBUF immediately when software update PERIOD/CMP. 116 * | | |Note: If IMMLDENn is enabled, WINLDENn and CTRLDn will be invalid. 117 * |[17] |IMMLDEN1 |Immediately Load Enable Bits 118 * | | |0 = PERIOD will load to PBUF at the end point of each period 119 * | | |CMP will load to CMPBUF at the end point or center point of each period by setting CTRLD bit. 120 * | | |1 = PERIOD/CMP will load to PBUF and CMPBUF immediately when software update PERIOD/CMP. 121 * | | |Note: If IMMLDENn is enabled, WINLDENn and CTRLDn will be invalid. 122 * |[18] |IMMLDEN2 |Immediately Load Enable Bits 123 * | | |0 = PERIOD will load to PBUF at the end point of each period 124 * | | |CMP will load to CMPBUF at the end point or center point of each period by setting CTRLD bit. 125 * | | |1 = PERIOD/CMP will load to PBUF and CMPBUF immediately when software update PERIOD/CMP. 126 * | | |Note: If IMMLDENn is enabled, WINLDENn and CTRLDn will be invalid. 127 * |[19] |IMMLDEN3 |Immediately Load Enable Bits 128 * | | |0 = PERIOD will load to PBUF at the end point of each period 129 * | | |CMP will load to CMPBUF at the end point or center point of each period by setting CTRLD bit. 130 * | | |1 = PERIOD/CMP will load to PBUF and CMPBUF immediately when software update PERIOD/CMP. 131 * | | |Note: If IMMLDENn is enabled, WINLDENn and CTRLDn will be invalid. 132 * |[20] |IMMLDEN4 |Immediately Load Enable Bits 133 * | | |0 = PERIOD will load to PBUF at the end point of each period 134 * | | |CMP will load to CMPBUF at the end point or center point of each period by setting CTRLD bit. 135 * | | |1 = PERIOD/CMP will load to PBUF and CMPBUF immediately when software update PERIOD/CMP. 136 * | | |Note: If IMMLDENn is enabled, WINLDENn and CTRLDn will be invalid. 137 * |[21] |IMMLDEN5 |Immediately Load Enable Bits 138 * | | |0 = PERIOD will load to PBUF at the end point of each period 139 * | | |CMP will load to CMPBUF at the end point or center point of each period by setting CTRLD bit. 140 * | | |1 = PERIOD/CMP will load to PBUF and CMPBUF immediately when software update PERIOD/CMP. 141 * | | |Note: If IMMLDENn is enabled, WINLDENn and CTRLDn will be invalid. 142 * |[24] |GROUPEN |Group Function Enable Bit 143 * | | |0 = The output waveform of each EPWM channel are independent. 144 * | | |1 = Unify the EPWM_CH2 and EPWM_CH4 to output the same waveform as EPWM_CH0 and unify the EPWM_CH3 and EPWM_CH5 to output the same waveform as EPWM_CH1. 145 * |[30] |DBGHALT |ICE Debug Mode Counter Halt (Write Protect) 146 * | | |If counter halt is enabled, EPWM all counters will keep current value until exit ICE debug mode. 147 * | | |0 = ICE debug mode counter halt Disabled. 148 * | | |1 = ICE debug mode counter halt Enabled. 149 * | | |Note: This bit is write protected. Refer toSYS_REGLCTL register. 150 * |[31] |DBGTRIOFF |ICE Debug Mode Acknowledge Disable Bit (Write Protect) 151 * | | |0 = ICE debug mode acknowledgement effects EPWM output. 152 * | | |EPWM pin will be forced as tri-state while ICE debug mode acknowledged. 153 * | | |1 = ICE debug mode acknowledgement disabled. 154 * | | |EPWM pin will keep output no matter ICE debug mode acknowledged or not. 155 * | | |Note: This bit is write protected. Refer toSYS_REGLCTL register. 156 * @var EPWM_T::CTL1 157 * Offset: 0x04 EPWM Control Register 1 158 * --------------------------------------------------------------------------------------------------- 159 * |Bits |Field |Descriptions 160 * | :----: | :----: | :---- | 161 * |[1:0] |CNTTYPE0 |EPWM Counter Behavior Type 162 * | | |00 = Up counter type (supported in capture mode). 163 * | | |01 = Down count type (supported in capture mode). 164 * | | |10 = Up-down counter type. 165 * | | |11 = Reserved. 166 * |[3:2] |CNTTYPE1 |EPWM Counter Behavior Type 167 * | | |00 = Up counter type (supported in capture mode). 168 * | | |01 = Down count type (supported in capture mode). 169 * | | |10 = Up-down counter type. 170 * | | |11 = Reserved. 171 * |[5:4] |CNTTYPE2 |EPWM Counter Behavior Type 172 * | | |00 = Up counter type (supported in capture mode). 173 * | | |01 = Down count type (supported in capture mode). 174 * | | |10 = Up-down counter type. 175 * | | |11 = Reserved. 176 * |[7:6] |CNTTYPE3 |EPWM Counter Behavior Type 177 * | | |00 = Up counter type (supported in capture mode). 178 * | | |01 = Down count type (supported in capture mode). 179 * | | |10 = Up-down counter type. 180 * | | |11 = Reserved. 181 * |[9:8] |CNTTYPE4 |EPWM Counter Behavior Type 182 * | | |00 = Up counter type (supported in capture mode). 183 * | | |01 = Down count type (supported in capture mode). 184 * | | |10 = Up-down counter type. 185 * | | |11 = Reserved. 186 * |[11:10] |CNTTYPE5 |EPWM Counter Behavior Type 187 * | | |00 = Up counter type (supported in capture mode). 188 * | | |01 = Down count type (supported in capture mode). 189 * | | |10 = Up-down counter type. 190 * | | |11 = Reserved. 191 * |[16] |CNTMODE0 |EPWM Counter Mode 192 * | | |0 = Auto-reload mode. 193 * | | |1 = One-shot mode. 194 * |[17] |CNTMODE1 |EPWM Counter Mode 195 * | | |0 = Auto-reload mode. 196 * | | |1 = One-shot mode. 197 * |[18] |CNTMODE2 |EPWM Counter Mode 198 * | | |0 = Auto-reload mode. 199 * | | |1 = One-shot mode. 200 * |[19] |CNTMODE3 |EPWM Counter Mode 201 * | | |0 = Auto-reload mode. 202 * | | |1 = One-shot mode. 203 * |[20] |CNTMODE4 |EPWM Counter Mode 204 * | | |0 = Auto-reload mode. 205 * | | |1 = One-shot mode. 206 * |[21] |CNTMODE5 |EPWM Counter Mode 207 * | | |0 = Auto-reload mode. 208 * | | |1 = One-shot mode. 209 * |[24] |OUTMODE0 |EPWM Output Mode 210 * | | |Each bit n controls the output mode of corresponding EPWM channel n. 211 * | | |0 = EPWM independent mode. 212 * | | |1 = EPWM complementary mode. 213 * | | |Note: When operating in group function, these bits must all set to the same mode. 214 * |[25] |OUTMODE2 |EPWM Output Mode 215 * | | |Each bit n controls the output mode of corresponding EPWM channel n. 216 * | | |0 = EPWM independent mode. 217 * | | |1 = EPWM complementary mode. 218 * | | |Note: When operating in group function, these bits must all set to the same mode. 219 * |[26] |OUTMODE4 |EPWM Output Mode 220 * | | |Each bit n controls the output mode of corresponding EPWM channel n. 221 * | | |0 = EPWM independent mode. 222 * | | |1 = EPWM complementary mode. 223 * | | |Note: When operating in group function, these bits must all set to the same mode. 224 * @var EPWM_T::SYNC 225 * Offset: 0x08 EPWM Synchronization Register 226 * --------------------------------------------------------------------------------------------------- 227 * |Bits |Field |Descriptions 228 * | :----: | :----: | :---- | 229 * |[0] |PHSEN0 |SYNC Phase Enable Bits 230 * | | |0 = EPWM counter disable to load PHS value. 231 * | | |1 = EPWM counter enable to load PHS value. 232 * |[1] |PHSEN2 |SYNC Phase Enable Bits 233 * | | |0 = EPWM counter disable to load PHS value. 234 * | | |1 = EPWM counter enable to load PHS value. 235 * |[2] |PHSEN4 |SYNC Phase Enable Bits 236 * | | |0 = EPWM counter disable to load PHS value. 237 * | | |1 = EPWM counter enable to load PHS value. 238 * |[9:8] |SINSRC0 |EPWM0_SYNC_IN Source Selection 239 * | | |00 = Synchronize source from SYNC_IN or SWSYNC. 240 * | | |01 = Counter equal to 0. 241 * | | |10 = Counter equal to EPWM_CMPDATm, m denotes 1, 3, 5. 242 * | | |11 = SYNC_OUT will not be generated. 243 * |[11:10] |SINSRC2 |EPWM0_SYNC_IN Source Selection 244 * | | |00 = Synchronize source from SYNC_IN or SWSYNC. 245 * | | |01 = Counter equal to 0. 246 * | | |10 = Counter equal to EPWM_CMPDATm, m denotes 1, 3, 5. 247 * | | |11 = SYNC_OUT will not be generated. 248 * |[13:12] |SINSRC4 |EPWM0_SYNC_IN Source Selection 249 * | | |00 = Synchronize source from SYNC_IN or SWSYNC. 250 * | | |01 = Counter equal to 0. 251 * | | |10 = Counter equal to EPWM_CMPDATm, m denotes 1, 3, 5. 252 * | | |11 = SYNC_OUT will not be generated. 253 * |[16] |SNFLTEN |EPWM0_SYNC_IN Noise Filter Enable Bits 254 * | | |0 = Noise filter of input pin EPWM0_SYNC_IN Disabled. 255 * | | |1 = Noise filter of input pin EPWM0_SYNC_IN Enabled. 256 * |[19:17] |SFLTCSEL |SYNC Edge Detector Filter Clock Selection 257 * | | |000 = Filter clock = HCLK. 258 * | | |001 = Filter clock = HCLK/2. 259 * | | |010 = Filter clock = HCLK/4. 260 * | | |011 = Filter clock = HCLK/8. 261 * | | |100 = Filter clock = HCLK/16. 262 * | | |101 = Filter clock = HCLK/32. 263 * | | |110 = Filter clock = HCLK/64. 264 * | | |111 = Filter clock = HCLK/128. 265 * |[22:20] |SFLTCNT |SYNC Edge Detector Filter Count 266 * | | |The register bits control the counter number of edge detector. 267 * |[23] |SINPINV |SYNC Input Pin Inverse 268 * | | |0 = The state of pin SYNC is passed to the negative edge detector. 269 * | | |1 = The inversed state of pin SYNC is passed to the negative edge detector. 270 * |[24] |PHSDIR0 |EPWM Phase Direction Control 271 * | | |0 = Control EPWM counter count decrement after synchronizing. 272 * | | |1 = Control EPWM counter count increment after synchronizing. 273 * |[25] |PHSDIR2 |EPWM Phase Direction Control 274 * | | |0 = Control EPWM counter count decrement after synchronizing. 275 * | | |1 = Control EPWM counter count increment after synchronizing. 276 * |[26] |PHSDIR4 |EPWM Phase Direction Control 277 * | | |0 = Control EPWM counter count decrement after synchronizing. 278 * | | |1 = Control EPWM counter count increment after synchronizing. 279 * @var EPWM_T::SWSYNC 280 * Offset: 0x0C EPWM Software Control Synchronization Register 281 * --------------------------------------------------------------------------------------------------- 282 * |Bits |Field |Descriptions 283 * | :----: | :----: | :---- | 284 * |[0] |SWSYNC0 |Software SYNC Function (Write Only) 285 * | | |When SINSRCn (EPWM_SYNC[13:8]) is selected to 0, SYNC_OUT source comes from SYNC_IN or this bit. 286 * |[1] |SWSYNC2 |Software SYNC Function (Write Only) 287 * | | |When SINSRCn (EPWM_SYNC[13:8]) is selected to 0, SYNC_OUT source comes from SYNC_IN or this bit. 288 * |[2] |SWSYNC4 |Software SYNC Function (Write Only) 289 * | | |When SINSRCn (EPWM_SYNC[13:8]) is selected to 0, SYNC_OUT source comes from SYNC_IN or this bit. 290 * @var EPWM_T::CLKSRC 291 * Offset: 0x10 EPWM Clock Source Register 292 * --------------------------------------------------------------------------------------------------- 293 * |Bits |Field |Descriptions 294 * | :----: | :----: | :---- | 295 * |[2:0] |ECLKSRC0 |EPWM_CH01 External Clock Source Select 296 * | | |000 = EPWMx_CLK, x denotes 0 or 1. 297 * | | |001 = TIMER0 overflow. 298 * | | |010 = TIMER1 overflow. 299 * | | |011 = TIMER2 overflow. 300 * | | |100 = TIMER3 overflow. 301 * | | |Others = Reserved. 302 * |[10:8] |ECLKSRC2 |EPWM_CH23 External Clock Source Select 303 * | | |000 = EPWMx_CLK, x denotes 0 or 1. 304 * | | |001 = TIMER0 overflow. 305 * | | |010 = TIMER1 overflow. 306 * | | |011 = TIMER2 overflow. 307 * | | |100 = TIMER3 overflow. 308 * | | |Others = Reserved. 309 * |[18:16] |ECLKSRC4 |EPWM_CH45 External Clock Source Select 310 * | | |000 = EPWMx_CLK, x denotes 0 or 1. 311 * | | |001 = TIMER0 overflow. 312 * | | |010 = TIMER1 overflow. 313 * | | |011 = TIMER2 overflow. 314 * | | |100 = TIMER3 overflow. 315 * | | |Others = Reserved. 316 * @var EPWM_T::CNTEN 317 * Offset: 0x20 EPWM Counter Enable Register 318 * --------------------------------------------------------------------------------------------------- 319 * |Bits |Field |Descriptions 320 * | :----: | :----: | :---- | 321 * |[0] |CNTEN0 |EPWM Counter Enable Bits 322 * | | |0 = EPWM Counter and clock prescaler stop running. 323 * | | |1 = EPWM Counter and clock prescaler start running. 324 * |[1] |CNTEN1 |EPWM Counter Enable Bits 325 * | | |0 = EPWM Counter and clock prescaler stop running. 326 * | | |1 = EPWM Counter and clock prescaler start running. 327 * |[2] |CNTEN2 |EPWM Counter Enable Bits 328 * | | |0 = EPWM Counter and clock prescaler stop running. 329 * | | |1 = EPWM Counter and clock prescaler start running. 330 * |[3] |CNTEN3 |EPWM Counter Enable Bits 331 * | | |0 = EPWM Counter and clock prescaler stop running. 332 * | | |1 = EPWM Counter and clock prescaler start running. 333 * |[4] |CNTEN4 |EPWM Counter Enable Bits 334 * | | |0 = EPWM Counter and clock prescaler stop running. 335 * | | |1 = EPWM Counter and clock prescaler start running. 336 * |[5] |CNTEN5 |EPWM Counter Enable Bits 337 * | | |0 = EPWM Counter and clock prescaler stop running. 338 * | | |1 = EPWM Counter and clock prescaler start running. 339 * @var EPWM_T::CNTCLR 340 * Offset: 0x24 EPWM Clear Counter Register 341 * --------------------------------------------------------------------------------------------------- 342 * |Bits |Field |Descriptions 343 * | :----: | :----: | :---- | 344 * |[0] |CNTCLR0 |Clear EPWM Counter Control Bit 345 * | | |It is automatically cleared by hardware. Each bit n controls the corresponding EPWM channel n. 346 * | | |0 = No effect. 347 * | | |1 = Clear 16-bit EPWM counter to 0000H. 348 * |[1] |CNTCLR1 |Clear EPWM Counter Control Bit 349 * | | |It is automatically cleared by hardware. Each bit n controls the corresponding EPWM channel n. 350 * | | |0 = No effect. 351 * | | |1 = Clear 16-bit EPWM counter to 0000H. 352 * |[2] |CNTCLR2 |Clear EPWM Counter Control Bit 353 * | | |It is automatically cleared by hardware. Each bit n controls the corresponding EPWM channel n. 354 * | | |0 = No effect. 355 * | | |1 = Clear 16-bit EPWM counter to 0000H. 356 * |[3] |CNTCLR3 |Clear EPWM Counter Control Bit 357 * | | |It is automatically cleared by hardware. Each bit n controls the corresponding EPWM channel n. 358 * | | |0 = No effect. 359 * | | |1 = Clear 16-bit EPWM counter to 0000H. 360 * |[4] |CNTCLR4 |Clear EPWM Counter Control Bit 361 * | | |It is automatically cleared by hardware. Each bit n controls the corresponding EPWM channel n. 362 * | | |0 = No effect. 363 * | | |1 = Clear 16-bit EPWM counter to 0000H. 364 * |[5] |CNTCLR5 |Clear EPWM Counter Control Bit 365 * | | |It is automatically cleared by hardware. Each bit n controls the corresponding EPWM channel n. 366 * | | |0 = No effect. 367 * | | |1 = Clear 16-bit EPWM counter to 0000H. 368 * @var EPWM_T::LOAD 369 * Offset: 0x28 EPWM Load Register 370 * --------------------------------------------------------------------------------------------------- 371 * |Bits |Field |Descriptions 372 * | :----: | :----: | :---- | 373 * |[0] |LOAD0 |Re-load EPWM Comparator Register Control Bit 374 * | | |This bit is software write to reload EPWM_CMPDATn, n=0~5. Hardware clear when current EPWM period end. 375 * | | |Write Operation: 376 * | | |0 = No effect. 377 * | | |1 = Set load window of window loading mode. 378 * | | |Read Operation: 379 * | | |0 = No load window is set. 380 * | | |1 = Load window is set. 381 * | | |Note: This bit only use in window loading mode, WINLDENn(EPWM_CTL0[13:8]) = 1. 382 * |[1] |LOAD1 |Re-load EPWM Comparator Register Control Bit 383 * | | |This bit is software write to reload EPWM_CMPDATn, n=0~5. Hardware clear when current EPWM period end. 384 * | | |Write Operation: 385 * | | |0 = No effect. 386 * | | |1 = Set load window of window loading mode. 387 * | | |Read Operation: 388 * | | |0 = No load window is set. 389 * | | |1 = Load window is set. 390 * | | |Note: This bit only use in window loading mode, WINLDENn(EPWM_CTL0[13:8]) = 1. 391 * |[2] |LOAD2 |Re-load EPWM Comparator Register Control Bit 392 * | | |This bit is software write to reload EPWM_CMPDATn, n=0~5. Hardware clear when current EPWM period end. 393 * | | |Write Operation: 394 * | | |0 = No effect. 395 * | | |1 = Set load window of window loading mode. 396 * | | |Read Operation: 397 * | | |0 = No load window is set. 398 * | | |1 = Load window is set. 399 * | | |Note: This bit only use in window loading mode, WINLDENn(EPWM_CTL0[13:8]) = 1. 400 * |[3] |LOAD3 |Re-load EPWM Comparator Register Control Bit 401 * | | |This bit is software write to reload EPWM_CMPDATn, n=0~5. Hardware clear when current EPWM period end. 402 * | | |Write Operation: 403 * | | |0 = No effect. 404 * | | |1 = Set load window of window loading mode. 405 * | | |Read Operation: 406 * | | |0 = No load window is set. 407 * | | |1 = Load window is set. 408 * | | |Note: This bit only use in window loading mode, WINLDENn(EPWM_CTL0[13:8]) = 1. 409 * |[4] |LOAD4 |Re-load EPWM Comparator Register Control Bit 410 * | | |This bit is software write to reload EPWM_CMPDATn, n=0~5. Hardware clear when current EPWM period end. 411 * | | |Write Operation: 412 * | | |0 = No effect. 413 * | | |1 = Set load window of window loading mode. 414 * | | |Read Operation: 415 * | | |0 = No load window is set. 416 * | | |1 = Load window is set. 417 * | | |Note: This bit only use in window loading mode, WINLDENn(EPWM_CTL0[13:8]) = 1. 418 * |[5] |LOAD5 |Re-load EPWM Comparator Register Control Bit 419 * | | |This bit is software write to reload EPWM_CMPDATn, n=0~5. Hardware clear when current EPWM period end. 420 * | | |Write Operation: 421 * | | |0 = No effect. 422 * | | |1 = Set load window of window loading mode. 423 * | | |Read Operation: 424 * | | |0 = No load window is set. 425 * | | |1 = Load window is set. 426 * | | |Note: This bit only use in window loading mode, WINLDENn(EPWM_CTL0[13:8]) = 1. 427 * @var EPWM_T::PERIOD[6] 428 * Offset: 0x30 EPWM Period Register 0~5 429 * --------------------------------------------------------------------------------------------------- 430 * |Bits |Field |Descriptions 431 * | :----: | :----: | :---- | 432 * |[15:0] |PERIOD |EPWM Period Register 433 * | | |Up-Count mode: 434 * | | |In this mode, EPWM counter counts from 0 to PERIOD, and restarts from 0. 435 * | | |EPWM period time = (PERIOD+1) * (CLKPSC+1) * EPWM_CLK . 436 * | | |Down-Count mode: 437 * | | |In this mode, EPWM counter counts from PERIOD to 0, and restarts from PERIOD. 438 * | | |EPWM period time = (PERIOD+1) * (CLKPSC+1) * EPWM_CLK . 439 * | | |Up-Down-Count mode: 440 * | | |In this mode, EPWM counter counts from 0 to PERIOD, then decrements to 0 and repeats again. 441 * | | |EPWM period time = 2 * PERIOD * (CLKPSC+1) * EPWM_CLK. 442 * @var EPWM_T::CMPDAT[6] 443 * Offset: 0x50 EPWM Comparator Register 0 444 * --------------------------------------------------------------------------------------------------- 445 * |Bits |Field |Descriptions 446 * | :----: | :----: | :---- | 447 * |[15:0] |CMP |EPWM Comparator Register 448 * | | |CMP is used to compare with CNT (EPWM_CNTn[15:0]) bits to generate EPWM waveform, interrupt and trigger EADC/DAC. 449 * | | |In independent mode, EPWM_CMPDATn, n=0,1..5 denote as 6 independent EPWM_CH0~5 compared point. 450 * | | |In complementary mode, EPWM_CMPDAT0, EPWM_CMPDAT 2, EPWM_CMPDAT4 denote as first compared point, and EPWM_CMPDAT1, EPWM_CMPDAT3, EPWM_CMPDAT5 denote as second compared point for the corresponding 3 complementary pairs EPWM_CH0 and EPWM_CH1, EPWM_CH2 and EPWM_CH3, EPWM_CH4 and EPWM_CH5. 451 * @var EPWM_T::PHS[3] 452 * Offset: 0x80 EPWM Counter Phase Register 0/1,2/3,4/5 453 * --------------------------------------------------------------------------------------------------- 454 * |Bits |Field |Descriptions 455 * | :----: | :----: | :---- | 456 * |[15:0] |PHS |EPWM Synchronous Start Phase Bits 457 * | | |PHS determines the EPWM synchronous start phase value. These bits only use in synchronous function. 458 * @var EPWM_T::CNT[6] 459 * Offset: 0x90 EPWM Counter Register 0~5 460 * --------------------------------------------------------------------------------------------------- 461 * |Bits |Field |Descriptions 462 * | :----: | :----: | :---- | 463 * |[15:0] |CNT |EPWM Data Register (Read Only) 464 * | | |User can monitor CNTR to know the current value in 16-bit period counter. 465 * |[16] |DIRF |EPWM Direction Indicator Flag (Read Only) 466 * | | |0 = Counter is counting down. 467 * | | |1 = Counter is counting up. 468 * @var EPWM_T::WGCTL0 469 * Offset: 0xB0 EPWM Generation Register 0 470 * --------------------------------------------------------------------------------------------------- 471 * |Bits |Field |Descriptions 472 * | :----: | :----: | :---- | 473 * |[1:0] |ZPCTL0 |EPWM Zero Point Control 474 * | | |EPWM can control output level when EPWM counter counts to 0. 475 * | | |00 = Do nothing. 476 * | | |01 = EPWM zero point output Low. 477 * | | |10 = EPWM zero point output High. 478 * | | |11 = EPWM zero point output Toggle. 479 * |[3:2] |ZPCTL1 |EPWM Zero Point Control 480 * | | |EPWM can control output level when EPWM counter counts to 0. 481 * | | |00 = Do nothing. 482 * | | |01 = EPWM zero point output Low. 483 * | | |10 = EPWM zero point output High. 484 * | | |11 = EPWM zero point output Toggle. 485 * |[5:4] |ZPCTL2 |EPWM Zero Point Control 486 * | | |EPWM can control output level when EPWM counter counts to 0. 487 * | | |00 = Do nothing. 488 * | | |01 = EPWM zero point output Low. 489 * | | |10 = EPWM zero point output High. 490 * | | |11 = EPWM zero point output Toggle. 491 * |[7:6] |ZPCTL3 |EPWM Zero Point Control 492 * | | |EPWM can control output level when EPWM counter counts to 0. 493 * | | |00 = Do nothing. 494 * | | |01 = EPWM zero point output Low. 495 * | | |10 = EPWM zero point output High. 496 * | | |11 = EPWM zero point output Toggle. 497 * |[9:8] |ZPCTL4 |EPWM Zero Point Control 498 * | | |EPWM can control output level when EPWM counter counts to 0. 499 * | | |00 = Do nothing. 500 * | | |01 = EPWM zero point output Low. 501 * | | |10 = EPWM zero point output High. 502 * | | |11 = EPWM zero point output Toggle. 503 * |[11:10] |ZPCTL5 |EPWM Zero Point Control 504 * | | |EPWM can control output level when EPWM counter counts to 0. 505 * | | |00 = Do nothing. 506 * | | |01 = EPWM zero point output Low. 507 * | | |10 = EPWM zero point output High. 508 * | | |11 = EPWM zero point output Toggle. 509 * |[17:16] |PRDPCTL0 |EPWM Period or Center Point Control 510 * | | |EPWM can control output level when EPWM counter counts to (PERIODn+1). 511 * | | |00 = Do nothing. 512 * | | |01 = EPWM period (center) point output Low. 513 * | | |10 = EPWM period (center) point output High. 514 * | | |11 = EPWM period (center) point output Toggle. 515 * | | |Note: This bit is center point control when EPWM counter operating in up-down counter type. 516 * |[19:18] |PRDPCTL1 |EPWM Period or Center Point Control 517 * | | |EPWM can control output level when EPWM counter counts to (PERIODn+1). 518 * | | |00 = Do nothing. 519 * | | |01 = EPWM period (center) point output Low. 520 * | | |10 = EPWM period (center) point output High. 521 * | | |11 = EPWM period (center) point output Toggle. 522 * | | |Note: This bit is center point control when EPWM counter operating in up-down counter type. 523 * |[21:20] |PRDPCTL2 |EPWM Period or Center Point Control 524 * | | |EPWM can control output level when EPWM counter counts to (PERIODn+1). 525 * | | |00 = Do nothing. 526 * | | |01 = EPWM period (center) point output Low. 527 * | | |10 = EPWM period (center) point output High. 528 * | | |11 = EPWM period (center) point output Toggle. 529 * | | |Note: This bit is center point control when EPWM counter operating in up-down counter type. 530 * |[23:22] |PRDPCTL3 |EPWM Period or Center Point Control 531 * | | |EPWM can control output level when EPWM counter counts to (PERIODn+1). 532 * | | |00 = Do nothing. 533 * | | |01 = EPWM period (center) point output Low. 534 * | | |10 = EPWM period (center) point output High. 535 * | | |11 = EPWM period (center) point output Toggle. 536 * | | |Note: This bit is center point control when EPWM counter operating in up-down counter type. 537 * |[25:24] |PRDPCTL4 |EPWM Period or Center Point Control 538 * | | |EPWM can control output level when EPWM counter counts to (PERIODn+1). 539 * | | |00 = Do nothing. 540 * | | |01 = EPWM period (center) point output Low. 541 * | | |10 = EPWM period (center) point output High. 542 * | | |11 = EPWM period (center) point output Toggle. 543 * | | |Note: This bit is center point control when EPWM counter operating in up-down counter type. 544 * |[27:26] |PRDPCTL5 |EPWM Period or Center Point Control 545 * | | |EPWM can control output level when EPWM counter counts to (PERIODn+1). 546 * | | |00 = Do nothing. 547 * | | |01 = EPWM period (center) point output Low. 548 * | | |10 = EPWM period (center) point output High. 549 * | | |11 = EPWM period (center) point output Toggle. 550 * | | |Note: This bit is center point control when EPWM counter operating in up-down counter type. 551 * @var EPWM_T::WGCTL1 552 * Offset: 0xB4 EPWM Generation Register 1 553 * --------------------------------------------------------------------------------------------------- 554 * |Bits |Field |Descriptions 555 * | :----: | :----: | :---- | 556 * |[1:0] |CMPUCTL0 |EPWM Compare Up Point Control 557 * | | |EPWM can control output level when EPWM counter counts up to CMP. 558 * | | |00 = Do nothing. 559 * | | |01 = EPWM compare up point output Low. 560 * | | |10 = EPWM compare up point output High. 561 * | | |11 = EPWM compare up point output Toggle. 562 * | | |Note: In complementary mode, CMPUCTL1, 3, 5 is used as another CMPUCTL for channel 0, 2, 4. 563 * |[3:2] |CMPUCTL1 |EPWM Compare Up Point Control 564 * | | |EPWM can control output level when EPWM counter counts up to CMP. 565 * | | |00 = Do nothing. 566 * | | |01 = EPWM compare up point output Low. 567 * | | |10 = EPWM compare up point output High. 568 * | | |11 = EPWM compare up point output Toggle. 569 * | | |Note: In complementary mode, CMPUCTL1, 3, 5 is used as another CMPUCTL for channel 0, 2, 4. 570 * |[5:4] |CMPUCTL2 |EPWM Compare Up Point Control 571 * | | |EPWM can control output level when EPWM counter counts up to CMP. 572 * | | |00 = Do nothing. 573 * | | |01 = EPWM compare up point output Low. 574 * | | |10 = EPWM compare up point output High. 575 * | | |11 = EPWM compare up point output Toggle. 576 * | | |Note: In complementary mode, CMPUCTL1, 3, 5 is used as another CMPUCTL for channel 0, 2, 4. 577 * |[7:6] |CMPUCTL3 |EPWM Compare Up Point Control 578 * | | |EPWM can control output level when EPWM counter counts up to CMP. 579 * | | |00 = Do nothing. 580 * | | |01 = EPWM compare up point output Low. 581 * | | |10 = EPWM compare up point output High. 582 * | | |11 = EPWM compare up point output Toggle. 583 * | | |Note: In complementary mode, CMPUCTL1, 3, 5 is used as another CMPUCTL for channel 0, 2, 4. 584 * |[9:8] |CMPUCTL4 |EPWM Compare Up Point Control 585 * | | |EPWM can control output level when EPWM counter counts up to CMP. 586 * | | |00 = Do nothing. 587 * | | |01 = EPWM compare up point output Low. 588 * | | |10 = EPWM compare up point output High. 589 * | | |11 = EPWM compare up point output Toggle. 590 * | | |Note: In complementary mode, CMPUCTL1, 3, 5 is used as another CMPUCTL for channel 0, 2, 4. 591 * |[11:10] |CMPUCTL5 |EPWM Compare Up Point Control 592 * | | |EPWM can control output level when EPWM counter counts up to CMP. 593 * | | |00 = Do nothing. 594 * | | |01 = EPWM compare up point output Low. 595 * | | |10 = EPWM compare up point output High. 596 * | | |11 = EPWM compare up point output Toggle. 597 * | | |Note: In complementary mode, CMPUCTL1, 3, 5 is used as another CMPUCTL for channel 0, 2, 4. 598 * |[17:16] |CMPDCTL0 |EPWM Compare Down Point Control 599 * | | |EPWM can control output level when EPWM counter counts down to CMP. 600 * | | |00 = Do nothing. 601 * | | |01 = EPWM compare down point output Low. 602 * | | |10 = EPWM compare down point output High. 603 * | | |11 = EPWM compare down point output Toggle. 604 * | | |Note: In complementary mode, CMPDCTL1, 3, 5 is used as another CMPDCTL for channel 0, 2, 4. 605 * |[19:18] |CMPDCTL1 |EPWM Compare Down Point Control 606 * | | |EPWM can control output level when EPWM counter counts down to CMP. 607 * | | |00 = Do nothing. 608 * | | |01 = EPWM compare down point output Low. 609 * | | |10 = EPWM compare down point output High. 610 * | | |11 = EPWM compare down point output Toggle. 611 * | | |Note: In complementary mode, CMPDCTL1, 3, 5 is used as another CMPDCTL for channel 0, 2, 4. 612 * |[21:20] |CMPDCTL2 |EPWM Compare Down Point Control 613 * | | |EPWM can control output level when EPWM counter counts down to CMP. 614 * | | |00 = Do nothing. 615 * | | |01 = EPWM compare down point output Low. 616 * | | |10 = EPWM compare down point output High. 617 * | | |11 = EPWM compare down point output Toggle. 618 * | | |Note: In complementary mode, CMPDCTL1, 3, 5 is used as another CMPDCTL for channel 0, 2, 4. 619 * |[23:22] |CMPDCTL3 |EPWM Compare Down Point Control 620 * | | |EPWM can control output level when EPWM counter counts down to CMP. 621 * | | |00 = Do nothing. 622 * | | |01 = EPWM compare down point output Low. 623 * | | |10 = EPWM compare down point output High. 624 * | | |11 = EPWM compare down point output Toggle. 625 * | | |Note: In complementary mode, CMPDCTL1, 3, 5 is used as another CMPDCTL for channel 0, 2, 4. 626 * |[25:24] |CMPDCTL4 |EPWM Compare Down Point Control 627 * | | |EPWM can control output level when EPWM counter counts down to CMP. 628 * | | |00 = Do nothing. 629 * | | |01 = EPWM compare down point output Low. 630 * | | |10 = EPWM compare down point output High. 631 * | | |11 = EPWM compare down point output Toggle. 632 * | | |Note: In complementary mode, CMPDCTL1, 3, 5 is used as another CMPDCTL for channel 0, 2, 4. 633 * |[27:26] |CMPDCTL5 |EPWM Compare Down Point Control 634 * | | |EPWM can control output level when EPWM counter counts down to CMP. 635 * | | |00 = Do nothing. 636 * | | |01 = EPWM compare down point output Low. 637 * | | |10 = EPWM compare down point output High. 638 * | | |11 = EPWM compare down point output Toggle. 639 * | | |Note: In complementary mode, CMPDCTL1, 3, 5 is used as another CMPDCTL for channel 0, 2, 4. 640 * @var EPWM_T::MSKEN 641 * Offset: 0xB8 EPWM Mask Enable Register 642 * --------------------------------------------------------------------------------------------------- 643 * |Bits |Field |Descriptions 644 * | :----: | :----: | :---- | 645 * |[0] |MSKEN0 |EPWM Mask Enable Bits 646 * | | |The EPWM output signal will be masked when this bit is enabled 647 * | | |The corresponding EPWM channel n will output MSKDATn (EPWM_MSK[5:0]) data. 648 * | | |0 = EPWM output signal is non-masked. 649 * | | |1 = EPWM output signal is masked and output MSKDATn data. 650 * |[1] |MSKEN1 |EPWM Mask Enable Bits 651 * | | |The EPWM output signal will be masked when this bit is enabled 652 * | | |The corresponding EPWM channel n will output MSKDATn (EPWM_MSK[5:0]) data. 653 * | | |0 = EPWM output signal is non-masked. 654 * | | |1 = EPWM output signal is masked and output MSKDATn data. 655 * |[2] |MSKEN2 |EPWM Mask Enable Bits 656 * | | |The EPWM output signal will be masked when this bit is enabled 657 * | | |The corresponding EPWM channel n will output MSKDATn (EPWM_MSK[5:0]) data. 658 * | | |0 = EPWM output signal is non-masked. 659 * | | |1 = EPWM output signal is masked and output MSKDATn data. 660 * |[3] |MSKEN3 |EPWM Mask Enable Bits 661 * | | |The EPWM output signal will be masked when this bit is enabled 662 * | | |The corresponding EPWM channel n will output MSKDATn (EPWM_MSK[5:0]) data. 663 * | | |0 = EPWM output signal is non-masked. 664 * | | |1 = EPWM output signal is masked and output MSKDATn data. 665 * |[4] |MSKEN4 |EPWM Mask Enable Bits 666 * | | |The EPWM output signal will be masked when this bit is enabled 667 * | | |The corresponding EPWM channel n will output MSKDATn (EPWM_MSK[5:0]) data. 668 * | | |0 = EPWM output signal is non-masked. 669 * | | |1 = EPWM output signal is masked and output MSKDATn data. 670 * |[5] |MSKEN5 |EPWM Mask Enable Bits 671 * | | |The EPWM output signal will be masked when this bit is enabled 672 * | | |The corresponding EPWM channel n will output MSKDATn (EPWM_MSK[5:0]) data. 673 * | | |0 = EPWM output signal is non-masked. 674 * | | |1 = EPWM output signal is masked and output MSKDATn data. 675 * @var EPWM_T::MSK 676 * Offset: 0xBC EPWM Mask Data Register 677 * --------------------------------------------------------------------------------------------------- 678 * |Bits |Field |Descriptions 679 * | :----: | :----: | :---- | 680 * |[0] |MSKDAT0 |EPWM Mask Data Bit 681 * | | |This data bit control the state of EPWMn output pin, if corresponding mask function is enabled. 682 * | | |0 = Output logic low to EPWM channel n. 683 * | | |1 = Output logic high to EPWM channel n. 684 * |[1] |MSKDAT1 |EPWM Mask Data Bit 685 * | | |This data bit control the state of EPWMn output pin, if corresponding mask function is enabled. 686 * | | |0 = Output logic low to EPWM channel n. 687 * | | |1 = Output logic high to EPWM channel n. 688 * |[2] |MSKDAT2 |EPWM Mask Data Bit 689 * | | |This data bit control the state of EPWMn output pin, if corresponding mask function is enabled. 690 * | | |0 = Output logic low to EPWM channel n. 691 * | | |1 = Output logic high to EPWM channel n. 692 * |[3] |MSKDAT3 |EPWM Mask Data Bit 693 * | | |This data bit control the state of EPWMn output pin, if corresponding mask function is enabled. 694 * | | |0 = Output logic low to EPWM channel n. 695 * | | |1 = Output logic high to EPWM channel n. 696 * |[4] |MSKDAT4 |EPWM Mask Data Bit 697 * | | |This data bit control the state of EPWMn output pin, if corresponding mask function is enabled. 698 * | | |0 = Output logic low to EPWM channel n. 699 * | | |1 = Output logic high to EPWM channel n. 700 * |[5] |MSKDAT5 |EPWM Mask Data Bit 701 * | | |This data bit control the state of EPWMn output pin, if corresponding mask function is enabled. 702 * | | |0 = Output logic low to EPWM channel n. 703 * | | |1 = Output logic high to EPWM channel n. 704 * @var EPWM_T::BNF 705 * Offset: 0xC0 EPWM Brake Noise Filter Register 706 * --------------------------------------------------------------------------------------------------- 707 * |Bits |Field |Descriptions 708 * | :----: | :----: | :---- | 709 * |[0] |BRK0NFEN |EPWM Brake 0 Noise Filter Enable Bit 710 * | | |0 = Noise filter of EPWM Brake 0 Disabled. 711 * | | |1 = Noise filter of EPWM Brake 0 Enabled. 712 * |[3:1] |BRK0NFSEL |Brake 0 Edge Detector Filter Clock Selection 713 * | | |000 = Filter clock = HCLK. 714 * | | |001 = Filter clock = HCLK/2. 715 * | | |010 = Filter clock = HCLK/4. 716 * | | |011 = Filter clock = HCLK/8. 717 * | | |100 = Filter clock = HCLK/16. 718 * | | |101 = Filter clock = HCLK/32. 719 * | | |110 = Filter clock = HCLK/64. 720 * | | |111 = Filter clock = HCLK/128. 721 * |[6:4] |BRK0FCNT |Brake 0 Edge Detector Filter Count 722 * | | |The register bits control the Brake0 filter counter to count from 0 to BRK0FCNT. 723 * |[7] |BRK0PINV |Brake 0 Pin Inverse 724 * | | |0 = brake pin event will be detected if EPWMx_BRAKE0 pin status transfer from low to high in edge-detect, or pin status is high in level-detect. 725 * | | |1 = brake pin event will be detected if EPWMx_BRAKE0 pin status transfer from high to low in edge-detect, or pin status is low in level-detect. 726 * |[8] |BRK1NFEN |EPWM Brake 1 Noise Filter Enable Bit 727 * | | |0 = Noise filter of EPWM Brake 1 Disabled. 728 * | | |1 = Noise filter of EPWM Brake 1 Enabled. 729 * |[11:9] |BRK1NFSEL |Brake 1 Edge Detector Filter Clock Selection 730 * | | |000 = Filter clock = HCLK. 731 * | | |001 = Filter clock = HCLK/2. 732 * | | |010 = Filter clock = HCLK/4. 733 * | | |011 = Filter clock = HCLK/8. 734 * | | |100 = Filter clock = HCLK/16. 735 * | | |101 = Filter clock = HCLK/32. 736 * | | |110 = Filter clock = HCLK/64. 737 * | | |111 = Filter clock = HCLK/128. 738 * |[14:12] |BRK1FCNT |Brake 1 Edge Detector Filter Count 739 * | | |The register bits control the Brake1 filter counter to count from 0 to BRK1FCNT. 740 * |[15] |BRK1PINV |Brake 1 Pin Inverse 741 * | | |0 = brake pin event will be detected if EPWMx_BRAKE1 pin status transfer from low to high in edge-detect, or pin status is high in level-detect. 742 * | | |1 = brake pin event will be detected if EPWMx_BRAKE1 pin status transfer from high to low in edge-detect, or pin status is low in level-detect. 743 * |[16] |BK0SRC |Brake 0 Pin Source Select 744 * | | |For EPWM0 setting: 745 * | | |0 = Brake 0 pin source come from EPWM0_BRAKE0. 746 * | | |1 = Brake 0 pin source come from EPWM1_BRAKE0. 747 * | | |For EPWM1 setting: 748 * | | |0 = Brake 0 pin source come from EPWM1_BRAKE0. 749 * | | |1 = Brake 0 pin source come from EPWM0_BRAKE0. 750 * |[24] |BK1SRC |Brake 1 Pin Source Select 751 * | | |For EPWM0 setting: 752 * | | |0 = Brake 1 pin source come from EPWM0_BRAKE1. 753 * | | |1 = Brake 1 pin source come from EPWM1_BRAKE1. 754 * | | |For EPWM1 setting: 755 * | | |0 = Brake 1 pin source come from EPWM1_BRAKE1. 756 * | | |1 = Brake 1 pin source come from EPWM0_BRAKE1. 757 * @var EPWM_T::FAILBRK 758 * Offset: 0xC4 EPWM System Fail Brake Control Register 759 * --------------------------------------------------------------------------------------------------- 760 * |Bits |Field |Descriptions 761 * | :----: | :----: | :---- | 762 * |[0] |CSSBRKEN |Clock Security System Detection Trigger EPWM Brake Function 0 Enable Bit 763 * | | |0 = Brake Function triggered by CSS detection Disabled. 764 * | | |1 = Brake Function triggered by CSS detection Enabled. 765 * |[1] |BODBRKEN |Brown-out Detection Trigger EPWM Brake Function 0 Enable Bit 766 * | | |0 = Brake Function triggered by BOD Disabled. 767 * | | |1 = Brake Function triggered by BOD Enabled. 768 * |[2] |RAMBRKEN |SRAM Parity Error Detection Trigger EPWM Brake Function 0 Enable Bit 769 * | | |0 = Brake Function triggered by SRAM parity error detection Disabled. 770 * | | |1 = Brake Function triggered by SRAM parity error detection Enabled. 771 * |[3] |CORBRKEN |Core Lockup Detection Trigger EPWM Brake Function 0 Enable Bit 772 * | | |0 = Brake Function triggered by Core lockup detection Disabled. 773 * | | |1 = Brake Function triggered by Core lockup detection Enabled. 774 * @var EPWM_T::BRKCTL[3] 775 * Offset: 0xC8 EPWM Brake Edge Detect Control Register 0/1,2/3,4/5 776 * --------------------------------------------------------------------------------------------------- 777 * |Bits |Field |Descriptions 778 * | :----: | :----: | :---- | 779 * |[0] |CPO0EBEN |Enable ACMP0_O Digital Output As Edge-detect Brake Source (Write Protect) 780 * | | |0 = ACMP0_O as edge-detect brake source Disabled. 781 * | | |1 = ACMP0_O as edge-detect brake source Enabled. 782 * | | |Note: This bit is write protected. Refer toSYS_REGLCTL register. 783 * |[1] |CPO1EBEN |Enable ACMP1_O Digital Output As Edge-detect Brake Source (Write Protect) 784 * | | |0 = ACMP1_O as edge-detect brake source Disabled. 785 * | | |1 = ACMP1_O as edge-detect brake source Enabled. 786 * | | |Note: This bit is write protected. Refer toSYS_REGLCTL register. 787 * |[2] |CPO2EBEN |Enable ACMP2_O Digital Output As Edge-detect Brake Source (Write Protect) 788 * | | |0 = ACMP2_O as edge-detect brake source Disabled. 789 * | | |1 = ACMP2_O as edge-detect brake source Enabled. 790 * | | |Note: This bit is write protected. Refer toSYS_REGLCTL register. 791 * |[3] |CPO3EBEN |Enable ACMP3_O Digital Output As Edge-detect Brake Source (Write Protect) 792 * | | |0 = ACMP3_O as edge-detect brake source Disabled. 793 * | | |1 = ACMP3_O as edge-detect brake source Enabled. 794 * | | |Note: This bit is write protected. Refer toSYS_REGLCTL register. 795 * |[4] |BRKP0EEN |Enable EPWMx_BRAKE0 Pin As Edge-detect Brake Source (Write Protect) 796 * | | |0 = EPWMx_BRAKE0 pin as edge-detect brake source Disabled. 797 * | | |1 = EPWMx_BRAKE0 pin as edge-detect brake source Enabled. 798 * | | |Note: This bit is write protected. Refer toSYS_REGLCTL register. 799 * |[5] |BRKP1EEN |Enable EPWMx_BRAKE1 Pin As Edge-detect Brake Source (Write Protect) 800 * | | |0 = EPWMx_BRAKE1 pin as edge-detect brake source Disabled. 801 * | | |1 = EPWMx_BRAKE1 pin as edge-detect brake source Enabled. 802 * | | |Note: This bit is write protected. Refer toSYS_REGLCTL register. 803 * |[7] |SYSEBEN |Enable System Fail As Edge-detect Brake Source (Write Protect) 804 * | | |0 = System Fail condition as edge-detect brake source Disabled. 805 * | | |1 = System Fail condition as edge-detect brake source Enabled. 806 * | | |Note: This bit is write protected. Refer toSYS_REGLCTL register. 807 * |[8] |CPO0LBEN |Enable ACMP0_O Digital Output As Level-detect Brake Source (Write Protect) 808 * | | |0 = ACMP0_O as level-detect brake source Disabled. 809 * | | |1 = ACMP0_O as level-detect brake source Enabled. 810 * | | |Note: This bit is write protected. Refer toSYS_REGLCTL register. 811 * |[9] |CPO1LBEN |Enable ACMP1_O Digital Output As Level-detect Brake Source (Write Protect) 812 * | | |0 = ACMP1_O as level-detect brake source Disabled. 813 * | | |1 = ACMP1_O as level-detect brake source Enabled. 814 * | | |Note: This bit is write protected. Refer toSYS_REGLCTL register. 815 * |[10] |CPO2LBEN |Enable ACMP2_O Digital Output As Level-detect Brake Source (Write Protect) 816 * | | |0 = ACMP2_O as level-detect brake source Disabled. 817 * | | |1 = ACMP2_O as level-detect brake source Enabled. 818 * | | |Note: This bit is write protected. Refer toSYS_REGLCTL register. 819 * |[11] |CPO3LBEN |Enable ACMP3_O Digital Output As Level-detect Brake Source (Write Protect) 820 * | | |0 = ACMP3_O as level-detect brake source Disabled. 821 * | | |1 = ACMP3_O as level-detect brake source Enabled. 822 * | | |Note: This bit is write protected. Refer toSYS_REGLCTL register. 823 * |[12] |BRKP0LEN |Enable BKP0 Pin As Level-detect Brake Source (Write Protect) 824 * | | |0 = EPWMx_BRAKE0 pin as level-detect brake source Disabled. 825 * | | |1 = EPWMx_BRAKE0 pin as level-detect brake source Enabled. 826 * | | |Note: This bit is write protected. Refer toSYS_REGLCTL register. 827 * |[13] |BRKP1LEN |Enable BKP1 Pin As Level-detect Brake Source (Write Protect) 828 * | | |0 = EPWMx_BRAKE1 pin as level-detect brake source Disabled. 829 * | | |1 = EPWMx_BRAKE1 pin as level-detect brake source Enabled. 830 * | | |Note: This bit is write protected. Refer toSYS_REGLCTL register. 831 * |[15] |SYSLBEN |Enable System Fail As Level-detect Brake Source (Write Protect) 832 * | | |0 = System Fail condition as level-detect brake source Disabled. 833 * | | |1 = System Fail condition as level-detect brake source Enabled. 834 * | | |Note: This bit is write protected. Refer toSYS_REGLCTL register. 835 * |[17:16] |BRKAEVEN |EPWM Brake Action Select for Even Channel (Write Protect) 836 * | | |00 = EPWMx brake event will not affect even channels output. 837 * | | |01 = EPWM even channel output tri-state when EPWMx brake event happened. 838 * | | |10 = EPWM even channel output low level when EPWMx brake event happened. 839 * | | |11 = EPWM even channel output high level when EPWMx brake event happened. 840 * | | |Note: This bit is write protected. Refer toSYS_REGLCTL register. 841 * |[19:18] |BRKAODD |EPWM Brake Action Select for Odd Channel (Write Protect) 842 * | | |00 = EPWMx brake event will not affect odd channels output. 843 * | | |01 = EPWM odd channel output tri-state when EPWMx brake event happened. 844 * | | |10 = EPWM odd channel output low level when EPWMx brake event happened. 845 * | | |11 = EPWM odd channel output high level when EPWMx brake event happened. 846 * | | |Note: This bit is write protected. Refer to SYS_REGLCTL register. 847 * |[20] |EADC0EBEN |Enable EADC0 Result Monitor as Edge-detect Brake Source (Write Protect) 848 * | | |0 = EADC0RM as edge-detect brake source Disabled. 849 * | | |1 = EADC0RM as edge-detect brake source Enabled. 850 * | | |Note: This bit is write protected. Refer to SYS_REGLCTL register. 851 * |[21] |EADC1EBEN |Enable EADC1 Result Monitor as Edge-detect Brake Source (Write Protect) 852 * | | |0 = EADC1RM as edge-detect brake source Disabled. 853 * | | |1 = EADC1RM as edge-detect brake source Enabled. 854 * | | |Note: This bit is write protected. Refer to SYS_REGLCTL register. 855 * |[22] |EADC2EBEN |Enable EADC2 Result Monitor as Edge-detect Brake Source (Write Protect) 856 * | | |0 = EADC1RM as edge-detect brake source Disabled. 857 * | | |1 = EADC1RM as edge-detect brake source Enabled. 858 * | | |Note: This bit is write protected. Refer to SYS_REGLCTL register. 859 * |[28] |EADC0LBEN |Enable EADC0 Result Monitor as Level-detect Brake Source (Write Protect) 860 * | | |0 = EADC0RM as level-detect brake source Disabled. 861 * | | |1 = EADC0RM as level-detect brake source Enabled. 862 * | | |Note: This bit is write protected. Refer to SYS_REGLCTL register. 863 * |[29] |EADC1LBEN |Enable EADC1 Result Monitor as Level-detect Brake Source (Write Protect) 864 * | | |0 = EADC1RM as level-detect brake source Disabled. 865 * | | |1 = EADC1RM as level-detect brake source Enabled. 866 * | | |Note: This bit is write protected. Refer to SYS_REGLCTL register. 867 * |[30] |EADC2LBEN |Enable EADC2 Result Monitor as Level-detect Brake Source (Write Protect) 868 * | | |0 = EADC2RM as level-detect brake source Disabled. 869 * | | |1 = EADC2RM as level-detect brake source Enabled. 870 * | | |Note: This bit is write protected. Refer to SYS_REGLCTL register. 871 * @var EPWM_T::POLCTL 872 * Offset: 0xD4 EPWM Pin Polar Inverse Register 873 * --------------------------------------------------------------------------------------------------- 874 * |Bits |Field |Descriptions 875 * | :----: | :----: | :---- | 876 * |[0] |PINV0 |EPWM PIN Polar Inverse Control 877 * | | |The register controls polarity state of EPWMx_CHn output pin. 878 * | | |0 = EPWMx_CHn output pin polar inverse Disabled. 879 * | | |1 = EPWMx_CHn output pin polar inverse Enabled. 880 * |[1] |PINV1 |EPWM PIN Polar Inverse Control 881 * | | |The register controls polarity state of EPWMx_CHn output pin. 882 * | | |0 = EPWMx_CHn output pin polar inverse Disabled. 883 * | | |1 = EPWMx_CHn output pin polar inverse Enabled. 884 * |[2] |PINV2 |EPWM PIN Polar Inverse Control 885 * | | |The register controls polarity state of EPWMx_CHn output pin. 886 * | | |0 = EPWMx_CHn output pin polar inverse Disabled. 887 * | | |1 = EPWMx_CHn output pin polar inverse Enabled. 888 * |[3] |PINV3 |EPWM PIN Polar Inverse Control 889 * | | |The register controls polarity state of EPWMx_CHn output pin. 890 * | | |0 = EPWMx_CHn output pin polar inverse Disabled. 891 * | | |1 = EPWMx_CHn output pin polar inverse Enabled. 892 * |[4] |PINV4 |EPWM PIN Polar Inverse Control 893 * | | |The register controls polarity state of EPWMx_CHn output pin. 894 * | | |0 = EPWMx_CHn output pin polar inverse Disabled. 895 * | | |1 = EPWMx_CHn output pin polar inverse Enabled. 896 * |[5] |PINV5 |EPWM PIN Polar Inverse Control 897 * | | |The register controls polarity state of EPWMx_CHn output pin. 898 * | | |0 = EPWMx_CHn output pin polar inverse Disabled. 899 * | | |1 = EPWMx_CHn output pin polar inverse Enabled. 900 * @var EPWM_T::POEN 901 * Offset: 0xD8 EPWM Output Enable Register 902 * --------------------------------------------------------------------------------------------------- 903 * |Bits |Field |Descriptions 904 * | :----: | :----: | :---- | 905 * |[0] |POEN0 |EPWM Pin Output Enable Bits 906 * | | |0 = EPWMx_CHn pin at tri-state. 907 * | | |1 = EPWMx_CHn pin in output mode. 908 * |[1] |POEN1 |EPWM Pin Output Enable Bits 909 * | | |0 = EPWMx_CHn pin at tri-state. 910 * | | |1 = EPWMx_CHn pin in output mode. 911 * |[2] |POEN2 |EPWM Pin Output Enable Bits 912 * | | |0 = EPWMx_CHn pin at tri-state. 913 * | | |1 = EPWMx_CHn pin in output mode. 914 * |[3] |POEN3 |EPWM Pin Output Enable Bits 915 * | | |0 = EPWMx_CHn pin at tri-state. 916 * | | |1 = EPWMx_CHn pin in output mode. 917 * |[4] |POEN4 |EPWM Pin Output Enable Bits 918 * | | |0 = EPWMx_CHn pin at tri-state. 919 * | | |1 = EPWMx_CHn pin in output mode. 920 * |[5] |POEN5 |EPWM Pin Output Enable Bits 921 * | | |0 = EPWMx_CHn pin at tri-state. 922 * | | |1 = EPWMx_CHn pin in output mode. 923 * @var EPWM_T::SWBRK 924 * Offset: 0xDC EPWM Software Brake Control Register 925 * --------------------------------------------------------------------------------------------------- 926 * |Bits |Field |Descriptions 927 * | :----: | :----: | :---- | 928 * |[0] |BRKETRG0 |EPWM Edge Brake Software Trigger (Write Only) (Write Protect) 929 * | | |Write 1 to this bit will trigger edge brake, and set BRKEIFn to 1 in EPWM_INTSTS1 register. 930 * | | |Note: This bit is write protected. Refer to SYS_REGLCTL register. 931 * |[1] |BRKETRG2 |EPWM Edge Brake Software Trigger (Write Only) (Write Protect) 932 * | | |Write 1 to this bit will trigger edge brake, and set BRKEIFn to 1 in EPWM_INTSTS1 register. 933 * | | |Note: This bit is write protected. Refer to SYS_REGLCTL register. 934 * |[2] |BRKETRG4 |EPWM Edge Brake Software Trigger (Write Only) (Write Protect) 935 * | | |Write 1 to this bit will trigger edge brake, and set BRKEIFn to 1 in EPWM_INTSTS1 register. 936 * | | |Note: This bit is write protected. Refer to SYS_REGLCTL register. 937 * |[8] |BRKLTRG0 |EPWM Level Brake Software Trigger (Write Only) (Write Protect) 938 * | | |Write 1 to this bit will trigger level brake, and set BRKLIFn to 1 in EPWM_INTSTS1 register. 939 * | | |Note: This bit is write protected. Refer to SYS_REGLCTL register. 940 * |[9] |BRKLTRG2 |EPWM Level Brake Software Trigger (Write Only) (Write Protect) 941 * | | |Write 1 to this bit will trigger level brake, and set BRKLIFn to 1 in EPWM_INTSTS1 register. 942 * | | |Note: This bit is write protected. Refer to SYS_REGLCTL register. 943 * |[10] |BRKLTRG4 |EPWM Level Brake Software Trigger (Write Only) (Write Protect) 944 * | | |Write 1 to this bit will trigger level brake, and set BRKLIFn to 1 in EPWM_INTSTS1 register. 945 * | | |Note: This bit is write protected. Refer to SYS_REGLCTL register. 946 * @var EPWM_T::INTEN0 947 * Offset: 0xE0 EPWM Interrupt Enable Register 0 948 * --------------------------------------------------------------------------------------------------- 949 * |Bits |Field |Descriptions 950 * | :----: | :----: | :---- | 951 * |[0] |ZIEN0 |EPWM Zero Point Interrupt Enable Bits 952 * | | |0 = Zero point interrupt Disabled. 953 * | | |1 = Zero point interrupt Enabled. 954 * | | |Note: Odd channels will read always 0 at complementary mode. 955 * |[1] |ZIEN1 |EPWM Zero Point Interrupt Enable Bits 956 * | | |0 = Zero point interrupt Disabled. 957 * | | |1 = Zero point interrupt Enabled. 958 * | | |Note: Odd channels will read always 0 at complementary mode. 959 * |[2] |ZIEN2 |EPWM Zero Point Interrupt Enable Bits 960 * | | |0 = Zero point interrupt Disabled. 961 * | | |1 = Zero point interrupt Enabled. 962 * | | |Note: Odd channels will read always 0 at complementary mode. 963 * |[3] |ZIEN3 |EPWM Zero Point Interrupt Enable Bits 964 * | | |0 = Zero point interrupt Disabled. 965 * | | |1 = Zero point interrupt Enabled. 966 * | | |Note: Odd channels will read always 0 at complementary mode. 967 * |[4] |ZIEN4 |EPWM Zero Point Interrupt Enable Bits 968 * | | |0 = Zero point interrupt Disabled. 969 * | | |1 = Zero point interrupt Enabled. 970 * | | |Note: Odd channels will read always 0 at complementary mode. 971 * |[5] |ZIEN5 |EPWM Zero Point Interrupt Enable Bits 972 * | | |0 = Zero point interrupt Disabled. 973 * | | |1 = Zero point interrupt Enabled. 974 * | | |Note: Odd channels will read always 0 at complementary mode. 975 * |[8] |PIEN0 |EPWM Period Point Interrupt Enable Bits 976 * | | |0 = Period point interrupt Disabled. 977 * | | |1 = Period point interrupt Enabled. 978 * | | |Note1: When up-down counter type period point means center point. 979 * | | |Note2: Odd channels will read always 0 at complementary mode. 980 * |[9] |PIEN1 |EPWM Period Point Interrupt Enable Bits 981 * | | |0 = Period point interrupt Disabled. 982 * | | |1 = Period point interrupt Enabled. 983 * | | |Note1: When up-down counter type period point means center point. 984 * | | |Note2: Odd channels will read always 0 at complementary mode. 985 * |[10] |PIEN2 |EPWM Period Point Interrupt Enable Bits 986 * | | |0 = Period point interrupt Disabled. 987 * | | |1 = Period point interrupt Enabled. 988 * | | |Note1: When up-down counter type period point means center point. 989 * | | |Note2: Odd channels will read always 0 at complementary mode. 990 * |[11] |PIEN3 |EPWM Period Point Interrupt Enable Bits 991 * | | |0 = Period point interrupt Disabled. 992 * | | |1 = Period point interrupt Enabled. 993 * | | |Note1: When up-down counter type period point means center point. 994 * | | |Note2: Odd channels will read always 0 at complementary mode. 995 * |[12] |PIEN4 |EPWM Period Point Interrupt Enable Bits 996 * | | |0 = Period point interrupt Disabled. 997 * | | |1 = Period point interrupt Enabled. 998 * | | |Note1: When up-down counter type period point means center point. 999 * | | |Note2: Odd channels will read always 0 at complementary mode. 1000 * |[13] |PIEN5 |EPWM Period Point Interrupt Enable Bits 1001 * | | |0 = Period point interrupt Disabled. 1002 * | | |1 = Period point interrupt Enabled. 1003 * | | |Note1: When up-down counter type period point means center point. 1004 * | | |Note2: Odd channels will read always 0 at complementary mode. 1005 * |[16] |CMPUIEN0 |EPWM Compare Up Count Interrupt Enable Bits 1006 * | | |0 = Compare up count interrupt Disabled. 1007 * | | |1 = Compare up count interrupt Enabled. 1008 * | | |Note: In complementary mode, CMPUIEN1, 3, 5 is used as another CMPUIEN for channel 0, 2, 4. 1009 * |[17] |CMPUIEN1 |EPWM Compare Up Count Interrupt Enable Bits 1010 * | | |0 = Compare up count interrupt Disabled. 1011 * | | |1 = Compare up count interrupt Enabled. 1012 * | | |Note: In complementary mode, CMPUIEN1, 3, 5 is used as another CMPUIEN for channel 0, 2, 4. 1013 * |[18] |CMPUIEN2 |EPWM Compare Up Count Interrupt Enable Bits 1014 * | | |0 = Compare up count interrupt Disabled. 1015 * | | |1 = Compare up count interrupt Enabled. 1016 * | | |Note: In complementary mode, CMPUIEN1, 3, 5 is used as another CMPUIEN for channel 0, 2, 4. 1017 * |[19] |CMPUIEN3 |EPWM Compare Up Count Interrupt Enable Bits 1018 * | | |0 = Compare up count interrupt Disabled. 1019 * | | |1 = Compare up count interrupt Enabled. 1020 * | | |Note: In complementary mode, CMPUIEN1, 3, 5 is used as another CMPUIEN for channel 0, 2, 4. 1021 * |[20] |CMPUIEN4 |EPWM Compare Up Count Interrupt Enable Bits 1022 * | | |0 = Compare up count interrupt Disabled. 1023 * | | |1 = Compare up count interrupt Enabled. 1024 * | | |Note: In complementary mode, CMPUIEN1, 3, 5 is used as another CMPUIEN for channel 0, 2, 4. 1025 * |[21] |CMPUIEN5 |EPWM Compare Up Count Interrupt Enable Bits 1026 * | | |0 = Compare up count interrupt Disabled. 1027 * | | |1 = Compare up count interrupt Enabled. 1028 * | | |Note: In complementary mode, CMPUIEN1, 3, 5 is used as another CMPUIEN for channel 0, 2, 4. 1029 * |[24] |CMPDIEN0 |EPWM Compare Down Count Interrupt Enable Bits 1030 * | | |0 = Compare down count interrupt Disabled. 1031 * | | |1 = Compare down count interrupt Enabled. 1032 * | | |Note: In complementary mode, CMPDIEN1, 3, 5 is used as another CMPDIEN for channel 0, 2, 4. 1033 * |[25] |CMPDIEN1 |EPWM Compare Down Count Interrupt Enable Bits 1034 * | | |0 = Compare down count interrupt Disabled. 1035 * | | |1 = Compare down count interrupt Enabled. 1036 * | | |Note: In complementary mode, CMPDIEN1, 3, 5 is used as another CMPDIEN for channel 0, 2, 4. 1037 * |[26] |CMPDIEN2 |EPWM Compare Down Count Interrupt Enable Bits 1038 * | | |0 = Compare down count interrupt Disabled. 1039 * | | |1 = Compare down count interrupt Enabled. 1040 * | | |Note: In complementary mode, CMPDIEN1, 3, 5 is used as another CMPDIEN for channel 0, 2, 4. 1041 * |[27] |CMPDIEN3 |EPWM Compare Down Count Interrupt Enable Bits 1042 * | | |0 = Compare down count interrupt Disabled. 1043 * | | |1 = Compare down count interrupt Enabled. 1044 * | | |Note: In complementary mode, CMPDIEN1, 3, 5 is used as another CMPDIEN for channel 0, 2, 4. 1045 * |[28] |CMPDIEN4 |EPWM Compare Down Count Interrupt Enable Bits 1046 * | | |0 = Compare down count interrupt Disabled. 1047 * | | |1 = Compare down count interrupt Enabled. 1048 * | | |Note: In complementary mode, CMPDIEN1, 3, 5 is used as another CMPDIEN for channel 0, 2, 4. 1049 * |[29] |CMPDIEN5 |EPWM Compare Down Count Interrupt Enable Bits 1050 * | | |0 = Compare down count interrupt Disabled. 1051 * | | |1 = Compare down count interrupt Enabled. 1052 * | | |Note: In complementary mode, CMPDIEN1, 3, 5 is used as another CMPDIEN for channel 0, 2, 4. 1053 * @var EPWM_T::INTEN1 1054 * Offset: 0xE4 EPWM Interrupt Enable Register 1 1055 * --------------------------------------------------------------------------------------------------- 1056 * |Bits |Field |Descriptions 1057 * | :----: | :----: | :---- | 1058 * |[0] |BRKEIEN0_1|EPWM Edge-detect Brake Interrupt Enable for Channel0/1 (Write Protect) 1059 * | | |0 = Edge-detect Brake interrupt for channel0/1 Disabled. 1060 * | | |1 = Edge-detect Brake interrupt for channel0/1 Enabled. 1061 * | | |Note: This bit is write protected. Refer toSYS_REGLCTL register. 1062 * |[1] |BRKEIEN2_3|EPWM Edge-detect Brake Interrupt Enable for Channel2/3 (Write Protect) 1063 * | | |0 = Edge-detect Brake interrupt for channel2/3 Disabled. 1064 * | | |1 = Edge-detect Brake interrupt for channel2/3 Enabled. 1065 * | | |Note: This bit is write protected. Refer toSYS_REGLCTL register. 1066 * |[2] |BRKEIEN4_5|EPWM Edge-detect Brake Interrupt Enable for Channel4/5 (Write Protect) 1067 * | | |0 = Edge-detect Brake interrupt for channel4/5 Disabled. 1068 * | | |1 = Edge-detect Brake interrupt for channel4/5 Enabled. 1069 * | | |Note: This bit is write protected. Refer toSYS_REGLCTL register. 1070 * |[8] |BRKLIEN0_1|EPWM Level-detect Brake Interrupt Enable for Channel0/1 (Write Protect) 1071 * | | |0 = Level-detect Brake interrupt for channel0/1 Disabled. 1072 * | | |1 = Level-detect Brake interrupt for channel0/1 Enabled. 1073 * | | |Note: This bit is write protected. Refer toSYS_REGLCTL register. 1074 * |[9] |BRKLIEN2_3|EPWM Level-detect Brake Interrupt Enable for Channel2/3 (Write Protect) 1075 * | | |0 = Level-detect Brake interrupt for channel2/3 Disabled. 1076 * | | |1 = Level-detect Brake interrupt for channel2/3 Enabled. 1077 * | | |Note: This bit is write protected. Refer toSYS_REGLCTL register. 1078 * |[10] |BRKLIEN4_5|EPWM Level-detect Brake Interrupt Enable for Channel4/5 (Write Protect) 1079 * | | |0 = Level-detect Brake interrupt for channel4/5 Disabled. 1080 * | | |1 = Level-detect Brake interrupt for channel4/5 Enabled. 1081 * | | |Note: This bit is write protected. Refer toSYS_REGLCTL register. 1082 * @var EPWM_T::INTSTS0 1083 * Offset: 0xE8 EPWM Interrupt Flag Register 0 1084 * --------------------------------------------------------------------------------------------------- 1085 * |Bits |Field |Descriptions 1086 * | :----: | :----: | :---- | 1087 * |[0] |ZIF0 |EPWM Zero Point Interrupt Flag 1088 * | | |This bit is set by hardware when EPWM counter reaches 0. 1089 * | | |Note: This bit can be cleared to 0 by software writing 1 1090 * |[1] |ZIF1 |EPWM Zero Point Interrupt Flag 1091 * | | |This bit is set by hardware when EPWM counter reaches 0. 1092 * | | |Note: This bit can be cleared to 0 by software writing 1 1093 * |[2] |ZIF2 |EPWM Zero Point Interrupt Flag 1094 * | | |This bit is set by hardware when EPWM counter reaches 0. 1095 * | | |Note: This bit can be cleared to 0 by software writing 1 1096 * |[3] |ZIF3 |EPWM Zero Point Interrupt Flag 1097 * | | |This bit is set by hardware when EPWM counter reaches 0. 1098 * | | |Note: This bit can be cleared to 0 by software writing 1 1099 * |[4] |ZIF4 |EPWM Zero Point Interrupt Flag 1100 * | | |This bit is set by hardware when EPWM counter reaches 0. 1101 * | | |Note: This bit can be cleared to 0 by software writing 1 1102 * |[5] |ZIF5 |EPWM Zero Point Interrupt Flag 1103 * | | |This bit is set by hardware when EPWM counter reaches 0. 1104 * | | |Note: This bit can be cleared to 0 by software writing 1 1105 * |[8] |PIF0 |EPWM Period Point Interrupt Flag 1106 * | | |This bit is set by hardware when EPWM counter reaches EPWM_PERIODn. 1107 * | | |Note: This bit can be cleared to 0 by software writing 1. 1108 * |[9] |PIF1 |EPWM Period Point Interrupt Flag 1109 * | | |This bit is set by hardware when EPWM counter reaches EPWM_PERIODn. 1110 * | | |Note: This bit can be cleared to 0 by software writing 1. 1111 * |[10] |PIF2 |EPWM Period Point Interrupt Flag 1112 * | | |This bit is set by hardware when EPWM counter reaches EPWM_PERIODn. 1113 * | | |Note: This bit can be cleared to 0 by software writing 1. 1114 * |[11] |PIF3 |EPWM Period Point Interrupt Flag 1115 * | | |This bit is set by hardware when EPWM counter reaches EPWM_PERIODn. 1116 * | | |Note: This bit can be cleared to 0 by software writing 1. 1117 * |[12] |PIF4 |EPWM Period Point Interrupt Flag 1118 * | | |This bit is set by hardware when EPWM counter reaches EPWM_PERIODn. 1119 * | | |Note: This bit can be cleared to 0 by software writing 1. 1120 * |[13] |PIF5 |EPWM Period Point Interrupt Flag 1121 * | | |This bit is set by hardware when EPWM counter reaches EPWM_PERIODn. 1122 * | | |Note: This bit can be cleared to 0 by software writing 1. 1123 * |[16] |CMPUIF0 |EPWM Compare Up Count Interrupt Flag 1124 * | | |Flag is set by hardware when EPWM counter up count and reaches EPWM_CMPDATn, software can clear this bit by writing 1 to it. 1125 * | | |Note: In complementary mode, CMPUIF1, 3, 5 is used as another CMPUIF for channel 0, 2, 4. 1126 * |[17] |CMPUIF1 |EPWM Compare Up Count Interrupt Flag 1127 * | | |Flag is set by hardware when EPWM counter up count and reaches EPWM_CMPDATn, software can clear this bit by writing 1 to it. 1128 * | | |Note: In complementary mode, CMPUIF1, 3, 5 is used as another CMPUIF for channel 0, 2, 4. 1129 * |[18] |CMPUIF2 |EPWM Compare Up Count Interrupt Flag 1130 * | | |Flag is set by hardware when EPWM counter up count and reaches EPWM_CMPDATn, software can clear this bit by writing 1 to it. 1131 * | | |Note: In complementary mode, CMPUIF1, 3, 5 is used as another CMPUIF for channel 0, 2, 4. 1132 * |[19] |CMPUIF3 |EPWM Compare Up Count Interrupt Flag 1133 * | | |Flag is set by hardware when EPWM counter up count and reaches EPWM_CMPDATn, software can clear this bit by writing 1 to it. 1134 * | | |Note: In complementary mode, CMPUIF1, 3, 5 is used as another CMPUIF for channel 0, 2, 4. 1135 * |[20] |CMPUIF4 |EPWM Compare Up Count Interrupt Flag 1136 * | | |Flag is set by hardware when EPWM counter up count and reaches EPWM_CMPDATn, software can clear this bit by writing 1 to it. 1137 * | | |Note: In complementary mode, CMPUIF1, 3, 5 is used as another CMPUIF for channel 0, 2, 4. 1138 * |[21] |CMPUIF5 |EPWM Compare Up Count Interrupt Flag 1139 * | | |Flag is set by hardware when EPWM counter up count and reaches EPWM_CMPDATn, software can clear this bit by writing 1 to it. 1140 * | | |Note: In complementary mode, CMPUIF1, 3, 5 is used as another CMPUIF for channel 0, 2, 4. 1141 * |[24] |CMPDIF0 |EPWM Compare Down Count Interrupt Flag 1142 * | | |Flag is set by hardware when EPWM counter down count and reaches EPWM_CMPDATn, software can clear this bit by writing 1 to it. 1143 * | | |Note: In complementary mode, CMPDIF1, 3, 5 is used as another CMPDIF for channel 0, 2, 4. 1144 * |[25] |CMPDIF1 |EPWM Compare Down Count Interrupt Flag 1145 * | | |Flag is set by hardware when EPWM counter down count and reaches EPWM_CMPDATn, software can clear this bit by writing 1 to it. 1146 * | | |Note: In complementary mode, CMPDIF1, 3, 5 is used as another CMPDIF for channel 0, 2, 4. 1147 * |[26] |CMPDIF2 |EPWM Compare Down Count Interrupt Flag 1148 * | | |Flag is set by hardware when EPWM counter down count and reaches EPWM_CMPDATn, software can clear this bit by writing 1 to it. 1149 * | | |Note: In complementary mode, CMPDIF1, 3, 5 is used as another CMPDIF for channel 0, 2, 4. 1150 * |[27] |CMPDIF3 |EPWM Compare Down Count Interrupt Flag 1151 * | | |Flag is set by hardware when EPWM counter down count and reaches EPWM_CMPDATn, software can clear this bit by writing 1 to it. 1152 * | | |Note: In complementary mode, CMPDIF1, 3, 5 is used as another CMPDIF for channel 0, 2, 4. 1153 * |[28] |CMPDIF4 |EPWM Compare Down Count Interrupt Flag 1154 * | | |Flag is set by hardware when EPWM counter down count and reaches EPWM_CMPDATn, software can clear this bit by writing 1 to it. 1155 * | | |Note: In complementary mode, CMPDIF1, 3, 5 is used as another CMPDIF for channel 0, 2, 4. 1156 * |[29] |CMPDIF5 |EPWM Compare Down Count Interrupt Flag 1157 * | | |Flag is set by hardware when EPWM counter down count and reaches EPWM_CMPDATn, software can clear this bit by writing 1 to it. 1158 * | | |Note: In complementary mode, CMPDIF1, 3, 5 is used as another CMPDIF for channel 0, 2, 4. 1159 * @var EPWM_T::INTSTS1 1160 * Offset: 0xEC EPWM Interrupt Flag Register 1 1161 * --------------------------------------------------------------------------------------------------- 1162 * |Bits |Field |Descriptions 1163 * | :----: | :----: | :---- | 1164 * |[0] |BRKEIF0 |EPWM Channel0 Edge-detect Brake Interrupt Flag (Write Protect) 1165 * | | |0 = EPWM channel0 edge-detect brake event do not happened. 1166 * | | |1 = When EPWM channel0 edge-detect brake event happened, this bit is set to 1, writing 1 to clear. 1167 * | | |Note: This bit is write protected. Refer toSYS_REGLCTL register. 1168 * |[1] |BRKEIF1 |EPWM Channel1 Edge-detect Brake Interrupt Flag (Write Protect) 1169 * | | |0 = EPWM channel1 edge-detect brake event do not happened. 1170 * | | |1 = When EPWM channel1 edge-detect brake event happened, this bit is set to 1, writing 1 to clear. 1171 * | | |Note: This bit is write protected. Refer toSYS_REGLCTL register. 1172 * |[2] |BRKEIF2 |EPWM Channel2 Edge-detect Brake Interrupt Flag (Write Protect) 1173 * | | |0 = EPWM channel2 edge-detect brake event do not happened. 1174 * | | |1 = When EPWM channel2 edge-detect brake event happened, this bit is set to 1, writing 1 to clear. 1175 * | | |Note: This bit is write protected. Refer toSYS_REGLCTL register. 1176 * |[3] |BRKEIF3 |EPWM Channel3 Edge-detect Brake Interrupt Flag (Write Protect) 1177 * | | |0 = EPWM channel3 edge-detect brake event do not happened. 1178 * | | |1 = When EPWM channel3 edge-detect brake event happened, this bit is set to 1, writing 1 to clear. 1179 * | | |Note: This bit is write protected. Refer toSYS_REGLCTL register. 1180 * |[4] |BRKEIF4 |EPWM Channel4 Edge-detect Brake Interrupt Flag (Write Protect) 1181 * | | |0 = EPWM channel4 edge-detect brake event do not happened. 1182 * | | |1 = When EPWM channel4 edge-detect brake event happened, this bit is set to 1, writing 1 to clear. 1183 * | | |Note: This bit is write protected. Refer toSYS_REGLCTL register. 1184 * |[5] |BRKEIF5 |EPWM Channel5 Edge-detect Brake Interrupt Flag (Write Protect) 1185 * | | |0 = EPWM channel5 edge-detect brake event do not happened. 1186 * | | |1 = When EPWM channel5 edge-detect brake event happened, this bit is set to 1, writing 1 to clear. 1187 * | | |Note: This bit is write protected. Refer toSYS_REGLCTL register. 1188 * |[8] |BRKLIF0 |EPWM Channel0 Level-detect Brake Interrupt Flag (Write Protect) 1189 * | | |0 = EPWM channel0 level-detect brake event do not happened. 1190 * | | |1 = When EPWM channel0 level-detect brake event happened, this bit is set to 1, writing 1 to clear. 1191 * | | |Note: This bit is write protected. Refer toSYS_REGLCTL register. 1192 * |[9] |BRKLIF1 |EPWM Channel1 Level-detect Brake Interrupt Flag (Write Protect) 1193 * | | |0 = EPWM channel1 level-detect brake event do not happened. 1194 * | | |1 = When EPWM channel1 level-detect brake event happened, this bit is set to 1, writing 1 to clear. 1195 * | | |Note: This bit is write protected. Refer toSYS_REGLCTL register. 1196 * |[10] |BRKLIF2 |EPWM Channel2 Level-detect Brake Interrupt Flag (Write Protect) 1197 * | | |0 = EPWM channel2 level-detect brake event do not happened. 1198 * | | |1 = When EPWM channel2 level-detect brake event happened, this bit is set to 1, writing 1 to clear. 1199 * | | |Note: This bit is write protected. Refer toSYS_REGLCTL register. 1200 * |[11] |BRKLIF3 |EPWM Channel3 Level-detect Brake Interrupt Flag (Write Protect) 1201 * | | |0 = EPWM channel3 level-detect brake event do not happened. 1202 * | | |1 = When EPWM channel3 level-detect brake event happened, this bit is set to 1, writing 1 to clear. 1203 * | | |Note: This bit is write protected. Refer toSYS_REGLCTL register. 1204 * |[12] |BRKLIF4 |EPWM Channel4 Level-detect Brake Interrupt Flag (Write Protect) 1205 * | | |0 = EPWM channel4 level-detect brake event do not happened. 1206 * | | |1 = When EPWM channel4 level-detect brake event happened, this bit is set to 1, writing 1 to clear. 1207 * | | |Note: This bit is write protected. Refer toSYS_REGLCTL register. 1208 * |[13] |BRKLIF5 |EPWM Channel5 Level-detect Brake Interrupt Flag (Write Protect) 1209 * | | |0 = EPWM channel5 level-detect brake event do not happened. 1210 * | | |1 = When EEPWM channel5 level-detect brake event happened, this bit is set to 1, writing 1 to clear. 1211 * | | |Note: This bit is write protected. Refer toSYS_REGLCTL register. 1212 * |[16] |BRKESTS0 |EPWM Channel0 Edge-detect Brake Status (Read Only) 1213 * | | |0 = EPWM channel0 edge-detect brake state is released. 1214 * | | |1 = When EPWM channel0 edge-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the EPWM channel0 at brake state, writing 1 to clear. 1215 * | | |Note: This bit is read only and auto cleared by hardware 1216 * | | |When edge-detect brake interrupt flag is cleared, EPWM will release brake state until current EPWM period finished 1217 * | | |The EPWM waveform will start output from next full EPWM period. 1218 * |[17] |BRKESTS1 |EPWM Channel1 Edge-detect Brake Status (Read Only) 1219 * | | |0 = EPWM channel1 edge-detect brake state is released. 1220 * | | |1 = When EPWM channel1 edge-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the EPWM channel1 at brake state, writing 1 to clear. 1221 * | | |Note: This bit is read only and auto cleared by hardware 1222 * | | |When edge-detect brake interrupt flag is cleared, EPWM will release brake state until current EPWM period finished 1223 * | | |The EPWM waveform will start output from next full EPWM period. 1224 * |[18] |BRKESTS2 |EPWM Channel2 Edge-detect Brake Status (Read Only) 1225 * | | |0 = EPWM channel2 edge-detect brake state is released. 1226 * | | |1 = When EPWM channel2 edge-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the EPWM channel2 at brake state, writing 1 to clear. 1227 * | | |Note: This bit is read only and auto cleared by hardware 1228 * | | |When edge-detect brake interrupt flag is cleared, EPWM will release brake state until current EPWM period finished 1229 * | | |The EPWM waveform will start output from next full EPWM period. 1230 * |[19] |BRKESTS3 |EPWM Channel3 Edge-detect Brake Status (Read Only) 1231 * | | |0 = EPWM channel3 edge-detect brake state is released. 1232 * | | |1 = When EPWM channel3 edge-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the EPWM channel3 at brake state, writing 1 to clear. 1233 * | | |Note: This bit is read only and auto cleared by hardware 1234 * | | |When edge-detect brake interrupt flag is cleared, EPWM will release brake state until current EPWM period finished 1235 * | | |The EPWM waveform will start output from next full EPWM period. 1236 * |[20] |BRKESTS4 |EPWM Channel4 Edge-detect Brake Status (Read Only) 1237 * | | |0 = EPWM channel4 edge-detect brake state is released. 1238 * | | |1 = When EPWM channel4 edge-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the EPWM channel4 at brake state, writing 1 to clear. 1239 * | | |Note: This bit is read only and auto cleared by hardware 1240 * | | |When edge-detect brake interrupt flag is cleared, EPWM will release brake state until current EPWM period finished 1241 * | | |The EPWM waveform will start output from next full EPWM period. 1242 * |[21] |BRKESTS5 |EPWM Channel5 Edge-detect Brake Status (Read Only) 1243 * | | |0 = EPWM channel5 edge-detect brake state is released. 1244 * | | |1 = When EPWM channel5 edge-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the EPWM channel5 at brake state, writing 1 to clear. 1245 * | | |Note: This bit is read only and auto cleared by hardware 1246 * | | |When edge-detect brake interrupt flag is cleared, EPWM will release brake state until current EPWM period finished 1247 * | | |The EPWM waveform will start output from next full EPWM period. 1248 * |[24] |BRKLSTS0 |EPWM Channel0 Level-detect Brake Status (Read Only) 1249 * | | |0 = EPWM channel0 level-detect brake state is released. 1250 * | | |1 = When EPWM channel0 level-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the EPWM channel0 at brake state. 1251 * | | |Note: This bit is read only and auto cleared by hardware 1252 * | | |When enabled brake source return to high level, EPWM will release brake state until current EPWM period finished 1253 * | | |The EPWM waveform will start output from next full EPWM period. 1254 * |[25] |BRKLSTS1 |EPWM Channel1 Level-detect Brake Status (Read Only) 1255 * | | |0 = EPWM channel1 level-detect brake state is released. 1256 * | | |1 = When EPWM channel1 level-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the EPWM channel1 at brake state. 1257 * | | |Note: This bit is read only and auto cleared by hardware 1258 * | | |When enabled brake source return to high level, EPWM will release brake state until current EPWM period finished 1259 * | | |The EPWM waveform will start output from next full EPWM period. 1260 * |[26] |BRKLSTS2 |EPWM Channel2 Level-detect Brake Status (Read Only) 1261 * | | |0 = EPWM channel2 level-detect brake state is released. 1262 * | | |1 = When EPWM channel2 level-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the EPWM channel2 at brake state. 1263 * | | |Note: This bit is read only and auto cleared by hardware 1264 * | | |When enabled brake source return to high level, EPWM will release brake state until current EPWM period finished 1265 * | | |The EPWM waveform will start output from next full EPWM period. 1266 * |[27] |BRKLSTS3 |EPWM Channel3 Level-detect Brake Status (Read Only) 1267 * | | |0 = EPWM channel3 level-detect brake state is released. 1268 * | | |1 = When EPWM channel3 level-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the EPWM channel3 at brake state. 1269 * | | |Note: This bit is read only and auto cleared by hardware 1270 * | | |When enabled brake source return to high level, EPWM will release brake state until current EPWM period finished 1271 * | | |The EPWM waveform will start output from next full EPWM period. 1272 * |[28] |BRKLSTS4 |EPWM Channel4 Level-detect Brake Status (Read Only) 1273 * | | |0 = EPWM channel4 level-detect brake state is released. 1274 * | | |1 = When EPWM channel4 level-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the EPWM channel4 at brake state. 1275 * | | |Note: This bit is read only and auto cleared by hardware 1276 * | | |When enabled brake source return to high level, EPWM will release brake state until current EPWM period finished 1277 * | | |The EPWM waveform will start output from next full EPWM period. 1278 * |[29] |BRKLSTS5 |EPWM Channel5 Level-detect Brake Status (Read Only) 1279 * | | |0 = EPWM channel5 level-detect brake state is released. 1280 * | | |1 = When EPWM channel5 level-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the EPWM channel5 at brake state. 1281 * | | |Note: This bit is read only and auto cleared by hardware 1282 * | | |When enabled brake source return to high level, EPWM will release brake state until current EPWM period finished 1283 * | | |The EPWM waveform will start output from next full EPWM period. 1284 * @var EPWM_T::DACTRGEN 1285 * Offset: 0xF4 EPWM Trigger DAC Enable Register 1286 * --------------------------------------------------------------------------------------------------- 1287 * |Bits |Field |Descriptions 1288 * | :----: | :----: | :---- | 1289 * |[0] |ZTE0 |EPWM Zero Point Trigger DAC Enable Bits 1290 * | | |EPWM can trigger DAC to start action when EPWM counter down count to zero if this bit is set to1. 1291 * | | |0 = EPWM period point trigger DAC function Disabled. 1292 * | | |1 = EPWM period point trigger DAC function Enabled. 1293 * |[1] |ZTE1 |EPWM Zero Point Trigger DAC Enable Bits 1294 * | | |EPWM can trigger DAC to start action when EPWM counter down count to zero if this bit is set to1. 1295 * | | |0 = EPWM period point trigger DAC function Disabled. 1296 * | | |1 = EPWM period point trigger DAC function Enabled. 1297 * |[2] |ZTE2 |EPWM Zero Point Trigger DAC Enable Bits 1298 * | | |EPWM can trigger DAC to start action when EPWM counter down count to zero if this bit is set to1. 1299 * | | |0 = EPWM period point trigger DAC function Disabled. 1300 * | | |1 = EPWM period point trigger DAC function Enabled. 1301 * |[3] |ZTE3 |EPWM Zero Point Trigger DAC Enable Bits 1302 * | | |EPWM can trigger DAC to start action when EPWM counter down count to zero if this bit is set to1. 1303 * | | |0 = EPWM period point trigger DAC function Disabled. 1304 * | | |1 = EPWM period point trigger DAC function Enabled. 1305 * |[4] |ZTE4 |EPWM Zero Point Trigger DAC Enable Bits 1306 * | | |EPWM can trigger DAC to start action when EPWM counter down count to zero if this bit is set to1. 1307 * | | |0 = EPWM period point trigger DAC function Disabled. 1308 * | | |1 = EPWM period point trigger DAC function Enabled. 1309 * |[5] |ZTE5 |EPWM Zero Point Trigger DAC Enable Bits 1310 * | | |EPWM can trigger DAC to start action when EPWM counter down count to zero if this bit is set to1. 1311 * | | |0 = EPWM period point trigger DAC function Disabled. 1312 * | | |1 = EPWM period point trigger DAC function Enabled. 1313 * |[8] |PTE0 |EPWM Period Point Trigger DAC Enable Bits 1314 * | | |EPWM can trigger DAC to start action when EPWM counter counts up to (PERIODn+1) if this bit is set to1. 1315 * | | |0 = EPWM period point trigger DAC function Disabled. 1316 * | | |1 = EPWM period point trigger DAC function Enabled. 1317 * |[9] |PTE1 |EPWM Period Point Trigger DAC Enable Bits 1318 * | | |EPWM can trigger DAC to start action when EPWM counter counts up to (PERIODn+1) if this bit is set to1. 1319 * | | |0 = EPWM period point trigger DAC function Disabled. 1320 * | | |1 = EPWM period point trigger DAC function Enabled. 1321 * |[10] |PTE2 |EPWM Period Point Trigger DAC Enable Bits 1322 * | | |EPWM can trigger DAC to start action when EPWM counter counts up to (PERIODn+1) if this bit is set to1. 1323 * | | |0 = EPWM period point trigger DAC function Disabled. 1324 * | | |1 = EPWM period point trigger DAC function Enabled. 1325 * |[11] |PTE3 |EPWM Period Point Trigger DAC Enable Bits 1326 * | | |EPWM can trigger DAC to start action when EPWM counter counts up to (PERIODn+1) if this bit is set to1. 1327 * | | |0 = EPWM period point trigger DAC function Disabled. 1328 * | | |1 = EPWM period point trigger DAC function Enabled. 1329 * |[12] |PTE4 |EPWM Period Point Trigger DAC Enable Bits 1330 * | | |EPWM can trigger DAC to start action when EPWM counter counts up to (PERIODn+1) if this bit is set to1. 1331 * | | |0 = EPWM period point trigger DAC function Disabled. 1332 * | | |1 = EPWM period point trigger DAC function Enabled. 1333 * |[13] |PTE5 |EPWM Period Point Trigger DAC Enable Bits 1334 * | | |EPWM can trigger DAC to start action when EPWM counter counts up to (PERIODn+1) if this bit is set to1. 1335 * | | |0 = EPWM period point trigger DAC function Disabled. 1336 * | | |1 = EPWM period point trigger DAC function Enabled. 1337 * |[16] |CUTRGEN0 |EPWM Compare Up Count Point Trigger DAC Enable Bits 1338 * | | |EPWM can trigger DAC to start action when EPWM counter counts up to CMP if this bit is set to1. 1339 * | | |0 = EPWM Compare Up point trigger DAC function Disabled. 1340 * | | |1 = EPWM Compare Up point trigger DAC function Enabled. 1341 * | | |Note 1: This bit should keep at 0 when EPWM counter operating in down counter type. 1342 * | | |Note 2: In complementary mode, CUTRGEN1, 3, 5 is used as another CUTRGEN for channel 0, 2, 4. 1343 * |[17] |CUTRGEN1 |EPWM Compare Up Count Point Trigger DAC Enable Bits 1344 * | | |EPWM can trigger DAC to start action when EPWM counter counts up to CMP if this bit is set to1. 1345 * | | |0 = EPWM Compare Up point trigger DAC function Disabled. 1346 * | | |1 = EPWM Compare Up point trigger DAC function Enabled. 1347 * | | |Note 1: This bit should keep at 0 when EPWM counter operating in down counter type. 1348 * | | |Note 2: In complementary mode, CUTRGEN1, 3, 5 is used as another CUTRGEN for channel 0, 2, 4. 1349 * |[18] |CUTRGEN2 |EPWM Compare Up Count Point Trigger DAC Enable Bits 1350 * | | |EPWM can trigger DAC to start action when EPWM counter counts up to CMP if this bit is set to1. 1351 * | | |0 = EPWM Compare Up point trigger DAC function Disabled. 1352 * | | |1 = EPWM Compare Up point trigger DAC function Enabled. 1353 * | | |Note 1: This bit should keep at 0 when EPWM counter operating in down counter type. 1354 * | | |Note 2: In complementary mode, CUTRGEN1, 3, 5 is used as another CUTRGEN for channel 0, 2, 4. 1355 * |[19] |CUTRGEN3 |EPWM Compare Up Count Point Trigger DAC Enable Bits 1356 * | | |EPWM can trigger DAC to start action when EPWM counter counts up to CMP if this bit is set to1. 1357 * | | |0 = EPWM Compare Up point trigger DAC function Disabled. 1358 * | | |1 = EPWM Compare Up point trigger DAC function Enabled. 1359 * | | |Note 1: This bit should keep at 0 when EPWM counter operating in down counter type. 1360 * | | |Note 2: In complementary mode, CUTRGEN1, 3, 5 is used as another CUTRGEN for channel 0, 2, 4. 1361 * |[20] |CUTRGEN4 |EPWM Compare Up Count Point Trigger DAC Enable Bits 1362 * | | |EPWM can trigger DAC to start action when EPWM counter counts up to CMP if this bit is set to1. 1363 * | | |0 = EPWM Compare Up point trigger DAC function Disabled. 1364 * | | |1 = EPWM Compare Up point trigger DAC function Enabled. 1365 * | | |Note 1: This bit should keep at 0 when EPWM counter operating in down counter type. 1366 * | | |Note 2: In complementary mode, CUTRGEN1, 3, 5 is used as another CUTRGEN for channel 0, 2, 4. 1367 * |[21] |CUTRGEN5 |EPWM Compare Up Count Point Trigger DAC Enable Bits 1368 * | | |EPWM can trigger DAC to start action when EPWM counter counts up to CMP if this bit is set to1. 1369 * | | |0 = EPWM Compare Up point trigger DAC function Disabled. 1370 * | | |1 = EPWM Compare Up point trigger DAC function Enabled. 1371 * | | |Note 1: This bit should keep at 0 when EPWM counter operating in down counter type. 1372 * | | |Note 2: In complementary mode, CUTRGEN1, 3, 5 is used as another CUTRGEN for channel 0, 2, 4. 1373 * |[24] |CDTRGEN0 |EPWM Compare Down Count Point Trigger DAC Enable Bits 1374 * | | |EPWM can trigger DAC to start action when EPWM counter down count to CMP if this bit is set to1. 1375 * | | |0 = EPWM Compare Down count point trigger DAC function Disabled. 1376 * | | |1 = EPWM Compare Down count point trigger DAC function Enabled. 1377 * | | |Note 1: This bit should keep at 0 when EPWM counter operating in up counter type. 1378 * | | |Note 2: In complementary mode, CDTRGEN1, 3, 5 is used as another CDTRGEN for channel 0, 2, 4. 1379 * |[25] |CDTRGEN1 |EPWM Compare Down Count Point Trigger DAC Enable Bits 1380 * | | |EPWM can trigger DAC to start action when EPWM counter down count to CMP if this bit is set to1. 1381 * | | |0 = EPWM Compare Down count point trigger DAC function Disabled. 1382 * | | |1 = EPWM Compare Down count point trigger DAC function Enabled. 1383 * | | |Note 1: This bit should keep at 0 when EPWM counter operating in up counter type. 1384 * | | |Note 2: In complementary mode, CDTRGEN1, 3, 5 is used as another CDTRGEN for channel 0, 2, 4. 1385 * |[26] |CDTRGEN2 |EPWM Compare Down Count Point Trigger DAC Enable Bits 1386 * | | |EPWM can trigger DAC to start action when EPWM counter down count to CMP if this bit is set to1. 1387 * | | |0 = EPWM Compare Down count point trigger DAC function Disabled. 1388 * | | |1 = EPWM Compare Down count point trigger DAC function Enabled. 1389 * | | |Note 1: This bit should keep at 0 when EPWM counter operating in up counter type. 1390 * | | |Note 2: In complementary mode, CDTRGEN1, 3, 5 is used as another CDTRGEN for channel 0, 2, 4. 1391 * |[27] |CDTRGEN3 |EPWM Compare Down Count Point Trigger DAC Enable Bits 1392 * | | |EPWM can trigger DAC to start action when EPWM counter down count to CMP if this bit is set to1. 1393 * | | |0 = EPWM Compare Down count point trigger DAC function Disabled. 1394 * | | |1 = EPWM Compare Down count point trigger DAC function Enabled. 1395 * | | |Note 1: This bit should keep at 0 when EPWM counter operating in up counter type. 1396 * | | |Note 2: In complementary mode, CDTRGEN1, 3, 5 is used as another CDTRGEN for channel 0, 2, 4. 1397 * |[28] |CDTRGEN4 |EPWM Compare Down Count Point Trigger DAC Enable Bits 1398 * | | |EPWM can trigger DAC to start action when EPWM counter down count to CMP if this bit is set to1. 1399 * | | |0 = EPWM Compare Down count point trigger DAC function Disabled. 1400 * | | |1 = EPWM Compare Down count point trigger DAC function Enabled. 1401 * | | |Note 1: This bit should keep at 0 when EPWM counter operating in up counter type. 1402 * | | |Note 2: In complementary mode, CDTRGEN1, 3, 5 is used as another CDTRGEN for channel 0, 2, 4. 1403 * |[29] |CDTRGEN5 |EPWM Compare Down Count Point Trigger DAC Enable Bits 1404 * | | |EPWM can trigger DAC to start action when EPWM counter down count to CMP if this bit is set to1. 1405 * | | |0 = EPWM Compare Down count point trigger DAC function Disabled. 1406 * | | |1 = EPWM Compare Down count point trigger DAC function Enabled. 1407 * | | |Note 1: This bit should keep at 0 when EPWM counter operating in up counter type. 1408 * | | |Note 2: In complementary mode, CDTRGEN1, 3, 5 is used as another CDTRGEN for channel 0, 2, 4. 1409 * @var EPWM_T::EADCTS0 1410 * Offset: 0xF8 EPWM Trigger EADC Source Select Register 0 1411 * --------------------------------------------------------------------------------------------------- 1412 * |Bits |Field |Descriptions 1413 * | :----: | :----: | :---- | 1414 * |[4:0] |TRGSEL0 |EPWM_CH0 Trigger EADC Source Select 1415 * | | |00000 = EPWM_CH0 zero point. 1416 * | | |00001 = EPWM_CH0 period point. 1417 * | | |00010 = EPWM_CH0 zero or period point. 1418 * | | |00011 = EPWM_CH0 up-count compared point. 1419 * | | |00100 = EPWM_CH0 down-count compared point. 1420 * | | |00101 = EPWM_CH1 zero point. 1421 * | | |00110 = EPWM_CH1 period point. 1422 * | | |00111 = EPWM_CH1 zero or period point. 1423 * | | |01000 = EPWM_CH1 up-count compared point. 1424 * | | |01001 = EPWM_CH1 down-count compared point. 1425 * | | |01010 = EPWM_CH0 up-count free trigger compared point. 1426 * | | |01011 = EPWM_CH0 down-count free trigger compared point. 1427 * | | |01100 = EPWM_CH2 up-count free trigger compared point. 1428 * | | |01101 = EPWM_CH2 down-count free trigger compared point. 1429 * | | |01110 = EPWM_CH4 up-count free trigger compared point. 1430 * | | |01111 = EPWM_CH4 down-count free trigger compared point. 1431 * | | |10000 = EPWM_CH0 Interrupt Flag Accumulator Interrupt. 1432 * | | |10001 = EPWM_CH1 Interrupt Flag Accumulator Interrupt. 1433 * |[7] |TRGEN0 |EPWM_CH0 Trigger EADC Enable Bit 1434 * | | |0 = EPWM_CH0 Trigger EADC function Disabled. 1435 * | | |1 = EPWM_CH0 Trigger EADC function Enabled. 1436 * |[12:8] |TRGSEL1 |EPWM_CH1 Trigger EADC Source Select 1437 * | | |00000 = EPWM_CH0 zero point. 1438 * | | |00001 = EPWM_CH0 period point. 1439 * | | |00010 = EPWM_CH0 zero or period point. 1440 * | | |00011 = EPWM_CH0 up-count compared point. 1441 * | | |00100 = EPWM_CH0 down-count compared point. 1442 * | | |00101 = EPWM_CH1 zero point. 1443 * | | |00110 = EPWM_CH1 period point. 1444 * | | |00111 = EPWM_CH1 zero or period point. 1445 * | | |01000 = EPWM_CH1 up-count compared point. 1446 * | | |01001 = EPWM_CH1 down-count compared point. 1447 * | | |01010 = EPWM_CH0 up-count free trigger compared point. 1448 * | | |01011 = EPWM_CH0 down-count free trigger compared point. 1449 * | | |01100 = EPWM_CH2 up-count free trigger compared point. 1450 * | | |01101 = EPWM_CH2 down-count free trigger compared point. 1451 * | | |01110 = EPWM_CH4 up-count free trigger compared point. 1452 * | | |01111 = EPWM_CH4 down-count free trigger compared point. 1453 * | | |10000 = EPWM_CH0 Interrupt Flag Accumulator Interrupt. 1454 * | | |10001 = EPWM_CH1 Interrupt Flag Accumulator Interrupt. 1455 * |[15] |TRGEN1 |EPWM_CH1 Trigger EADC Enable Bit 1456 * | | |0 = EPWM_CH1 Trigger EADC function Disabled. 1457 * | | |1 = EPWM_CH1 Trigger EADC function Enabled. 1458 * |[20:16] |TRGSEL2 |EPWM_CH2 Trigger EADC Source Select 1459 * | | |00000 = EPWM_CH2 zero point. 1460 * | | |00001 = EPWM_CH2 period point. 1461 * | | |00010 = EPWM_CH2 zero or period point. 1462 * | | |00011 = EPWM_CH2 up-count compared point. 1463 * | | |00100 = EPWM_CH2 down-count compared point. 1464 * | | |00101 = EPWM_CH3 zero point. 1465 * | | |00110 = EPWM_CH3 period point. 1466 * | | |00111 = EPWM_CH3 zero or period point. 1467 * | | |01000 = EPWM_CH3 up-count compared point. 1468 * | | |01001 = EPWM_CH3 down-count compared point. 1469 * | | |01010 = EPWM_CH0 up-count free trigger compared point. 1470 * | | |01011 = EPWM_CH0 down-count free trigger compared point. 1471 * | | |01100 = EPWM_CH2 up-count free trigger compared point. 1472 * | | |01101 = EPWM_CH2 down-count free trigger compared point. 1473 * | | |01110 = EPWM_CH4 up-count free trigger compared point. 1474 * | | |01111 = EPWM_CH4 down-count free trigger compared point. 1475 * | | |10000 = EPWM_CH2 Interrupt Flag Accumulator Interrupt. 1476 * | | |10001 = EPWM_CH3 Interrupt Flag Accumulator Interrupt. 1477 * |[23] |TRGEN2 |EPWM_CH2 Trigger EADC Enable Bit 1478 * | | |0 = EPWM_CH2 Trigger EADC function Disabled. 1479 * | | |1 = EPWM_CH2 Trigger EADC function Enabled. 1480 * |[28:24] |TRGSEL3 |EPWM_CH3 Trigger EADC Source Select 1481 * | | |00000 = EPWM_CH2 zero point. 1482 * | | |00001 = EPWM_CH2 period point. 1483 * | | |00010 = EPWM_CH2 zero or period point. 1484 * | | |00011 = EPWM_CH2 up-count compared point. 1485 * | | |00100 = EPWM_CH2 down-count compared point. 1486 * | | |00101 = EPWM_CH3 zero point. 1487 * | | |00110 = EPWM_CH3 period point. 1488 * | | |00111 = EPWM_CH3 zero or period point. 1489 * | | |01000 = EPWM_CH3 up-count compared point. 1490 * | | |01001 = EPWM_CH3 down-count compared point. 1491 * | | |01010 = EPWM_CH0 up-count free trigger compared point. 1492 * | | |01011 = EPWM_CH0 down-count free trigger compared point. 1493 * | | |01100 = EPWM_CH2 up-count free trigger compared point. 1494 * | | |01101 = EPWM_CH2 down-count free trigger compared point. 1495 * | | |01110 = EPWM_CH4 up-count free trigger compared point. 1496 * | | |01111 = EPWM_CH4 down-count free trigger compared point. 1497 * | | |10000 = EPWM_CH2 Interrupt Flag Accumulator Interrupt. 1498 * | | |10001 = EPWM_CH3 Interrupt Flag Accumulator Interrupt. 1499 * |[31] |TRGEN3 |EPWM_CH3 Trigger EADC Enable Bit 1500 * | | |0 = EPWM_CH3 Trigger EADC function Disabled. 1501 * | | |1 = EPWM_CH3 Trigger EADC function Enabled. 1502 * @var EPWM_T::EADCTS1 1503 * Offset: 0xFC EPWM Trigger EADC Source Select Register 1 1504 * --------------------------------------------------------------------------------------------------- 1505 * |Bits |Field |Descriptions 1506 * | :----: | :----: | :---- | 1507 * |[4:0] |TRGSEL4 |EPWM_CH4 Trigger EADC Source Select 1508 * | | |00000 = EPWM_CH4 zero point. 1509 * | | |00001 = EPWM_CH4 period point. 1510 * | | |00010 = EPWM_CH4 zero or period point. 1511 * | | |00011 = EPWM_CH4 up-count compared point. 1512 * | | |00100 = EPWM_CH4 down-count compared point. 1513 * | | |00101 = EPWM_CH5 zero point. 1514 * | | |00110 = EPWM_CH5 period point. 1515 * | | |00111 = EPWM_CH5 zero or period point. 1516 * | | |01000 = EPWM_CH5 up-count compared point. 1517 * | | |01001 = EPWM_CH5 down-count compared point. 1518 * | | |01010 = EPWM_CH0 up-count free trigger compared point. 1519 * | | |01011 = EPWM_CH0 down-count free trigger compared point. 1520 * | | |01100 = EPWM_CH2 up-count free trigger compared point. 1521 * | | |01101 = EPWM_CH2 down-count free trigger compared point. 1522 * | | |01110 = EPWM_CH4 up-count free trigger compared point. 1523 * | | |01111 = EPWM_CH4 down-count free trigger compared point. 1524 * | | |10000 = EPWM_CH4 Interrupt Flag Accumulator Interrupt. 1525 * | | |10001 = EPWM_CH5 Interrupt Flag Accumulator Interrupt. 1526 * |[7] |TRGEN4 |EPWM_CH4 Trigger EADC Enable Bit 1527 * | | |0 = EPWM_CH4 Trigger EADC function Disabled. 1528 * | | |1 = EPWM_CH4 Trigger EADC function Enabled. 1529 * |[12:8] |TRGSEL5 |EPWM_CH5 Trigger EADC Source Select 1530 * | | |00000 = EPWM_CH4 zero point. 1531 * | | |00001 = EPWM_CH4 period point. 1532 * | | |00010 = EPWM_CH4 zero or period point. 1533 * | | |00011 = EPWM_CH4 up-count compared point. 1534 * | | |00100 = EPWM_CH4 down-count compared point. 1535 * | | |00101 = EPWM_CH5 zero point. 1536 * | | |00110 = EPWM_CH5 period point. 1537 * | | |00111 = EPWM_CH5 zero or period point. 1538 * | | |01000 = EPWM_CH5 up-count compared point. 1539 * | | |01001 = EPWM_CH5 down-count compared point. 1540 * | | |01010 = EPWM_CH0 up-count free trigger compared point. 1541 * | | |01011 = EPWM_CH0 down-count free trigger compared point. 1542 * | | |01100 = EPWM_CH2 up-count free trigger compared point. 1543 * | | |01101 = EPWM_CH2 down-count free trigger compared point. 1544 * | | |01110 = EPWM_CH4 up-count free trigger compared point. 1545 * | | |01111 = EPWM_CH4 down-count free trigger compared point. 1546 * | | |10000 = EPWM_CH4 Interrupt Flag Accumulator Interrupt. 1547 * | | |10001 = EPWM_CH5 Interrupt Flag Accumulator Interrupt. 1548 * |[15] |TRGEN5 |EPWM_CH5 Trigger EADC Enable Bit 1549 * | | |0 = EPWM_CH5 Trigger EADC function Disabled. 1550 * | | |1 = EPWM_CH5 Trigger EADC function Enabled. 1551 * @var EPWM_T::FTCMPDAT[3] 1552 * Offset: 0x100 EPWM Free Trigger Compare Register 0/1,2/3,4/5 1553 * --------------------------------------------------------------------------------------------------- 1554 * |Bits |Field |Descriptions 1555 * | :----: | :----: | :---- | 1556 * |[15:0] |FTCMP |EPWM Free Trigger Compare Register 1557 * | | |FTCMP use to compare with even CNT (EPWM_CNTm[15:0], m=0,2,4) to trigger EADC 1558 * | | |EPWM_FTCMPDAT0_1, EPWM_FTCMPDAT2_3, EPWM_FTCMPDAT4_5 corresponding complementary pairs EPWM_CH0and EPWM_CH1, EPWM_CH2 and EPWM_CH3, EPWM_CH4 and EPWM_CH5. 1559 * @var EPWM_T::SSCTL 1560 * Offset: 0x110 EPWM Synchronous Start Control Register 1561 * --------------------------------------------------------------------------------------------------- 1562 * |Bits |Field |Descriptions 1563 * | :----: | :----: | :---- | 1564 * |[0] |SSEN0 |EPWM Synchronous Start Function Enable Bits 1565 * | | |When synchronous start function is enabled, the EPWM counter enable register (EPWM_CNTEN) can be enabled by writing EPWM synchronous start trigger bit (CNTSEN). 1566 * | | |0 = EPWM synchronous start function Disabled. 1567 * | | |1 = EPWM synchronous start function Enabled. 1568 * |[1] |SSEN1 |EPWM Synchronous Start Function Enable Bits 1569 * | | |When synchronous start function is enabled, the EPWM counter enable register (EPWM_CNTEN) can be enabled by writing EPWM synchronous start trigger bit (CNTSEN). 1570 * | | |0 = EPWM synchronous start function Disabled. 1571 * | | |1 = EPWM synchronous start function Enabled. 1572 * |[2] |SSEN2 |EPWM Synchronous Start Function Enable Bits 1573 * | | |When synchronous start function is enabled, the EPWM counter enable register (EPWM_CNTEN) can be enabled by writing EPWM synchronous start trigger bit (CNTSEN). 1574 * | | |0 = EPWM synchronous start function Disabled. 1575 * | | |1 = EPWM synchronous start function Enabled. 1576 * |[3] |SSEN3 |EPWM Synchronous Start Function Enable Bits 1577 * | | |When synchronous start function is enabled, the EPWM counter enable register (EPWM_CNTEN) can be enabled by writing EPWM synchronous start trigger bit (CNTSEN). 1578 * | | |0 = EPWM synchronous start function Disabled. 1579 * | | |1 = EPWM synchronous start function Enabled. 1580 * |[4] |SSEN4 |EPWM Synchronous Start Function Enable Bits 1581 * | | |When synchronous start function is enabled, the EPWM counter enable register (EPWM_CNTEN) can be enabled by writing EPWM synchronous start trigger bit (CNTSEN). 1582 * | | |0 = EPWM synchronous start function Disabled. 1583 * | | |1 = EPWM synchronous start function Enabled. 1584 * |[5] |SSEN5 |EPWM Synchronous Start Function Enable Bits 1585 * | | |When synchronous start function is enabled, the EPWM counter enable register (EPWM_CNTEN) can be enabled by writing EPWM synchronous start trigger bit (CNTSEN). 1586 * | | |0 = EPWM synchronous start function Disabled. 1587 * | | |1 = EPWM synchronous start function Enabled. 1588 * |[9:8] |SSRC |EPWM Synchronous Start Source Select Bits 1589 * | | |00 = Synchronous start source come from EPWM0. 1590 * | | |01 = Synchronous start source come from EPWM1. 1591 * | | |10 = Synchronous start source come from BPWM0. 1592 * | | |11 = Synchronous start source come from BPWM1. 1593 * @var EPWM_T::SSTRG 1594 * Offset: 0x114 EPWM Synchronous Start Trigger Register 1595 * --------------------------------------------------------------------------------------------------- 1596 * |Bits |Field |Descriptions 1597 * | :----: | :----: | :---- | 1598 * |[0] |CNTSEN |EPWM Counter Synchronous Start Enable (Write Only) 1599 * | | |PMW counter synchronous enable function is used to make selected EPWM channels (include EPWM0_CHx and EPWM1_CHx) start counting at the same time. 1600 * | | |Writing this bit to 1 will also set the counter enable bit (CNTENn, n denotes channel 0 to 5) if correlated EPWM channel counter synchronous start function is enabled. 1601 * @var EPWM_T::LEBCTL 1602 * Offset: 0x118 EPWM Leading Edge Blanking Control Register 1603 * --------------------------------------------------------------------------------------------------- 1604 * |Bits |Field |Descriptions 1605 * | :----: | :----: | :---- | 1606 * |[0] |LEBEN |EPWM Leading Edge Blanking Enable Bit 1607 * | | |0 = EPWM Leading Edge Blanking Disabled. 1608 * | | |1 = EPWM Leading Edge Blanking Enabled. 1609 * |[8] |SRCEN0 |EPWM Leading Edge Blanking Source From EPWM_CH0 Enable Bit 1610 * | | |0 = EPWM Leading Edge Blanking Source from EPWM_CH0 Disabled. 1611 * | | |1 = EPWM Leading Edge Blanking Source from EPWM_CH0 Enabled. 1612 * |[9] |SRCEN2 |EPWM Leading Edge Blanking Source From EPWM_CH2 Enable Bit 1613 * | | |0 = EPWM Leading Edge Blanking Source from EPWM_CH2 Disabled. 1614 * | | |1 = EPWM Leading Edge Blanking Source from EPWM_CH2 Enabled. 1615 * |[10] |SRCEN4 |EPWM Leading Edge Blanking Source From EPWM_CH4 Enable Bit 1616 * | | |0 = EPWM Leading Edge Blanking Source from EPWM_CH4 Disabled. 1617 * | | |1 = EPWM Leading Edge Blanking Source from EPWM_CH4 Enabled. 1618 * |[17:16] |TRGTYPE |EPWM Leading Edge Blanking Trigger Type 1619 * | | |0 = When detect leading edge blanking source rising edge, blanking counter start counting. 1620 * | | |1 = When detect leading edge blanking source falling edge, blanking counter start counting. 1621 * | | |2 = When detect leading edge blanking source rising or falling edge, blanking counter start counting. 1622 * | | |3 = Reserved. 1623 * @var EPWM_T::LEBCNT 1624 * Offset: 0x11C EPWM Leading Edge Blanking Counter Register 1625 * --------------------------------------------------------------------------------------------------- 1626 * |Bits |Field |Descriptions 1627 * | :----: | :----: | :---- | 1628 * |[8:0] |LEBCNT |EPWM Leading Edge Blanking Counter 1629 * | | |This counter value decides leading edge blanking window size 1630 * | | |Blanking window size = LEBCNT+1, and LEB counter clock base is ECLK. 1631 * @var EPWM_T::STATUS 1632 * Offset: 0x120 EPWM Status Register 1633 * --------------------------------------------------------------------------------------------------- 1634 * |Bits |Field |Descriptions 1635 * | :----: | :----: | :---- | 1636 * |[0] |CNTMAXF0 |Time-base Counter Equal to 0xFFFF Latched Flag 1637 * | | |0 = The time-base counter never reached its maximum value 0xFFFF. 1638 * | | |1 = The time-base counter reached its maximum value. 1639 * | | |Note: This bit can be cleared by software writing 1. 1640 * |[1] |CNTMAXF1 |Time-base Counter Equal to 0xFFFF Latched Flag 1641 * | | |0 = The time-base counter never reached its maximum value 0xFFFF. 1642 * | | |1 = The time-base counter reached its maximum value. 1643 * | | |Note: This bit can be cleared by software writing 1. 1644 * |[2] |CNTMAXF2 |Time-base Counter Equal to 0xFFFF Latched Flag 1645 * | | |0 = The time-base counter never reached its maximum value 0xFFFF. 1646 * | | |1 = The time-base counter reached its maximum value. 1647 * | | |Note: This bit can be cleared by software writing 1. 1648 * |[3] |CNTMAXF3 |Time-base Counter Equal to 0xFFFF Latched Flag 1649 * | | |0 = The time-base counter never reached its maximum value 0xFFFF. 1650 * | | |1 = The time-base counter reached its maximum value. 1651 * | | |Note: This bit can be cleared by software writing 1. 1652 * |[4] |CNTMAXF4 |Time-base Counter Equal to 0xFFFF Latched Flag 1653 * | | |0 = The time-base counter never reached its maximum value 0xFFFF. 1654 * | | |1 = The time-base counter reached its maximum value. 1655 * | | |Note: This bit can be cleared by software writing 1. 1656 * |[5] |CNTMAXF5 |Time-base Counter Equal to 0xFFFF Latched Flag 1657 * | | |0 = The time-base counter never reached its maximum value 0xFFFF. 1658 * | | |1 = The time-base counter reached its maximum value. 1659 * | | |Note: This bit can be cleared by software writing 1. 1660 * |[8] |SYNCINF0 |Input Synchronization Latched Flag 1661 * | | |0 = No SYNC_IN event has occurred. 1662 * | | |1 = A SYNC_IN event has occurred. 1663 * | | |Note: This bit can be cleared by software writing 1. 1664 * |[9] |SYNCINF2 |Input Synchronization Latched Flag 1665 * | | |0 = No SYNC_IN event has occurred. 1666 * | | |1 = A SYNC_IN event has occurred. 1667 * | | |Note: This bit can be cleared by software writing 1. 1668 * |[10] |SYNCINF4 |Input Synchronization Latched Flag 1669 * | | |0 = No SYNC_IN event has occurred. 1670 * | | |1 = A SYNC_IN event has occurred. 1671 * | | |Note: This bit can be cleared by software writing 1. 1672 * |[16] |EADCTRGF0 |EADC Start of Conversion Flag 1673 * | | |0 = No EADC start of conversion trigger event has occurred. 1674 * | | |1 = An EADC start of conversion trigger event has occurred. 1675 * | | |Note: This bit can be cleared by software writing 1. 1676 * |[17] |EADCTRGF1 |EADC Start of Conversion Flag 1677 * | | |0 = No EADC start of conversion trigger event has occurred. 1678 * | | |1 = An EADC start of conversion trigger event has occurred. 1679 * | | |Note: This bit can be cleared by software writing 1. 1680 * |[18] |EADCTRGF2 |EADC Start of Conversion Flag 1681 * | | |0 = No EADC start of conversion trigger event has occurred. 1682 * | | |1 = An EADC start of conversion trigger event has occurred. 1683 * | | |Note: This bit can be cleared by software writing 1. 1684 * |[19] |EADCTRGF3 |EADC Start of Conversion Flag 1685 * | | |0 = No EADC start of conversion trigger event has occurred. 1686 * | | |1 = An EADC start of conversion trigger event has occurred. 1687 * | | |Note: This bit can be cleared by software writing 1. 1688 * |[20] |EADCTRGF4 |EADC Start of Conversion Flag 1689 * | | |0 = No EADC start of conversion trigger event has occurred. 1690 * | | |1 = An EADC start of conversion trigger event has occurred. 1691 * | | |Note: This bit can be cleared by software writing 1. 1692 * |[21] |EADCTRGF5 |EADC Start of Conversion Flag 1693 * | | |0 = No EADC start of conversion trigger event has occurred. 1694 * | | |1 = An EADC start of conversion trigger event has occurred. 1695 * | | |Note: This bit can be cleared by software writing 1. 1696 * |[24] |DACTRGF |DAC Start of Conversion Flag 1697 * | | |0 = No DAC start of conversion trigger event has occurred. 1698 * | | |1 = A DAC start of conversion trigger event has occurred. 1699 * | | |Note: This bit can be cleared by software writing 1. 1700 * @var EPWM_T::IFA[6] 1701 * Offset: 0x130 EPWM Interrupt Flag Accumulator Register 0~5 1702 * --------------------------------------------------------------------------------------------------- 1703 * |Bits |Field |Descriptions 1704 * | :----: | :----: | :---- | 1705 * |[15:0] |IFACNT |EPWM_CHn Interrupt Flag Counter 1706 * | | |The register sets the count number which defines (IFACNT+1) times of EPWM_CHn period occurs to set bit IFAIFn to request the EPWM period interrupt. 1707 * | | |EPWM flag will be set in every IFACNT[15:0] times of EPWM period. 1708 * |[24] |STPMOD |EPWM_CHn Accumulator Stop Mode Enable Bits 1709 * | | |0 = EPWM_CHn Stop Mode Disabled. 1710 * | | |1 = EPWM_CHn Stop Mode Enabled. 1711 * |[29:28] |IFASEL |EPWM_CHn Interrupt Flag Accumulator Source Select 1712 * | | |00 = EPWM_CHn zero point. 1713 * | | |01 = EPWM_CHn period in channel n. 1714 * | | |10 = EPWM_CHn up-count compared point. 1715 * | | |11 = EPWM_CHn down-count compared point. 1716 * |[31] |IFAEN |EPWM_CHn Interrupt Flag Accumulator Enable Bits 1717 * | | |0 = EPWM_CHn interrupt flag accumulator disable. 1718 * | | |1 = EPWM_CHn interrupt flag accumulator enable. 1719 * @var EPWM_T::AINTSTS 1720 * Offset: 0x150 EPWM Accumulator Interrupt Flag Register 1721 * --------------------------------------------------------------------------------------------------- 1722 * |Bits |Field |Descriptions 1723 * | :----: | :----: | :---- | 1724 * |[0] |IFAIF0 |EPWM_CHn Interrupt Flag Accumulator Interrupt Flag 1725 * | | |Flag is set by hardware when condition match IFASEL in EPWM_IFAn register, software can clear this bit by writing 1 to it. 1726 * |[1] |IFAIF1 |EPWM_CHn Interrupt Flag Accumulator Interrupt Flag 1727 * | | |Flag is set by hardware when condition match IFASEL in EPWM_IFAn register, software can clear this bit by writing 1 to it. 1728 * |[2] |IFAIF2 |EPWM_CHn Interrupt Flag Accumulator Interrupt Flag 1729 * | | |Flag is set by hardware when condition match IFASEL in EPWM_IFAn register, software can clear this bit by writing 1 to it. 1730 * |[3] |IFAIF3 |EPWM_CHn Interrupt Flag Accumulator Interrupt Flag 1731 * | | |Flag is set by hardware when condition match IFASEL in EPWM_IFAn register, software can clear this bit by writing 1 to it. 1732 * |[4] |IFAIF4 |EPWM_CHn Interrupt Flag Accumulator Interrupt Flag 1733 * | | |Flag is set by hardware when condition match IFASEL in EPWM_IFAn register, software can clear this bit by writing 1 to it. 1734 * |[5] |IFAIF5 |EPWM_CHn Interrupt Flag Accumulator Interrupt Flag 1735 * | | |Flag is set by hardware when condition match IFASEL in EPWM_IFAn register, software can clear this bit by writing 1 to it. 1736 * @var EPWM_T::AINTEN 1737 * Offset: 0x154 EPWM Accumulator Interrupt Enable Register 1738 * --------------------------------------------------------------------------------------------------- 1739 * |Bits |Field |Descriptions 1740 * | :----: | :----: | :---- | 1741 * |[0] |IFAIEN0 |EPWM_CHn Interrupt Flag Accumulator Interrupt Enable Bits 1742 * | | |0 = Interrupt Flag accumulator interrupt Disabled. 1743 * | | |1 = Interrupt Flag accumulator interrupt Enabled. 1744 * |[1] |IFAIEN1 |EPWM_CHn Interrupt Flag Accumulator Interrupt Enable Bits 1745 * | | |0 = Interrupt Flag accumulator interrupt Disabled. 1746 * | | |1 = Interrupt Flag accumulator interrupt Enabled. 1747 * |[2] |IFAIEN2 |EPWM_CHn Interrupt Flag Accumulator Interrupt Enable Bits 1748 * | | |0 = Interrupt Flag accumulator interrupt Disabled. 1749 * | | |1 = Interrupt Flag accumulator interrupt Enabled. 1750 * |[3] |IFAIEN3 |EPWM_CHn Interrupt Flag Accumulator Interrupt Enable Bits 1751 * | | |0 = Interrupt Flag accumulator interrupt Disabled. 1752 * | | |1 = Interrupt Flag accumulator interrupt Enabled. 1753 * |[4] |IFAIEN4 |EPWM_CHn Interrupt Flag Accumulator Interrupt Enable Bits 1754 * | | |0 = Interrupt Flag accumulator interrupt Disabled. 1755 * | | |1 = Interrupt Flag accumulator interrupt Enabled. 1756 * |[5] |IFAIEN5 |EPWM_CHn Interrupt Flag Accumulator Interrupt Enable Bits 1757 * | | |0 = Interrupt Flag accumulator interrupt Disabled. 1758 * | | |1 = Interrupt Flag accumulator interrupt Enabled. 1759 * @var EPWM_T::APDMACTL 1760 * Offset: 0x158 EPWM Accumulator PDMA Control Register 1761 * --------------------------------------------------------------------------------------------------- 1762 * |Bits |Field |Descriptions 1763 * | :----: | :----: | :---- | 1764 * |[0] |APDMAEN0 |Channel n Accumulator PDMA Enable Bits 1765 * | | |0 = Channel n PDMA function Disabled. 1766 * | | |1 = Channel n PDMA function Enabled for the channel n to trigger PDMA to transfer memory data to register. 1767 * |[1] |APDMAEN1 |Channel n Accumulator PDMA Enable Bits 1768 * | | |0 = Channel n PDMA function Disabled. 1769 * | | |1 = Channel n PDMA function Enabled for the channel n to trigger PDMA to transfer memory data to register. 1770 * |[2] |APDMAEN2 |Channel n Accumulator PDMA Enable Bits 1771 * | | |0 = Channel n PDMA function Disabled. 1772 * | | |1 = Channel n PDMA function Enabled for the channel n to trigger PDMA to transfer memory data to register. 1773 * |[3] |APDMAEN3 |Channel n Accumulator PDMA Enable Bits 1774 * | | |0 = Channel n PDMA function Disabled. 1775 * | | |1 = Channel n PDMA function Enabled for the channel n to trigger PDMA to transfer memory data to register. 1776 * |[4] |APDMAEN4 |Channel n Accumulator PDMA Enable Bits 1777 * | | |0 = Channel n PDMA function Disabled. 1778 * | | |1 = Channel n PDMA function Enabled for the channel n to trigger PDMA to transfer memory data to register. 1779 * |[5] |APDMAEN5 |Channel n Accumulator PDMA Enable Bits 1780 * | | |0 = Channel n PDMA function Disabled. 1781 * | | |1 = Channel n PDMA function Enabled for the channel n to trigger PDMA to transfer memory data to register. 1782 * @var EPWM_T::FDEN 1783 * Offset: 0x160 EPWM Fault Detect Enable Register 1784 * --------------------------------------------------------------------------------------------------- 1785 * |Bits |Field |Descriptions 1786 * | :----: | :----: | :---- | 1787 * |[0] |FDEN0 |EPWM Fault Detect Function Enable Bit 1788 * | | |0 = Fault detect function Disabled. 1789 * | | |1 = Fault detect function Enabled. 1790 * |[1] |FDEN1 |EPWM Fault Detect Function Enable Bit 1791 * | | |0 = Fault detect function Disabled. 1792 * | | |1 = Fault detect function Enabled. 1793 * |[2] |FDEN2 |EPWM Fault Detect Function Enable Bit 1794 * | | |0 = Fault detect function Disabled. 1795 * | | |1 = Fault detect function Enabled. 1796 * |[3] |FDEN3 |EPWM Fault Detect Function Enable Bit 1797 * | | |0 = Fault detect function Disabled. 1798 * | | |1 = Fault detect function Enabled. 1799 * |[4] |FDEN4 |EPWM Fault Detect Function Enable Bit 1800 * | | |0 = Fault detect function Disabled. 1801 * | | |1 = Fault detect function Enabled. 1802 * |[5] |FDEN5 |EPWM Fault Detect Function Enable Bit 1803 * | | |0 = Fault detect function Disabled. 1804 * | | |1 = Fault detect function Enabled. 1805 * |[8] |FDODIS0 |EPWM Channel n Output Fault Detect Disable Bit 1806 * | | |0 = EPWM detect fault and output Enabled. 1807 * | | |1 = EPWM detect fault and output Disabled. 1808 * |[9] |FDODIS1 |EPWM Channel n Output Fault Detect Disable Bit 1809 * | | |0 = EPWM detect fault and output Enabled. 1810 * | | |1 = EPWM detect fault and output Disabled. 1811 * |[10] |FDODIS2 |EPWM Channel n Output Fault Detect Disable Bit 1812 * | | |0 = EPWM detect fault and output Enabled. 1813 * | | |1 = EPWM detect fault and output Disabled. 1814 * |[11] |FDODIS3 |EPWM Channel n Output Fault Detect Disable Bit 1815 * | | |0 = EPWM detect fault and output Enabled. 1816 * | | |1 = EPWM detect fault and output Disabled. 1817 * |[12] |FDODIS4 |EPWM Channel n Output Fault Detect Disable Bit 1818 * | | |0 = EPWM detect fault and output Enabled. 1819 * | | |1 = EPWM detect fault and output Disabled. 1820 * |[13] |FDODIS5 |EPWM Channel n Output Fault Detect Disable Bit 1821 * | | |0 = EPWM detect fault and output Enabled. 1822 * | | |1 = EPWM detect fault and output Disabled. 1823 * |[16] |FDCKS0 |EPWM Channel n Fault Detect Clock Source Select Bit 1824 * | | |0 = EPWMx_CLK, x denotes 0 or 1. 1825 * | | |1 = EPWMx_CLK divide by prescaler, x denotes 0 or 1. 1826 * |[17] |FDCKS1 |EPWM Channel n Fault Detect Clock Source Select Bit 1827 * | | |0 = EPWMx_CLK, x denotes 0 or 1. 1828 * | | |1 = EPWMx_CLK divide by prescaler, x denotes 0 or 1. 1829 * |[18] |FDCKS2 |EPWM Channel n Fault Detect Clock Source Select Bit 1830 * | | |0 = EPWMx_CLK, x denotes 0 or 1. 1831 * | | |1 = EPWMx_CLK divide by prescaler, x denotes 0 or 1. 1832 * |[19] |FDCKS3 |EPWM Channel n Fault Detect Clock Source Select Bit 1833 * | | |0 = EPWMx_CLK, x denotes 0 or 1. 1834 * | | |1 = EPWMx_CLK divide by prescaler, x denotes 0 or 1. 1835 * |[20] |FDCKS4 |EPWM Channel n Fault Detect Clock Source Select Bit 1836 * | | |0 = EPWMx_CLK, x denotes 0 or 1. 1837 * | | |1 = EPWMx_CLK divide by prescaler, x denotes 0 or 1. 1838 * |[21] |FDCKS5 |EPWM Channel n Fault Detect Clock Source Select Bit 1839 * | | |0 = EPWMx_CLK, x denotes 0 or 1. 1840 * | | |1 = EPWMx_CLK divide by prescaler, x denotes 0 or 1. 1841 * @var EPWM_T::FDCTL0 1842 * Offset: 0x164 EPWM Fault Detect Control Register 0 1843 * --------------------------------------------------------------------------------------------------- 1844 * |Bits |Field |Descriptions 1845 * | :----: | :----: | :---- | 1846 * |[6:0] |TRMSKCNT |Transition Mask Counter 1847 * | | |The fault detect result will be masked before counter count from 0 to TRMSKCNT. 1848 * | | |1. FDCKS is set to 0: 1849 * | | |Mask time is EPWMx_CLK * (2^FDCKSEL) * (TRMSKCNT+2) 1850 * | | |2. FDCKS is set to 1: 1851 * | | |Mask time EPWMx_CLK * CLKPSC * (2^FDCKSEL) * (TRMSKCNT+2) 1852 * | | |Note: 1853 * | | |CLKPSC (EPWM_CLKPSCn[11:0]) is 0: 1854 * | | |TRMSKCNT >= DGSMPCYC + 2. 1855 * | | |FDCKS is 1 and CLKPSC (EPWM_CLKPSCn[11:0]) is 1: 1856 * | | |TRMSKCNT >= DGSMPCYC + 1. 1857 * | | |FDCKS is 1 and CLKPSC (EPWM_CLKPSCn[11:0]) is 2: 1858 * | | |TRMSKCNT >= DGSMPCYC. 1859 * |[15] |FDMSKEN |Fault Detect Mask Enable Bit 1860 * | | |0 = Fault detect mask function Disabled. 1861 * | | |1 = Fault detect mask function Enabled. 1862 * |[18:16] |DGSMPCYC |Deglitch Sampling Cycle 1863 * | | |1. FDCKS is set to 0: 1864 * | | |Sampling detect signal each EPWMx_CLK * (2^FDCKSEL) period and detect DGSMPCYC+1 times 1865 * | | |2. FDCKS is set to 1: 1866 * | | |Sampling detect signal each EPWMx_CLK * CLKPSC * (2^FDCKSEL) period and detect DGSMPCYC+1 times 1867 * | | |Note: 1868 * | | |CLKPSC (EPWM_CLKPSCn[11:0]) is 0: 1869 * | | |TRMSKCNT >= DGSMPCYC + 2. 1870 * | | |FDCKS is 1 and CLKPSC (EPWM_CLKPSCn[11:0]) is 1: 1871 * | | |TRMSKCNT >= DGSMPCYC + 1. 1872 * | | |FDCKS is 1 and CLKPSC (EPWM_CLKPSCn[11:0]) is 2: 1873 * | | |TRMSKCNT >= DGSMPCYC. 1874 * |[29:28] |FDCKSEL |EPWM Channel Fault Detect Clock Select 1875 * | | |00 = FLT_CLK/1. 1876 * | | |01 = FLT_CLK/2. 1877 * | | |10 = FLT_CLK/4. 1878 * | | |11 = FLT_CLK/8. 1879 * | | |Note: FLT_CLK is FDCKSn (EPWM_FDENn[16+n], n=0,1..5) selected clock. 1880 * |[31] |FDDGEN |Fault Detect Deglitch Enable Bit 1881 * | | |0 = Fault detect deglitch function Disabled. 1882 * | | |1 = Fault detect deglitch function Enabled. 1883 * @var EPWM_T::FDCTL1 1884 * Offset: 0x168 EPWM Fault Detect Control Register 1 1885 * --------------------------------------------------------------------------------------------------- 1886 * |Bits |Field |Descriptions 1887 * | :----: | :----: | :---- | 1888 * |[6:0] |TRMSKCNT |Transition Mask Counter 1889 * | | |The fault detect result will be masked before counter count from 0 to TRMSKCNT. 1890 * | | |1. FDCKS is set to 0: 1891 * | | |Mask time is EPWMx_CLK * (2^FDCKSEL) * (TRMSKCNT+2) 1892 * | | |2. FDCKS is set to 1: 1893 * | | |Mask time EPWMx_CLK * CLKPSC * (2^FDCKSEL) * (TRMSKCNT+2) 1894 * | | |Note: 1895 * | | |CLKPSC (EPWM_CLKPSCn[11:0]) is 0: 1896 * | | |TRMSKCNT >= DGSMPCYC + 2. 1897 * | | |FDCKS is 1 and CLKPSC (EPWM_CLKPSCn[11:0]) is 1: 1898 * | | |TRMSKCNT >= DGSMPCYC + 1. 1899 * | | |FDCKS is 1 and CLKPSC (EPWM_CLKPSCn[11:0]) is 2: 1900 * | | |TRMSKCNT >= DGSMPCYC. 1901 * |[15] |FDMSKEN |Fault Detect Mask Enable Bit 1902 * | | |0 = Fault detect mask function Disabled. 1903 * | | |1 = Fault detect mask function Enabled. 1904 * |[18:16] |DGSMPCYC |Deglitch Sampling Cycle 1905 * | | |1. FDCKS is set to 0: 1906 * | | |Sampling detect signal each EPWMx_CLK * (2^FDCKSEL) period and detect DGSMPCYC+1 times 1907 * | | |2. FDCKS is set to 1: 1908 * | | |Sampling detect signal each EPWMx_CLK * CLKPSC * (2^FDCKSEL) period and detect DGSMPCYC+1 times 1909 * | | |Note: 1910 * | | |CLKPSC (EPWM_CLKPSCn[11:0]) is 0: 1911 * | | |TRMSKCNT >= DGSMPCYC + 2. 1912 * | | |FDCKS is 1 and CLKPSC (EPWM_CLKPSCn[11:0]) is 1: 1913 * | | |TRMSKCNT >= DGSMPCYC + 1. 1914 * | | |FDCKS is 1 and CLKPSC (EPWM_CLKPSCn[11:0]) is 2: 1915 * | | |TRMSKCNT >= DGSMPCYC. 1916 * |[29:28] |FDCKSEL |EPWM Channel Fault Detect Clock Select 1917 * | | |00 = FLT_CLK/1. 1918 * | | |01 = FLT_CLK/2. 1919 * | | |10 = FLT_CLK/4. 1920 * | | |11 = FLT_CLK/8. 1921 * | | |Note: FLT_CLK is FDCKSn (EPWM_FDENn[16+n], n=0,1..5) selected clock. 1922 * |[31] |FDDGEN |Fault Detect Deglitch Enable Bit 1923 * | | |0 = Fault detect deglitch function Disabled. 1924 * | | |1 = Fault detect deglitch function Enabled. 1925 * @var EPWM_T::FDCTL2 1926 * Offset: 0x16C EPWM Fault Detect Control Register 2 1927 * --------------------------------------------------------------------------------------------------- 1928 * |Bits |Field |Descriptions 1929 * | :----: | :----: | :---- | 1930 * |[6:0] |TRMSKCNT |Transition Mask Counter 1931 * | | |The fault detect result will be masked before counter count from 0 to TRMSKCNT. 1932 * | | |1. FDCKS is set to 0: 1933 * | | |Mask time is EPWMx_CLK * (2^FDCKSEL) * (TRMSKCNT+2) 1934 * | | |2. FDCKS is set to 1: 1935 * | | |Mask time EPWMx_CLK * CLKPSC * (2^FDCKSEL) * (TRMSKCNT+2) 1936 * | | |Note: 1937 * | | |CLKPSC (EPWM_CLKPSCn[11:0]) is 0: 1938 * | | |TRMSKCNT >= DGSMPCYC + 2. 1939 * | | |FDCKS is 1 and CLKPSC (EPWM_CLKPSCn[11:0]) is 1: 1940 * | | |TRMSKCNT >= DGSMPCYC + 1. 1941 * | | |FDCKS is 1 and CLKPSC (EPWM_CLKPSCn[11:0]) is 2: 1942 * | | |TRMSKCNT >= DGSMPCYC. 1943 * |[15] |FDMSKEN |Fault Detect Mask Enable Bit 1944 * | | |0 = Fault detect mask function Disabled. 1945 * | | |1 = Fault detect mask function Enabled. 1946 * |[18:16] |DGSMPCYC |Deglitch Sampling Cycle 1947 * | | |1. FDCKS is set to 0: 1948 * | | |Sampling detect signal each EPWMx_CLK * (2^FDCKSEL) period and detect DGSMPCYC+1 times 1949 * | | |2. FDCKS is set to 1: 1950 * | | |Sampling detect signal each EPWMx_CLK * CLKPSC * (2^FDCKSEL) period and detect DGSMPCYC+1 times 1951 * | | |Note: 1952 * | | |CLKPSC (EPWM_CLKPSCn[11:0]) is 0: 1953 * | | |TRMSKCNT >= DGSMPCYC + 2. 1954 * | | |FDCKS is 1 and CLKPSC (EPWM_CLKPSCn[11:0]) is 1: 1955 * | | |TRMSKCNT >= DGSMPCYC + 1. 1956 * | | |FDCKS is 1 and CLKPSC (EPWM_CLKPSCn[11:0]) is 2: 1957 * | | |TRMSKCNT >= DGSMPCYC. 1958 * |[29:28] |FDCKSEL |EPWM Channel Fault Detect Clock Select 1959 * | | |00 = FLT_CLK/1. 1960 * | | |01 = FLT_CLK/2. 1961 * | | |10 = FLT_CLK/4. 1962 * | | |11 = FLT_CLK/8. 1963 * | | |Note: FLT_CLK is FDCKSn (EPWM_FDENn[16+n], n=0,1..5) selected clock. 1964 * |[31] |FDDGEN |Fault Detect Deglitch Enable Bit 1965 * | | |0 = Fault detect deglitch function Disabled. 1966 * | | |1 = Fault detect deglitch function Enabled. 1967 * @var EPWM_T::FDCTL3 1968 * Offset: 0x170 EPWM Fault Detect Control Register 3 1969 * --------------------------------------------------------------------------------------------------- 1970 * |Bits |Field |Descriptions 1971 * | :----: | :----: | :---- | 1972 * |[6:0] |TRMSKCNT |Transition Mask Counter 1973 * | | |The fault detect result will be masked before counter count from 0 to TRMSKCNT. 1974 * | | |1. FDCKS is set to 0: 1975 * | | |Mask time is EPWMx_CLK * (2^FDCKSEL) * (TRMSKCNT+2) 1976 * | | |2. FDCKS is set to 1: 1977 * | | |Mask time EPWMx_CLK * CLKPSC * (2^FDCKSEL) * (TRMSKCNT+2) 1978 * | | |Note: 1979 * | | |CLKPSC (EPWM_CLKPSCn[11:0]) is 0: 1980 * | | |TRMSKCNT >= DGSMPCYC + 2. 1981 * | | |FDCKS is 1 and CLKPSC (EPWM_CLKPSCn[11:0]) is 1: 1982 * | | |TRMSKCNT >= DGSMPCYC + 1. 1983 * | | |FDCKS is 1 and CLKPSC (EPWM_CLKPSCn[11:0]) is 2: 1984 * | | |TRMSKCNT >= DGSMPCYC. 1985 * |[15] |FDMSKEN |Fault Detect Mask Enable Bit 1986 * | | |0 = Fault detect mask function Disabled. 1987 * | | |1 = Fault detect mask function Enabled. 1988 * |[18:16] |DGSMPCYC |Deglitch Sampling Cycle 1989 * | | |1. FDCKS is set to 0: 1990 * | | |Sampling detect signal each EPWMx_CLK * (2^FDCKSEL) period and detect DGSMPCYC+1 times 1991 * | | |2. FDCKS is set to 1: 1992 * | | |Sampling detect signal each EPWMx_CLK * CLKPSC * (2^FDCKSEL) period and detect DGSMPCYC+1 times 1993 * | | |Note: 1994 * | | |CLKPSC (EPWM_CLKPSCn[11:0]) is 0: 1995 * | | |TRMSKCNT >= DGSMPCYC + 2. 1996 * | | |FDCKS is 1 and CLKPSC (EPWM_CLKPSCn[11:0]) is 1: 1997 * | | |TRMSKCNT >= DGSMPCYC + 1. 1998 * | | |FDCKS is 1 and CLKPSC (EPWM_CLKPSCn[11:0]) is 2: 1999 * | | |TRMSKCNT >= DGSMPCYC. 2000 * |[29:28] |FDCKSEL |EPWM Channel Fault Detect Clock Select 2001 * | | |00 = FLT_CLK/1. 2002 * | | |01 = FLT_CLK/2. 2003 * | | |10 = FLT_CLK/4. 2004 * | | |11 = FLT_CLK/8. 2005 * | | |Note: FLT_CLK is FDCKSn (EPWM_FDENn[16+n], n=0,1..5) selected clock. 2006 * |[31] |FDDGEN |Fault Detect Deglitch Enable Bit 2007 * | | |0 = Fault detect deglitch function Disabled. 2008 * | | |1 = Fault detect deglitch function Enabled. 2009 * @var EPWM_T::FDCTL4 2010 * Offset: 0x174 EPWM Fault Detect Control Register 4 2011 * --------------------------------------------------------------------------------------------------- 2012 * |Bits |Field |Descriptions 2013 * | :----: | :----: | :---- | 2014 * |[6:0] |TRMSKCNT |Transition Mask Counter 2015 * | | |The fault detect result will be masked before counter count from 0 to TRMSKCNT. 2016 * | | |1. FDCKS is set to 0: 2017 * | | |Mask time is EPWMx_CLK * (2^FDCKSEL) * (TRMSKCNT+2) 2018 * | | |2. FDCKS is set to 1: 2019 * | | |Mask time EPWMx_CLK * CLKPSC * (2^FDCKSEL) * (TRMSKCNT+2) 2020 * | | |Note: 2021 * | | |CLKPSC (EPWM_CLKPSCn[11:0]) is 0: 2022 * | | |TRMSKCNT >= DGSMPCYC + 2. 2023 * | | |FDCKS is 1 and CLKPSC (EPWM_CLKPSCn[11:0]) is 1: 2024 * | | |TRMSKCNT >= DGSMPCYC + 1. 2025 * | | |FDCKS is 1 and CLKPSC (EPWM_CLKPSCn[11:0]) is 2: 2026 * | | |TRMSKCNT >= DGSMPCYC. 2027 * |[15] |FDMSKEN |Fault Detect Mask Enable Bit 2028 * | | |0 = Fault detect mask function Disabled. 2029 * | | |1 = Fault detect mask function Enabled. 2030 * |[18:16] |DGSMPCYC |Deglitch Sampling Cycle 2031 * | | |1. FDCKS is set to 0: 2032 * | | |Sampling detect signal each EPWMx_CLK * (2^FDCKSEL) period and detect DGSMPCYC+1 times 2033 * | | |2. FDCKS is set to 1: 2034 * | | |Sampling detect signal each EPWMx_CLK * CLKPSC * (2^FDCKSEL) period and detect DGSMPCYC+1 times 2035 * | | |Note: 2036 * | | |CLKPSC (EPWM_CLKPSCn[11:0]) is 0: 2037 * | | |TRMSKCNT >= DGSMPCYC + 2. 2038 * | | |FDCKS is 1 and CLKPSC (EPWM_CLKPSCn[11:0]) is 1: 2039 * | | |TRMSKCNT >= DGSMPCYC + 1. 2040 * | | |FDCKS is 1 and CLKPSC (EPWM_CLKPSCn[11:0]) is 2: 2041 * | | |TRMSKCNT >= DGSMPCYC. 2042 * |[29:28] |FDCKSEL |EPWM Channel Fault Detect Clock Select 2043 * | | |00 = FLT_CLK/1. 2044 * | | |01 = FLT_CLK/2. 2045 * | | |10 = FLT_CLK/4. 2046 * | | |11 = FLT_CLK/8. 2047 * | | |Note: FLT_CLK is FDCKSn (EPWM_FDENn[16+n], n=0,1..5) selected clock. 2048 * |[31] |FDDGEN |Fault Detect Deglitch Enable Bit 2049 * | | |0 = Fault detect deglitch function Disabled. 2050 * | | |1 = Fault detect deglitch function Enabled. 2051 * @var EPWM_T::FDCTL5 2052 * Offset: 0x178 EPWM Fault Detect Control Register 5 2053 * --------------------------------------------------------------------------------------------------- 2054 * |Bits |Field |Descriptions 2055 * | :----: | :----: | :---- | 2056 * |[6:0] |TRMSKCNT |Transition Mask Counter 2057 * | | |The fault detect result will be masked before counter count from 0 to TRMSKCNT. 2058 * | | |1. FDCKS is set to 0: 2059 * | | |Mask time is EPWMx_CLK * (2^FDCKSEL) * (TRMSKCNT+2) 2060 * | | |2. FDCKS is set to 1: 2061 * | | |Mask time EPWMx_CLK * CLKPSC * (2^FDCKSEL) * (TRMSKCNT+2) 2062 * | | |Note: 2063 * | | |CLKPSC (EPWM_CLKPSCn[11:0]) is 0: 2064 * | | |TRMSKCNT >= DGSMPCYC + 2. 2065 * | | |FDCKS is 1 and CLKPSC (EPWM_CLKPSCn[11:0]) is 1: 2066 * | | |TRMSKCNT >= DGSMPCYC + 1. 2067 * | | |FDCKS is 1 and CLKPSC (EPWM_CLKPSCn[11:0]) is 2: 2068 * | | |TRMSKCNT >= DGSMPCYC. 2069 * |[15] |FDMSKEN |Fault Detect Mask Enable Bit 2070 * | | |0 = Fault detect mask function Disabled. 2071 * | | |1 = Fault detect mask function Enabled. 2072 * |[18:16] |DGSMPCYC |Deglitch Sampling Cycle 2073 * | | |1. FDCKS is set to 0: 2074 * | | |Sampling detect signal each EPWMx_CLK * (2^FDCKSEL) period and detect DGSMPCYC+1 times 2075 * | | |2. FDCKS is set to 1: 2076 * | | |Sampling detect signal each EPWMx_CLK * CLKPSC * (2^FDCKSEL) period and detect DGSMPCYC+1 times 2077 * | | |Note: 2078 * | | |CLKPSC (EPWM_CLKPSCn[11:0]) is 0: 2079 * | | |TRMSKCNT >= DGSMPCYC + 2. 2080 * | | |FDCKS is 1 and CLKPSC (EPWM_CLKPSCn[11:0]) is 1: 2081 * | | |TRMSKCNT >= DGSMPCYC + 1. 2082 * | | |FDCKS is 1 and CLKPSC (EPWM_CLKPSCn[11:0]) is 2: 2083 * | | |TRMSKCNT >= DGSMPCYC. 2084 * |[29:28] |FDCKSEL |EPWM Channel Fault Detect Clock Select 2085 * | | |00 = FLT_CLK/1. 2086 * | | |01 = FLT_CLK/2. 2087 * | | |10 = FLT_CLK/4. 2088 * | | |11 = FLT_CLK/8. 2089 * | | |Note: FLT_CLK is FDCKSn (EPWM_FDENn[16+n], n=0,1..5) selected clock. 2090 * |[31] |FDDGEN |Fault Detect Deglitch Enable Bit 2091 * | | |0 = Fault detect deglitch function Disabled. 2092 * | | |1 = Fault detect deglitch function Enabled. 2093 * @var EPWM_T::FDIEN 2094 * Offset: 0x17C EPWM Fault Detect Interrupt Enable Register 2095 * --------------------------------------------------------------------------------------------------- 2096 * |Bits |Field |Descriptions 2097 * | :----: | :----: | :---- | 2098 * |[0] |FDIENn |EPWM Channel n Fault Detect Interrupt Enable Bit 2099 * | | |0 = EPWM Channel n Fault Detect Interrupt Disabled. 2100 * | | |1 = EPWM Channel n Fault Detect Interrupt Enabled. 2101 * @var EPWM_T::FDSTS 2102 * Offset: 0x180 EPWM Fault Detect Interrupt Flag Register 2103 * --------------------------------------------------------------------------------------------------- 2104 * |Bits |Field |Descriptions 2105 * | :----: | :----: | :---- | 2106 * |[5:0] |FDIFn |EPWM Channel n Fault Detect Interrupt Flag Bit 2107 * | | |Fault Detect Interrupt Flag will be set when EPWM output short 2108 * | | |Software can clear this bit by writing 1 to it. 2109 * @var EPWM_T::EADCPSCCTL 2110 * Offset: 0x184 EPWM Trigger EADC Prescale Control Register 2111 * --------------------------------------------------------------------------------------------------- 2112 * |Bits |Field |Descriptions 2113 * | :----: | :----: | :---- | 2114 * |[0] |PSCEN0 |EPWM Trigger EADC Pre-scale Function Enable Bits 2115 * | | |0 = EPWM Trigger EADC Pre-scale Function Disabled. 2116 * | | |1 = EPWM Trigger EADC Pre-scale Function Enabled. 2117 * |[1] |PSCEN1 |EPWM Trigger EADC Pre-scale Function Enable Bits 2118 * | | |0 = EPWM Trigger EADC Pre-scale Function Disabled. 2119 * | | |1 = EPWM Trigger EADC Pre-scale Function Enabled. 2120 * |[2] |PSCEN2 |EPWM Trigger EADC Pre-scale Function Enable Bits 2121 * | | |0 = EPWM Trigger EADC Pre-scale Function Disabled. 2122 * | | |1 = EPWM Trigger EADC Pre-scale Function Enabled. 2123 * |[3] |PSCEN3 |EPWM Trigger EADC Pre-scale Function Enable Bits 2124 * | | |0 = EPWM Trigger EADC Pre-scale Function Disabled. 2125 * | | |1 = EPWM Trigger EADC Pre-scale Function Enabled. 2126 * |[4] |PSCEN4 |EPWM Trigger EADC Pre-scale Function Enable Bits 2127 * | | |0 = EPWM Trigger EADC Pre-scale Function Disabled. 2128 * | | |1 = EPWM Trigger EADC Pre-scale Function Enabled. 2129 * |[5] |PSCEN5 |EPWM Trigger EADC Pre-scale Function Enable Bits 2130 * | | |0 = EPWM Trigger EADC Pre-scale Function Disabled. 2131 * | | |1 = EPWM Trigger EADC Pre-scale Function Enabled. 2132 * @var EPWM_T::EADCPSC0 2133 * Offset: 0x188 EPWM Trigger EADC Prescale Register 0 2134 * --------------------------------------------------------------------------------------------------- 2135 * |Bits |Field |Descriptions 2136 * | :----: | :----: | :---- | 2137 * |[3:0] |EADCPSC0 |EPWM Channel 0 Trigger EADC Prescale 2138 * | | |The register sets the count number which defines (EADCPSC0+1) times of EPWM_CH0 trigger EADC event occurs to trigger EADC and set trigger EADC flag bit EADCTRGF0. 2139 * |[11:8] |EADCPSC1 |EPWM Channel 1 Trigger EADC Prescale 2140 * | | |The register sets the count number which defines (EADCPSC1+1) times of EPWM_CH1 trigger EADC event occurs to trigger EADC and set trigger EADC flag bit EADCTRGF1. 2141 * |[19:16] |EADCPSC2 |EPWM Channel 2 Trigger EADC Prescale 2142 * | | |The register sets the count number which defines (EADCPSC2+1) times of EPWM_CH2 trigger EADC event occurs to trigger EADC and set trigger EADC flag bit EADCTRGF2. 2143 * |[27:24] |EADCPSC3 |EPWM Channel 3 Trigger EADC Prescale 2144 * | | |The register sets the count number which defines (EADCPSC3+1) times of EPWM_CH3 trigger EADC event occurs to trigger EADC and set trigger EADC flag bit EADCTRGF3. 2145 * @var EPWM_T::EADCPSC1 2146 * Offset: 0x18C EPWM Trigger EADC Prescale Register 1 2147 * --------------------------------------------------------------------------------------------------- 2148 * |Bits |Field |Descriptions 2149 * | :----: | :----: | :---- | 2150 * |[3:0] |EADCPSC4 |EPWM Channel 4 Trigger EADC Prescale 2151 * | | |The register sets the count number which defines (EADCPSC4+1) times of EPWM_CH4 trigger EADC event occurs to trigger EADC and set trigger EADC flag bit EADCTRGF4. 2152 * |[11:8] |EADCPSC5 |EPWM Channel 5 Trigger EADC Prescale 2153 * | | |The register sets the count number which defines (EADCPSC5+1) times of EPWM_CH5 trigger EADC event occurs to trigger EADC and set trigger EADC flag bit EADCTRGF5. 2154 * @var EPWM_T::EADCPSCNT0 2155 * Offset: 0x190 EPWM Trigger EADC Prescale Counter Register 0 2156 * --------------------------------------------------------------------------------------------------- 2157 * |Bits |Field |Descriptions 2158 * | :----: | :----: | :---- | 2159 * |[3:0] |PSCNT0 |EPWM Trigger EADC Prescale Counter 0 2160 * | | |User can monitor PSCNT0 to know the current value in 4-bit trigger EADC prescale counter. 2161 * | | |Note 1: user can write only when PSCEN0 is 0. 2162 * | | |Note 2: Write data limitation: PSCNT0 < EADCPSC0. 2163 * |[11:8] |PSCNT1 |EPWM Trigger EADC Prescale Counter 1 2164 * | | |User can monitor PSCNT1 to know the current value in 4-bit trigger EADC prescale counter. 2165 * | | |Note 1: user can write only when PSCEN1 is 0. 2166 * | | |Note 2: Write data limitation: PSCNT1 < EADCPSC1. 2167 * |[19:16] |PSCNT2 |EPWM Trigger EADC Prescale Counter 2 2168 * | | |User can monitor PSCNT2 to know the current value in 4-bit trigger EADC prescale counter. 2169 * | | |Note 1: user can write only when PSCEN2 is 0. 2170 * | | |Note 2: Write data limitation: PSCNT2 < EADCPSC2. 2171 * |[27:24] |PSCNT3 |EPWM Trigger EADC Prescale Counter 3 2172 * | | |User can monitor PSCNT3 to know the current value in 4-bit trigger EADC prescale counter. 2173 * | | |Note 1: user can write only when PSCEN3 is 0. 2174 * | | |Note 2: Write data limitation: PSCNT3 < EADCPSC3. 2175 * @var EPWM_T::EADCPSCNT1 2176 * Offset: 0x194 EPWM Trigger EADC Prescale Counter Register 1 2177 * --------------------------------------------------------------------------------------------------- 2178 * |Bits |Field |Descriptions 2179 * | :----: | :----: | :---- | 2180 * |[3:0] |PSCNT4 |EPWM Trigger EADC Prescale Counter 4 2181 * | | |User can monitor PSCNT4 to know the current value in 4-bit trigger EADC prescale counter. 2182 * | | |Note 1: User can write only when PSCEN4 is 0. 2183 * | | |Note 2: Write data limitation: PSCNT4 < EADCPSC4. 2184 * |[11:8] |PSCNT5 |EPWM Trigger EADC Prescale Counter 5 2185 * | | |User can monitor PSCNT5 to know the current value in 4-bit trigger EADC prescale counter. 2186 * | | |Note 1: User can write only when PSCEN5 is 0. 2187 * | | |Note 2: Write data limitation: PSCNT5 < EADCPSC5. 2188 * @var EPWM_T::CAPINEN 2189 * Offset: 0x200 EPWM Capture Input Enable Register 2190 * --------------------------------------------------------------------------------------------------- 2191 * |Bits |Field |Descriptions 2192 * | :----: | :----: | :---- | 2193 * |[0] |CAPINEN0 |Capture Input Enable Bits 2194 * | | |0 = EPWM Channel capture input path Disabled 2195 * | | |The input of EPWM channel capture function is always regarded as 0. 2196 * | | |1 = EPWM Channel capture input path Enabled 2197 * | | |The input of EPWM channel capture function comes from correlative multifunction pin. 2198 * |[1] |CAPINEN1 |Capture Input Enable Bits 2199 * | | |0 = EPWM Channel capture input path Disabled 2200 * | | |The input of EPWM channel capture function is always regarded as 0. 2201 * | | |1 = EPWM Channel capture input path Enabled 2202 * | | |The input of EPWM channel capture function comes from correlative multifunction pin. 2203 * |[2] |CAPINEN2 |Capture Input Enable Bits 2204 * | | |0 = EPWM Channel capture input path Disabled 2205 * | | |The input of EPWM channel capture function is always regarded as 0. 2206 * | | |1 = EPWM Channel capture input path Enabled 2207 * | | |The input of EPWM channel capture function comes from correlative multifunction pin. 2208 * |[3] |CAPINEN3 |Capture Input Enable Bits 2209 * | | |0 = EPWM Channel capture input path Disabled 2210 * | | |The input of EPWM channel capture function is always regarded as 0. 2211 * | | |1 = EPWM Channel capture input path Enabled 2212 * | | |The input of EPWM channel capture function comes from correlative multifunction pin. 2213 * |[4] |CAPINEN4 |Capture Input Enable Bits 2214 * | | |0 = EPWM Channel capture input path Disabled 2215 * | | |The input of EPWM channel capture function is always regarded as 0. 2216 * | | |1 = EPWM Channel capture input path Enabled 2217 * | | |The input of EPWM channel capture function comes from correlative multifunction pin. 2218 * |[5] |CAPINEN5 |Capture Input Enable Bits 2219 * | | |0 = EPWM Channel capture input path Disabled 2220 * | | |The input of EPWM channel capture function is always regarded as 0. 2221 * | | |1 = EPWM Channel capture input path Enabled 2222 * | | |The input of EPWM channel capture function comes from correlative multifunction pin. 2223 * @var EPWM_T::CAPCTL 2224 * Offset: 0x204 EPWM Capture Control Register 2225 * --------------------------------------------------------------------------------------------------- 2226 * |Bits |Field |Descriptions 2227 * | :----: | :----: | :---- | 2228 * |[0] |CAPEN0 |Capture Function Enable Bits 2229 * | | |0 = Capture function Disabled. EPWM_RCAPDATn/EPWM_FCAPDATn register will not be updated. 2230 * | | |1 = Capture function Enabled 2231 * | | |Capture latched the EPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch). 2232 * |[1] |CAPEN1 |Capture Function Enable Bits 2233 * | | |0 = Capture function Disabled. EPWM_RCAPDATn/EPWM_FCAPDATn register will not be updated. 2234 * | | |1 = Capture function Enabled 2235 * | | |Capture latched the EPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch). 2236 * |[2] |CAPEN2 |Capture Function Enable Bits 2237 * | | |0 = Capture function Disabled. EPWM_RCAPDATn/EPWM_FCAPDATn register will not be updated. 2238 * | | |1 = Capture function Enabled 2239 * | | |Capture latched the EPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch). 2240 * |[3] |CAPEN3 |Capture Function Enable Bits 2241 * | | |0 = Capture function Disabled. EPWM_RCAPDATn/EPWM_FCAPDATn register will not be updated. 2242 * | | |1 = Capture function Enabled 2243 * | | |Capture latched the EPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch). 2244 * |[4] |CAPEN4 |Capture Function Enable Bits 2245 * | | |0 = Capture function Disabled. EPWM_RCAPDATn/EPWM_FCAPDATn register will not be updated. 2246 * | | |1 = Capture function Enabled 2247 * | | |Capture latched the EPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch). 2248 * |[5] |CAPEN5 |Capture Function Enable Bits 2249 * | | |0 = Capture function Disabled. EPWM_RCAPDATn/EPWM_FCAPDATn register will not be updated. 2250 * | | |1 = Capture function Enabled 2251 * | | |Capture latched the EPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch). 2252 * |[8] |CAPINV0 |Capture Inverter Enable Bits 2253 * | | |0 = Capture source inverter Disabled. 2254 * | | |1 = Capture source inverter Enabled. Reverse the input signal from GPIO. 2255 * |[9] |CAPINV1 |Capture Inverter Enable Bits 2256 * | | |0 = Capture source inverter Disabled. 2257 * | | |1 = Capture source inverter Enabled. Reverse the input signal from GPIO. 2258 * |[10] |CAPINV2 |Capture Inverter Enable Bits 2259 * | | |0 = Capture source inverter Disabled. 2260 * | | |1 = Capture source inverter Enabled. Reverse the input signal from GPIO. 2261 * |[11] |CAPINV3 |Capture Inverter Enable Bits 2262 * | | |0 = Capture source inverter Disabled. 2263 * | | |1 = Capture source inverter Enabled. Reverse the input signal from GPIO. 2264 * |[12] |CAPINV4 |Capture Inverter Enable Bits 2265 * | | |0 = Capture source inverter Disabled. 2266 * | | |1 = Capture source inverter Enabled. Reverse the input signal from GPIO. 2267 * |[13] |CAPINV5 |Capture Inverter Enable Bits 2268 * | | |0 = Capture source inverter Disabled. 2269 * | | |1 = Capture source inverter Enabled. Reverse the input signal from GPIO. 2270 * |[16] |RCRLDEN0 |Rising Capture Reload Enable Bits 2271 * | | |0 = Rising capture reload counter Disabled. 2272 * | | |1 = Rising capture reload counter Enabled. 2273 * |[17] |RCRLDEN1 |Rising Capture Reload Enable Bits 2274 * | | |0 = Rising capture reload counter Disabled. 2275 * | | |1 = Rising capture reload counter Enabled. 2276 * |[18] |RCRLDEN2 |Rising Capture Reload Enable Bits 2277 * | | |0 = Rising capture reload counter Disabled. 2278 * | | |1 = Rising capture reload counter Enabled. 2279 * |[19] |RCRLDEN3 |Rising Capture Reload Enable Bits 2280 * | | |0 = Rising capture reload counter Disabled. 2281 * | | |1 = Rising capture reload counter Enabled. 2282 * |[20] |RCRLDEN4 |Rising Capture Reload Enable Bits 2283 * | | |0 = Rising capture reload counter Disabled. 2284 * | | |1 = Rising capture reload counter Enabled. 2285 * |[21] |RCRLDEN5 |Rising Capture Reload Enable Bits 2286 * | | |0 = Rising capture reload counter Disabled. 2287 * | | |1 = Rising capture reload counter Enabled. 2288 * |[24] |FCRLDEN0 |Falling Capture Reload Enable Bits 2289 * | | |0 = Falling capture reload counter Disabled. 2290 * | | |1 = Falling capture reload counter Enabled. 2291 * |[25] |FCRLDEN1 |Falling Capture Reload Enable Bits 2292 * | | |0 = Falling capture reload counter Disabled. 2293 * | | |1 = Falling capture reload counter Enabled. 2294 * |[26] |FCRLDEN2 |Falling Capture Reload Enable Bits 2295 * | | |0 = Falling capture reload counter Disabled. 2296 * | | |1 = Falling capture reload counter Enabled. 2297 * |[27] |FCRLDEN3 |Falling Capture Reload Enable Bits 2298 * | | |0 = Falling capture reload counter Disabled. 2299 * | | |1 = Falling capture reload counter Enabled. 2300 * |[28] |FCRLDEN4 |Falling Capture Reload Enable Bits 2301 * | | |0 = Falling capture reload counter Disabled. 2302 * | | |1 = Falling capture reload counter Enabled. 2303 * |[29] |FCRLDEN5 |Falling Capture Reload Enable Bits 2304 * | | |0 = Falling capture reload counter Disabled. 2305 * | | |1 = Falling capture reload counter Enabled. 2306 * @var EPWM_T::CAPSTS 2307 * Offset: 0x208 EPWM Capture Status Register 2308 * --------------------------------------------------------------------------------------------------- 2309 * |Bits |Field |Descriptions 2310 * | :----: | :----: | :---- | 2311 * |[0] |CRLIFOV0 |Capture Rising Latch Interrupt Flag Overrun Status (Read Only) 2312 * | | |This flag indicates if rising latch happened when the corresponding CRLIFn(EPWM_CAPIF[n]) is 1. 2313 * | | |Note: This bit will be cleared automatically when user clears corresponding CRLIFn(EPWM_CAPIF[n]). 2314 * |[1] |CRLIFOV1 |Capture Rising Latch Interrupt Flag Overrun Status (Read Only) 2315 * | | |This flag indicates if rising latch happened when the corresponding CRLIFn(EPWM_CAPIF[n]) is 1. 2316 * | | |Note: This bit will be cleared automatically when user clears corresponding CRLIFn(EPWM_CAPIF[n]). 2317 * |[2] |CRLIFOV2 |Capture Rising Latch Interrupt Flag Overrun Status (Read Only) 2318 * | | |This flag indicates if rising latch happened when the corresponding CRLIFn(EPWM_CAPIF[n]) is 1. 2319 * | | |Note: This bit will be cleared automatically when user clears corresponding CRLIFn(EPWM_CAPIF[n]). 2320 * |[3] |CRLIFOV3 |Capture Rising Latch Interrupt Flag Overrun Status (Read Only) 2321 * | | |This flag indicates if rising latch happened when the corresponding CRLIFn(EPWM_CAPIF[n]) is 1. 2322 * | | |Note: This bit will be cleared automatically when user clears corresponding CRLIFn(EPWM_CAPIF[n]). 2323 * |[4] |CRLIFOV4 |Capture Rising Latch Interrupt Flag Overrun Status (Read Only) 2324 * | | |This flag indicates if rising latch happened when the corresponding CRLIFn(EPWM_CAPIF[n]) is 1. 2325 * | | |Note: This bit will be cleared automatically when user clears corresponding CRLIFn(EPWM_CAPIF[n]). 2326 * |[5] |CRLIFOV5 |Capture Rising Latch Interrupt Flag Overrun Status (Read Only) 2327 * | | |This flag indicates if rising latch happened when the corresponding CRLIFn(EPWM_CAPIF[n]) is 1. 2328 * | | |Note: This bit will be cleared automatically when user clears corresponding CRLIFn(EPWM_CAPIF[n]). 2329 * |[8] |CFLIFOV0 |Capture Falling Latch Interrupt Flag Overrun Status (Read Only) 2330 * | | |This flag indicates if falling latch happened when the corresponding CFLIFn(EPWM_CAPIF[8+n]) is 1. 2331 * | | |Note: This bit will be cleared automatically when user clears corresponding CFLIFn(EPWM_CAPIF[8+n]). 2332 * |[9] |CFLIFOV1 |Capture Falling Latch Interrupt Flag Overrun Status (Read Only) 2333 * | | |This flag indicates if falling latch happened when the corresponding CFLIFn(EPWM_CAPIF[8+n]) is 1. 2334 * | | |Note: This bit will be cleared automatically when user clears corresponding CFLIFn(EPWM_CAPIF[8+n]). 2335 * |[10] |CFLIFOV2 |Capture Falling Latch Interrupt Flag Overrun Status (Read Only) 2336 * | | |This flag indicates if falling latch happened when the corresponding CFLIFn(EPWM_CAPIF[8+n]) is 1. 2337 * | | |Note: This bit will be cleared automatically when user clears corresponding CFLIFn(EPWM_CAPIF[8+n]). 2338 * |[11] |CFLIFOV3 |Capture Falling Latch Interrupt Flag Overrun Status (Read Only) 2339 * | | |This flag indicates if falling latch happened when the corresponding CFLIFn(EPWM_CAPIF[8+n]) is 1. 2340 * | | |Note: This bit will be cleared automatically when user clears corresponding CFLIFn(EPWM_CAPIF[8+n]). 2341 * |[12] |CFLIFOV4 |Capture Falling Latch Interrupt Flag Overrun Status (Read Only) 2342 * | | |This flag indicates if falling latch happened when the corresponding CFLIFn(EPWM_CAPIF[8+n]) is 1. 2343 * | | |Note: This bit will be cleared automatically when user clears corresponding CFLIFn(EPWM_CAPIF[8+n]). 2344 * |[13] |CFLIFOV5 |Capture Falling Latch Interrupt Flag Overrun Status (Read Only) 2345 * | | |This flag indicates if falling latch happened when the corresponding CFLIFn(EPWM_CAPIF[8+n]) is 1. 2346 * | | |Note: This bit will be cleared automatically when user clears corresponding CFLIFn(EPWM_CAPIF[8+n]). 2347 * @var EPWM_T::RCAPDAT0 2348 * Offset: 0x20C EPWM Rising Capture Data Register 0 2349 * --------------------------------------------------------------------------------------------------- 2350 * |Bits |Field |Descriptions 2351 * | :----: | :----: | :---- | 2352 * |[15:0] |RCAPDAT |EPWM Rising Capture Data Register (Read Only) 2353 * | | |When rising capture condition happened, the EPWM counter value will be saved in this register. 2354 * @var EPWM_T::FCAPDAT0 2355 * Offset: 0x210 EPWM Falling Capture Data Register 0 2356 * --------------------------------------------------------------------------------------------------- 2357 * |Bits |Field |Descriptions 2358 * | :----: | :----: | :---- | 2359 * |[15:0] |FCAPDAT |EPWM Falling Capture Data Register (Read Only) 2360 * | | |When falling capture condition happened, the EPWM counter value will be saved in this register. 2361 * @var EPWM_T::RCAPDAT1 2362 * Offset: 0x214 EPWM Rising Capture Data Register 1 2363 * --------------------------------------------------------------------------------------------------- 2364 * |Bits |Field |Descriptions 2365 * | :----: | :----: | :---- | 2366 * |[15:0] |RCAPDAT |EPWM Rising Capture Data Register (Read Only) 2367 * | | |When rising capture condition happened, the EPWM counter value will be saved in this register. 2368 * @var EPWM_T::FCAPDAT1 2369 * Offset: 0x218 EPWM Falling Capture Data Register 1 2370 * --------------------------------------------------------------------------------------------------- 2371 * |Bits |Field |Descriptions 2372 * | :----: | :----: | :---- | 2373 * |[15:0] |FCAPDAT |EPWM Falling Capture Data Register (Read Only) 2374 * | | |When falling capture condition happened, the EPWM counter value will be saved in this register. 2375 * @var EPWM_T::RCAPDAT2 2376 * Offset: 0x21C EPWM Rising Capture Data Register 2 2377 * --------------------------------------------------------------------------------------------------- 2378 * |Bits |Field |Descriptions 2379 * | :----: | :----: | :---- | 2380 * |[15:0] |RCAPDAT |EPWM Rising Capture Data Register (Read Only) 2381 * | | |When rising capture condition happened, the EPWM counter value will be saved in this register. 2382 * @var EPWM_T::FCAPDAT2 2383 * Offset: 0x220 EPWM Falling Capture Data Register 2 2384 * --------------------------------------------------------------------------------------------------- 2385 * |Bits |Field |Descriptions 2386 * | :----: | :----: | :---- | 2387 * |[15:0] |FCAPDAT |EPWM Falling Capture Data Register (Read Only) 2388 * | | |When falling capture condition happened, the EPWM counter value will be saved in this register. 2389 * @var EPWM_T::RCAPDAT3 2390 * Offset: 0x224 EPWM Rising Capture Data Register 3 2391 * --------------------------------------------------------------------------------------------------- 2392 * |Bits |Field |Descriptions 2393 * | :----: | :----: | :---- | 2394 * |[15:0] |RCAPDAT |EPWM Rising Capture Data Register (Read Only) 2395 * | | |When rising capture condition happened, the EPWM counter value will be saved in this register. 2396 * @var EPWM_T::FCAPDAT3 2397 * Offset: 0x228 EPWM Falling Capture Data Register 3 2398 * --------------------------------------------------------------------------------------------------- 2399 * |Bits |Field |Descriptions 2400 * | :----: | :----: | :---- | 2401 * |[15:0] |FCAPDAT |EPWM Falling Capture Data Register (Read Only) 2402 * | | |When falling capture condition happened, the EPWM counter value will be saved in this register. 2403 * @var EPWM_T::RCAPDAT4 2404 * Offset: 0x22C EPWM Rising Capture Data Register 4 2405 * --------------------------------------------------------------------------------------------------- 2406 * |Bits |Field |Descriptions 2407 * | :----: | :----: | :---- | 2408 * |[15:0] |RCAPDAT |EPWM Rising Capture Data Register (Read Only) 2409 * | | |When rising capture condition happened, the EPWM counter value will be saved in this register. 2410 * @var EPWM_T::FCAPDAT4 2411 * Offset: 0x230 EPWM Falling Capture Data Register 4 2412 * --------------------------------------------------------------------------------------------------- 2413 * |Bits |Field |Descriptions 2414 * | :----: | :----: | :---- | 2415 * |[15:0] |FCAPDAT |EPWM Falling Capture Data Register (Read Only) 2416 * | | |When falling capture condition happened, the EPWM counter value will be saved in this register. 2417 * @var EPWM_T::RCAPDAT5 2418 * Offset: 0x234 EPWM Rising Capture Data Register 5 2419 * --------------------------------------------------------------------------------------------------- 2420 * |Bits |Field |Descriptions 2421 * | :----: | :----: | :---- | 2422 * |[15:0] |RCAPDAT |EPWM Rising Capture Data Register (Read Only) 2423 * | | |When rising capture condition happened, the EPWM counter value will be saved in this register. 2424 * @var EPWM_T::FCAPDAT5 2425 * Offset: 0x238 EPWM Falling Capture Data Register 5 2426 * --------------------------------------------------------------------------------------------------- 2427 * |Bits |Field |Descriptions 2428 * | :----: | :----: | :---- | 2429 * |[15:0] |FCAPDAT |EPWM Falling Capture Data Register (Read Only) 2430 * | | |When falling capture condition happened, the EPWM counter value will be saved in this register. 2431 * @var EPWM_T::PDMACTL 2432 * Offset: 0x23C EPWM PDMA Control Register 2433 * --------------------------------------------------------------------------------------------------- 2434 * |Bits |Field |Descriptions 2435 * | :----: | :----: | :---- | 2436 * |[0] |CHEN0_1 |Channel 0/1 PDMA Enable Bit 2437 * | | |0 = Channel 0/1 PDMA function Disabled. 2438 * | | |1 = Channel 0/1 PDMA function Enabled for the channel 0/1 captured data and transfer to memory. 2439 * |[2:1] |CAPMOD0_1 |Select EPWM_RCAPDAT0/1 or EPWM_FCAPDAT0/1 to Do PDMA Transfer 2440 * | | |00 = Reserved. 2441 * | | |01 = EPWM_RCAPDAT0/1. 2442 * | | |10 = EPWM_FCAPDAT0/1. 2443 * | | |11 = Both EPWM_RCAPDAT0/1 and EPWM_FCAPDAT0/1. 2444 * |[3] |CAPORD0_1 |Capture Channel 0/1 Rising/Falling Order 2445 * | | |Set this bit to determine whether the EPWM_RCAPDAT0/1 or EPWM_FCAPDAT0/1 is the first captured data transferred to memory through PDMA when CAPMOD0_1 =11. 2446 * | | |0 = EPWM_FCAPDAT0/1 is the first captured data to memory. 2447 * | | |1 = EPWM_RCAPDAT0/1 is the first captured data to memory. 2448 * |[4] |CHSEL0_1 |Select Channel 0/1 to Do PDMA Transfer 2449 * | | |0 = Channel0. 2450 * | | |1 = Channel1. 2451 * |[8] |CHEN2_3 |Channel 2/3 PDMA Enable Bit 2452 * | | |0 = Channel 2/3 PDMA function Disabled. 2453 * | | |1 = Channel 2/3 PDMA function Enabled for the channel 2/3 captured data and transfer to memory. 2454 * |[10:9] |CAPMOD2_3 |Select EPWM_RCAPDAT2/3 or EPWM_FCAODAT2/3 to Do PDMA Transfer 2455 * | | |00 = Reserved. 2456 * | | |01 = EPWM_RCAPDAT2/3. 2457 * | | |10 = EPWM_FCAPDAT2/3. 2458 * | | |11 = Both EPWM_RCAPDAT2/3 and EPWM_FCAPDAT2/3. 2459 * |[11] |CAPORD2_3 |Capture Channel 2/3 Rising/Falling Order 2460 * | | |Set this bit to determine whether the EPWM_RCAPDAT2/3 or EPWM_FCAPDAT2/3 is the first captured data transferred to memory through PDMA when CAPMOD2_3 =11. 2461 * | | |0 = EPWM_FCAPDAT2/3 is the first captured data to memory. 2462 * | | |1 = EPWM_RCAPDAT2/3 is the first captured data to memory. 2463 * |[12] |CHSEL2_3 |Select Channel 2/3 to Do PDMA Transfer 2464 * | | |0 = Channel2. 2465 * | | |1 = Channel3. 2466 * |[16] |CHEN4_5 |Channel 4/5 PDMA Enable Bit 2467 * | | |0 = Channel 4/5 PDMA function Disabled. 2468 * | | |1 = Channel 4/5 PDMA function Enabled for the channel 4/5 captured data and transfer to memory. 2469 * |[18:17] |CAPMOD4_5 |Select EPWM_RCAPDAT4/5 or EPWM_FCAPDAT4/5 to Do PDMA Transfer 2470 * | | |00 = Reserved. 2471 * | | |01 = EPWM_RCAPDAT4/5. 2472 * | | |10 = EPWM_FCAPDAT4/5. 2473 * | | |11 = Both EPWM_RCAPDAT4/5 and EPWM_FCAPDAT4/5. 2474 * |[19] |CAPORD4_5 |Capture Channel 4/5 Rising/Falling Order 2475 * | | |Set this bit to determine whether the EPWM_RCAPDAT4/5 or EPWM_FCAPDAT4/5 is the first captured data transferred to memory through PDMA when CAPMOD4_5 =11. 2476 * | | |0 = EPWM_FCAPDAT4/5 is the first captured data to memory. 2477 * | | |1 = EPWM_RCAPDAT4/5 is the first captured data to memory. 2478 * |[20] |CHSEL4_5 |Select Channel 4/5 to Do PDMA Transfer 2479 * | | |0 = Channel4. 2480 * | | |1 = Channel5. 2481 * @var EPWM_T::PDMACAP[3] 2482 * Offset: 0x240 EPWM Capture Channel 01 PDMA Register 2483 * --------------------------------------------------------------------------------------------------- 2484 * |Bits |Field |Descriptions 2485 * | :----: | :----: | :---- | 2486 * |[15:0] |CAPBUF |EPWM Capture PDMA Register (Read Only) 2487 * | | |This register is used as a buffer to transfer EPWM capture rising or falling data to memory by PDMA. 2488 * @var EPWM_T::CAPIEN 2489 * Offset: 0x250 EPWM Capture Interrupt Enable Register 2490 * --------------------------------------------------------------------------------------------------- 2491 * |Bits |Field |Descriptions 2492 * | :----: | :----: | :---- | 2493 * |[0] |CAPRIEN0 |EPWM Capture Rising Latch Interrupt Enable Bits 2494 * | | |0 = Capture rising edge latch interrupt Disabled. 2495 * | | |1 = Capture rising edge latch interrupt Enabled. 2496 * |[1] |CAPRIEN1 |EPWM Capture Rising Latch Interrupt Enable Bits 2497 * | | |0 = Capture rising edge latch interrupt Disabled. 2498 * | | |1 = Capture rising edge latch interrupt Enabled. 2499 * |[2] |CAPRIEN2 |EPWM Capture Rising Latch Interrupt Enable Bits 2500 * | | |0 = Capture rising edge latch interrupt Disabled. 2501 * | | |1 = Capture rising edge latch interrupt Enabled. 2502 * |[3] |CAPRIEN3 |EPWM Capture Rising Latch Interrupt Enable Bits 2503 * | | |0 = Capture rising edge latch interrupt Disabled. 2504 * | | |1 = Capture rising edge latch interrupt Enabled. 2505 * |[4] |CAPRIEN4 |EPWM Capture Rising Latch Interrupt Enable Bits 2506 * | | |0 = Capture rising edge latch interrupt Disabled. 2507 * | | |1 = Capture rising edge latch interrupt Enabled. 2508 * |[5] |CAPRIEN5 |EPWM Capture Rising Latch Interrupt Enable Bits 2509 * | | |0 = Capture rising edge latch interrupt Disabled. 2510 * | | |1 = Capture rising edge latch interrupt Enabled. 2511 * |[8] |CAPFIEN0 |EPWM Capture Falling Latch Interrupt Enable Bits 2512 * | | |0 = Capture falling edge latch interrupt Disabled. 2513 * | | |1 = Capture falling edge latch interrupt Enabled. 2514 * |[9] |CAPFIEN1 |EPWM Capture Falling Latch Interrupt Enable Bits 2515 * | | |0 = Capture falling edge latch interrupt Disabled. 2516 * | | |1 = Capture falling edge latch interrupt Enabled. 2517 * |[10] |CAPFIEN2 |EPWM Capture Falling Latch Interrupt Enable Bits 2518 * | | |0 = Capture falling edge latch interrupt Disabled. 2519 * | | |1 = Capture falling edge latch interrupt Enabled. 2520 * |[11] |CAPFIEN3 |EPWM Capture Falling Latch Interrupt Enable Bits 2521 * | | |0 = Capture falling edge latch interrupt Disabled. 2522 * | | |1 = Capture falling edge latch interrupt Enabled. 2523 * |[12] |CAPFIEN4 |EPWM Capture Falling Latch Interrupt Enable Bits 2524 * | | |0 = Capture falling edge latch interrupt Disabled. 2525 * | | |1 = Capture falling edge latch interrupt Enabled. 2526 * |[13] |CAPFIEN5 |EPWM Capture Falling Latch Interrupt Enable Bits 2527 * | | |0 = Capture falling edge latch interrupt Disabled. 2528 * | | |1 = Capture falling edge latch interrupt Enabled. 2529 * @var EPWM_T::CAPIF 2530 * Offset: 0x254 EPWM Capture Interrupt Flag Register 2531 * --------------------------------------------------------------------------------------------------- 2532 * |Bits |Field |Descriptions 2533 * | :----: | :----: | :---- | 2534 * |[0] |CRLIF0 |EPWM Capture Rising Latch Interrupt Flag 2535 * | | |0 = No capture rising latch condition happened. 2536 * | | |1 = Capture rising latch condition happened, this flag will be set to high. 2537 * | | |Note 1: When Capture with PDMA operating, EPWM_CAPIF corresponding channel CRLIFn will be cleared by hardware after PDMA transfer data. 2538 * | | |Note 2: This bit is cleared by writing 1 to it. 2539 * |[1] |CRLIF1 |EPWM Capture Rising Latch Interrupt Flag 2540 * | | |0 = No capture rising latch condition happened. 2541 * | | |1 = Capture rising latch condition happened, this flag will be set to high. 2542 * | | |Note 1: When Capture with PDMA operating, EPWM_CAPIF corresponding channel CRLIFn will be cleared by hardware after PDMA transfer data. 2543 * | | |Note 2: This bit is cleared by writing 1 to it. 2544 * |[2] |CRLIF2 |EPWM Capture Rising Latch Interrupt Flag 2545 * | | |0 = No capture rising latch condition happened. 2546 * | | |1 = Capture rising latch condition happened, this flag will be set to high. 2547 * | | |Note 1: When Capture with PDMA operating, EPWM_CAPIF corresponding channel CRLIFn will be cleared by hardware after PDMA transfer data. 2548 * | | |Note 2: This bit is cleared by writing 1 to it. 2549 * |[3] |CRLIF3 |EPWM Capture Rising Latch Interrupt Flag 2550 * | | |0 = No capture rising latch condition happened. 2551 * | | |1 = Capture rising latch condition happened, this flag will be set to high. 2552 * | | |Note 1: When Capture with PDMA operating, EPWM_CAPIF corresponding channel CRLIFn will be cleared by hardware after PDMA transfer data. 2553 * | | |Note 2: This bit is cleared by writing 1 to it. 2554 * |[4] |CRLIF4 |EPWM Capture Rising Latch Interrupt Flag 2555 * | | |0 = No capture rising latch condition happened. 2556 * | | |1 = Capture rising latch condition happened, this flag will be set to high. 2557 * | | |Note 1: When Capture with PDMA operating, EPWM_CAPIF corresponding channel CRLIFn will be cleared by hardware after PDMA transfer data. 2558 * | | |Note 2: This bit is cleared by writing 1 to it. 2559 * |[5] |CRLIF5 |EPWM Capture Rising Latch Interrupt Flag 2560 * | | |0 = No capture rising latch condition happened. 2561 * | | |1 = Capture rising latch condition happened, this flag will be set to high. 2562 * | | |Note 1: When Capture with PDMA operating, EPWM_CAPIF corresponding channel CRLIFn will be cleared by hardware after PDMA transfer data. 2563 * | | |Note 2: This bit is cleared by writing 1 to it. 2564 * |[8] |CFLIF0 |EPWM Capture Falling Latch Interrupt Flag 2565 * | | |0 = No capture falling latch condition happened. 2566 * | | |1 = Capture falling latch condition happened, and this flag will be set to high. 2567 * | | |Note 1: When Capture with PDMA operating, EPWM_CAPIF corresponding channel CFLIFn will be cleared by hardware after PDMA transfer data. 2568 * | | |Note 2: This bit is cleared by writing 1 to it. 2569 * |[9] |CFLIF1 |EPWM Capture Falling Latch Interrupt Flag 2570 * | | |0 = No capture falling latch condition happened. 2571 * | | |1 = Capture falling latch condition happened, and this flag will be set to high. 2572 * | | |Note 1: When Capture with PDMA operating, EPWM_CAPIF corresponding channel CFLIFn will be cleared by hardware after PDMA transfer data. 2573 * | | |Note 2: This bit is cleared by writing 1 to it. 2574 * |[10] |CFLIF2 |EPWM Capture Falling Latch Interrupt Flag 2575 * | | |0 = No capture falling latch condition happened. 2576 * | | |1 = Capture falling latch condition happened, and this flag will be set to high. 2577 * | | |Note 1: When Capture with PDMA operating, EPWM_CAPIF corresponding channel CFLIFn will be cleared by hardware after PDMA transfer data. 2578 * | | |Note 2: This bit is cleared by writing 1 to it. 2579 * |[11] |CFLIF3 |EPWM Capture Falling Latch Interrupt Flag 2580 * | | |0 = No capture falling latch condition happened. 2581 * | | |1 = Capture falling latch condition happened, and this flag will be set to high. 2582 * | | |Note 1: When Capture with PDMA operating, EPWM_CAPIF corresponding channel CFLIFn will be cleared by hardware after PDMA transfer data. 2583 * | | |Note 2: This bit is cleared by writing 1 to it. 2584 * |[12] |CFLIF4 |EPWM Capture Falling Latch Interrupt Flag 2585 * | | |0 = No capture falling latch condition happened. 2586 * | | |1 = Capture falling latch condition happened, and this flag will be set to high. 2587 * | | |Note 1: When Capture with PDMA operating, EPWM_CAPIF corresponding channel CFLIFn will be cleared by hardware after PDMA transfer data. 2588 * | | |Note 2: This bit is cleared by writing 1 to it. 2589 * |[13] |CFLIF5 |EPWM Capture Falling Latch Interrupt Flag 2590 * | | |0 = No capture falling latch condition happened. 2591 * | | |1 = Capture falling latch condition happened, and this flag will be set to high. 2592 * | | |Note 1: When Capture with PDMA operating, EPWM_CAPIF corresponding channel CFLIFn will be cleared by hardware after PDMA transfer data. 2593 * | | |Note 2: This bit is cleared by writing 1 to it. 2594 * @var EPWM_T::CAPNF0 2595 * Offset: 0x258 EPWM Capture Input Noise Filter Register 0 2596 * --------------------------------------------------------------------------------------------------- 2597 * |Bits |Field |Descriptions 2598 * | :----: | :----: | :---- | 2599 * |[0] |CAPNFEN |Capture Noise Filter Enable 2600 * | | |0 = Capture Noise Filter function Disabled. 2601 * | | |1 = Capture Noise Filter function Enabled. 2602 * |[6:4] |CAPNFSEL |Capture Edge Detector Noise Filter Clock Selection 2603 * | | |000 = Filter clock = PCLK. 2604 * | | |001 = Filter clock = PCLK/2. 2605 * | | |010 = Filter clock = PCLK/4. 2606 * | | |011 = Filter clock = PCLK/8. 2607 * | | |100 = Filter clock = PCLK/16. 2608 * | | |101 = Filter clock = PCLK/32. 2609 * | | |110 = Filter clock = PCLK/64. 2610 * | | |111 = Filter clock = PCLK/128. 2611 * |[10:8] |CAPNFCNT |Capture Edge Detector Noise Filter Count 2612 * | | |The register bits control the capture filter counter to count from 0 to CAPNFCNT. 2613 * @var EPWM_T::CAPNF1 2614 * Offset: 0x25C EPWM Capture Input Noise Filter Register 1 2615 * --------------------------------------------------------------------------------------------------- 2616 * |Bits |Field |Descriptions 2617 * | :----: | :----: | :---- | 2618 * |[0] |CAPNFEN |Capture Noise Filter Enable 2619 * | | |0 = Capture Noise Filter function Disabled. 2620 * | | |1 = Capture Noise Filter function Enabled. 2621 * |[6:4] |CAPNFSEL |Capture Edge Detector Noise Filter Clock Selection 2622 * | | |000 = Filter clock = PCLK. 2623 * | | |001 = Filter clock = PCLK/2. 2624 * | | |010 = Filter clock = PCLK/4. 2625 * | | |011 = Filter clock = PCLK/8. 2626 * | | |100 = Filter clock = PCLK/16. 2627 * | | |101 = Filter clock = PCLK/32. 2628 * | | |110 = Filter clock = PCLK/64. 2629 * | | |111 = Filter clock = PCLK/128. 2630 * |[10:8] |CAPNFCNT |Capture Edge Detector Noise Filter Count 2631 * | | |The register bits control the capture filter counter to count from 0 to CAPNFCNT. 2632 * @var EPWM_T::CAPNF2 2633 * Offset: 0x260 EPWM Capture Input Noise Filter Register 2 2634 * --------------------------------------------------------------------------------------------------- 2635 * |Bits |Field |Descriptions 2636 * | :----: | :----: | :---- | 2637 * |[0] |CAPNFEN |Capture Noise Filter Enable 2638 * | | |0 = Capture Noise Filter function Disabled. 2639 * | | |1 = Capture Noise Filter function Enabled. 2640 * |[6:4] |CAPNFSEL |Capture Edge Detector Noise Filter Clock Selection 2641 * | | |000 = Filter clock = PCLK. 2642 * | | |001 = Filter clock = PCLK/2. 2643 * | | |010 = Filter clock = PCLK/4. 2644 * | | |011 = Filter clock = PCLK/8. 2645 * | | |100 = Filter clock = PCLK/16. 2646 * | | |101 = Filter clock = PCLK/32. 2647 * | | |110 = Filter clock = PCLK/64. 2648 * | | |111 = Filter clock = PCLK/128. 2649 * |[10:8] |CAPNFCNT |Capture Edge Detector Noise Filter Count 2650 * | | |The register bits control the capture filter counter to count from 0 to CAPNFCNT. 2651 * @var EPWM_T::CAPNF3 2652 * Offset: 0x264 EPWM Capture Input Noise Filter Register 3 2653 * --------------------------------------------------------------------------------------------------- 2654 * |Bits |Field |Descriptions 2655 * | :----: | :----: | :---- | 2656 * |[0] |CAPNFEN |Capture Noise Filter Enable 2657 * | | |0 = Capture Noise Filter function Disabled. 2658 * | | |1 = Capture Noise Filter function Enabled. 2659 * |[6:4] |CAPNFSEL |Capture Edge Detector Noise Filter Clock Selection 2660 * | | |000 = Filter clock = PCLK. 2661 * | | |001 = Filter clock = PCLK/2. 2662 * | | |010 = Filter clock = PCLK/4. 2663 * | | |011 = Filter clock = PCLK/8. 2664 * | | |100 = Filter clock = PCLK/16. 2665 * | | |101 = Filter clock = PCLK/32. 2666 * | | |110 = Filter clock = PCLK/64. 2667 * | | |111 = Filter clock = PCLK/128. 2668 * |[10:8] |CAPNFCNT |Capture Edge Detector Noise Filter Count 2669 * | | |The register bits control the capture filter counter to count from 0 to CAPNFCNT. 2670 * @var EPWM_T::CAPNF4 2671 * Offset: 0x268 EPWM Capture Input Noise Filter Register 4 2672 * --------------------------------------------------------------------------------------------------- 2673 * |Bits |Field |Descriptions 2674 * | :----: | :----: | :---- | 2675 * |[0] |CAPNFEN |Capture Noise Filter Enable 2676 * | | |0 = Capture Noise Filter function Disabled. 2677 * | | |1 = Capture Noise Filter function Enabled. 2678 * |[6:4] |CAPNFSEL |Capture Edge Detector Noise Filter Clock Selection 2679 * | | |000 = Filter clock = PCLK. 2680 * | | |001 = Filter clock = PCLK/2. 2681 * | | |010 = Filter clock = PCLK/4. 2682 * | | |011 = Filter clock = PCLK/8. 2683 * | | |100 = Filter clock = PCLK/16. 2684 * | | |101 = Filter clock = PCLK/32. 2685 * | | |110 = Filter clock = PCLK/64. 2686 * | | |111 = Filter clock = PCLK/128. 2687 * |[10:8] |CAPNFCNT |Capture Edge Detector Noise Filter Count 2688 * | | |The register bits control the capture filter counter to count from 0 to CAPNFCNT. 2689 * @var EPWM_T::CAPNF5 2690 * Offset: 0x26C EPWM Capture Input Noise Filter Register 5 2691 * --------------------------------------------------------------------------------------------------- 2692 * |Bits |Field |Descriptions 2693 * | :----: | :----: | :---- | 2694 * |[0] |CAPNFEN |Capture Noise Filter Enable 2695 * | | |0 = Capture Noise Filter function Disabled. 2696 * | | |1 = Capture Noise Filter function Enabled. 2697 * |[6:4] |CAPNFSEL |Capture Edge Detector Noise Filter Clock Selection 2698 * | | |000 = Filter clock = PCLK. 2699 * | | |001 = Filter clock = PCLK/2. 2700 * | | |010 = Filter clock = PCLK/4. 2701 * | | |011 = Filter clock = PCLK/8. 2702 * | | |100 = Filter clock = PCLK/16. 2703 * | | |101 = Filter clock = PCLK/32. 2704 * | | |110 = Filter clock = PCLK/64. 2705 * | | |111 = Filter clock = PCLK/128. 2706 * |[10:8] |CAPNFCNT |Capture Edge Detector Noise Filter Count 2707 * | | |The register bits control the capture filter counter to count from 0 to CAPNFCNT. 2708 * @var EPWM_T::EXTETCTL0 2709 * Offset: 0x270 EPWM External Event Trigger Control Register 0 2710 * --------------------------------------------------------------------------------------------------- 2711 * |Bits |Field |Descriptions 2712 * | :----: | :----: | :---- | 2713 * |[0] |EXETEN |External Event Trigger Enable Bit 2714 * | | |0 = External Event Trigger function Disabled. 2715 * | | |1 = External Event Trigger function Enabled. 2716 * |[5:4] |CNTACTS |Counter Action Selection 2717 * | | |00 = Counter reset. 2718 * | | |01 = Counter start. 2719 * | | |10 = Counter reset and start. 2720 * | | |11 = Reserved. 2721 * |[11:8] |EXTTRGS |External Trigger Selection 2722 * | | |0000 = INT0. 2723 * | | |0001 = INT1. 2724 * | | |0010 = INT2. 2725 * | | |0011 = INT3. 2726 * | | |0100 = INT4. 2727 * | | |0101 = INT5. 2728 * | | |0110 = INT6. 2729 * | | |0111 = INT7. 2730 * | | |Other = Reserved. 2731 * @var EPWM_T::EXTETCTL1 2732 * Offset: 0x274 EPWM External Event Trigger Control Register 1 2733 * --------------------------------------------------------------------------------------------------- 2734 * |Bits |Field |Descriptions 2735 * | :----: | :----: | :---- | 2736 * |[0] |EXETEN |External Event Trigger Enable Bit 2737 * | | |0 = External Event Trigger function Disabled. 2738 * | | |1 = External Event Trigger function Enabled. 2739 * |[5:4] |CNTACTS |Counter Action Selection 2740 * | | |00 = Counter reset. 2741 * | | |01 = Counter start. 2742 * | | |10 = Counter reset and start. 2743 * | | |11 = Reserved. 2744 * |[11:8] |EXTTRGS |External Trigger Selection 2745 * | | |0000 = INT0. 2746 * | | |0001 = INT1. 2747 * | | |0010 = INT2. 2748 * | | |0011 = INT3. 2749 * | | |0100 = INT4. 2750 * | | |0101 = INT5. 2751 * | | |0110 = INT6. 2752 * | | |0111 = INT7. 2753 * | | |Other = Reserved. 2754 * @var EPWM_T::EXTETCTL2 2755 * Offset: 0x278 EPWM External Event Trigger Control Register 2 2756 * --------------------------------------------------------------------------------------------------- 2757 * |Bits |Field |Descriptions 2758 * | :----: | :----: | :---- | 2759 * |[0] |EXETEN |External Event Trigger Enable Bit 2760 * | | |0 = External Event Trigger function Disabled. 2761 * | | |1 = External Event Trigger function Enabled. 2762 * |[5:4] |CNTACTS |Counter Action Selection 2763 * | | |00 = Counter reset. 2764 * | | |01 = Counter start. 2765 * | | |10 = Counter reset and start. 2766 * | | |11 = Reserved. 2767 * |[11:8] |EXTTRGS |External Trigger Selection 2768 * | | |0000 = INT0. 2769 * | | |0001 = INT1. 2770 * | | |0010 = INT2. 2771 * | | |0011 = INT3. 2772 * | | |0100 = INT4. 2773 * | | |0101 = INT5. 2774 * | | |0110 = INT6. 2775 * | | |0111 = INT7. 2776 * | | |Other = Reserved. 2777 * @var EPWM_T::EXTETCTL3 2778 * Offset: 0x27C EPWM External Event Trigger Control Register 3 2779 * --------------------------------------------------------------------------------------------------- 2780 * |Bits |Field |Descriptions 2781 * | :----: | :----: | :---- | 2782 * |[0] |EXETEN |External Event Trigger Enable Bit 2783 * | | |0 = External Event Trigger function Disabled. 2784 * | | |1 = External Event Trigger function Enabled. 2785 * |[5:4] |CNTACTS |Counter Action Selection 2786 * | | |00 = Counter reset. 2787 * | | |01 = Counter start. 2788 * | | |10 = Counter reset and start. 2789 * | | |11 = Reserved. 2790 * |[11:8] |EXTTRGS |External Trigger Selection 2791 * | | |0000 = INT0. 2792 * | | |0001 = INT1. 2793 * | | |0010 = INT2. 2794 * | | |0011 = INT3. 2795 * | | |0100 = INT4. 2796 * | | |0101 = INT5. 2797 * | | |0110 = INT6. 2798 * | | |0111 = INT7. 2799 * | | |Other = Reserved. 2800 * @var EPWM_T::EXTETCTL4 2801 * Offset: 0x280 EPWM External Event Trigger Control Register 4 2802 * --------------------------------------------------------------------------------------------------- 2803 * |Bits |Field |Descriptions 2804 * | :----: | :----: | :---- | 2805 * |[0] |EXETEN |External Event Trigger Enable Bit 2806 * | | |0 = External Event Trigger function Disabled. 2807 * | | |1 = External Event Trigger function Enabled. 2808 * |[5:4] |CNTACTS |Counter Action Selection 2809 * | | |00 = Counter reset. 2810 * | | |01 = Counter start. 2811 * | | |10 = Counter reset and start. 2812 * | | |11 = Reserved. 2813 * |[11:8] |EXTTRGS |External Trigger Selection 2814 * | | |0000 = INT0. 2815 * | | |0001 = INT1. 2816 * | | |0010 = INT2. 2817 * | | |0011 = INT3. 2818 * | | |0100 = INT4. 2819 * | | |0101 = INT5. 2820 * | | |0110 = INT6. 2821 * | | |0111 = INT7. 2822 * | | |Other = Reserved. 2823 * @var EPWM_T::EXTETCTL5 2824 * Offset: 0x284 EPWM External Event Trigger Control Register 5 2825 * --------------------------------------------------------------------------------------------------- 2826 * |Bits |Field |Descriptions 2827 * | :----: | :----: | :---- | 2828 * |[0] |EXETEN |External Event Trigger Enable Bit 2829 * | | |0 = External Event Trigger function Disabled. 2830 * | | |1 = External Event Trigger function Enabled. 2831 * |[5:4] |CNTACTS |Counter Action Selection 2832 * | | |00 = Counter reset. 2833 * | | |01 = Counter start. 2834 * | | |10 = Counter reset and start. 2835 * | | |11 = Reserved. 2836 * |[11:8] |EXTTRGS |External Trigger Selection 2837 * | | |0000 = INT0. 2838 * | | |0001 = INT1. 2839 * | | |0010 = INT2. 2840 * | | |0011 = INT3. 2841 * | | |0100 = INT4. 2842 * | | |0101 = INT5. 2843 * | | |0110 = INT6. 2844 * | | |0111 = INT7. 2845 * | | |Other = Reserved. 2846 * @var EPWM_T::SWEOFCTL 2847 * Offset: 0x288 EPWM Software Event Output Force Control Register 2848 * --------------------------------------------------------------------------------------------------- 2849 * |Bits |Field |Descriptions 2850 * | :----: | :----: | :---- | 2851 * |[1:0] |OUTACTS0 |Output Action Selection 2852 * | | |00 = Do nothing. 2853 * | | |01 = EPWM output Low. 2854 * | | |10 = EPWM output High. 2855 * | | |11 = EPWM output Toggle. 2856 * |[3:2] |OUTACTS1 |Output Action Selection 2857 * | | |00 = Do nothing. 2858 * | | |01 = EPWM output Low. 2859 * | | |10 = EPWM output High. 2860 * | | |11 = EPWM output Toggle. 2861 * |[5:4] |OUTACTS2 |Output Action Selection 2862 * | | |00 = Do nothing. 2863 * | | |01 = EPWM output Low. 2864 * | | |10 = EPWM output High. 2865 * | | |11 = EPWM output Toggle. 2866 * |[7:6] |OUTACTS3 |Output Action Selection 2867 * | | |00 = Do nothing. 2868 * | | |01 = EPWM output Low. 2869 * | | |10 = EPWM output High. 2870 * | | |11 = EPWM output Toggle. 2871 * |[9:8] |OUTACTS4 |Output Action Selection 2872 * | | |00 = Do nothing. 2873 * | | |01 = EPWM output Low. 2874 * | | |10 = EPWM output High. 2875 * | | |11 = EPWM output Toggle. 2876 * |[11:10] |OUTACTS5 |Output Action Selection 2877 * | | |00 = Do nothing. 2878 * | | |01 = EPWM output Low. 2879 * | | |10 = EPWM output High. 2880 * | | |11 = EPWM output Toggle. 2881 * @var EPWM_T::SWEOFTRG 2882 * Offset: 0x28C EPWM Software Event Output Force Trigger Register 2883 * --------------------------------------------------------------------------------------------------- 2884 * |Bits |Field |Descriptions 2885 * | :----: | :----: | :---- | 2886 * |[0] |SWETRG0 |Software Event Trigger 2887 * | | |Write 1 to this bit will change EPWM output status according to OUTACTSn in EPWMx_SWEOFCTL setting. 2888 * | | |Note: This bit will auto cleared by hardware. 2889 * |[1] |SWETRG1 |Software Event Trigger 2890 * | | |Write 1 to this bit will change EPWM output status according to OUTACTSn in EPWMx_SWEOFCTL setting. 2891 * | | |Note: This bit will auto cleared by hardware. 2892 * |[2] |SWETRG2 |Software Event Trigger 2893 * | | |Write 1 to this bit will change EPWM output status according to OUTACTSn in EPWMx_SWEOFCTL setting. 2894 * | | |Note: This bit will auto cleared by hardware. 2895 * |[3] |SWETRG3 |Software Event Trigger 2896 * | | |Write 1 to this bit will change EPWM output status according to OUTACTSn in EPWMx_SWEOFCTL setting. 2897 * | | |Note: This bit will auto cleared by hardware. 2898 * |[4] |SWETRG4 |Software Event Trigger 2899 * | | |Write 1 to this bit will change EPWM output status according to OUTACTSn in EPWMx_SWEOFCTL setting. 2900 * | | |Note: This bit will auto cleared by hardware. 2901 * |[5] |SWETRG5 |Software Event Trigger 2902 * | | |Write 1 to this bit will change EPWM output status according to OUTACTSn in EPWMx_SWEOFCTL setting. 2903 * | | |Note: This bit will auto cleared by hardware. 2904 * @var EPWM_T::CLKPSC0 2905 * Offset: 0x290 EPWM Clock Prescale Register 0 2906 * --------------------------------------------------------------------------------------------------- 2907 * |Bits |Field |Descriptions 2908 * | :----: | :----: | :---- | 2909 * |[11:0] |CLKPSC |EPWM Counter Clock Prescale 2910 * | | |The clock of EPWM counter is decided by clock prescaler 2911 * | | |Each EPWM pair shares one EPWM counter clock prescaler 2912 * | | |The clock of EPWM counter is divided by (CLKPSC+ 1) 2913 * @var EPWM_T::CLKPSC1 2914 * Offset: 0x294 EPWM Clock Prescale Register 1 2915 * --------------------------------------------------------------------------------------------------- 2916 * |Bits |Field |Descriptions 2917 * | :----: | :----: | :---- | 2918 * |[11:0] |CLKPSC |EPWM Counter Clock Prescale 2919 * | | |The clock of EPWM counter is decided by clock prescaler 2920 * | | |Each EPWM pair shares one EPWM counter clock prescaler 2921 * | | |The clock of EPWM counter is divided by (CLKPSC+ 1) 2922 * @var EPWM_T::CLKPSC2 2923 * Offset: 0x298 EPWM Clock Prescale Register 2 2924 * --------------------------------------------------------------------------------------------------- 2925 * |Bits |Field |Descriptions 2926 * | :----: | :----: | :---- | 2927 * |[11:0] |CLKPSC |EPWM Counter Clock Prescale 2928 * | | |The clock of EPWM counter is decided by clock prescaler 2929 * | | |Each EPWM pair shares one EPWM counter clock prescaler 2930 * | | |The clock of EPWM counter is divided by (CLKPSC+ 1) 2931 * @var EPWM_T::CLKPSC3 2932 * Offset: 0x29C EPWM Clock Prescale Register 3 2933 * --------------------------------------------------------------------------------------------------- 2934 * |Bits |Field |Descriptions 2935 * | :----: | :----: | :---- | 2936 * |[11:0] |CLKPSC |EPWM Counter Clock Prescale 2937 * | | |The clock of EPWM counter is decided by clock prescaler 2938 * | | |Each EPWM pair shares one EPWM counter clock prescaler 2939 * | | |The clock of EPWM counter is divided by (CLKPSC+ 1) 2940 * @var EPWM_T::CLKPSC4 2941 * Offset: 0x2A0 EPWM Clock Prescale Register 4 2942 * --------------------------------------------------------------------------------------------------- 2943 * |Bits |Field |Descriptions 2944 * | :----: | :----: | :---- | 2945 * |[11:0] |CLKPSC |EPWM Counter Clock Prescale 2946 * | | |The clock of EPWM counter is decided by clock prescaler 2947 * | | |Each EPWM pair shares one EPWM counter clock prescaler 2948 * | | |The clock of EPWM counter is divided by (CLKPSC+ 1) 2949 * @var EPWM_T::CLKPSC5 2950 * Offset: 0x2A4 EPWM Clock Prescale Register 5 2951 * --------------------------------------------------------------------------------------------------- 2952 * |Bits |Field |Descriptions 2953 * | :----: | :----: | :---- | 2954 * |[11:0] |CLKPSC |EPWM Counter Clock Prescale 2955 * | | |The clock of EPWM counter is decided by clock prescaler 2956 * | | |Each EPWM pair shares one EPWM counter clock prescaler 2957 * | | |The clock of EPWM counter is divided by (CLKPSC+ 1) 2958 * @var EPWM_T::RDTCNT0_1 2959 * Offset: 0x2A8 EPWM Rising Dead-time Counter Register 0/1 2960 * --------------------------------------------------------------------------------------------------- 2961 * |Bits |Field |Descriptions 2962 * | :----: | :----: | :---- | 2963 * |[11:0] |RDTCNT |Rising Dead-time Counter (Write Protect) 2964 * | | |The Rising dead-time can be calculated from the following formula: 2965 * | | |RDTCKSEL=0: Rising Dead-time = (RDTCNT[11:0]+1) * EPWM_CLK period. 2966 * | | |RDTCKSEL=1: Rising Dead-time = (RDTCNT[11:0]+1) * EPWM_CLK period * (CLKPSC+1). 2967 * | | |Note: This bit is write protected. Refer to SYS_REGLCTL register. 2968 * @var EPWM_T::RDTCNT2_3 2969 * Offset: 0x2AC EPWM Rising Dead-time Counter Register 2/3 2970 * --------------------------------------------------------------------------------------------------- 2971 * |Bits |Field |Descriptions 2972 * | :----: | :----: | :---- | 2973 * |[11:0] |RDTCNT |Rising Dead-time Counter (Write Protect) 2974 * | | |The Rising dead-time can be calculated from the following formula: 2975 * | | |RDTCKSEL=0: Rising Dead-time = (RDTCNT[11:0]+1) * EPWM_CLK period. 2976 * | | |RDTCKSEL=1: Rising Dead-time = (RDTCNT[11:0]+1) * EPWM_CLK period * (CLKPSC+1). 2977 * | | |Note: This bit is write protected. Refer to SYS_REGLCTL register. 2978 * @var EPWM_T::RDTCNT4_5 2979 * Offset: 0x2B0 EPWM Rising Dead-time Counter Register 4/5 2980 * --------------------------------------------------------------------------------------------------- 2981 * |Bits |Field |Descriptions 2982 * | :----: | :----: | :---- | 2983 * |[11:0] |RDTCNT |Rising Dead-time Counter (Write Protect) 2984 * | | |The Rising dead-time can be calculated from the following formula: 2985 * | | |RDTCKSEL=0: Rising Dead-time = (RDTCNT[11:0]+1) * EPWM_CLK period. 2986 * | | |RDTCKSEL=1: Rising Dead-time = (RDTCNT[11:0]+1) * EPWM_CLK period * (CLKPSC+1). 2987 * | | |Note: This bit is write protected. Refer to SYS_REGLCTL register. 2988 * @var EPWM_T::FDTCNT0_1 2989 * Offset: 0x2B4 EPWM Falling Dead-time Counter Register 0/1 2990 * --------------------------------------------------------------------------------------------------- 2991 * |Bits |Field |Descriptions 2992 * | :----: | :----: | :---- | 2993 * |[11:0] |FDTCNT |Falling Dead-time Counter (Write Protect) 2994 * | | |The dead-time can be calculated from the following formula: 2995 * | | |FDTCKSEL=0: Falling Dead-time = (FDTCNT[11:0]+1) * EPWM_CLK period. 2996 * | | |FDTCKSEL=1: Falling Dead-time = (FDTCNT[11:0]+1) * EPWM_CLK period * (CLKPSC+1). 2997 * | | |Note: This bit is write protected. Refer to SYS_REGLCTL register. 2998 * @var EPWM_T::FDTCNT2_3 2999 * Offset: 0x2B8 EPWM Falling Dead-time Counter Register 2/3 3000 * --------------------------------------------------------------------------------------------------- 3001 * |Bits |Field |Descriptions 3002 * | :----: | :----: | :---- | 3003 * |[11:0] |FDTCNT |Falling Dead-time Counter (Write Protect) 3004 * | | |The dead-time can be calculated from the following formula: 3005 * | | |FDTCKSEL=0: Falling Dead-time = (FDTCNT[11:0]+1) * EPWM_CLK period. 3006 * | | |FDTCKSEL=1: Falling Dead-time = (FDTCNT[11:0]+1) * EPWM_CLK period * (CLKPSC+1). 3007 * | | |Note: This bit is write protected. Refer to SYS_REGLCTL register. 3008 * @var EPWM_T::FDTCNT4_5 3009 * Offset: 0x2BC EPWM Falling Dead-time Counter Register 4/5 3010 * --------------------------------------------------------------------------------------------------- 3011 * |Bits |Field |Descriptions 3012 * | :----: | :----: | :---- | 3013 * |[11:0] |FDTCNT |Falling Dead-time Counter (Write Protect) 3014 * | | |The dead-time can be calculated from the following formula: 3015 * | | |FDTCKSEL=0: Falling Dead-time = (FDTCNT[11:0]+1) * EPWM_CLK period. 3016 * | | |FDTCKSEL=1: Falling Dead-time = (FDTCNT[11:0]+1) * EPWM_CLK period * (CLKPSC+1). 3017 * | | |Note: This bit is write protected. Refer to SYS_REGLCTL register. 3018 * @var EPWM_T::DTCTL 3019 * Offset: 0x2C0 EPWM Dead-time Control Register 3020 * --------------------------------------------------------------------------------------------------- 3021 * |Bits |Field |Descriptions 3022 * | :----: | :----: | :---- | 3023 * |[0] |RDTEN0 |Enable Rising Dead-time Insertion for EPWM Pair (Write Protect) 3024 * | | |Rising Dead-time insertion is only active when this pair of complementary EPWM is enabled 3025 * | | |If rising dead- time insertion is inactive, the outputs of pin pair are complementary without any delay. 3026 * | | |0 = Rising Dead-time insertion Disabled on the pin pair. 3027 * | | |1 = Rising Dead-time insertion Enabled on the pin pair. 3028 * | | |Note: This bit is write protected. Refer to SYS_REGLCTL register. 3029 * |[1] |RDTEN2 |Enable Rising Dead-time Insertion for EPWM Pair (Write Protect) 3030 * | | |Rising Dead-time insertion is only active when this pair of complementary EPWM is enabled 3031 * | | |If rising dead- time insertion is inactive, the outputs of pin pair are complementary without any delay. 3032 * | | |0 = Rising Dead-time insertion Disabled on the pin pair. 3033 * | | |1 = Rising Dead-time insertion Enabled on the pin pair. 3034 * | | |Note: This bit is write protected. Refer to SYS_REGLCTL register. 3035 * |[2] |RDTEN4 |Enable Rising Dead-time Insertion for EPWM Pair (Write Protect) 3036 * | | |Rising Dead-time insertion is only active when this pair of complementary EPWM is enabled 3037 * | | |If rising dead- time insertion is inactive, the outputs of pin pair are complementary without any delay. 3038 * | | |0 = Rising Dead-time insertion Disabled on the pin pair. 3039 * | | |1 = Rising Dead-time insertion Enabled on the pin pair. 3040 * | | |Note: This bit is write protected. Refer to SYS_REGLCTL register. 3041 * |[8] |FDTEN0 |Enable Falling Dead-time Insertion for EPWM Pair (Write Protect) 3042 * | | |Falling Dead-time insertion is only active when this pair of complementary EPWM is enabled 3043 * | | |If falling dead- time insertion is inactive, the outputs of pin pair are complementary without any delay. 3044 * | | |0 = Falling Dead-time insertion Disabled on the pin pair. 3045 * | | |1 = Falling Dead-time insertion Enabled on the pin pair. 3046 * | | |Note: This bit is write protected. Refer to SYS_REGLCTL register. 3047 * |[9] |FDTEN2 |Enable Falling Dead-time Insertion for EPWM Pair (Write Protect) 3048 * | | |Falling Dead-time insertion is only active when this pair of complementary EPWM is enabled 3049 * | | |If falling dead- time insertion is inactive, the outputs of pin pair are complementary without any delay. 3050 * | | |0 = Falling Dead-time insertion Disabled on the pin pair. 3051 * | | |1 = Falling Dead-time insertion Enabled on the pin pair. 3052 * | | |Note: This bit is write protected. Refer to SYS_REGLCTL register. 3053 * |[10] |FDTEN4 |Enable Falling Dead-time Insertion for EPWM Pair (Write Protect) 3054 * | | |Falling Dead-time insertion is only active when this pair of complementary EPWM is enabled 3055 * | | |If falling dead- time insertion is inactive, the outputs of pin pair are complementary without any delay. 3056 * | | |0 = Falling Dead-time insertion Disabled on the pin pair. 3057 * | | |1 = Falling Dead-time insertion Enabled on the pin pair. 3058 * | | |Note: This bit is write protected. Refer to SYS_REGLCTL register. 3059 * |[16] |DTCKSELn |Dead-time Clock Select for EPWM Pair (Write Protect) 3060 * | | |0 = Dead-time clock source from EPWM_CLK. 3061 * | | |1 = Dead-time clock source from prescaler output. 3062 * | | |Note: This bit is write protected. Refer to SYS_REGLCTL register. 3063 * @var EPWM_T::PBUF[6] 3064 * Offset: 0x304 EPWM PERIOD0~5 Buffer 3065 * --------------------------------------------------------------------------------------------------- 3066 * |Bits |Field |Descriptions 3067 * | :----: | :----: | :---- | 3068 * |[15:0] |PBUF |EPWM Period Register Buffer (Read Only) 3069 * | | |Used as PERIOD active register. 3070 * @var EPWM_T::CMPBUF[6] 3071 * Offset: 0x31C EPWM CMPDAT0~5 Buffer 3072 * --------------------------------------------------------------------------------------------------- 3073 * |Bits |Field |Descriptions 3074 * | :----: | :----: | :---- | 3075 * |[15:0] |CMPBUF |EPWM Comparator Register Buffer (Read Only) 3076 * | | |Used as CMP active register. 3077 * @var EPWM_T::CPSCBUF[3] 3078 * Offset: 0x334 EPWM CLKPSC0_1/2_3/4_5 Buffer 3079 * --------------------------------------------------------------------------------------------------- 3080 * |Bits |Field |Descriptions 3081 * | :----: | :----: | :---- | 3082 * |[11:0] |CPSCBUF |EPWM Counter Clock Prescale Buffer 3083 * | | |Use as EPWM counter clock prescale active register. 3084 * @var EPWM_T::FTCBUF[3] 3085 * Offset: 0x340 EPWM FTCMPDAT0_1/2_3/4_5 Buffer 3086 * --------------------------------------------------------------------------------------------------- 3087 * |Bits |Field |Descriptions 3088 * | :----: | :----: | :---- | 3089 * |[15:0] |FTCMPBUF |EPWM FTCMPDAT Buffer (Read Only) 3090 * | | |Used as FTCMP active buffer. 3091 * @var EPWM_T::FTCI 3092 * Offset: 0x34C EPWM FTCMPDAT Indicator Register 3093 * --------------------------------------------------------------------------------------------------- 3094 * |Bits |Field |Descriptions 3095 * | :----: | :----: | :---- | 3096 * |[0] |FTCMU0 |EPWM FTCMPDAT Up Indicator 3097 * | | |Indicator is set by hardware when EPWM counter up counts and reaches EPWM_FTCMPDATn 3098 * | | |Software can clear this bit by writing 1 to it. 3099 * |[1] |FTCMU2 |EPWM FTCMPDAT Up Indicator 3100 * | | |Indicator is set by hardware when EPWM counter up counts and reaches EPWM_FTCMPDATn 3101 * | | |Software can clear this bit by writing 1 to it. 3102 * |[2] |FTCMU4 |EPWM FTCMPDAT Up Indicator 3103 * | | |Indicator is set by hardware when EPWM counter up counts and reaches EPWM_FTCMPDATn 3104 * | | |Software can clear this bit by writing 1 to it. 3105 * |[8] |FTCMD0 |EPWM FTCMPDAT Down Indicator 3106 * | | |Indicator is set by hardware when EPWM counter down counts and reaches EPWM_FTCMPDATn 3107 * | | |Software can clear this bit by writing 1 to it. 3108 * |[9] |FTCMD2 |EPWM FTCMPDAT Down Indicator 3109 * | | |Indicator is set by hardware when EPWM counter down counts and reaches EPWM_FTCMPDATn 3110 * | | |Software can clear this bit by writing 1 to it. 3111 * |[10] |FTCMD4 |EPWM FTCMPDAT Down Indicator 3112 * | | |Indicator is set by hardware when EPWM counter down counts and reaches EPWM_FTCMPDATn 3113 * | | |Software can clear this bit by writing 1 to it. 3114 * @var EPWM_T::CPSCBUF0 3115 * Offset: 0x350 EPWM CLKPSC0 Buffer 3116 * --------------------------------------------------------------------------------------------------- 3117 * |Bits |Field |Descriptions 3118 * | :----: | :----: | :---- | 3119 * |[11:0] |CPSCBUF |EPWM Counter Clock Prescale Buffer 3120 * | | |Used as EPWM counter clock pre-scare active register. 3121 * @var EPWM_T::CPSCBUF1 3122 * Offset: 0x354 EPWM CLKPSC1 Buffer 3123 * --------------------------------------------------------------------------------------------------- 3124 * |Bits |Field |Descriptions 3125 * | :----: | :----: | :---- | 3126 * |[11:0] |CPSCBUF |EPWM Counter Clock Prescale Buffer 3127 * | | |Used as EPWM counter clock pre-scare active register. 3128 * @var EPWM_T::CPSCBUF2 3129 * Offset: 0x358 EPWM CLKPSC2 Buffer 3130 * --------------------------------------------------------------------------------------------------- 3131 * |Bits |Field |Descriptions 3132 * | :----: | :----: | :---- | 3133 * |[11:0] |CPSCBUF |EPWM Counter Clock Prescale Buffer 3134 * | | |Used as EPWM counter clock pre-scare active register. 3135 * @var EPWM_T::CPSCBUF3 3136 * Offset: 0x35C EPWM CLKPSC3 Buffer 3137 * --------------------------------------------------------------------------------------------------- 3138 * |Bits |Field |Descriptions 3139 * | :----: | :----: | :---- | 3140 * |[11:0] |CPSCBUF |EPWM Counter Clock Prescale Buffer 3141 * | | |Used as EPWM counter clock pre-scare active register. 3142 * @var EPWM_T::CPSCBUF4 3143 * Offset: 0x360 EPWM CLKPSC4 Buffer 3144 * --------------------------------------------------------------------------------------------------- 3145 * |Bits |Field |Descriptions 3146 * | :----: | :----: | :---- | 3147 * |[11:0] |CPSCBUF |EPWM Counter Clock Prescale Buffer 3148 * | | |Used as EPWM counter clock pre-scare active register. 3149 * @var EPWM_T::CPSCBUF5 3150 * Offset: 0x364 EPWM CLKPSC5 Buffer 3151 * --------------------------------------------------------------------------------------------------- 3152 * |Bits |Field |Descriptions 3153 * | :----: | :----: | :---- | 3154 * |[11:0] |CPSCBUF |EPWM Counter Clock Prescale Buffer 3155 * | | |Used as EPWM counter clock pre-scare active register. 3156 * @var EPWM_T::IFACNT0 3157 * Offset: 0x368 EPWM Interrupt Flag Accumulator Counter 0 3158 * --------------------------------------------------------------------------------------------------- 3159 * |Bits |Field |Descriptions 3160 * | :----: | :----: | :---- | 3161 * |[15:0] |ACUCNT |Accumulator Counter (Read Only) 3162 * | | |This value indicates how many interrupt are accumulated when using interrupt flag accumulator function. 3163 * @var EPWM_T::IFACNT1 3164 * Offset: 0x36C EPWM Interrupt Flag Accumulator Counter 1 3165 * --------------------------------------------------------------------------------------------------- 3166 * |Bits |Field |Descriptions 3167 * | :----: | :----: | :---- | 3168 * |[15:0] |ACUCNT |Accumulator Counter (Read Only) 3169 * | | |This value indicates how many interrupt are accumulated when using interrupt flag accumulator function. 3170 * @var EPWM_T::IFACNT2 3171 * Offset: 0x370 EPWM Interrupt Flag Accumulator Counter 2 3172 * --------------------------------------------------------------------------------------------------- 3173 * |Bits |Field |Descriptions 3174 * | :----: | :----: | :---- | 3175 * |[15:0] |ACUCNT |Accumulator Counter (Read Only) 3176 * | | |This value indicates how many interrupt are accumulated when using interrupt flag accumulator function. 3177 * @var EPWM_T::IFACNT3 3178 * Offset: 0x374 EPWM Interrupt Flag Accumulator Counter 3 3179 * --------------------------------------------------------------------------------------------------- 3180 * |Bits |Field |Descriptions 3181 * | :----: | :----: | :---- | 3182 * |[15:0] |ACUCNT |Accumulator Counter (Read Only) 3183 * | | |This value indicates how many interrupt are accumulated when using interrupt flag accumulator function. 3184 * @var EPWM_T::IFACNT4 3185 * Offset: 0x378 EPWM Interrupt Flag Accumulator Counter 4 3186 * --------------------------------------------------------------------------------------------------- 3187 * |Bits |Field |Descriptions 3188 * | :----: | :----: | :---- | 3189 * |[15:0] |ACUCNT |Accumulator Counter (Read Only) 3190 * | | |This value indicates how many interrupt are accumulated when using interrupt flag accumulator function. 3191 * @var EPWM_T::IFACNT5 3192 * Offset: 0x37C EPWM Interrupt Flag Accumulator Counter 5 3193 * --------------------------------------------------------------------------------------------------- 3194 * |Bits |Field |Descriptions 3195 * | :----: | :----: | :---- | 3196 * |[15:0] |ACUCNT |Accumulator Counter (Read Only) 3197 * | | |This value indicates how many interrupt are accumulated when using interrupt flag accumulator function. 3198 */ 3199 __IO uint32_t CTL0; /*!< [0x0000] EPWM Control Register 0 */ 3200 __IO uint32_t CTL1; /*!< [0x0004] EPWM Control Register 1 */ 3201 __IO uint32_t SYNC; /*!< [0x0008] EPWM Synchronization Register */ 3202 __IO uint32_t SWSYNC; /*!< [0x000c] EPWM Software Control Synchronization Register */ 3203 __IO uint32_t CLKSRC; /*!< [0x0010] EPWM Clock Source Register */ 3204 /// @cond HIDDEN_SYMBOLS 3205 __I uint32_t RESERVE0[3]; 3206 /// @endcond //HIDDEN_SYMBOLS 3207 __IO uint32_t CNTEN; /*!< [0x0020] EPWM Counter Enable Register */ 3208 __IO uint32_t CNTCLR; /*!< [0x0024] EPWM Clear Counter Register */ 3209 __IO uint32_t LOAD; /*!< [0x0028] EPWM Load Register */ 3210 /// @cond HIDDEN_SYMBOLS 3211 __I uint32_t RESERVE1[1]; 3212 /// @endcond //HIDDEN_SYMBOLS 3213 __IO uint32_t PERIOD[6]; /*!< [0x0030] EPWM Period Register 0~5 */ 3214 /// @cond HIDDEN_SYMBOLS 3215 __I uint32_t RESERVE2[2]; 3216 /// @endcond //HIDDEN_SYMBOLS 3217 __IO uint32_t CMPDAT[6]; /*!< [0x0050] EPWM Comparator Register 0~5 */ 3218 /// @cond HIDDEN_SYMBOLS 3219 __I uint32_t RESERVE3[6]; 3220 /// @endcond //HIDDEN_SYMBOLS 3221 __IO uint32_t PHS[3]; /*!< [0x0080] EPWM Counter Phase Register 0/1,2/3,4/5 */ 3222 /// @cond HIDDEN_SYMBOLS 3223 __I uint32_t RESERVE4[1]; 3224 /// @endcond //HIDDEN_SYMBOLS 3225 __I uint32_t CNT[6]; /*!< [0x0090] EPWM Counter Register 0~5 */ 3226 /// @cond HIDDEN_SYMBOLS 3227 __I uint32_t RESERVE5[2]; 3228 /// @endcond //HIDDEN_SYMBOLS 3229 __IO uint32_t WGCTL0; /*!< [0x00b0] EPWM Generation Register 0 */ 3230 __IO uint32_t WGCTL1; /*!< [0x00b4] EPWM Generation Register 1 */ 3231 __IO uint32_t MSKEN; /*!< [0x00b8] EPWM Mask Enable Register */ 3232 __IO uint32_t MSK; /*!< [0x00bc] EPWM Mask Data Register */ 3233 __IO uint32_t BNF; /*!< [0x00c0] EPWM Brake Noise Filter Register */ 3234 __IO uint32_t FAILBRK; /*!< [0x00c4] EPWM System Fail Brake Control Register */ 3235 __IO uint32_t BRKCTL[3]; /*!< [0x00c8] EPWM Brake Edge Detect Control Register 0/1,2/3,4/5 */ 3236 __IO uint32_t POLCTL; /*!< [0x00d4] EPWM Pin Polar Inverse Register */ 3237 __IO uint32_t POEN; /*!< [0x00d8] EPWM Output Enable Register */ 3238 __O uint32_t SWBRK; /*!< [0x00dc] EPWM Software Brake Control Register */ 3239 __IO uint32_t INTEN0; /*!< [0x00e0] EPWM Interrupt Enable Register 0 */ 3240 __IO uint32_t INTEN1; /*!< [0x00e4] EPWM Interrupt Enable Register 1 */ 3241 __IO uint32_t INTSTS0; /*!< [0x00e8] EPWM Interrupt Flag Register 0 */ 3242 __IO uint32_t INTSTS1; /*!< [0x00ec] EPWM Interrupt Flag Register 1 */ 3243 /// @cond HIDDEN_SYMBOLS 3244 __I uint32_t RESERVE6[1]; 3245 /// @endcond //HIDDEN_SYMBOLS 3246 __IO uint32_t DACTRGEN; /*!< [0x00f4] EPWM Trigger DAC Enable Register */ 3247 __IO uint32_t EADCTS0; /*!< [0x00f8] EPWM Trigger EADC Source Select Register 0 */ 3248 __IO uint32_t EADCTS1; /*!< [0x00fc] EPWM Trigger EADC Source Select Register 1 */ 3249 __IO uint32_t FTCMPDAT[3]; /*!< [0x0100] EPWM Free Trigger Compare Register 0/1,2/3,4/5 */ 3250 /// @cond HIDDEN_SYMBOLS 3251 __I uint32_t RESERVE7[1]; 3252 /// @endcond //HIDDEN_SYMBOLS 3253 __IO uint32_t SSCTL; /*!< [0x0110] EPWM Synchronous Start Control Register */ 3254 __O uint32_t SSTRG; /*!< [0x0114] EPWM Synchronous Start Trigger Register */ 3255 __IO uint32_t LEBCTL; /*!< [0x0118] EPWM Leading Edge Blanking Control Register */ 3256 __IO uint32_t LEBCNT; /*!< [0x011c] EPWM Leading Edge Blanking Counter Register */ 3257 __IO uint32_t STATUS; /*!< [0x0120] EPWM Status Register */ 3258 /// @cond HIDDEN_SYMBOLS 3259 __I uint32_t RESERVE8[3]; 3260 /// @endcond //HIDDEN_SYMBOLS 3261 __IO uint32_t IFA[6]; /*!< [0x0130] EPWM Interrupt Flag Accumulator Register 0~5 */ 3262 /// @cond HIDDEN_SYMBOLS 3263 __I uint32_t RESERVE9[2]; 3264 /// @endcond //HIDDEN_SYMBOLS 3265 __IO uint32_t AINTSTS; /*!< [0x0150] EPWM Accumulator Interrupt Flag Register */ 3266 __IO uint32_t AINTEN; /*!< [0x0154] EPWM Accumulator Interrupt Enable Register */ 3267 __IO uint32_t APDMACTL; /*!< [0x0158] EPWM Accumulator PDMA Control Register */ 3268 /// @cond HIDDEN_SYMBOLS 3269 __I uint32_t RESERVE10[1]; 3270 /// @endcond //HIDDEN_SYMBOLS 3271 __IO uint32_t FDEN; /*!< [0x0160] EPWM Fault Detect Enable Register */ 3272 __IO uint32_t FDCTL[6]; /*!< [0x0164~0x178] EPWM Fault Detect Control Register 0~5 */ 3273 __IO uint32_t FDIEN; /*!< [0x017C] EPWM Fault Detect Interrupt Enable Register */ 3274 __IO uint32_t FDSTS; /*!< [0x0180] EPWM Fault Detect Interrupt Flag Register */ 3275 __IO uint32_t EADCPSCCTL; /*!< [0x0184] EPWM Trigger EADC Prescale Control Register */ 3276 __IO uint32_t EADCPSC0; /*!< [0x0188] EPWM Trigger EADC Prescale Register 0 */ 3277 __IO uint32_t EADCPSC1; /*!< [0x018C] EPWM Trigger EADC Prescale Register 1 */ 3278 __IO uint32_t EADCPSCNT0; /*!< [0x0190] EPWM Trigger EADC Prescale Counter Register 0 */ 3279 __IO uint32_t EADCPSCNT1; /*!< [0x0194] EPWM Trigger EADC Prescale Counter Register 1 */ 3280 /// @cond HIDDEN_SYMBOLS 3281 __I uint32_t RESERVE11[26]; 3282 /// @endcond //HIDDEN_SYMBOLS 3283 __IO uint32_t CAPINEN; /*!< [0x0200] EPWM Capture Input Enable Register */ 3284 __IO uint32_t CAPCTL; /*!< [0x0204] EPWM Capture Control Register */ 3285 __I uint32_t CAPSTS; /*!< [0x0208] EPWM Capture Status Register */ 3286 ECAPDAT_T CAPDAT[6]; /*!< [0x020C] EPWM Rising and Falling Capture Data Register 0~5 */ 3287 __IO uint32_t PDMACTL; /*!< [0x023c] EPWM PDMA Control Register */ 3288 __I uint32_t PDMACAP[3]; /*!< [0x0240] EPWM Capture Channel 01,23,45 PDMA Register */ 3289 /// @cond HIDDEN_SYMBOLS 3290 __I uint32_t RESERVE12[1]; 3291 /// @endcond //HIDDEN_SYMBOLS 3292 __IO uint32_t CAPIEN; /*!< [0x0250] EPWM Capture Interrupt Enable Register */ 3293 __IO uint32_t CAPIF; /*!< [0x0254] EPWM Capture Interrupt Flag Register */ 3294 __IO uint32_t CAPNF[6]; /*!< [0x0258~0x26C] EPWM Capture Input Noise Filter Register 0~5 */ 3295 __IO uint32_t EXTETCTL[6]; /*!< [0x0270~0x284] EPWM External Event Trigger Control Register 0~5 */ 3296 __IO uint32_t SWEOFCTL; /*!< [0x0288] EPWM Software Event Output Force Control Register */ 3297 __IO uint32_t SWEOFTRG; /*!< [0x028C] EPWM Software Event Output Force Trigger Register */ 3298 __IO uint32_t CLKPSC[6]; /*!< [0x0290~0x2A4] EPWM Clock Prescale Register 0~5 */ 3299 __IO uint32_t RDTCNT[3]; /*!< [0x02A8~0x2B0] EPWM Rising Dead-time Counter Register 0/1, 2/3, 4/5 */ 3300 __IO uint32_t FDTCNT[3]; /*!< [0x02B4~0x2BC] EPWM Falling Dead-time Counter Register 0/1, 2/3, 4/5 */ 3301 __IO uint32_t DTCTL; /*!< [0x02C0] EPWM Dead-Time Control Register */ 3302 /// @cond HIDDEN_SYMBOLS 3303 __I uint32_t RESERVE13[16]; 3304 /// @endcond //HIDDEN_SYMBOLS 3305 __I uint32_t PBUF[6]; /*!< [0x0304] EPWM PERIOD0~5 Buffer */ 3306 __I uint32_t CMPBUF[6]; /*!< [0x031c] EPWM CMPDAT0~5 Buffer */ 3307 /// @cond HIDDEN_SYMBOLS 3308 __I uint32_t RESERVE14[3]; 3309 /// @endcond //HIDDEN_SYMBOLS 3310 __I uint32_t FTCBUF[3]; /*!< [0x0340] EPWM FTCMPDAT0_1/2_3/4_5 Buffer */ 3311 __IO uint32_t FTCI; /*!< [0x034c] EPWM FTCMPDAT Indicator Register */ 3312 __I uint32_t CPSCBUF[5]; /*!< [0x0350~0x364] EPWM CLKPSC0~5 Buffer */ 3313 __I uint32_t IFACNT[5]; /*!< [0x0368~0x37C] EPWM Interrupt Flag Accumulator Counter 0~5 */ 3314 3315 } EPWM_T; 3316 3317 /** 3318 @addtogroup EPWM_CONST EPWM Bit Field Definition 3319 Constant Definitions for EPWM Controller 3320 @{ */ 3321 3322 #define EPWM_CTL0_CTRLD0_Pos (0) /*!< EPWM_T::CTL0: CTRLD0 Position */ 3323 #define EPWM_CTL0_CTRLD0_Msk (0x1ul << EPWM_CTL0_CTRLD0_Pos) /*!< EPWM_T::CTL0: CTRLD0 Mask */ 3324 3325 #define EPWM_CTL0_CTRLD1_Pos (1) /*!< EPWM_T::CTL0: CTRLD1 Position */ 3326 #define EPWM_CTL0_CTRLD1_Msk (0x1ul << EPWM_CTL0_CTRLD1_Pos) /*!< EPWM_T::CTL0: CTRLD1 Mask */ 3327 3328 #define EPWM_CTL0_CTRLD2_Pos (2) /*!< EPWM_T::CTL0: CTRLD2 Position */ 3329 #define EPWM_CTL0_CTRLD2_Msk (0x1ul << EPWM_CTL0_CTRLD2_Pos) /*!< EPWM_T::CTL0: CTRLD2 Mask */ 3330 3331 #define EPWM_CTL0_CTRLD3_Pos (3) /*!< EPWM_T::CTL0: CTRLD3 Position */ 3332 #define EPWM_CTL0_CTRLD3_Msk (0x1ul << EPWM_CTL0_CTRLD3_Pos) /*!< EPWM_T::CTL0: CTRLD3 Mask */ 3333 3334 #define EPWM_CTL0_CTRLD4_Pos (4) /*!< EPWM_T::CTL0: CTRLD4 Position */ 3335 #define EPWM_CTL0_CTRLD4_Msk (0x1ul << EPWM_CTL0_CTRLD4_Pos) /*!< EPWM_T::CTL0: CTRLD4 Mask */ 3336 3337 #define EPWM_CTL0_CTRLD5_Pos (5) /*!< EPWM_T::CTL0: CTRLD5 Position */ 3338 #define EPWM_CTL0_CTRLD5_Msk (0x1ul << EPWM_CTL0_CTRLD5_Pos) /*!< EPWM_T::CTL0: CTRLD5 Mask */ 3339 3340 #define EPWM_CTL0_WINLDEN0_Pos (8) /*!< EPWM_T::CTL0: WINLDEN0 Position */ 3341 #define EPWM_CTL0_WINLDEN0_Msk (0x1ul << EPWM_CTL0_WINLDEN0_Pos) /*!< EPWM_T::CTL0: WINLDEN0 Mask */ 3342 3343 #define EPWM_CTL0_WINLDEN1_Pos (9) /*!< EPWM_T::CTL0: WINLDEN1 Position */ 3344 #define EPWM_CTL0_WINLDEN1_Msk (0x1ul << EPWM_CTL0_WINLDEN1_Pos) /*!< EPWM_T::CTL0: WINLDEN1 Mask */ 3345 3346 #define EPWM_CTL0_WINLDEN2_Pos (10) /*!< EPWM_T::CTL0: WINLDEN2 Position */ 3347 #define EPWM_CTL0_WINLDEN2_Msk (0x1ul << EPWM_CTL0_WINLDEN2_Pos) /*!< EPWM_T::CTL0: WINLDEN2 Mask */ 3348 3349 #define EPWM_CTL0_WINLDEN3_Pos (11) /*!< EPWM_T::CTL0: WINLDEN3 Position */ 3350 #define EPWM_CTL0_WINLDEN3_Msk (0x1ul << EPWM_CTL0_WINLDEN3_Pos) /*!< EPWM_T::CTL0: WINLDEN3 Mask */ 3351 3352 #define EPWM_CTL0_WINLDEN4_Pos (12) /*!< EPWM_T::CTL0: WINLDEN4 Position */ 3353 #define EPWM_CTL0_WINLDEN4_Msk (0x1ul << EPWM_CTL0_WINLDEN4_Pos) /*!< EPWM_T::CTL0: WINLDEN4 Mask */ 3354 3355 #define EPWM_CTL0_WINLDEN5_Pos (13) /*!< EPWM_T::CTL0: WINLDEN5 Position */ 3356 #define EPWM_CTL0_WINLDEN5_Msk (0x1ul << EPWM_CTL0_WINLDEN5_Pos) /*!< EPWM_T::CTL0: WINLDEN5 Mask */ 3357 3358 #define EPWM_CTL0_IMMLDEN0_Pos (16) /*!< EPWM_T::CTL0: IMMLDEN0 Position */ 3359 #define EPWM_CTL0_IMMLDEN0_Msk (0x1ul << EPWM_CTL0_IMMLDEN0_Pos) /*!< EPWM_T::CTL0: IMMLDEN0 Mask */ 3360 3361 #define EPWM_CTL0_IMMLDEN1_Pos (17) /*!< EPWM_T::CTL0: IMMLDEN1 Position */ 3362 #define EPWM_CTL0_IMMLDEN1_Msk (0x1ul << EPWM_CTL0_IMMLDEN1_Pos) /*!< EPWM_T::CTL0: IMMLDEN1 Mask */ 3363 3364 #define EPWM_CTL0_IMMLDEN2_Pos (18) /*!< EPWM_T::CTL0: IMMLDEN2 Position */ 3365 #define EPWM_CTL0_IMMLDEN2_Msk (0x1ul << EPWM_CTL0_IMMLDEN2_Pos) /*!< EPWM_T::CTL0: IMMLDEN2 Mask */ 3366 3367 #define EPWM_CTL0_IMMLDEN3_Pos (19) /*!< EPWM_T::CTL0: IMMLDEN3 Position */ 3368 #define EPWM_CTL0_IMMLDEN3_Msk (0x1ul << EPWM_CTL0_IMMLDEN3_Pos) /*!< EPWM_T::CTL0: IMMLDEN3 Mask */ 3369 3370 #define EPWM_CTL0_IMMLDEN4_Pos (20) /*!< EPWM_T::CTL0: IMMLDEN4 Position */ 3371 #define EPWM_CTL0_IMMLDEN4_Msk (0x1ul << EPWM_CTL0_IMMLDEN4_Pos) /*!< EPWM_T::CTL0: IMMLDEN4 Mask */ 3372 3373 #define EPWM_CTL0_IMMLDEN5_Pos (21) /*!< EPWM_T::CTL0: IMMLDEN5 Position */ 3374 #define EPWM_CTL0_IMMLDEN5_Msk (0x1ul << EPWM_CTL0_IMMLDEN5_Pos) /*!< EPWM_T::CTL0: IMMLDEN5 Mask */ 3375 3376 #define EPWM_CTL0_GROUPEN_Pos (24) /*!< EPWM_T::CTL0: GROUPEN Position */ 3377 #define EPWM_CTL0_GROUPEN_Msk (0x1ul << EPWM_CTL0_GROUPEN_Pos) /*!< EPWM_T::CTL0: GROUPEN Mask */ 3378 3379 #define EPWM_CTL0_DBGHALT_Pos (30) /*!< EPWM_T::CTL0: DBGHALT Position */ 3380 #define EPWM_CTL0_DBGHALT_Msk (0x1ul << EPWM_CTL0_DBGHALT_Pos) /*!< EPWM_T::CTL0: DBGHALT Mask */ 3381 3382 #define EPWM_CTL0_DBGTRIOFF_Pos (31) /*!< EPWM_T::CTL0: DBGTRIOFF Position */ 3383 #define EPWM_CTL0_DBGTRIOFF_Msk (0x1ul << EPWM_CTL0_DBGTRIOFF_Pos) /*!< EPWM_T::CTL0: DBGTRIOFF Mask */ 3384 3385 #define EPWM_CTL1_CNTTYPE0_Pos (0) /*!< EPWM_T::CTL1: CNTTYPE0 Position */ 3386 #define EPWM_CTL1_CNTTYPE0_Msk (0x3ul << EPWM_CTL1_CNTTYPE0_Pos) /*!< EPWM_T::CTL1: CNTTYPE0 Mask */ 3387 3388 #define EPWM_CTL1_CNTTYPE1_Pos (2) /*!< EPWM_T::CTL1: CNTTYPE1 Position */ 3389 #define EPWM_CTL1_CNTTYPE1_Msk (0x3ul << EPWM_CTL1_CNTTYPE1_Pos) /*!< EPWM_T::CTL1: CNTTYPE1 Mask */ 3390 3391 #define EPWM_CTL1_CNTTYPE2_Pos (4) /*!< EPWM_T::CTL1: CNTTYPE2 Position */ 3392 #define EPWM_CTL1_CNTTYPE2_Msk (0x3ul << EPWM_CTL1_CNTTYPE2_Pos) /*!< EPWM_T::CTL1: CNTTYPE2 Mask */ 3393 3394 #define EPWM_CTL1_CNTTYPE3_Pos (6) /*!< EPWM_T::CTL1: CNTTYPE3 Position */ 3395 #define EPWM_CTL1_CNTTYPE3_Msk (0x3ul << EPWM_CTL1_CNTTYPE3_Pos) /*!< EPWM_T::CTL1: CNTTYPE3 Mask */ 3396 3397 #define EPWM_CTL1_CNTTYPE4_Pos (8) /*!< EPWM_T::CTL1: CNTTYPE4 Position */ 3398 #define EPWM_CTL1_CNTTYPE4_Msk (0x3ul << EPWM_CTL1_CNTTYPE4_Pos) /*!< EPWM_T::CTL1: CNTTYPE4 Mask */ 3399 3400 #define EPWM_CTL1_CNTTYPE5_Pos (10) /*!< EPWM_T::CTL1: CNTTYPE5 Position */ 3401 #define EPWM_CTL1_CNTTYPE5_Msk (0x3ul << EPWM_CTL1_CNTTYPE5_Pos) /*!< EPWM_T::CTL1: CNTTYPE5 Mask */ 3402 3403 #define EPWM_CTL1_CNTMODE0_Pos (16) /*!< EPWM_T::CTL1: CNTMODE0 Position */ 3404 #define EPWM_CTL1_CNTMODE0_Msk (0x1ul << EPWM_CTL1_CNTMODE0_Pos) /*!< EPWM_T::CTL1: CNTMODE0 Mask */ 3405 3406 #define EPWM_CTL1_CNTMODE1_Pos (17) /*!< EPWM_T::CTL1: CNTMODE1 Position */ 3407 #define EPWM_CTL1_CNTMODE1_Msk (0x1ul << EPWM_CTL1_CNTMODE1_Pos) /*!< EPWM_T::CTL1: CNTMODE1 Mask */ 3408 3409 #define EPWM_CTL1_CNTMODE2_Pos (18) /*!< EPWM_T::CTL1: CNTMODE2 Position */ 3410 #define EPWM_CTL1_CNTMODE2_Msk (0x1ul << EPWM_CTL1_CNTMODE2_Pos) /*!< EPWM_T::CTL1: CNTMODE2 Mask */ 3411 3412 #define EPWM_CTL1_CNTMODE3_Pos (19) /*!< EPWM_T::CTL1: CNTMODE3 Position */ 3413 #define EPWM_CTL1_CNTMODE3_Msk (0x1ul << EPWM_CTL1_CNTMODE3_Pos) /*!< EPWM_T::CTL1: CNTMODE3 Mask */ 3414 3415 #define EPWM_CTL1_CNTMODE4_Pos (20) /*!< EPWM_T::CTL1: CNTMODE4 Position */ 3416 #define EPWM_CTL1_CNTMODE4_Msk (0x1ul << EPWM_CTL1_CNTMODE4_Pos) /*!< EPWM_T::CTL1: CNTMODE4 Mask */ 3417 3418 #define EPWM_CTL1_CNTMODE5_Pos (21) /*!< EPWM_T::CTL1: CNTMODE5 Position */ 3419 #define EPWM_CTL1_CNTMODE5_Msk (0x1ul << EPWM_CTL1_CNTMODE5_Pos) /*!< EPWM_T::CTL1: CNTMODE5 Mask */ 3420 3421 #define EPWM_CTL1_OUTMODE0_Pos (24) /*!< EPWM_T::CTL1: OUTMODE0 Position */ 3422 #define EPWM_CTL1_OUTMODE0_Msk (0x1ul << EPWM_CTL1_OUTMODE0_Pos) /*!< EPWM_T::CTL1: OUTMODE0 Mask */ 3423 3424 #define EPWM_CTL1_OUTMODE2_Pos (25) /*!< EPWM_T::CTL1: OUTMODE2 Position */ 3425 #define EPWM_CTL1_OUTMODE2_Msk (0x1ul << EPWM_CTL1_OUTMODE2_Pos) /*!< EPWM_T::CTL1: OUTMODE2 Mask */ 3426 3427 #define EPWM_CTL1_OUTMODE4_Pos (26) /*!< EPWM_T::CTL1: OUTMODE4 Position */ 3428 #define EPWM_CTL1_OUTMODE4_Msk (0x1ul << EPWM_CTL1_OUTMODE4_Pos) /*!< EPWM_T::CTL1: OUTMODE4 Mask */ 3429 3430 #define EPWM_SYNC_PHSEN0_Pos (0) /*!< EPWM_T::SYNC: PHSEN0 Position */ 3431 #define EPWM_SYNC_PHSEN0_Msk (0x1ul << EPWM_SYNC_PHSEN0_Pos) /*!< EPWM_T::SYNC: PHSEN0 Mask */ 3432 3433 #define EPWM_SYNC_PHSEN2_Pos (1) /*!< EPWM_T::SYNC: PHSEN2 Position */ 3434 #define EPWM_SYNC_PHSEN2_Msk (0x1ul << EPWM_SYNC_PHSEN2_Pos) /*!< EPWM_T::SYNC: PHSEN2 Mask */ 3435 3436 #define EPWM_SYNC_PHSEN4_Pos (2) /*!< EPWM_T::SYNC: PHSEN4 Position */ 3437 #define EPWM_SYNC_PHSEN4_Msk (0x1ul << EPWM_SYNC_PHSEN4_Pos) /*!< EPWM_T::SYNC: PHSEN4 Mask */ 3438 3439 #define EPWM_SYNC_SINSRC0_Pos (8) /*!< EPWM_T::SYNC: SINSRC0 Position */ 3440 #define EPWM_SYNC_SINSRC0_Msk (0x3ul << EPWM_SYNC_SINSRC0_Pos) /*!< EPWM_T::SYNC: SINSRC0 Mask */ 3441 3442 #define EPWM_SYNC_SINSRC2_Pos (10) /*!< EPWM_T::SYNC: SINSRC2 Position */ 3443 #define EPWM_SYNC_SINSRC2_Msk (0x3ul << EPWM_SYNC_SINSRC2_Pos) /*!< EPWM_T::SYNC: SINSRC2 Mask */ 3444 3445 #define EPWM_SYNC_SINSRC4_Pos (12) /*!< EPWM_T::SYNC: SINSRC4 Position */ 3446 #define EPWM_SYNC_SINSRC4_Msk (0x3ul << EPWM_SYNC_SINSRC4_Pos) /*!< EPWM_T::SYNC: SINSRC4 Mask */ 3447 3448 #define EPWM_SYNC_SNFLTEN_Pos (16) /*!< EPWM_T::SYNC: SNFLTEN Position */ 3449 #define EPWM_SYNC_SNFLTEN_Msk (0x1ul << EPWM_SYNC_SNFLTEN_Pos) /*!< EPWM_T::SYNC: SNFLTEN Mask */ 3450 3451 #define EPWM_SYNC_SFLTCSEL_Pos (17) /*!< EPWM_T::SYNC: SFLTCSEL Position */ 3452 #define EPWM_SYNC_SFLTCSEL_Msk (0x7ul << EPWM_SYNC_SFLTCSEL_Pos) /*!< EPWM_T::SYNC: SFLTCSEL Mask */ 3453 3454 #define EPWM_SYNC_SFLTCNT_Pos (20) /*!< EPWM_T::SYNC: SFLTCNT Position */ 3455 #define EPWM_SYNC_SFLTCNT_Msk (0x7ul << EPWM_SYNC_SFLTCNT_Pos) /*!< EPWM_T::SYNC: SFLTCNT Mask */ 3456 3457 #define EPWM_SYNC_SINPINV_Pos (23) /*!< EPWM_T::SYNC: SINPINV Position */ 3458 #define EPWM_SYNC_SINPINV_Msk (0x1ul << EPWM_SYNC_SINPINV_Pos) /*!< EPWM_T::SYNC: SINPINV Mask */ 3459 3460 #define EPWM_SYNC_PHSDIR0_Pos (24) /*!< EPWM_T::SYNC: PHSDIR0 Position */ 3461 #define EPWM_SYNC_PHSDIR0_Msk (0x1ul << EPWM_SYNC_PHSDIR0_Pos) /*!< EPWM_T::SYNC: PHSDIR0 Mask */ 3462 3463 #define EPWM_SYNC_PHSDIR2_Pos (25) /*!< EPWM_T::SYNC: PHSDIR2 Position */ 3464 #define EPWM_SYNC_PHSDIR2_Msk (0x1ul << EPWM_SYNC_PHSDIR2_Pos) /*!< EPWM_T::SYNC: PHSDIR2 Mask */ 3465 3466 #define EPWM_SYNC_PHSDIR4_Pos (26) /*!< EPWM_T::SYNC: PHSDIR4 Position */ 3467 #define EPWM_SYNC_PHSDIR4_Msk (0x1ul << EPWM_SYNC_PHSDIR4_Pos) /*!< EPWM_T::SYNC: PHSDIR4 Mask */ 3468 3469 #define EPWM_SWSYNC_SWSYNC0_Pos (0) /*!< EPWM_T::SWSYNC: SWSYNC0 Position */ 3470 #define EPWM_SWSYNC_SWSYNC0_Msk (0x1ul << EPWM_SWSYNC_SWSYNC0_Pos) /*!< EPWM_T::SWSYNC: SWSYNC0 Mask */ 3471 3472 #define EPWM_SWSYNC_SWSYNC2_Pos (1) /*!< EPWM_T::SWSYNC: SWSYNC2 Position */ 3473 #define EPWM_SWSYNC_SWSYNC2_Msk (0x1ul << EPWM_SWSYNC_SWSYNC2_Pos) /*!< EPWM_T::SWSYNC: SWSYNC2 Mask */ 3474 3475 #define EPWM_SWSYNC_SWSYNC4_Pos (2) /*!< EPWM_T::SWSYNC: SWSYNC4 Position */ 3476 #define EPWM_SWSYNC_SWSYNC4_Msk (0x1ul << EPWM_SWSYNC_SWSYNC4_Pos) /*!< EPWM_T::SWSYNC: SWSYNC4 Mask */ 3477 3478 #define EPWM_CLKSRC_ECLKSRC0_Pos (0) /*!< EPWM_T::CLKSRC: ECLKSRC0 Position */ 3479 #define EPWM_CLKSRC_ECLKSRC0_Msk (0x7ul << EPWM_CLKSRC_ECLKSRC0_Pos) /*!< EPWM_T::CLKSRC: ECLKSRC0 Mask */ 3480 3481 #define EPWM_CLKSRC_ECLKSRC2_Pos (8) /*!< EPWM_T::CLKSRC: ECLKSRC2 Position */ 3482 #define EPWM_CLKSRC_ECLKSRC2_Msk (0x7ul << EPWM_CLKSRC_ECLKSRC2_Pos) /*!< EPWM_T::CLKSRC: ECLKSRC2 Mask */ 3483 3484 #define EPWM_CLKSRC_ECLKSRC4_Pos (16) /*!< EPWM_T::CLKSRC: ECLKSRC4 Position */ 3485 #define EPWM_CLKSRC_ECLKSRC4_Msk (0x7ul << EPWM_CLKSRC_ECLKSRC4_Pos) /*!< EPWM_T::CLKSRC: ECLKSRC4 Mask */ 3486 3487 #define EPWM_CNTEN_CNTEN0_Pos (0) /*!< EPWM_T::CNTEN: CNTEN0 Position */ 3488 #define EPWM_CNTEN_CNTEN0_Msk (0x1ul << EPWM_CNTEN_CNTEN0_Pos) /*!< EPWM_T::CNTEN: CNTEN0 Mask */ 3489 3490 #define EPWM_CNTEN_CNTEN1_Pos (1) /*!< EPWM_T::CNTEN: CNTEN1 Position */ 3491 #define EPWM_CNTEN_CNTEN1_Msk (0x1ul << EPWM_CNTEN_CNTEN1_Pos) /*!< EPWM_T::CNTEN: CNTEN1 Mask */ 3492 3493 #define EPWM_CNTEN_CNTEN2_Pos (2) /*!< EPWM_T::CNTEN: CNTEN2 Position */ 3494 #define EPWM_CNTEN_CNTEN2_Msk (0x1ul << EPWM_CNTEN_CNTEN2_Pos) /*!< EPWM_T::CNTEN: CNTEN2 Mask */ 3495 3496 #define EPWM_CNTEN_CNTEN3_Pos (3) /*!< EPWM_T::CNTEN: CNTEN3 Position */ 3497 #define EPWM_CNTEN_CNTEN3_Msk (0x1ul << EPWM_CNTEN_CNTEN3_Pos) /*!< EPWM_T::CNTEN: CNTEN3 Mask */ 3498 3499 #define EPWM_CNTEN_CNTEN4_Pos (4) /*!< EPWM_T::CNTEN: CNTEN4 Position */ 3500 #define EPWM_CNTEN_CNTEN4_Msk (0x1ul << EPWM_CNTEN_CNTEN4_Pos) /*!< EPWM_T::CNTEN: CNTEN4 Mask */ 3501 3502 #define EPWM_CNTEN_CNTEN5_Pos (5) /*!< EPWM_T::CNTEN: CNTEN5 Position */ 3503 #define EPWM_CNTEN_CNTEN5_Msk (0x1ul << EPWM_CNTEN_CNTEN5_Pos) /*!< EPWM_T::CNTEN: CNTEN5 Mask */ 3504 3505 #define EPWM_CNTCLR_CNTCLR0_Pos (0) /*!< EPWM_T::CNTCLR: CNTCLR0 Position */ 3506 #define EPWM_CNTCLR_CNTCLR0_Msk (0x1ul << EPWM_CNTCLR_CNTCLR0_Pos) /*!< EPWM_T::CNTCLR: CNTCLR0 Mask */ 3507 3508 #define EPWM_CNTCLR_CNTCLR1_Pos (1) /*!< EPWM_T::CNTCLR: CNTCLR1 Position */ 3509 #define EPWM_CNTCLR_CNTCLR1_Msk (0x1ul << EPWM_CNTCLR_CNTCLR1_Pos) /*!< EPWM_T::CNTCLR: CNTCLR1 Mask */ 3510 3511 #define EPWM_CNTCLR_CNTCLR2_Pos (2) /*!< EPWM_T::CNTCLR: CNTCLR2 Position */ 3512 #define EPWM_CNTCLR_CNTCLR2_Msk (0x1ul << EPWM_CNTCLR_CNTCLR2_Pos) /*!< EPWM_T::CNTCLR: CNTCLR2 Mask */ 3513 3514 #define EPWM_CNTCLR_CNTCLR3_Pos (3) /*!< EPWM_T::CNTCLR: CNTCLR3 Position */ 3515 #define EPWM_CNTCLR_CNTCLR3_Msk (0x1ul << EPWM_CNTCLR_CNTCLR3_Pos) /*!< EPWM_T::CNTCLR: CNTCLR3 Mask */ 3516 3517 #define EPWM_CNTCLR_CNTCLR4_Pos (4) /*!< EPWM_T::CNTCLR: CNTCLR4 Position */ 3518 #define EPWM_CNTCLR_CNTCLR4_Msk (0x1ul << EPWM_CNTCLR_CNTCLR4_Pos) /*!< EPWM_T::CNTCLR: CNTCLR4 Mask */ 3519 3520 #define EPWM_CNTCLR_CNTCLR5_Pos (5) /*!< EPWM_T::CNTCLR: CNTCLR5 Position */ 3521 #define EPWM_CNTCLR_CNTCLR5_Msk (0x1ul << EPWM_CNTCLR_CNTCLR5_Pos) /*!< EPWM_T::CNTCLR: CNTCLR5 Mask */ 3522 3523 #define EPWM_LOAD_LOAD0_Pos (0) /*!< EPWM_T::LOAD: LOAD0 Position */ 3524 #define EPWM_LOAD_LOAD0_Msk (0x1ul << EPWM_LOAD_LOAD0_Pos) /*!< EPWM_T::LOAD: LOAD0 Mask */ 3525 3526 #define EPWM_LOAD_LOAD1_Pos (1) /*!< EPWM_T::LOAD: LOAD1 Position */ 3527 #define EPWM_LOAD_LOAD1_Msk (0x1ul << EPWM_LOAD_LOAD1_Pos) /*!< EPWM_T::LOAD: LOAD1 Mask */ 3528 3529 #define EPWM_LOAD_LOAD2_Pos (2) /*!< EPWM_T::LOAD: LOAD2 Position */ 3530 #define EPWM_LOAD_LOAD2_Msk (0x1ul << EPWM_LOAD_LOAD2_Pos) /*!< EPWM_T::LOAD: LOAD2 Mask */ 3531 3532 #define EPWM_LOAD_LOAD3_Pos (3) /*!< EPWM_T::LOAD: LOAD3 Position */ 3533 #define EPWM_LOAD_LOAD3_Msk (0x1ul << EPWM_LOAD_LOAD3_Pos) /*!< EPWM_T::LOAD: LOAD3 Mask */ 3534 3535 #define EPWM_LOAD_LOAD4_Pos (4) /*!< EPWM_T::LOAD: LOAD4 Position */ 3536 #define EPWM_LOAD_LOAD4_Msk (0x1ul << EPWM_LOAD_LOAD4_Pos) /*!< EPWM_T::LOAD: LOAD4 Mask */ 3537 3538 #define EPWM_LOAD_LOAD5_Pos (5) /*!< EPWM_T::LOAD: LOAD5 Position */ 3539 #define EPWM_LOAD_LOAD5_Msk (0x1ul << EPWM_LOAD_LOAD5_Pos) /*!< EPWM_T::LOAD: LOAD5 Mask */ 3540 3541 #define EPWM_PERIOD0_PERIOD_Pos (0) /*!< EPWM_T::PERIOD0: PERIOD Position */ 3542 #define EPWM_PERIOD0_PERIOD_Msk (0xfffful << EPWM_PERIOD0_PERIOD_Pos) /*!< EPWM_T::PERIOD0: PERIOD Mask */ 3543 3544 #define EPWM_PERIOD1_PERIOD_Pos (0) /*!< EPWM_T::PERIOD1: PERIOD Position */ 3545 #define EPWM_PERIOD1_PERIOD_Msk (0xfffful << EPWM_PERIOD1_PERIOD_Pos) /*!< EPWM_T::PERIOD1: PERIOD Mask */ 3546 3547 #define EPWM_PERIOD2_PERIOD_Pos (0) /*!< EPWM_T::PERIOD2: PERIOD Position */ 3548 #define EPWM_PERIOD2_PERIOD_Msk (0xfffful << EPWM_PERIOD2_PERIOD_Pos) /*!< EPWM_T::PERIOD2: PERIOD Mask */ 3549 3550 #define EPWM_PERIOD3_PERIOD_Pos (0) /*!< EPWM_T::PERIOD3: PERIOD Position */ 3551 #define EPWM_PERIOD3_PERIOD_Msk (0xfffful << EPWM_PERIOD3_PERIOD_Pos) /*!< EPWM_T::PERIOD3: PERIOD Mask */ 3552 3553 #define EPWM_PERIOD4_PERIOD_Pos (0) /*!< EPWM_T::PERIOD4: PERIOD Position */ 3554 #define EPWM_PERIOD4_PERIOD_Msk (0xfffful << EPWM_PERIOD4_PERIOD_Pos) /*!< EPWM_T::PERIOD4: PERIOD Mask */ 3555 3556 #define EPWM_PERIOD5_PERIOD_Pos (0) /*!< EPWM_T::PERIOD5: PERIOD Position */ 3557 #define EPWM_PERIOD5_PERIOD_Msk (0xfffful << EPWM_PERIOD5_PERIOD_Pos) /*!< EPWM_T::PERIOD5: PERIOD Mask */ 3558 3559 #define EPWM_CMPDAT0_CMP_Pos (0) /*!< EPWM_T::CMPDAT0: CMP Position */ 3560 #define EPWM_CMPDAT0_CMP_Msk (0xfffful << EPWM_CMPDAT0_CMP_Pos) /*!< EPWM_T::CMPDAT0: CMP Mask */ 3561 3562 #define EPWM_CMPDAT1_CMP_Pos (0) /*!< EPWM_T::CMPDAT1: CMP Position */ 3563 #define EPWM_CMPDAT1_CMP_Msk (0xfffful << EPWM_CMPDAT1_CMP_Pos) /*!< EPWM_T::CMPDAT1: CMP Mask */ 3564 3565 #define EPWM_CMPDAT2_CMP_Pos (0) /*!< EPWM_T::CMPDAT2: CMP Position */ 3566 #define EPWM_CMPDAT2_CMP_Msk (0xfffful << EPWM_CMPDAT2_CMP_Pos) /*!< EPWM_T::CMPDAT2: CMP Mask */ 3567 3568 #define EPWM_CMPDAT3_CMP_Pos (0) /*!< EPWM_T::CMPDAT3: CMP Position */ 3569 #define EPWM_CMPDAT3_CMP_Msk (0xfffful << EPWM_CMPDAT3_CMP_Pos) /*!< EPWM_T::CMPDAT3: CMP Mask */ 3570 3571 #define EPWM_CMPDAT4_CMP_Pos (0) /*!< EPWM_T::CMPDAT4: CMP Position */ 3572 #define EPWM_CMPDAT4_CMP_Msk (0xfffful << EPWM_CMPDAT4_CMP_Pos) /*!< EPWM_T::CMPDAT4: CMP Mask */ 3573 3574 #define EPWM_CMPDAT5_CMP_Pos (0) /*!< EPWM_T::CMPDAT5: CMP Position */ 3575 #define EPWM_CMPDAT5_CMP_Msk (0xfffful << EPWM_CMPDAT5_CMP_Pos) /*!< EPWM_T::CMPDAT5: CMP Mask */ 3576 3577 #define EPWM_PHS0_1_PHS_Pos (0) /*!< EPWM_T::PHS0_1: PHS Position */ 3578 #define EPWM_PHS0_1_PHS_Msk (0xfffful << EPWM_PHS0_1_PHS_Pos) /*!< EPWM_T::PHS0_1: PHS Mask */ 3579 3580 #define EPWM_PHS2_3_PHS_Pos (0) /*!< EPWM_T::PHS2_3: PHS Position */ 3581 #define EPWM_PHS2_3_PHS_Msk (0xfffful << EPWM_PHS2_3_PHS_Pos) /*!< EPWM_T::PHS2_3: PHS Mask */ 3582 3583 #define EPWM_PHS4_5_PHS_Pos (0) /*!< EPWM_T::PHS4_5: PHS Position */ 3584 #define EPWM_PHS4_5_PHS_Msk (0xfffful << EPWM_PHS4_5_PHS_Pos) /*!< EPWM_T::PHS4_5: PHS Mask */ 3585 3586 #define EPWM_CNT0_CNT_Pos (0) /*!< EPWM_T::CNT0: CNT Position */ 3587 #define EPWM_CNT0_CNT_Msk (0xfffful << EPWM_CNT0_CNT_Pos) /*!< EPWM_T::CNT0: CNT Mask */ 3588 3589 #define EPWM_CNT0_DIRF_Pos (16) /*!< EPWM_T::CNT0: DIRF Position */ 3590 #define EPWM_CNT0_DIRF_Msk (0x1ul << EPWM_CNT0_DIRF_Pos) /*!< EPWM_T::CNT0: DIRF Mask */ 3591 3592 #define EPWM_CNT1_CNT_Pos (0) /*!< EPWM_T::CNT1: CNT Position */ 3593 #define EPWM_CNT1_CNT_Msk (0xfffful << EPWM_CNT1_CNT_Pos) /*!< EPWM_T::CNT1: CNT Mask */ 3594 3595 #define EPWM_CNT1_DIRF_Pos (16) /*!< EPWM_T::CNT1: DIRF Position */ 3596 #define EPWM_CNT1_DIRF_Msk (0x1ul << EPWM_CNT1_DIRF_Pos) /*!< EPWM_T::CNT1: DIRF Mask */ 3597 3598 #define EPWM_CNT2_CNT_Pos (0) /*!< EPWM_T::CNT2: CNT Position */ 3599 #define EPWM_CNT2_CNT_Msk (0xfffful << EPWM_CNT2_CNT_Pos) /*!< EPWM_T::CNT2: CNT Mask */ 3600 3601 #define EPWM_CNT2_DIRF_Pos (16) /*!< EPWM_T::CNT2: DIRF Position */ 3602 #define EPWM_CNT2_DIRF_Msk (0x1ul << EPWM_CNT2_DIRF_Pos) /*!< EPWM_T::CNT2: DIRF Mask */ 3603 3604 #define EPWM_CNT3_CNT_Pos (0) /*!< EPWM_T::CNT3: CNT Position */ 3605 #define EPWM_CNT3_CNT_Msk (0xfffful << EPWM_CNT3_CNT_Pos) /*!< EPWM_T::CNT3: CNT Mask */ 3606 3607 #define EPWM_CNT3_DIRF_Pos (16) /*!< EPWM_T::CNT3: DIRF Position */ 3608 #define EPWM_CNT3_DIRF_Msk (0x1ul << EPWM_CNT3_DIRF_Pos) /*!< EPWM_T::CNT3: DIRF Mask */ 3609 3610 #define EPWM_CNT4_CNT_Pos (0) /*!< EPWM_T::CNT4: CNT Position */ 3611 #define EPWM_CNT4_CNT_Msk (0xfffful << EPWM_CNT4_CNT_Pos) /*!< EPWM_T::CNT4: CNT Mask */ 3612 3613 #define EPWM_CNT4_DIRF_Pos (16) /*!< EPWM_T::CNT4: DIRF Position */ 3614 #define EPWM_CNT4_DIRF_Msk (0x1ul << EPWM_CNT4_DIRF_Pos) /*!< EPWM_T::CNT4: DIRF Mask */ 3615 3616 #define EPWM_CNT5_CNT_Pos (0) /*!< EPWM_T::CNT5: CNT Position */ 3617 #define EPWM_CNT5_CNT_Msk (0xfffful << EPWM_CNT5_CNT_Pos) /*!< EPWM_T::CNT5: CNT Mask */ 3618 3619 #define EPWM_CNT5_DIRF_Pos (16) /*!< EPWM_T::CNT5: DIRF Position */ 3620 #define EPWM_CNT5_DIRF_Msk (0x1ul << EPWM_CNT5_DIRF_Pos) /*!< EPWM_T::CNT5: DIRF Mask */ 3621 3622 #define EPWM_WGCTL0_ZPCTL0_Pos (0) /*!< EPWM_T::WGCTL0: ZPCTL0 Position */ 3623 #define EPWM_WGCTL0_ZPCTL0_Msk (0x3ul << EPWM_WGCTL0_ZPCTL0_Pos) /*!< EPWM_T::WGCTL0: ZPCTL0 Mask */ 3624 3625 #define EPWM_WGCTL0_ZPCTL1_Pos (2) /*!< EPWM_T::WGCTL0: ZPCTL1 Position */ 3626 #define EPWM_WGCTL0_ZPCTL1_Msk (0x3ul << EPWM_WGCTL0_ZPCTL1_Pos) /*!< EPWM_T::WGCTL0: ZPCTL1 Mask */ 3627 3628 #define EPWM_WGCTL0_ZPCTL2_Pos (4) /*!< EPWM_T::WGCTL0: ZPCTL2 Position */ 3629 #define EPWM_WGCTL0_ZPCTL2_Msk (0x3ul << EPWM_WGCTL0_ZPCTL2_Pos) /*!< EPWM_T::WGCTL0: ZPCTL2 Mask */ 3630 3631 #define EPWM_WGCTL0_ZPCTL3_Pos (6) /*!< EPWM_T::WGCTL0: ZPCTL3 Position */ 3632 #define EPWM_WGCTL0_ZPCTL3_Msk (0x3ul << EPWM_WGCTL0_ZPCTL3_Pos) /*!< EPWM_T::WGCTL0: ZPCTL3 Mask */ 3633 3634 #define EPWM_WGCTL0_ZPCTL4_Pos (8) /*!< EPWM_T::WGCTL0: ZPCTL4 Position */ 3635 #define EPWM_WGCTL0_ZPCTL4_Msk (0x3ul << EPWM_WGCTL0_ZPCTL4_Pos) /*!< EPWM_T::WGCTL0: ZPCTL4 Mask */ 3636 3637 #define EPWM_WGCTL0_ZPCTL5_Pos (10) /*!< EPWM_T::WGCTL0: ZPCTL5 Position */ 3638 #define EPWM_WGCTL0_ZPCTL5_Msk (0x3ul << EPWM_WGCTL0_ZPCTL5_Pos) /*!< EPWM_T::WGCTL0: ZPCTL5 Mask */ 3639 3640 #define EPWM_WGCTL0_PRDPCTL0_Pos (16) /*!< EPWM_T::WGCTL0: PRDPCTL0 Position */ 3641 #define EPWM_WGCTL0_PRDPCTL0_Msk (0x3ul << EPWM_WGCTL0_PRDPCTL0_Pos) /*!< EPWM_T::WGCTL0: PRDPCTL0 Mask */ 3642 3643 #define EPWM_WGCTL0_PRDPCTL1_Pos (18) /*!< EPWM_T::WGCTL0: PRDPCTL1 Position */ 3644 #define EPWM_WGCTL0_PRDPCTL1_Msk (0x3ul << EPWM_WGCTL0_PRDPCTL1_Pos) /*!< EPWM_T::WGCTL0: PRDPCTL1 Mask */ 3645 3646 #define EPWM_WGCTL0_PRDPCTL2_Pos (20) /*!< EPWM_T::WGCTL0: PRDPCTL2 Position */ 3647 #define EPWM_WGCTL0_PRDPCTL2_Msk (0x3ul << EPWM_WGCTL0_PRDPCTL2_Pos) /*!< EPWM_T::WGCTL0: PRDPCTL2 Mask */ 3648 3649 #define EPWM_WGCTL0_PRDPCTL3_Pos (22) /*!< EPWM_T::WGCTL0: PRDPCTL3 Position */ 3650 #define EPWM_WGCTL0_PRDPCTL3_Msk (0x3ul << EPWM_WGCTL0_PRDPCTL3_Pos) /*!< EPWM_T::WGCTL0: PRDPCTL3 Mask */ 3651 3652 #define EPWM_WGCTL0_PRDPCTL4_Pos (24) /*!< EPWM_T::WGCTL0: PRDPCTL4 Position */ 3653 #define EPWM_WGCTL0_PRDPCTL4_Msk (0x3ul << EPWM_WGCTL0_PRDPCTL4_Pos) /*!< EPWM_T::WGCTL0: PRDPCTL4 Mask */ 3654 3655 #define EPWM_WGCTL0_PRDPCTL5_Pos (26) /*!< EPWM_T::WGCTL0: PRDPCTL5 Position */ 3656 #define EPWM_WGCTL0_PRDPCTL5_Msk (0x3ul << EPWM_WGCTL0_PRDPCTL5_Pos) /*!< EPWM_T::WGCTL0: PRDPCTL5 Mask */ 3657 3658 #define EPWM_WGCTL1_CMPUCTL0_Pos (0) /*!< EPWM_T::WGCTL1: CMPUCTL0 Position */ 3659 #define EPWM_WGCTL1_CMPUCTL0_Msk (0x3ul << EPWM_WGCTL1_CMPUCTL0_Pos) /*!< EPWM_T::WGCTL1: CMPUCTL0 Mask */ 3660 3661 #define EPWM_WGCTL1_CMPUCTL1_Pos (2) /*!< EPWM_T::WGCTL1: CMPUCTL1 Position */ 3662 #define EPWM_WGCTL1_CMPUCTL1_Msk (0x3ul << EPWM_WGCTL1_CMPUCTL1_Pos) /*!< EPWM_T::WGCTL1: CMPUCTL1 Mask */ 3663 3664 #define EPWM_WGCTL1_CMPUCTL2_Pos (4) /*!< EPWM_T::WGCTL1: CMPUCTL2 Position */ 3665 #define EPWM_WGCTL1_CMPUCTL2_Msk (0x3ul << EPWM_WGCTL1_CMPUCTL2_Pos) /*!< EPWM_T::WGCTL1: CMPUCTL2 Mask */ 3666 3667 #define EPWM_WGCTL1_CMPUCTL3_Pos (6) /*!< EPWM_T::WGCTL1: CMPUCTL3 Position */ 3668 #define EPWM_WGCTL1_CMPUCTL3_Msk (0x3ul << EPWM_WGCTL1_CMPUCTL3_Pos) /*!< EPWM_T::WGCTL1: CMPUCTL3 Mask */ 3669 3670 #define EPWM_WGCTL1_CMPUCTL4_Pos (8) /*!< EPWM_T::WGCTL1: CMPUCTL4 Position */ 3671 #define EPWM_WGCTL1_CMPUCTL4_Msk (0x3ul << EPWM_WGCTL1_CMPUCTL4_Pos) /*!< EPWM_T::WGCTL1: CMPUCTL4 Mask */ 3672 3673 #define EPWM_WGCTL1_CMPUCTL5_Pos (10) /*!< EPWM_T::WGCTL1: CMPUCTL5 Position */ 3674 #define EPWM_WGCTL1_CMPUCTL5_Msk (0x3ul << EPWM_WGCTL1_CMPUCTL5_Pos) /*!< EPWM_T::WGCTL1: CMPUCTL5 Mask */ 3675 3676 #define EPWM_WGCTL1_CMPDCTL0_Pos (16) /*!< EPWM_T::WGCTL1: CMPDCTL0 Position */ 3677 #define EPWM_WGCTL1_CMPDCTL0_Msk (0x3ul << EPWM_WGCTL1_CMPDCTL0_Pos) /*!< EPWM_T::WGCTL1: CMPDCTL0 Mask */ 3678 3679 #define EPWM_WGCTL1_CMPDCTL1_Pos (18) /*!< EPWM_T::WGCTL1: CMPDCTL1 Position */ 3680 #define EPWM_WGCTL1_CMPDCTL1_Msk (0x3ul << EPWM_WGCTL1_CMPDCTL1_Pos) /*!< EPWM_T::WGCTL1: CMPDCTL1 Mask */ 3681 3682 #define EPWM_WGCTL1_CMPDCTL2_Pos (20) /*!< EPWM_T::WGCTL1: CMPDCTL2 Position */ 3683 #define EPWM_WGCTL1_CMPDCTL2_Msk (0x3ul << EPWM_WGCTL1_CMPDCTL2_Pos) /*!< EPWM_T::WGCTL1: CMPDCTL2 Mask */ 3684 3685 #define EPWM_WGCTL1_CMPDCTL3_Pos (22) /*!< EPWM_T::WGCTL1: CMPDCTL3 Position */ 3686 #define EPWM_WGCTL1_CMPDCTL3_Msk (0x3ul << EPWM_WGCTL1_CMPDCTL3_Pos) /*!< EPWM_T::WGCTL1: CMPDCTL3 Mask */ 3687 3688 #define EPWM_WGCTL1_CMPDCTL4_Pos (24) /*!< EPWM_T::WGCTL1: CMPDCTL4 Position */ 3689 #define EPWM_WGCTL1_CMPDCTL4_Msk (0x3ul << EPWM_WGCTL1_CMPDCTL4_Pos) /*!< EPWM_T::WGCTL1: CMPDCTL4 Mask */ 3690 3691 #define EPWM_WGCTL1_CMPDCTL5_Pos (26) /*!< EPWM_T::WGCTL1: CMPDCTL5 Position */ 3692 #define EPWM_WGCTL1_CMPDCTL5_Msk (0x3ul << EPWM_WGCTL1_CMPDCTL5_Pos) /*!< EPWM_T::WGCTL1: CMPDCTL5 Mask */ 3693 3694 #define EPWM_MSKEN_MSKEN0_Pos (0) /*!< EPWM_T::MSKEN: MSKEN0 Position */ 3695 #define EPWM_MSKEN_MSKEN0_Msk (0x1ul << EPWM_MSKEN_MSKEN0_Pos) /*!< EPWM_T::MSKEN: MSKEN0 Mask */ 3696 3697 #define EPWM_MSKEN_MSKEN1_Pos (1) /*!< EPWM_T::MSKEN: MSKEN1 Position */ 3698 #define EPWM_MSKEN_MSKEN1_Msk (0x1ul << EPWM_MSKEN_MSKEN1_Pos) /*!< EPWM_T::MSKEN: MSKEN1 Mask */ 3699 3700 #define EPWM_MSKEN_MSKEN2_Pos (2) /*!< EPWM_T::MSKEN: MSKEN2 Position */ 3701 #define EPWM_MSKEN_MSKEN2_Msk (0x1ul << EPWM_MSKEN_MSKEN2_Pos) /*!< EPWM_T::MSKEN: MSKEN2 Mask */ 3702 3703 #define EPWM_MSKEN_MSKEN3_Pos (3) /*!< EPWM_T::MSKEN: MSKEN3 Position */ 3704 #define EPWM_MSKEN_MSKEN3_Msk (0x1ul << EPWM_MSKEN_MSKEN3_Pos) /*!< EPWM_T::MSKEN: MSKEN3 Mask */ 3705 3706 #define EPWM_MSKEN_MSKEN4_Pos (4) /*!< EPWM_T::MSKEN: MSKEN4 Position */ 3707 #define EPWM_MSKEN_MSKEN4_Msk (0x1ul << EPWM_MSKEN_MSKEN4_Pos) /*!< EPWM_T::MSKEN: MSKEN4 Mask */ 3708 3709 #define EPWM_MSKEN_MSKEN5_Pos (5) /*!< EPWM_T::MSKEN: MSKEN5 Position */ 3710 #define EPWM_MSKEN_MSKEN5_Msk (0x1ul << EPWM_MSKEN_MSKEN5_Pos) /*!< EPWM_T::MSKEN: MSKEN5 Mask */ 3711 3712 #define EPWM_MSK_MSKDAT0_Pos (0) /*!< EPWM_T::MSK: MSKDAT0 Position */ 3713 #define EPWM_MSK_MSKDAT0_Msk (0x1ul << EPWM_MSK_MSKDAT0_Pos) /*!< EPWM_T::MSK: MSKDAT0 Mask */ 3714 3715 #define EPWM_MSK_MSKDAT1_Pos (1) /*!< EPWM_T::MSK: MSKDAT1 Position */ 3716 #define EPWM_MSK_MSKDAT1_Msk (0x1ul << EPWM_MSK_MSKDAT1_Pos) /*!< EPWM_T::MSK: MSKDAT1 Mask */ 3717 3718 #define EPWM_MSK_MSKDAT2_Pos (2) /*!< EPWM_T::MSK: MSKDAT2 Position */ 3719 #define EPWM_MSK_MSKDAT2_Msk (0x1ul << EPWM_MSK_MSKDAT2_Pos) /*!< EPWM_T::MSK: MSKDAT2 Mask */ 3720 3721 #define EPWM_MSK_MSKDAT3_Pos (3) /*!< EPWM_T::MSK: MSKDAT3 Position */ 3722 #define EPWM_MSK_MSKDAT3_Msk (0x1ul << EPWM_MSK_MSKDAT3_Pos) /*!< EPWM_T::MSK: MSKDAT3 Mask */ 3723 3724 #define EPWM_MSK_MSKDAT4_Pos (4) /*!< EPWM_T::MSK: MSKDAT4 Position */ 3725 #define EPWM_MSK_MSKDAT4_Msk (0x1ul << EPWM_MSK_MSKDAT4_Pos) /*!< EPWM_T::MSK: MSKDAT4 Mask */ 3726 3727 #define EPWM_MSK_MSKDAT5_Pos (5) /*!< EPWM_T::MSK: MSKDAT5 Position */ 3728 #define EPWM_MSK_MSKDAT5_Msk (0x1ul << EPWM_MSK_MSKDAT5_Pos) /*!< EPWM_T::MSK: MSKDAT5 Mask */ 3729 3730 #define EPWM_BNF_BRK0NFEN_Pos (0) /*!< EPWM_T::BNF: BRK0NFEN Position */ 3731 #define EPWM_BNF_BRK0NFEN_Msk (0x1ul << EPWM_BNF_BRK0NFEN_Pos) /*!< EPWM_T::BNF: BRK0NFEN Mask */ 3732 3733 #define EPWM_BNF_BRK0NFSEL_Pos (1) /*!< EPWM_T::BNF: BRK0NFSEL Position */ 3734 #define EPWM_BNF_BRK0NFSEL_Msk (0x7ul << EPWM_BNF_BRK0NFSEL_Pos) /*!< EPWM_T::BNF: BRK0NFSEL Mask */ 3735 3736 #define EPWM_BNF_BRK0FCNT_Pos (4) /*!< EPWM_T::BNF: BRK0FCNT Position */ 3737 #define EPWM_BNF_BRK0FCNT_Msk (0x7ul << EPWM_BNF_BRK0FCNT_Pos) /*!< EPWM_T::BNF: BRK0FCNT Mask */ 3738 3739 #define EPWM_BNF_BRK0PINV_Pos (7) /*!< EPWM_T::BNF: BRK0PINV Position */ 3740 #define EPWM_BNF_BRK0PINV_Msk (0x1ul << EPWM_BNF_BRK0PINV_Pos) /*!< EPWM_T::BNF: BRK0PINV Mask */ 3741 3742 #define EPWM_BNF_BRK1NFEN_Pos (8) /*!< EPWM_T::BNF: BRK1NFEN Position */ 3743 #define EPWM_BNF_BRK1NFEN_Msk (0x1ul << EPWM_BNF_BRK1NFEN_Pos) /*!< EPWM_T::BNF: BRK1NFEN Mask */ 3744 3745 #define EPWM_BNF_BRK1NFSEL_Pos (9) /*!< EPWM_T::BNF: BRK1NFSEL Position */ 3746 #define EPWM_BNF_BRK1NFSEL_Msk (0x7ul << EPWM_BNF_BRK1NFSEL_Pos) /*!< EPWM_T::BNF: BRK1NFSEL Mask */ 3747 3748 #define EPWM_BNF_BRK1FCNT_Pos (12) /*!< EPWM_T::BNF: BRK1FCNT Position */ 3749 #define EPWM_BNF_BRK1FCNT_Msk (0x7ul << EPWM_BNF_BRK1FCNT_Pos) /*!< EPWM_T::BNF: BRK1FCNT Mask */ 3750 3751 #define EPWM_BNF_BRK1PINV_Pos (15) /*!< EPWM_T::BNF: BRK1PINV Position */ 3752 #define EPWM_BNF_BRK1PINV_Msk (0x1ul << EPWM_BNF_BRK1PINV_Pos) /*!< EPWM_T::BNF: BRK1PINV Mask */ 3753 3754 #define EPWM_BNF_BK0SRC_Pos (16) /*!< EPWM_T::BNF: BK0SRC Position */ 3755 #define EPWM_BNF_BK0SRC_Msk (0x1ul << EPWM_BNF_BK0SRC_Pos) /*!< EPWM_T::BNF: BK0SRC Mask */ 3756 3757 #define EPWM_BNF_BK1SRC_Pos (24) /*!< EPWM_T::BNF: BK1SRC Position */ 3758 #define EPWM_BNF_BK1SRC_Msk (0x1ul << EPWM_BNF_BK1SRC_Pos) /*!< EPWM_T::BNF: BK1SRC Mask */ 3759 3760 #define EPWM_FAILBRK_CSSBRKEN_Pos (0) /*!< EPWM_T::FAILBRK: CSSBRKEN Position */ 3761 #define EPWM_FAILBRK_CSSBRKEN_Msk (0x1ul << EPWM_FAILBRK_CSSBRKEN_Pos) /*!< EPWM_T::FAILBRK: CSSBRKEN Mask */ 3762 3763 #define EPWM_FAILBRK_BODBRKEN_Pos (1) /*!< EPWM_T::FAILBRK: BODBRKEN Position */ 3764 #define EPWM_FAILBRK_BODBRKEN_Msk (0x1ul << EPWM_FAILBRK_BODBRKEN_Pos) /*!< EPWM_T::FAILBRK: BODBRKEN Mask */ 3765 3766 #define EPWM_FAILBRK_RAMBRKEN_Pos (2) /*!< EPWM_T::FAILBRK: RAMBRKEN Position */ 3767 #define EPWM_FAILBRK_RAMBRKEN_Msk (0x1ul << EPWM_FAILBRK_RAMBRKEN_Pos) /*!< EPWM_T::FAILBRK: RAMBRKEN Mask */ 3768 3769 #define EPWM_FAILBRK_CORBRKEN_Pos (3) /*!< EPWM_T::FAILBRK: CORBRKEN Position */ 3770 #define EPWM_FAILBRK_CORBRKEN_Msk (0x1ul << EPWM_FAILBRK_CORBRKEN_Pos) /*!< EPWM_T::FAILBRK: CORBRKEN Mask */ 3771 3772 #define EPWM_BRKCTL0_1_CPO0EBEN_Pos (0) /*!< EPWM_T::BRKCTL0_1: CPO0EBEN Position */ 3773 #define EPWM_BRKCTL0_1_CPO0EBEN_Msk (0x1ul << EPWM_BRKCTL0_1_CPO0EBEN_Pos) /*!< EPWM_T::BRKCTL0_1: CPO0EBEN Mask */ 3774 3775 #define EPWM_BRKCTL0_1_CPO1EBEN_Pos (1) /*!< EPWM_T::BRKCTL0_1: CPO1EBEN Position */ 3776 #define EPWM_BRKCTL0_1_CPO1EBEN_Msk (0x1ul << EPWM_BRKCTL0_1_CPO1EBEN_Pos) /*!< EPWM_T::BRKCTL0_1: CPO1EBEN Mask */ 3777 3778 #define EPWM_BRKCTL0_1_CPO2EBEN_Pos (2) /*!< EPWM_T::BRKCTL0_1: CPO2EBEN Position */ 3779 #define EPWM_BRKCTL0_1_CPO2EBEN_Msk (0x1ul << EPWM_BRKCTL0_1_CPO2EBEN_Pos) /*!< EPWM_T::BRKCTL0_1: CPO2EBEN Mask */ 3780 3781 #define EPWM_BRKCTL0_1_CPO3EBEN_Pos (3) /*!< EPWM_T::BRKCTL0_1: CPO3EBEN Position */ 3782 #define EPWM_BRKCTL0_1_CPO3EBEN_Msk (0x1ul << EPWM_BRKCTL0_1_CPO3EBEN_Pos) /*!< EPWM_T::BRKCTL0_1: CPO3EBEN Mask */ 3783 3784 #define EPWM_BRKCTL0_1_BRKP0EEN_Pos (4) /*!< EPWM_T::BRKCTL0_1: BRKP0EEN Position */ 3785 #define EPWM_BRKCTL0_1_BRKP0EEN_Msk (0x1ul << EPWM_BRKCTL0_1_BRKP0EEN_Pos) /*!< EPWM_T::BRKCTL0_1: BRKP0EEN Mask */ 3786 3787 #define EPWM_BRKCTL0_1_BRKP1EEN_Pos (5) /*!< EPWM_T::BRKCTL0_1: BRKP1EEN Position */ 3788 #define EPWM_BRKCTL0_1_BRKP1EEN_Msk (0x1ul << EPWM_BRKCTL0_1_BRKP1EEN_Pos) /*!< EPWM_T::BRKCTL0_1: BRKP1EEN Mask */ 3789 3790 #define EPWM_BRKCTL0_1_SYSEBEN_Pos (7) /*!< EPWM_T::BRKCTL0_1: SYSEBEN Position */ 3791 #define EPWM_BRKCTL0_1_SYSEBEN_Msk (0x1ul << EPWM_BRKCTL0_1_SYSEBEN_Pos) /*!< EPWM_T::BRKCTL0_1: SYSEBEN Mask */ 3792 3793 #define EPWM_BRKCTL0_1_CPO0LBEN_Pos (8) /*!< EPWM_T::BRKCTL0_1: CPO0LBEN Position */ 3794 #define EPWM_BRKCTL0_1_CPO0LBEN_Msk (0x1ul << EPWM_BRKCTL0_1_CPO0LBEN_Pos) /*!< EPWM_T::BRKCTL0_1: CPO0LBEN Mask */ 3795 3796 #define EPWM_BRKCTL0_1_CPO1LBEN_Pos (9) /*!< EPWM_T::BRKCTL0_1: CPO1LBEN Position */ 3797 #define EPWM_BRKCTL0_1_CPO1LBEN_Msk (0x1ul << EPWM_BRKCTL0_1_CPO1LBEN_Pos) /*!< EPWM_T::BRKCTL0_1: CPO1LBEN Mask */ 3798 3799 #define EPWM_BRKCTL0_1_CPO2LBEN_Pos (10) /*!< EPWM_T::BRKCTL0_1: CPO2LBEN Position */ 3800 #define EPWM_BRKCTL0_1_CPO2LBEN_Msk (0x1ul << EPWM_BRKCTL0_1_CPO2LBEN_Pos) /*!< EPWM_T::BRKCTL0_1: CPO2LBEN Mask */ 3801 3802 #define EPWM_BRKCTL0_1_CPO3LBEN_Pos (11) /*!< EPWM_T::BRKCTL0_1: CPO3LBEN Position */ 3803 #define EPWM_BRKCTL0_1_CPO3LBEN_Msk (0x1ul << EPWM_BRKCTL0_1_CPO3LBEN_Pos) /*!< EPWM_T::BRKCTL0_1: CPO3LBEN Mask */ 3804 3805 #define EPWM_BRKCTL0_1_BRKP0LEN_Pos (12) /*!< EPWM_T::BRKCTL0_1: BRKP0LEN Position */ 3806 #define EPWM_BRKCTL0_1_BRKP0LEN_Msk (0x1ul << EPWM_BRKCTL0_1_BRKP0LEN_Pos) /*!< EPWM_T::BRKCTL0_1: BRKP0LEN Mask */ 3807 3808 #define EPWM_BRKCTL0_1_BRKP1LEN_Pos (13) /*!< EPWM_T::BRKCTL0_1: BRKP1LEN Position */ 3809 #define EPWM_BRKCTL0_1_BRKP1LEN_Msk (0x1ul << EPWM_BRKCTL0_1_BRKP1LEN_Pos) /*!< EPWM_T::BRKCTL0_1: BRKP1LEN Mask */ 3810 3811 #define EPWM_BRKCTL0_1_SYSLBEN_Pos (15) /*!< EPWM_T::BRKCTL0_1: SYSLBEN Position */ 3812 #define EPWM_BRKCTL0_1_SYSLBEN_Msk (0x1ul << EPWM_BRKCTL0_1_SYSLBEN_Pos) /*!< EPWM_T::BRKCTL0_1: SYSLBEN Mask */ 3813 3814 #define EPWM_BRKCTL0_1_BRKAEVEN_Pos (16) /*!< EPWM_T::BRKCTL0_1: BRKAEVEN Position */ 3815 #define EPWM_BRKCTL0_1_BRKAEVEN_Msk (0x3ul << EPWM_BRKCTL0_1_BRKAEVEN_Pos) /*!< EPWM_T::BRKCTL0_1: BRKAEVEN Mask */ 3816 3817 #define EPWM_BRKCTL0_1_BRKAODD_Pos (18) /*!< EPWM_T::BRKCTL0_1: BRKAODD Position */ 3818 #define EPWM_BRKCTL0_1_BRKAODD_Msk (0x3ul << EPWM_BRKCTL0_1_BRKAODD_Pos) /*!< EPWM_T::BRKCTL0_1: BRKAODD Mask */ 3819 3820 #define EPWM_BRKCTL0_1_EADC0EBEN_Pos (20) /*!< EPWM_T::BRKCTL0_1: EADC0EBEN Position */ 3821 #define EPWM_BRKCTL0_1_EADC0EBEN_Msk (0x1ul << EPWM_BRKCTL0_1_EADC0EBEN_Pos) /*!< EPWM_T::BRKCTL0_1: EADC0EBEN Mask */ 3822 3823 #define EPWM_BRKCTL0_1_EADC1EBEN_Pos (21) /*!< EPWM_T::BRKCTL0_1: EADC1EBEN Position */ 3824 #define EPWM_BRKCTL0_1_EADC1EBEN_Msk (0x1ul << EPWM_BRKCTL0_1_EADC1EBEN_Pos) /*!< EPWM_T::BRKCTL0_1: EADC1EBEN Mask */ 3825 3826 #define EPWM_BRKCTL0_1_EADC2EBEN_Pos (22) /*!< EPWM_T::BRKCTL0_1: EADC2EBEN Position */ 3827 #define EPWM_BRKCTL0_1_EADC2EBEN_Msk (0x1ul << EPWM_BRKCTL0_1_EADC2EBEN_Pos) /*!< EPWM_T::BRKCTL0_1: EADC2EBEN Mask */ 3828 3829 #define EPWM_BRKCTL0_1_EADC0LBEN_Pos (28) /*!< EPWM_T::BRKCTL0_1: EADC0LBEN Position */ 3830 #define EPWM_BRKCTL0_1_EADC0LBEN_Msk (0x1ul << EPWM_BRKCTL0_1_EADC0LBEN_Pos) /*!< EPWM_T::BRKCTL0_1: EADC0LBEN Mask */ 3831 3832 #define EPWM_BRKCTL0_1_EADC1LBEN_Pos (29) /*!< EPWM_T::BRKCTL0_1: EADC1LBEN Position */ 3833 #define EPWM_BRKCTL0_1_EADC1LBEN_Msk (0x1ul << EPWM_BRKCTL0_1_EADC1LBEN_Pos) /*!< EPWM_T::BRKCTL0_1: EADC1LBEN Mask */ 3834 3835 #define EPWM_BRKCTL0_1_EADC2LBEN_Pos (30) /*!< EPWM_T::BRKCTL0_1: EADC2LBEN Position */ 3836 #define EPWM_BRKCTL0_1_EADC2LBEN_Msk (0x1ul << EPWM_BRKCTL0_1_EADC2LBEN_Pos) /*!< EPWM_T::BRKCTL0_1: EADC2LBEN Mask */ 3837 3838 #define EPWM_BRKCTL2_3_CPO0EBEN_Pos (0) /*!< EPWM_T::BRKCTL2_3: CPO0EBEN Position */ 3839 #define EPWM_BRKCTL2_3_CPO0EBEN_Msk (0x1ul << EPWM_BRKCTL2_3_CPO0EBEN_Pos) /*!< EPWM_T::BRKCTL2_3: CPO0EBEN Mask */ 3840 3841 #define EPWM_BRKCTL2_3_CPO1EBEN_Pos (1) /*!< EPWM_T::BRKCTL2_3: CPO1EBEN Position */ 3842 #define EPWM_BRKCTL2_3_CPO1EBEN_Msk (0x1ul << EPWM_BRKCTL2_3_CPO1EBEN_Pos) /*!< EPWM_T::BRKCTL2_3: CPO1EBEN Mask */ 3843 3844 #define EPWM_BRKCTL2_3_CPO2EBEN_Pos (2) /*!< EPWM_T::BRKCTL2_3: CPO2EBEN Position */ 3845 #define EPWM_BRKCTL2_3_CPO2EBEN_Msk (0x1ul << EPWM_BRKCTL2_3_CPO2EBEN_Pos) /*!< EPWM_T::BRKCTL2_3: CPO2EBEN Mask */ 3846 3847 #define EPWM_BRKCTL2_3_CPO3EBEN_Pos (3) /*!< EPWM_T::BRKCTL2_3: CPO3EBEN Position */ 3848 #define EPWM_BRKCTL2_3_CPO3EBEN_Msk (0x1ul << EPWM_BRKCTL2_3_CPO3EBEN_Pos) /*!< EPWM_T::BRKCTL2_3: CPO3EBEN Mask */ 3849 3850 #define EPWM_BRKCTL2_3_BRKP0EEN_Pos (4) /*!< EPWM_T::BRKCTL2_3: BRKP0EEN Position */ 3851 #define EPWM_BRKCTL2_3_BRKP0EEN_Msk (0x1ul << EPWM_BRKCTL2_3_BRKP0EEN_Pos) /*!< EPWM_T::BRKCTL2_3: BRKP0EEN Mask */ 3852 3853 #define EPWM_BRKCTL2_3_BRKP1EEN_Pos (5) /*!< EPWM_T::BRKCTL2_3: BRKP1EEN Position */ 3854 #define EPWM_BRKCTL2_3_BRKP1EEN_Msk (0x1ul << EPWM_BRKCTL2_3_BRKP1EEN_Pos) /*!< EPWM_T::BRKCTL2_3: BRKP1EEN Mask */ 3855 3856 #define EPWM_BRKCTL2_3_SYSEBEN_Pos (7) /*!< EPWM_T::BRKCTL2_3: SYSEBEN Position */ 3857 #define EPWM_BRKCTL2_3_SYSEBEN_Msk (0x1ul << EPWM_BRKCTL2_3_SYSEBEN_Pos) /*!< EPWM_T::BRKCTL2_3: SYSEBEN Mask */ 3858 3859 #define EPWM_BRKCTL2_3_CPO0LBEN_Pos (8) /*!< EPWM_T::BRKCTL2_3: CPO0LBEN Position */ 3860 #define EPWM_BRKCTL2_3_CPO0LBEN_Msk (0x1ul << EPWM_BRKCTL2_3_CPO0LBEN_Pos) /*!< EPWM_T::BRKCTL2_3: CPO0LBEN Mask */ 3861 3862 #define EPWM_BRKCTL2_3_CPO1LBEN_Pos (9) /*!< EPWM_T::BRKCTL2_3: CPO1LBEN Position */ 3863 #define EPWM_BRKCTL2_3_CPO1LBEN_Msk (0x1ul << EPWM_BRKCTL2_3_CPO1LBEN_Pos) /*!< EPWM_T::BRKCTL2_3: CPO1LBEN Mask */ 3864 3865 #define EPWM_BRKCTL2_3_CPO2LBEN_Pos (10) /*!< EPWM_T::BRKCTL2_3: CPO2LBEN Position */ 3866 #define EPWM_BRKCTL2_3_CPO2LBEN_Msk (0x1ul << EPWM_BRKCTL2_3_CPO2LBEN_Pos) /*!< EPWM_T::BRKCTL2_3: CPO2LBEN Mask */ 3867 3868 #define EPWM_BRKCTL2_3_CPO3LBEN_Pos (11) /*!< EPWM_T::BRKCTL2_3: CPO3LBEN Position */ 3869 #define EPWM_BRKCTL2_3_CPO3LBEN_Msk (0x1ul << EPWM_BRKCTL2_3_CPO3LBEN_Pos) /*!< EPWM_T::BRKCTL2_3: CPO3LBEN Mask */ 3870 3871 #define EPWM_BRKCTL2_3_BRKP0LEN_Pos (12) /*!< EPWM_T::BRKCTL2_3: BRKP0LEN Position */ 3872 #define EPWM_BRKCTL2_3_BRKP0LEN_Msk (0x1ul << EPWM_BRKCTL2_3_BRKP0LEN_Pos) /*!< EPWM_T::BRKCTL2_3: BRKP0LEN Mask */ 3873 3874 #define EPWM_BRKCTL2_3_BRKP1LEN_Pos (13) /*!< EPWM_T::BRKCTL2_3: BRKP1LEN Position */ 3875 #define EPWM_BRKCTL2_3_BRKP1LEN_Msk (0x1ul << EPWM_BRKCTL2_3_BRKP1LEN_Pos) /*!< EPWM_T::BRKCTL2_3: BRKP1LEN Mask */ 3876 3877 #define EPWM_BRKCTL2_3_SYSLBEN_Pos (15) /*!< EPWM_T::BRKCTL2_3: SYSLBEN Position */ 3878 #define EPWM_BRKCTL2_3_SYSLBEN_Msk (0x1ul << EPWM_BRKCTL2_3_SYSLBEN_Pos) /*!< EPWM_T::BRKCTL2_3: SYSLBEN Mask */ 3879 3880 #define EPWM_BRKCTL2_3_BRKAEVEN_Pos (16) /*!< EPWM_T::BRKCTL2_3: BRKAEVEN Position */ 3881 #define EPWM_BRKCTL2_3_BRKAEVEN_Msk (0x3ul << EPWM_BRKCTL2_3_BRKAEVEN_Pos) /*!< EPWM_T::BRKCTL2_3: BRKAEVEN Mask */ 3882 3883 #define EPWM_BRKCTL2_3_BRKAODD_Pos (18) /*!< EPWM_T::BRKCTL2_3: BRKAODD Position */ 3884 #define EPWM_BRKCTL2_3_BRKAODD_Msk (0x3ul << EPWM_BRKCTL2_3_BRKAODD_Pos) /*!< EPWM_T::BRKCTL2_3: BRKAODD Mask */ 3885 3886 #define EPWM_BRKCTL2_3_EADC0EBEN_Pos (20) /*!< EPWM_T::BRKCTL2_3: EADC0EBEN Position */ 3887 #define EPWM_BRKCTL2_3_EADC0EBEN_Msk (0x1ul << EPWM_BRKCTL2_3_EADC0EBEN_Pos) /*!< EPWM_T::BRKCTL2_3: EADC0EBEN Mask */ 3888 3889 #define EPWM_BRKCTL2_3_EADC1EBEN_Pos (21) /*!< EPWM_T::BRKCTL2_3: EADC1EBEN Position */ 3890 #define EPWM_BRKCTL2_3_EADC1EBEN_Msk (0x1ul << EPWM_BRKCTL2_3_EADC1EBEN_Pos) /*!< EPWM_T::BRKCTL2_3: EADC1EBEN Mask */ 3891 3892 #define EPWM_BRKCTL2_3_EADC2EBEN_Pos (22) /*!< EPWM_T::BRKCTL2_3: EADC2EBEN Position */ 3893 #define EPWM_BRKCTL2_3_EADC2EBEN_Msk (0x1ul << EPWM_BRKCTL2_3_EADC2EBEN_Pos) /*!< EPWM_T::BRKCTL2_3: EADC2EBEN Mask */ 3894 3895 #define EPWM_BRKCTL2_3_EADC0LBEN_Pos (28) /*!< EPWM_T::BRKCTL2_3: EADC0LBEN Position */ 3896 #define EPWM_BRKCTL2_3_EADC0LBEN_Msk (0x1ul << EPWM_BRKCTL2_3_EADC0LBEN_Pos) /*!< EPWM_T::BRKCTL2_3: EADC0LBEN Mask */ 3897 3898 #define EPWM_BRKCTL2_3_EADC1LBEN_Pos (29) /*!< EPWM_T::BRKCTL2_3: EADC1LBEN Position */ 3899 #define EPWM_BRKCTL2_3_EADC1LBEN_Msk (0x1ul << EPWM_BRKCTL2_3_EADC1LBEN_Pos) /*!< EPWM_T::BRKCTL2_3: EADC1LBEN Mask */ 3900 3901 #define EPWM_BRKCTL2_3_EADC2LBEN_Pos (30) /*!< EPWM_T::BRKCTL2_3: EADC2LBEN Position */ 3902 #define EPWM_BRKCTL2_3_EADC2LBEN_Msk (0x1ul << EPWM_BRKCTL2_3_EADC2LBEN_Pos) /*!< EPWM_T::BRKCTL2_3: EADC2LBEN Mask */ 3903 3904 #define EPWM_BRKCTL4_5_CPO0EBEN_Pos (0) /*!< EPWM_T::BRKCTL4_5: CPO0EBEN Position */ 3905 #define EPWM_BRKCTL4_5_CPO0EBEN_Msk (0x1ul << EPWM_BRKCTL4_5_CPO0EBEN_Pos) /*!< EPWM_T::BRKCTL4_5: CPO0EBEN Mask */ 3906 3907 #define EPWM_BRKCTL4_5_CPO1EBEN_Pos (1) /*!< EPWM_T::BRKCTL4_5: CPO1EBEN Position */ 3908 #define EPWM_BRKCTL4_5_CPO1EBEN_Msk (0x1ul << EPWM_BRKCTL4_5_CPO1EBEN_Pos) /*!< EPWM_T::BRKCTL4_5: CPO1EBEN Mask */ 3909 3910 #define EPWM_BRKCTL4_5_CPO2EBEN_Pos (2) /*!< EPWM_T::BRKCTL4_5: CPO2EBEN Position */ 3911 #define EPWM_BRKCTL4_5_CPO2EBEN_Msk (0x1ul << EPWM_BRKCTL4_5_CPO2EBEN_Pos) /*!< EPWM_T::BRKCTL4_5: CPO2EBEN Mask */ 3912 3913 #define EPWM_BRKCTL4_5_CPO3EBEN_Pos (3) /*!< EPWM_T::BRKCTL4_5: CPO3EBEN Position */ 3914 #define EPWM_BRKCTL4_5_CPO3EBEN_Msk (0x1ul << EPWM_BRKCTL4_5_CPO3EBEN_Pos) /*!< EPWM_T::BRKCTL4_5: CPO3EBEN Mask */ 3915 3916 #define EPWM_BRKCTL4_5_BRKP0EEN_Pos (4) /*!< EPWM_T::BRKCTL4_5: BRKP0EEN Position */ 3917 #define EPWM_BRKCTL4_5_BRKP0EEN_Msk (0x1ul << EPWM_BRKCTL4_5_BRKP0EEN_Pos) /*!< EPWM_T::BRKCTL4_5: BRKP0EEN Mask */ 3918 3919 #define EPWM_BRKCTL4_5_BRKP1EEN_Pos (5) /*!< EPWM_T::BRKCTL4_5: BRKP1EEN Position */ 3920 #define EPWM_BRKCTL4_5_BRKP1EEN_Msk (0x1ul << EPWM_BRKCTL4_5_BRKP1EEN_Pos) /*!< EPWM_T::BRKCTL4_5: BRKP1EEN Mask */ 3921 3922 #define EPWM_BRKCTL4_5_SYSEBEN_Pos (7) /*!< EPWM_T::BRKCTL4_5: SYSEBEN Position */ 3923 #define EPWM_BRKCTL4_5_SYSEBEN_Msk (0x1ul << EPWM_BRKCTL4_5_SYSEBEN_Pos) /*!< EPWM_T::BRKCTL4_5: SYSEBEN Mask */ 3924 3925 #define EPWM_BRKCTL4_5_CPO0LBEN_Pos (8) /*!< EPWM_T::BRKCTL4_5: CPO0LBEN Position */ 3926 #define EPWM_BRKCTL4_5_CPO0LBEN_Msk (0x1ul << EPWM_BRKCTL4_5_CPO0LBEN_Pos) /*!< EPWM_T::BRKCTL4_5: CPO0LBEN Mask */ 3927 3928 #define EPWM_BRKCTL4_5_CPO1LBEN_Pos (9) /*!< EPWM_T::BRKCTL4_5: CPO1LBEN Position */ 3929 #define EPWM_BRKCTL4_5_CPO1LBEN_Msk (0x1ul << EPWM_BRKCTL4_5_CPO1LBEN_Pos) /*!< EPWM_T::BRKCTL4_5: CPO1LBEN Mask */ 3930 3931 #define EPWM_BRKCTL4_5_CPO2LBEN_Pos (10) /*!< EPWM_T::BRKCTL4_5: CPO2LBEN Position */ 3932 #define EPWM_BRKCTL4_5_CPO2LBEN_Msk (0x1ul << EPWM_BRKCTL4_5_CPO2LBEN_Pos) /*!< EPWM_T::BRKCTL4_5: CPO2LBEN Mask */ 3933 3934 #define EPWM_BRKCTL4_5_CPO3LBEN_Pos (11) /*!< EPWM_T::BRKCTL4_5: CPO3LBEN Position */ 3935 #define EPWM_BRKCTL4_5_CPO3LBEN_Msk (0x1ul << EPWM_BRKCTL4_5_CPO3LBEN_Pos) /*!< EPWM_T::BRKCTL4_5: CPO3LBEN Mask */ 3936 3937 #define EPWM_BRKCTL4_5_BRKP0LEN_Pos (12) /*!< EPWM_T::BRKCTL4_5: BRKP0LEN Position */ 3938 #define EPWM_BRKCTL4_5_BRKP0LEN_Msk (0x1ul << EPWM_BRKCTL4_5_BRKP0LEN_Pos) /*!< EPWM_T::BRKCTL4_5: BRKP0LEN Mask */ 3939 3940 #define EPWM_BRKCTL4_5_BRKP1LEN_Pos (13) /*!< EPWM_T::BRKCTL4_5: BRKP1LEN Position */ 3941 #define EPWM_BRKCTL4_5_BRKP1LEN_Msk (0x1ul << EPWM_BRKCTL4_5_BRKP1LEN_Pos) /*!< EPWM_T::BRKCTL4_5: BRKP1LEN Mask */ 3942 3943 #define EPWM_BRKCTL4_5_SYSLBEN_Pos (15) /*!< EPWM_T::BRKCTL4_5: SYSLBEN Position */ 3944 #define EPWM_BRKCTL4_5_SYSLBEN_Msk (0x1ul << EPWM_BRKCTL4_5_SYSLBEN_Pos) /*!< EPWM_T::BRKCTL4_5: SYSLBEN Mask */ 3945 3946 #define EPWM_BRKCTL4_5_BRKAEVEN_Pos (16) /*!< EPWM_T::BRKCTL4_5: BRKAEVEN Position */ 3947 #define EPWM_BRKCTL4_5_BRKAEVEN_Msk (0x3ul << EPWM_BRKCTL4_5_BRKAEVEN_Pos) /*!< EPWM_T::BRKCTL4_5: BRKAEVEN Mask */ 3948 3949 #define EPWM_BRKCTL4_5_BRKAODD_Pos (18) /*!< EPWM_T::BRKCTL4_5: BRKAODD Position */ 3950 #define EPWM_BRKCTL4_5_BRKAODD_Msk (0x3ul << EPWM_BRKCTL4_5_BRKAODD_Pos) /*!< EPWM_T::BRKCTL4_5: BRKAODD Mask */ 3951 3952 #define EPWM_BRKCTL4_5_EADC0EBEN_Pos (20) /*!< EPWM_T::BRKCTL4_5: EADC0EBEN Position */ 3953 #define EPWM_BRKCTL4_5_EADC0EBEN_Msk (0x1ul << EPWM_BRKCTL4_5_EADC0EBEN_Pos) /*!< EPWM_T::BRKCTL4_5: EADC0EBEN Mask */ 3954 3955 #define EPWM_BRKCTL4_5_EADC1EBEN_Pos (21) /*!< EPWM_T::BRKCTL4_5: EADC1EBEN Position */ 3956 #define EPWM_BRKCTL4_5_EADC1EBEN_Msk (0x1ul << EPWM_BRKCTL4_5_EADC1EBEN_Pos) /*!< EPWM_T::BRKCTL4_5: EADC1EBEN Mask */ 3957 3958 #define EPWM_BRKCTL4_5_EADC2EBEN_Pos (22) /*!< EPWM_T::BRKCTL4_5: EADC2EBEN Position */ 3959 #define EPWM_BRKCTL4_5_EADC2EBEN_Msk (0x1ul << EPWM_BRKCTL4_5_EADC2EBEN_Pos) /*!< EPWM_T::BRKCTL4_5: EADC2EBEN Mask */ 3960 3961 #define EPWM_BRKCTL4_5_EADC0LBEN_Pos (28) /*!< EPWM_T::BRKCTL4_5: EADC0LBEN Position */ 3962 #define EPWM_BRKCTL4_5_EADC0LBEN_Msk (0x1ul << EPWM_BRKCTL4_5_EADC0LBEN_Pos) /*!< EPWM_T::BRKCTL4_5: EADC0LBEN Mask */ 3963 3964 #define EPWM_BRKCTL4_5_EADC1LBEN_Pos (29) /*!< EPWM_T::BRKCTL4_5: EADC1LBEN Position */ 3965 #define EPWM_BRKCTL4_5_EADC1LBEN_Msk (0x1ul << EPWM_BRKCTL4_5_EADC1LBEN_Pos) /*!< EPWM_T::BRKCTL4_5: EADC1LBEN Mask */ 3966 3967 #define EPWM_BRKCTL4_5_EADC2LBEN_Pos (30) /*!< EPWM_T::BRKCTL4_5: EADC2LBEN Position */ 3968 #define EPWM_BRKCTL4_5_EADC2LBEN_Msk (0x1ul << EPWM_BRKCTL4_5_EADC2LBEN_Pos) /*!< EPWM_T::BRKCTL4_5: EADC2LBEN Mask */ 3969 3970 #define EPWM_POLCTL_PINV0_Pos (0) /*!< EPWM_T::POLCTL: PINV0 Position */ 3971 #define EPWM_POLCTL_PINV0_Msk (0x1ul << EPWM_POLCTL_PINV0_Pos) /*!< EPWM_T::POLCTL: PINV0 Mask */ 3972 3973 #define EPWM_POLCTL_PINV1_Pos (1) /*!< EPWM_T::POLCTL: PINV1 Position */ 3974 #define EPWM_POLCTL_PINV1_Msk (0x1ul << EPWM_POLCTL_PINV1_Pos) /*!< EPWM_T::POLCTL: PINV1 Mask */ 3975 3976 #define EPWM_POLCTL_PINV2_Pos (2) /*!< EPWM_T::POLCTL: PINV2 Position */ 3977 #define EPWM_POLCTL_PINV2_Msk (0x1ul << EPWM_POLCTL_PINV2_Pos) /*!< EPWM_T::POLCTL: PINV2 Mask */ 3978 3979 #define EPWM_POLCTL_PINV3_Pos (3) /*!< EPWM_T::POLCTL: PINV3 Position */ 3980 #define EPWM_POLCTL_PINV3_Msk (0x1ul << EPWM_POLCTL_PINV3_Pos) /*!< EPWM_T::POLCTL: PINV3 Mask */ 3981 3982 #define EPWM_POLCTL_PINV4_Pos (4) /*!< EPWM_T::POLCTL: PINV4 Position */ 3983 #define EPWM_POLCTL_PINV4_Msk (0x1ul << EPWM_POLCTL_PINV4_Pos) /*!< EPWM_T::POLCTL: PINV4 Mask */ 3984 3985 #define EPWM_POLCTL_PINV5_Pos (5) /*!< EPWM_T::POLCTL: PINV5 Position */ 3986 #define EPWM_POLCTL_PINV5_Msk (0x1ul << EPWM_POLCTL_PINV5_Pos) /*!< EPWM_T::POLCTL: PINV5 Mask */ 3987 3988 #define EPWM_POEN_POEN0_Pos (0) /*!< EPWM_T::POEN: POEN0 Position */ 3989 #define EPWM_POEN_POEN0_Msk (0x1ul << EPWM_POEN_POEN0_Pos) /*!< EPWM_T::POEN: POEN0 Mask */ 3990 3991 #define EPWM_POEN_POEN1_Pos (1) /*!< EPWM_T::POEN: POEN1 Position */ 3992 #define EPWM_POEN_POEN1_Msk (0x1ul << EPWM_POEN_POEN1_Pos) /*!< EPWM_T::POEN: POEN1 Mask */ 3993 3994 #define EPWM_POEN_POEN2_Pos (2) /*!< EPWM_T::POEN: POEN2 Position */ 3995 #define EPWM_POEN_POEN2_Msk (0x1ul << EPWM_POEN_POEN2_Pos) /*!< EPWM_T::POEN: POEN2 Mask */ 3996 3997 #define EPWM_POEN_POEN3_Pos (3) /*!< EPWM_T::POEN: POEN3 Position */ 3998 #define EPWM_POEN_POEN3_Msk (0x1ul << EPWM_POEN_POEN3_Pos) /*!< EPWM_T::POEN: POEN3 Mask */ 3999 4000 #define EPWM_POEN_POEN4_Pos (4) /*!< EPWM_T::POEN: POEN4 Position */ 4001 #define EPWM_POEN_POEN4_Msk (0x1ul << EPWM_POEN_POEN4_Pos) /*!< EPWM_T::POEN: POEN4 Mask */ 4002 4003 #define EPWM_POEN_POEN5_Pos (5) /*!< EPWM_T::POEN: POEN5 Position */ 4004 #define EPWM_POEN_POEN5_Msk (0x1ul << EPWM_POEN_POEN5_Pos) /*!< EPWM_T::POEN: POEN5 Mask */ 4005 4006 #define EPWM_SWBRK_BRKETRG0_Pos (0) /*!< EPWM_T::SWBRK: BRKETRG0 Position */ 4007 #define EPWM_SWBRK_BRKETRG0_Msk (0x1ul << EPWM_SWBRK_BRKETRG0_Pos) /*!< EPWM_T::SWBRK: BRKETRG0 Mask */ 4008 4009 #define EPWM_SWBRK_BRKETRG2_Pos (1) /*!< EPWM_T::SWBRK: BRKETRG2 Position */ 4010 #define EPWM_SWBRK_BRKETRG2_Msk (0x1ul << EPWM_SWBRK_BRKETRG2_Pos) /*!< EPWM_T::SWBRK: BRKETRG2 Mask */ 4011 4012 #define EPWM_SWBRK_BRKETRG4_Pos (2) /*!< EPWM_T::SWBRK: BRKETRG4 Position */ 4013 #define EPWM_SWBRK_BRKETRG4_Msk (0x1ul << EPWM_SWBRK_BRKETRG4_Pos) /*!< EPWM_T::SWBRK: BRKETRG4 Mask */ 4014 4015 #define EPWM_SWBRK_BRKLTRG0_Pos (8) /*!< EPWM_T::SWBRK: BRKLTRG0 Position */ 4016 #define EPWM_SWBRK_BRKLTRG0_Msk (0x1ul << EPWM_SWBRK_BRKLTRG0_Pos) /*!< EPWM_T::SWBRK: BRKLTRG0 Mask */ 4017 4018 #define EPWM_SWBRK_BRKLTRG2_Pos (9) /*!< EPWM_T::SWBRK: BRKLTRG2 Position */ 4019 #define EPWM_SWBRK_BRKLTRG2_Msk (0x1ul << EPWM_SWBRK_BRKLTRG2_Pos) /*!< EPWM_T::SWBRK: BRKLTRG2 Mask */ 4020 4021 #define EPWM_SWBRK_BRKLTRG4_Pos (10) /*!< EPWM_T::SWBRK: BRKLTRG4 Position */ 4022 #define EPWM_SWBRK_BRKLTRG4_Msk (0x1ul << EPWM_SWBRK_BRKLTRG4_Pos) /*!< EPWM_T::SWBRK: BRKLTRG4 Mask */ 4023 4024 #define EPWM_INTEN0_ZIEN0_Pos (0) /*!< EPWM_T::INTEN0: ZIEN0 Position */ 4025 #define EPWM_INTEN0_ZIEN0_Msk (0x1ul << EPWM_INTEN0_ZIEN0_Pos) /*!< EPWM_T::INTEN0: ZIEN0 Mask */ 4026 4027 #define EPWM_INTEN0_ZIEN1_Pos (1) /*!< EPWM_T::INTEN0: ZIEN1 Position */ 4028 #define EPWM_INTEN0_ZIEN1_Msk (0x1ul << EPWM_INTEN0_ZIEN1_Pos) /*!< EPWM_T::INTEN0: ZIEN1 Mask */ 4029 4030 #define EPWM_INTEN0_ZIEN2_Pos (2) /*!< EPWM_T::INTEN0: ZIEN2 Position */ 4031 #define EPWM_INTEN0_ZIEN2_Msk (0x1ul << EPWM_INTEN0_ZIEN2_Pos) /*!< EPWM_T::INTEN0: ZIEN2 Mask */ 4032 4033 #define EPWM_INTEN0_ZIEN3_Pos (3) /*!< EPWM_T::INTEN0: ZIEN3 Position */ 4034 #define EPWM_INTEN0_ZIEN3_Msk (0x1ul << EPWM_INTEN0_ZIEN3_Pos) /*!< EPWM_T::INTEN0: ZIEN3 Mask */ 4035 4036 #define EPWM_INTEN0_ZIEN4_Pos (4) /*!< EPWM_T::INTEN0: ZIEN4 Position */ 4037 #define EPWM_INTEN0_ZIEN4_Msk (0x1ul << EPWM_INTEN0_ZIEN4_Pos) /*!< EPWM_T::INTEN0: ZIEN4 Mask */ 4038 4039 #define EPWM_INTEN0_ZIEN5_Pos (5) /*!< EPWM_T::INTEN0: ZIEN5 Position */ 4040 #define EPWM_INTEN0_ZIEN5_Msk (0x1ul << EPWM_INTEN0_ZIEN5_Pos) /*!< EPWM_T::INTEN0: ZIEN5 Mask */ 4041 4042 #define EPWM_INTEN0_PIEN0_Pos (8) /*!< EPWM_T::INTEN0: PIEN0 Position */ 4043 #define EPWM_INTEN0_PIEN0_Msk (0x1ul << EPWM_INTEN0_PIEN0_Pos) /*!< EPWM_T::INTEN0: PIEN0 Mask */ 4044 4045 #define EPWM_INTEN0_PIEN1_Pos (9) /*!< EPWM_T::INTEN0: PIEN1 Position */ 4046 #define EPWM_INTEN0_PIEN1_Msk (0x1ul << EPWM_INTEN0_PIEN1_Pos) /*!< EPWM_T::INTEN0: PIEN1 Mask */ 4047 4048 #define EPWM_INTEN0_PIEN2_Pos (10) /*!< EPWM_T::INTEN0: PIEN2 Position */ 4049 #define EPWM_INTEN0_PIEN2_Msk (0x1ul << EPWM_INTEN0_PIEN2_Pos) /*!< EPWM_T::INTEN0: PIEN2 Mask */ 4050 4051 #define EPWM_INTEN0_PIEN3_Pos (11) /*!< EPWM_T::INTEN0: PIEN3 Position */ 4052 #define EPWM_INTEN0_PIEN3_Msk (0x1ul << EPWM_INTEN0_PIEN3_Pos) /*!< EPWM_T::INTEN0: PIEN3 Mask */ 4053 4054 #define EPWM_INTEN0_PIEN4_Pos (12) /*!< EPWM_T::INTEN0: PIEN4 Position */ 4055 #define EPWM_INTEN0_PIEN4_Msk (0x1ul << EPWM_INTEN0_PIEN4_Pos) /*!< EPWM_T::INTEN0: PIEN4 Mask */ 4056 4057 #define EPWM_INTEN0_PIEN5_Pos (13) /*!< EPWM_T::INTEN0: PIEN5 Position */ 4058 #define EPWM_INTEN0_PIEN5_Msk (0x1ul << EPWM_INTEN0_PIEN5_Pos) /*!< EPWM_T::INTEN0: PIEN5 Mask */ 4059 4060 #define EPWM_INTEN0_CMPUIEN0_Pos (16) /*!< EPWM_T::INTEN0: CMPUIEN0 Position */ 4061 #define EPWM_INTEN0_CMPUIEN0_Msk (0x1ul << EPWM_INTEN0_CMPUIEN0_Pos) /*!< EPWM_T::INTEN0: CMPUIEN0 Mask */ 4062 4063 #define EPWM_INTEN0_CMPUIEN1_Pos (17) /*!< EPWM_T::INTEN0: CMPUIEN1 Position */ 4064 #define EPWM_INTEN0_CMPUIEN1_Msk (0x1ul << EPWM_INTEN0_CMPUIEN1_Pos) /*!< EPWM_T::INTEN0: CMPUIEN1 Mask */ 4065 4066 #define EPWM_INTEN0_CMPUIEN2_Pos (18) /*!< EPWM_T::INTEN0: CMPUIEN2 Position */ 4067 #define EPWM_INTEN0_CMPUIEN2_Msk (0x1ul << EPWM_INTEN0_CMPUIEN2_Pos) /*!< EPWM_T::INTEN0: CMPUIEN2 Mask */ 4068 4069 #define EPWM_INTEN0_CMPUIEN3_Pos (19) /*!< EPWM_T::INTEN0: CMPUIEN3 Position */ 4070 #define EPWM_INTEN0_CMPUIEN3_Msk (0x1ul << EPWM_INTEN0_CMPUIEN3_Pos) /*!< EPWM_T::INTEN0: CMPUIEN3 Mask */ 4071 4072 #define EPWM_INTEN0_CMPUIEN4_Pos (20) /*!< EPWM_T::INTEN0: CMPUIEN4 Position */ 4073 #define EPWM_INTEN0_CMPUIEN4_Msk (0x1ul << EPWM_INTEN0_CMPUIEN4_Pos) /*!< EPWM_T::INTEN0: CMPUIEN4 Mask */ 4074 4075 #define EPWM_INTEN0_CMPUIEN5_Pos (21) /*!< EPWM_T::INTEN0: CMPUIEN5 Position */ 4076 #define EPWM_INTEN0_CMPUIEN5_Msk (0x1ul << EPWM_INTEN0_CMPUIEN5_Pos) /*!< EPWM_T::INTEN0: CMPUIEN5 Mask */ 4077 4078 #define EPWM_INTEN0_CMPDIEN0_Pos (24) /*!< EPWM_T::INTEN0: CMPDIEN0 Position */ 4079 #define EPWM_INTEN0_CMPDIEN0_Msk (0x1ul << EPWM_INTEN0_CMPDIEN0_Pos) /*!< EPWM_T::INTEN0: CMPDIEN0 Mask */ 4080 4081 #define EPWM_INTEN0_CMPDIEN1_Pos (25) /*!< EPWM_T::INTEN0: CMPDIEN1 Position */ 4082 #define EPWM_INTEN0_CMPDIEN1_Msk (0x1ul << EPWM_INTEN0_CMPDIEN1_Pos) /*!< EPWM_T::INTEN0: CMPDIEN1 Mask */ 4083 4084 #define EPWM_INTEN0_CMPDIEN2_Pos (26) /*!< EPWM_T::INTEN0: CMPDIEN2 Position */ 4085 #define EPWM_INTEN0_CMPDIEN2_Msk (0x1ul << EPWM_INTEN0_CMPDIEN2_Pos) /*!< EPWM_T::INTEN0: CMPDIEN2 Mask */ 4086 4087 #define EPWM_INTEN0_CMPDIEN3_Pos (27) /*!< EPWM_T::INTEN0: CMPDIEN3 Position */ 4088 #define EPWM_INTEN0_CMPDIEN3_Msk (0x1ul << EPWM_INTEN0_CMPDIEN3_Pos) /*!< EPWM_T::INTEN0: CMPDIEN3 Mask */ 4089 4090 #define EPWM_INTEN0_CMPDIEN4_Pos (28) /*!< EPWM_T::INTEN0: CMPDIEN4 Position */ 4091 #define EPWM_INTEN0_CMPDIEN4_Msk (0x1ul << EPWM_INTEN0_CMPDIEN4_Pos) /*!< EPWM_T::INTEN0: CMPDIEN4 Mask */ 4092 4093 #define EPWM_INTEN0_CMPDIEN5_Pos (29) /*!< EPWM_T::INTEN0: CMPDIEN5 Position */ 4094 #define EPWM_INTEN0_CMPDIEN5_Msk (0x1ul << EPWM_INTEN0_CMPDIEN5_Pos) /*!< EPWM_T::INTEN0: CMPDIEN5 Mask */ 4095 4096 #define EPWM_INTEN1_BRKEIEN0_1_Pos (0) /*!< EPWM_T::INTEN1: BRKEIEN0_1 Position */ 4097 #define EPWM_INTEN1_BRKEIEN0_1_Msk (0x1ul << EPWM_INTEN1_BRKEIEN0_1_Pos) /*!< EPWM_T::INTEN1: BRKEIEN0_1 Mask */ 4098 4099 #define EPWM_INTEN1_BRKEIEN2_3_Pos (1) /*!< EPWM_T::INTEN1: BRKEIEN2_3 Position */ 4100 #define EPWM_INTEN1_BRKEIEN2_3_Msk (0x1ul << EPWM_INTEN1_BRKEIEN2_3_Pos) /*!< EPWM_T::INTEN1: BRKEIEN2_3 Mask */ 4101 4102 #define EPWM_INTEN1_BRKEIEN4_5_Pos (2) /*!< EPWM_T::INTEN1: BRKEIEN4_5 Position */ 4103 #define EPWM_INTEN1_BRKEIEN4_5_Msk (0x1ul << EPWM_INTEN1_BRKEIEN4_5_Pos) /*!< EPWM_T::INTEN1: BRKEIEN4_5 Mask */ 4104 4105 #define EPWM_INTEN1_BRKLIEN0_1_Pos (8) /*!< EPWM_T::INTEN1: BRKLIEN0_1 Position */ 4106 #define EPWM_INTEN1_BRKLIEN0_1_Msk (0x1ul << EPWM_INTEN1_BRKLIEN0_1_Pos) /*!< EPWM_T::INTEN1: BRKLIEN0_1 Mask */ 4107 4108 #define EPWM_INTEN1_BRKLIEN2_3_Pos (9) /*!< EPWM_T::INTEN1: BRKLIEN2_3 Position */ 4109 #define EPWM_INTEN1_BRKLIEN2_3_Msk (0x1ul << EPWM_INTEN1_BRKLIEN2_3_Pos) /*!< EPWM_T::INTEN1: BRKLIEN2_3 Mask */ 4110 4111 #define EPWM_INTEN1_BRKLIEN4_5_Pos (10) /*!< EPWM_T::INTEN1: BRKLIEN4_5 Position */ 4112 #define EPWM_INTEN1_BRKLIEN4_5_Msk (0x1ul << EPWM_INTEN1_BRKLIEN4_5_Pos) /*!< EPWM_T::INTEN1: BRKLIEN4_5 Mask */ 4113 4114 #define EPWM_INTSTS0_ZIF0_Pos (0) /*!< EPWM_T::INTSTS0: ZIF0 Position */ 4115 #define EPWM_INTSTS0_ZIF0_Msk (0x1ul << EPWM_INTSTS0_ZIF0_Pos) /*!< EPWM_T::INTSTS0: ZIF0 Mask */ 4116 4117 #define EPWM_INTSTS0_ZIF1_Pos (1) /*!< EPWM_T::INTSTS0: ZIF1 Position */ 4118 #define EPWM_INTSTS0_ZIF1_Msk (0x1ul << EPWM_INTSTS0_ZIF1_Pos) /*!< EPWM_T::INTSTS0: ZIF1 Mask */ 4119 4120 #define EPWM_INTSTS0_ZIF2_Pos (2) /*!< EPWM_T::INTSTS0: ZIF2 Position */ 4121 #define EPWM_INTSTS0_ZIF2_Msk (0x1ul << EPWM_INTSTS0_ZIF2_Pos) /*!< EPWM_T::INTSTS0: ZIF2 Mask */ 4122 4123 #define EPWM_INTSTS0_ZIF3_Pos (3) /*!< EPWM_T::INTSTS0: ZIF3 Position */ 4124 #define EPWM_INTSTS0_ZIF3_Msk (0x1ul << EPWM_INTSTS0_ZIF3_Pos) /*!< EPWM_T::INTSTS0: ZIF3 Mask */ 4125 4126 #define EPWM_INTSTS0_ZIF4_Pos (4) /*!< EPWM_T::INTSTS0: ZIF4 Position */ 4127 #define EPWM_INTSTS0_ZIF4_Msk (0x1ul << EPWM_INTSTS0_ZIF4_Pos) /*!< EPWM_T::INTSTS0: ZIF4 Mask */ 4128 4129 #define EPWM_INTSTS0_ZIF5_Pos (5) /*!< EPWM_T::INTSTS0: ZIF5 Position */ 4130 #define EPWM_INTSTS0_ZIF5_Msk (0x1ul << EPWM_INTSTS0_ZIF5_Pos) /*!< EPWM_T::INTSTS0: ZIF5 Mask */ 4131 4132 #define EPWM_INTSTS0_PIF0_Pos (8) /*!< EPWM_T::INTSTS0: PIF0 Position */ 4133 #define EPWM_INTSTS0_PIF0_Msk (0x1ul << EPWM_INTSTS0_PIF0_Pos) /*!< EPWM_T::INTSTS0: PIF0 Mask */ 4134 4135 #define EPWM_INTSTS0_PIF1_Pos (9) /*!< EPWM_T::INTSTS0: PIF1 Position */ 4136 #define EPWM_INTSTS0_PIF1_Msk (0x1ul << EPWM_INTSTS0_PIF1_Pos) /*!< EPWM_T::INTSTS0: PIF1 Mask */ 4137 4138 #define EPWM_INTSTS0_PIF2_Pos (10) /*!< EPWM_T::INTSTS0: PIF2 Position */ 4139 #define EPWM_INTSTS0_PIF2_Msk (0x1ul << EPWM_INTSTS0_PIF2_Pos) /*!< EPWM_T::INTSTS0: PIF2 Mask */ 4140 4141 #define EPWM_INTSTS0_PIF3_Pos (11) /*!< EPWM_T::INTSTS0: PIF3 Position */ 4142 #define EPWM_INTSTS0_PIF3_Msk (0x1ul << EPWM_INTSTS0_PIF3_Pos) /*!< EPWM_T::INTSTS0: PIF3 Mask */ 4143 4144 #define EPWM_INTSTS0_PIF4_Pos (12) /*!< EPWM_T::INTSTS0: PIF4 Position */ 4145 #define EPWM_INTSTS0_PIF4_Msk (0x1ul << EPWM_INTSTS0_PIF4_Pos) /*!< EPWM_T::INTSTS0: PIF4 Mask */ 4146 4147 #define EPWM_INTSTS0_PIF5_Pos (13) /*!< EPWM_T::INTSTS0: PIF5 Position */ 4148 #define EPWM_INTSTS0_PIF5_Msk (0x1ul << EPWM_INTSTS0_PIF5_Pos) /*!< EPWM_T::INTSTS0: PIF5 Mask */ 4149 4150 #define EPWM_INTSTS0_CMPUIF0_Pos (16) /*!< EPWM_T::INTSTS0: CMPUIF0 Position */ 4151 #define EPWM_INTSTS0_CMPUIF0_Msk (0x1ul << EPWM_INTSTS0_CMPUIF0_Pos) /*!< EPWM_T::INTSTS0: CMPUIF0 Mask */ 4152 4153 #define EPWM_INTSTS0_CMPUIF1_Pos (17) /*!< EPWM_T::INTSTS0: CMPUIF1 Position */ 4154 #define EPWM_INTSTS0_CMPUIF1_Msk (0x1ul << EPWM_INTSTS0_CMPUIF1_Pos) /*!< EPWM_T::INTSTS0: CMPUIF1 Mask */ 4155 4156 #define EPWM_INTSTS0_CMPUIF2_Pos (18) /*!< EPWM_T::INTSTS0: CMPUIF2 Position */ 4157 #define EPWM_INTSTS0_CMPUIF2_Msk (0x1ul << EPWM_INTSTS0_CMPUIF2_Pos) /*!< EPWM_T::INTSTS0: CMPUIF2 Mask */ 4158 4159 #define EPWM_INTSTS0_CMPUIF3_Pos (19) /*!< EPWM_T::INTSTS0: CMPUIF3 Position */ 4160 #define EPWM_INTSTS0_CMPUIF3_Msk (0x1ul << EPWM_INTSTS0_CMPUIF3_Pos) /*!< EPWM_T::INTSTS0: CMPUIF3 Mask */ 4161 4162 #define EPWM_INTSTS0_CMPUIF4_Pos (20) /*!< EPWM_T::INTSTS0: CMPUIF4 Position */ 4163 #define EPWM_INTSTS0_CMPUIF4_Msk (0x1ul << EPWM_INTSTS0_CMPUIF4_Pos) /*!< EPWM_T::INTSTS0: CMPUIF4 Mask */ 4164 4165 #define EPWM_INTSTS0_CMPUIF5_Pos (21) /*!< EPWM_T::INTSTS0: CMPUIF5 Position */ 4166 #define EPWM_INTSTS0_CMPUIF5_Msk (0x1ul << EPWM_INTSTS0_CMPUIF5_Pos) /*!< EPWM_T::INTSTS0: CMPUIF5 Mask */ 4167 4168 #define EPWM_INTSTS0_CMPDIF0_Pos (24) /*!< EPWM_T::INTSTS0: CMPDIF0 Position */ 4169 #define EPWM_INTSTS0_CMPDIF0_Msk (0x1ul << EPWM_INTSTS0_CMPDIF0_Pos) /*!< EPWM_T::INTSTS0: CMPDIF0 Mask */ 4170 4171 #define EPWM_INTSTS0_CMPDIF1_Pos (25) /*!< EPWM_T::INTSTS0: CMPDIF1 Position */ 4172 #define EPWM_INTSTS0_CMPDIF1_Msk (0x1ul << EPWM_INTSTS0_CMPDIF1_Pos) /*!< EPWM_T::INTSTS0: CMPDIF1 Mask */ 4173 4174 #define EPWM_INTSTS0_CMPDIF2_Pos (26) /*!< EPWM_T::INTSTS0: CMPDIF2 Position */ 4175 #define EPWM_INTSTS0_CMPDIF2_Msk (0x1ul << EPWM_INTSTS0_CMPDIF2_Pos) /*!< EPWM_T::INTSTS0: CMPDIF2 Mask */ 4176 4177 #define EPWM_INTSTS0_CMPDIF3_Pos (27) /*!< EPWM_T::INTSTS0: CMPDIF3 Position */ 4178 #define EPWM_INTSTS0_CMPDIF3_Msk (0x1ul << EPWM_INTSTS0_CMPDIF3_Pos) /*!< EPWM_T::INTSTS0: CMPDIF3 Mask */ 4179 4180 #define EPWM_INTSTS0_CMPDIF4_Pos (28) /*!< EPWM_T::INTSTS0: CMPDIF4 Position */ 4181 #define EPWM_INTSTS0_CMPDIF4_Msk (0x1ul << EPWM_INTSTS0_CMPDIF4_Pos) /*!< EPWM_T::INTSTS0: CMPDIF4 Mask */ 4182 4183 #define EPWM_INTSTS0_CMPDIF5_Pos (29) /*!< EPWM_T::INTSTS0: CMPDIF5 Position */ 4184 #define EPWM_INTSTS0_CMPDIF5_Msk (0x1ul << EPWM_INTSTS0_CMPDIF5_Pos) /*!< EPWM_T::INTSTS0: CMPDIF5 Mask */ 4185 4186 #define EPWM_INTSTS1_BRKEIF0_Pos (0) /*!< EPWM_T::INTSTS1: BRKEIF0 Position */ 4187 #define EPWM_INTSTS1_BRKEIF0_Msk (0x1ul << EPWM_INTSTS1_BRKEIF0_Pos) /*!< EPWM_T::INTSTS1: BRKEIF0 Mask */ 4188 4189 #define EPWM_INTSTS1_BRKEIF1_Pos (1) /*!< EPWM_T::INTSTS1: BRKEIF1 Position */ 4190 #define EPWM_INTSTS1_BRKEIF1_Msk (0x1ul << EPWM_INTSTS1_BRKEIF1_Pos) /*!< EPWM_T::INTSTS1: BRKEIF1 Mask */ 4191 4192 #define EPWM_INTSTS1_BRKEIF2_Pos (2) /*!< EPWM_T::INTSTS1: BRKEIF2 Position */ 4193 #define EPWM_INTSTS1_BRKEIF2_Msk (0x1ul << EPWM_INTSTS1_BRKEIF2_Pos) /*!< EPWM_T::INTSTS1: BRKEIF2 Mask */ 4194 4195 #define EPWM_INTSTS1_BRKEIF3_Pos (3) /*!< EPWM_T::INTSTS1: BRKEIF3 Position */ 4196 #define EPWM_INTSTS1_BRKEIF3_Msk (0x1ul << EPWM_INTSTS1_BRKEIF3_Pos) /*!< EPWM_T::INTSTS1: BRKEIF3 Mask */ 4197 4198 #define EPWM_INTSTS1_BRKEIF4_Pos (4) /*!< EPWM_T::INTSTS1: BRKEIF4 Position */ 4199 #define EPWM_INTSTS1_BRKEIF4_Msk (0x1ul << EPWM_INTSTS1_BRKEIF4_Pos) /*!< EPWM_T::INTSTS1: BRKEIF4 Mask */ 4200 4201 #define EPWM_INTSTS1_BRKEIF5_Pos (5) /*!< EPWM_T::INTSTS1: BRKEIF5 Position */ 4202 #define EPWM_INTSTS1_BRKEIF5_Msk (0x1ul << EPWM_INTSTS1_BRKEIF5_Pos) /*!< EPWM_T::INTSTS1: BRKEIF5 Mask */ 4203 4204 #define EPWM_INTSTS1_BRKLIF0_Pos (8) /*!< EPWM_T::INTSTS1: BRKLIF0 Position */ 4205 #define EPWM_INTSTS1_BRKLIF0_Msk (0x1ul << EPWM_INTSTS1_BRKLIF0_Pos) /*!< EPWM_T::INTSTS1: BRKLIF0 Mask */ 4206 4207 #define EPWM_INTSTS1_BRKLIF1_Pos (9) /*!< EPWM_T::INTSTS1: BRKLIF1 Position */ 4208 #define EPWM_INTSTS1_BRKLIF1_Msk (0x1ul << EPWM_INTSTS1_BRKLIF1_Pos) /*!< EPWM_T::INTSTS1: BRKLIF1 Mask */ 4209 4210 #define EPWM_INTSTS1_BRKLIF2_Pos (10) /*!< EPWM_T::INTSTS1: BRKLIF2 Position */ 4211 #define EPWM_INTSTS1_BRKLIF2_Msk (0x1ul << EPWM_INTSTS1_BRKLIF2_Pos) /*!< EPWM_T::INTSTS1: BRKLIF2 Mask */ 4212 4213 #define EPWM_INTSTS1_BRKLIF3_Pos (11) /*!< EPWM_T::INTSTS1: BRKLIF3 Position */ 4214 #define EPWM_INTSTS1_BRKLIF3_Msk (0x1ul << EPWM_INTSTS1_BRKLIF3_Pos) /*!< EPWM_T::INTSTS1: BRKLIF3 Mask */ 4215 4216 #define EPWM_INTSTS1_BRKLIF4_Pos (12) /*!< EPWM_T::INTSTS1: BRKLIF4 Position */ 4217 #define EPWM_INTSTS1_BRKLIF4_Msk (0x1ul << EPWM_INTSTS1_BRKLIF4_Pos) /*!< EPWM_T::INTSTS1: BRKLIF4 Mask */ 4218 4219 #define EPWM_INTSTS1_BRKLIF5_Pos (13) /*!< EPWM_T::INTSTS1: BRKLIF5 Position */ 4220 #define EPWM_INTSTS1_BRKLIF5_Msk (0x1ul << EPWM_INTSTS1_BRKLIF5_Pos) /*!< EPWM_T::INTSTS1: BRKLIF5 Mask */ 4221 4222 #define EPWM_INTSTS1_BRKESTS0_Pos (16) /*!< EPWM_T::INTSTS1: BRKESTS0 Position */ 4223 #define EPWM_INTSTS1_BRKESTS0_Msk (0x1ul << EPWM_INTSTS1_BRKESTS0_Pos) /*!< EPWM_T::INTSTS1: BRKESTS0 Mask */ 4224 4225 #define EPWM_INTSTS1_BRKESTS1_Pos (17) /*!< EPWM_T::INTSTS1: BRKESTS1 Position */ 4226 #define EPWM_INTSTS1_BRKESTS1_Msk (0x1ul << EPWM_INTSTS1_BRKESTS1_Pos) /*!< EPWM_T::INTSTS1: BRKESTS1 Mask */ 4227 4228 #define EPWM_INTSTS1_BRKESTS2_Pos (18) /*!< EPWM_T::INTSTS1: BRKESTS2 Position */ 4229 #define EPWM_INTSTS1_BRKESTS2_Msk (0x1ul << EPWM_INTSTS1_BRKESTS2_Pos) /*!< EPWM_T::INTSTS1: BRKESTS2 Mask */ 4230 4231 #define EPWM_INTSTS1_BRKESTS3_Pos (19) /*!< EPWM_T::INTSTS1: BRKESTS3 Position */ 4232 #define EPWM_INTSTS1_BRKESTS3_Msk (0x1ul << EPWM_INTSTS1_BRKESTS3_Pos) /*!< EPWM_T::INTSTS1: BRKESTS3 Mask */ 4233 4234 #define EPWM_INTSTS1_BRKESTS4_Pos (20) /*!< EPWM_T::INTSTS1: BRKESTS4 Position */ 4235 #define EPWM_INTSTS1_BRKESTS4_Msk (0x1ul << EPWM_INTSTS1_BRKESTS4_Pos) /*!< EPWM_T::INTSTS1: BRKESTS4 Mask */ 4236 4237 #define EPWM_INTSTS1_BRKESTS5_Pos (21) /*!< EPWM_T::INTSTS1: BRKESTS5 Position */ 4238 #define EPWM_INTSTS1_BRKESTS5_Msk (0x1ul << EPWM_INTSTS1_BRKESTS5_Pos) /*!< EPWM_T::INTSTS1: BRKESTS5 Mask */ 4239 4240 #define EPWM_INTSTS1_BRKLSTS0_Pos (24) /*!< EPWM_T::INTSTS1: BRKLSTS0 Position */ 4241 #define EPWM_INTSTS1_BRKLSTS0_Msk (0x1ul << EPWM_INTSTS1_BRKLSTS0_Pos) /*!< EPWM_T::INTSTS1: BRKLSTS0 Mask */ 4242 4243 #define EPWM_INTSTS1_BRKLSTS1_Pos (25) /*!< EPWM_T::INTSTS1: BRKLSTS1 Position */ 4244 #define EPWM_INTSTS1_BRKLSTS1_Msk (0x1ul << EPWM_INTSTS1_BRKLSTS1_Pos) /*!< EPWM_T::INTSTS1: BRKLSTS1 Mask */ 4245 4246 #define EPWM_INTSTS1_BRKLSTS2_Pos (26) /*!< EPWM_T::INTSTS1: BRKLSTS2 Position */ 4247 #define EPWM_INTSTS1_BRKLSTS2_Msk (0x1ul << EPWM_INTSTS1_BRKLSTS2_Pos) /*!< EPWM_T::INTSTS1: BRKLSTS2 Mask */ 4248 4249 #define EPWM_INTSTS1_BRKLSTS3_Pos (27) /*!< EPWM_T::INTSTS1: BRKLSTS3 Position */ 4250 #define EPWM_INTSTS1_BRKLSTS3_Msk (0x1ul << EPWM_INTSTS1_BRKLSTS3_Pos) /*!< EPWM_T::INTSTS1: BRKLSTS3 Mask */ 4251 4252 #define EPWM_INTSTS1_BRKLSTS4_Pos (28) /*!< EPWM_T::INTSTS1: BRKLSTS4 Position */ 4253 #define EPWM_INTSTS1_BRKLSTS4_Msk (0x1ul << EPWM_INTSTS1_BRKLSTS4_Pos) /*!< EPWM_T::INTSTS1: BRKLSTS4 Mask */ 4254 4255 #define EPWM_INTSTS1_BRKLSTS5_Pos (29) /*!< EPWM_T::INTSTS1: BRKLSTS5 Position */ 4256 #define EPWM_INTSTS1_BRKLSTS5_Msk (0x1ul << EPWM_INTSTS1_BRKLSTS5_Pos) /*!< EPWM_T::INTSTS1: BRKLSTS5 Mask */ 4257 4258 #define EPWM_DACTRGEN_ZTE0_Pos (0) /*!< EPWM_T::DACTRGEN: ZTE0 Position */ 4259 #define EPWM_DACTRGEN_ZTE0_Msk (0x1ul << EPWM_DACTRGEN_ZTE0_Pos) /*!< EPWM_T::DACTRGEN: ZTE0 Mask */ 4260 4261 #define EPWM_DACTRGEN_ZTE1_Pos (1) /*!< EPWM_T::DACTRGEN: ZTE1 Position */ 4262 #define EPWM_DACTRGEN_ZTE1_Msk (0x1ul << EPWM_DACTRGEN_ZTE1_Pos) /*!< EPWM_T::DACTRGEN: ZTE1 Mask */ 4263 4264 #define EPWM_DACTRGEN_ZTE2_Pos (2) /*!< EPWM_T::DACTRGEN: ZTE2 Position */ 4265 #define EPWM_DACTRGEN_ZTE2_Msk (0x1ul << EPWM_DACTRGEN_ZTE2_Pos) /*!< EPWM_T::DACTRGEN: ZTE2 Mask */ 4266 4267 #define EPWM_DACTRGEN_ZTE3_Pos (3) /*!< EPWM_T::DACTRGEN: ZTE3 Position */ 4268 #define EPWM_DACTRGEN_ZTE3_Msk (0x1ul << EPWM_DACTRGEN_ZTE3_Pos) /*!< EPWM_T::DACTRGEN: ZTE3 Mask */ 4269 4270 #define EPWM_DACTRGEN_ZTE4_Pos (4) /*!< EPWM_T::DACTRGEN: ZTE4 Position */ 4271 #define EPWM_DACTRGEN_ZTE4_Msk (0x1ul << EPWM_DACTRGEN_ZTE4_Pos) /*!< EPWM_T::DACTRGEN: ZTE4 Mask */ 4272 4273 #define EPWM_DACTRGEN_ZTE5_Pos (5) /*!< EPWM_T::DACTRGEN: ZTE5 Position */ 4274 #define EPWM_DACTRGEN_ZTE5_Msk (0x1ul << EPWM_DACTRGEN_ZTE5_Pos) /*!< EPWM_T::DACTRGEN: ZTE5 Mask */ 4275 4276 #define EPWM_DACTRGEN_PTE0_Pos (8) /*!< EPWM_T::DACTRGEN: PTE0 Position */ 4277 #define EPWM_DACTRGEN_PTE0_Msk (0x1ul << EPWM_DACTRGEN_PTE0_Pos) /*!< EPWM_T::DACTRGEN: PTE0 Mask */ 4278 4279 #define EPWM_DACTRGEN_PTE1_Pos (9) /*!< EPWM_T::DACTRGEN: PTE1 Position */ 4280 #define EPWM_DACTRGEN_PTE1_Msk (0x1ul << EPWM_DACTRGEN_PTE1_Pos) /*!< EPWM_T::DACTRGEN: PTE1 Mask */ 4281 4282 #define EPWM_DACTRGEN_PTE2_Pos (10) /*!< EPWM_T::DACTRGEN: PTE2 Position */ 4283 #define EPWM_DACTRGEN_PTE2_Msk (0x1ul << EPWM_DACTRGEN_PTE2_Pos) /*!< EPWM_T::DACTRGEN: PTE2 Mask */ 4284 4285 #define EPWM_DACTRGEN_PTE3_Pos (11) /*!< EPWM_T::DACTRGEN: PTE3 Position */ 4286 #define EPWM_DACTRGEN_PTE3_Msk (0x1ul << EPWM_DACTRGEN_PTE3_Pos) /*!< EPWM_T::DACTRGEN: PTE3 Mask */ 4287 4288 #define EPWM_DACTRGEN_PTE4_Pos (12) /*!< EPWM_T::DACTRGEN: PTE4 Position */ 4289 #define EPWM_DACTRGEN_PTE4_Msk (0x1ul << EPWM_DACTRGEN_PTE4_Pos) /*!< EPWM_T::DACTRGEN: PTE4 Mask */ 4290 4291 #define EPWM_DACTRGEN_PTE5_Pos (13) /*!< EPWM_T::DACTRGEN: PTE5 Position */ 4292 #define EPWM_DACTRGEN_PTE5_Msk (0x1ul << EPWM_DACTRGEN_PTE5_Pos) /*!< EPWM_T::DACTRGEN: PTE5 Mask */ 4293 4294 #define EPWM_DACTRGEN_CUTRGEN0_Pos (16) /*!< EPWM_T::DACTRGEN: CUTRGEN0 Position */ 4295 #define EPWM_DACTRGEN_CUTRGEN0_Msk (0x1ul << EPWM_DACTRGEN_CUTRGEN0_Pos) /*!< EPWM_T::DACTRGEN: CUTRGEN0 Mask */ 4296 4297 #define EPWM_DACTRGEN_CUTRGEN1_Pos (17) /*!< EPWM_T::DACTRGEN: CUTRGEN1 Position */ 4298 #define EPWM_DACTRGEN_CUTRGEN1_Msk (0x1ul << EPWM_DACTRGEN_CUTRGEN1_Pos) /*!< EPWM_T::DACTRGEN: CUTRGEN1 Mask */ 4299 4300 #define EPWM_DACTRGEN_CUTRGEN2_Pos (18) /*!< EPWM_T::DACTRGEN: CUTRGEN2 Position */ 4301 #define EPWM_DACTRGEN_CUTRGEN2_Msk (0x1ul << EPWM_DACTRGEN_CUTRGEN2_Pos) /*!< EPWM_T::DACTRGEN: CUTRGEN2 Mask */ 4302 4303 #define EPWM_DACTRGEN_CUTRGEN3_Pos (19) /*!< EPWM_T::DACTRGEN: CUTRGEN3 Position */ 4304 #define EPWM_DACTRGEN_CUTRGEN3_Msk (0x1ul << EPWM_DACTRGEN_CUTRGEN3_Pos) /*!< EPWM_T::DACTRGEN: CUTRGEN3 Mask */ 4305 4306 #define EPWM_DACTRGEN_CUTRGEN4_Pos (20) /*!< EPWM_T::DACTRGEN: CUTRGEN4 Position */ 4307 #define EPWM_DACTRGEN_CUTRGEN4_Msk (0x1ul << EPWM_DACTRGEN_CUTRGEN4_Pos) /*!< EPWM_T::DACTRGEN: CUTRGEN4 Mask */ 4308 4309 #define EPWM_DACTRGEN_CUTRGEN5_Pos (21) /*!< EPWM_T::DACTRGEN: CUTRGEN5 Position */ 4310 #define EPWM_DACTRGEN_CUTRGEN5_Msk (0x1ul << EPWM_DACTRGEN_CUTRGEN5_Pos) /*!< EPWM_T::DACTRGEN: CUTRGEN5 Mask */ 4311 4312 #define EPWM_DACTRGEN_CDTRGEN0_Pos (24) /*!< EPWM_T::DACTRGEN: CDTRGEN0 Position */ 4313 #define EPWM_DACTRGEN_CDTRGEN0_Msk (0x1ul << EPWM_DACTRGEN_CDTRGEN0_Pos) /*!< EPWM_T::DACTRGEN: CDTRGEN0 Mask */ 4314 4315 #define EPWM_DACTRGEN_CDTRGEN1_Pos (25) /*!< EPWM_T::DACTRGEN: CDTRGEN1 Position */ 4316 #define EPWM_DACTRGEN_CDTRGEN1_Msk (0x1ul << EPWM_DACTRGEN_CDTRGEN1_Pos) /*!< EPWM_T::DACTRGEN: CDTRGEN1 Mask */ 4317 4318 #define EPWM_DACTRGEN_CDTRGEN2_Pos (26) /*!< EPWM_T::DACTRGEN: CDTRGEN2 Position */ 4319 #define EPWM_DACTRGEN_CDTRGEN2_Msk (0x1ul << EPWM_DACTRGEN_CDTRGEN2_Pos) /*!< EPWM_T::DACTRGEN: CDTRGEN2 Mask */ 4320 4321 #define EPWM_DACTRGEN_CDTRGEN3_Pos (27) /*!< EPWM_T::DACTRGEN: CDTRGEN3 Position */ 4322 #define EPWM_DACTRGEN_CDTRGEN3_Msk (0x1ul << EPWM_DACTRGEN_CDTRGEN3_Pos) /*!< EPWM_T::DACTRGEN: CDTRGEN3 Mask */ 4323 4324 #define EPWM_DACTRGEN_CDTRGEN4_Pos (28) /*!< EPWM_T::DACTRGEN: CDTRGEN4 Position */ 4325 #define EPWM_DACTRGEN_CDTRGEN4_Msk (0x1ul << EPWM_DACTRGEN_CDTRGEN4_Pos) /*!< EPWM_T::DACTRGEN: CDTRGEN4 Mask */ 4326 4327 #define EPWM_DACTRGEN_CDTRGEN5_Pos (29) /*!< EPWM_T::DACTRGEN: CDTRGEN5 Position */ 4328 #define EPWM_DACTRGEN_CDTRGEN5_Msk (0x1ul << EPWM_DACTRGEN_CDTRGEN5_Pos) /*!< EPWM_T::DACTRGEN: CDTRGEN5 Mask */ 4329 4330 #define EPWM_EADCTS0_TRGSEL0_Pos (0) /*!< EPWM_T::EADCTS0: TRGSEL0 Position */ 4331 #define EPWM_EADCTS0_TRGSEL0_Msk (0x1ful << EPWM_EADCTS0_TRGSEL0_Pos) /*!< EPWM_T::EADCTS0: TRGSEL0 Mask */ 4332 4333 #define EPWM_EADCTS0_TRGEN0_Pos (7) /*!< EPWM_T::EADCTS0: TRGEN0 Position */ 4334 #define EPWM_EADCTS0_TRGEN0_Msk (0x1ul << EPWM_EADCTS0_TRGEN0_Pos) /*!< EPWM_T::EADCTS0: TRGEN0 Mask */ 4335 4336 #define EPWM_EADCTS0_TRGSEL1_Pos (8) /*!< EPWM_T::EADCTS0: TRGSEL1 Position */ 4337 #define EPWM_EADCTS0_TRGSEL1_Msk (0x1ful << EPWM_EADCTS0_TRGSEL1_Pos) /*!< EPWM_T::EADCTS0: TRGSEL1 Mask */ 4338 4339 #define EPWM_EADCTS0_TRGEN1_Pos (15) /*!< EPWM_T::EADCTS0: TRGEN1 Position */ 4340 #define EPWM_EADCTS0_TRGEN1_Msk (0x1ul << EPWM_EADCTS0_TRGEN1_Pos) /*!< EPWM_T::EADCTS0: TRGEN1 Mask */ 4341 4342 #define EPWM_EADCTS0_TRGSEL2_Pos (16) /*!< EPWM_T::EADCTS0: TRGSEL2 Position */ 4343 #define EPWM_EADCTS0_TRGSEL2_Msk (0x1ful << EPWM_EADCTS0_TRGSEL2_Pos) /*!< EPWM_T::EADCTS0: TRGSEL2 Mask */ 4344 4345 #define EPWM_EADCTS0_TRGEN2_Pos (23) /*!< EPWM_T::EADCTS0: TRGEN2 Position */ 4346 #define EPWM_EADCTS0_TRGEN2_Msk (0x1ul << EPWM_EADCTS0_TRGEN2_Pos) /*!< EPWM_T::EADCTS0: TRGEN2 Mask */ 4347 4348 #define EPWM_EADCTS0_TRGSEL3_Pos (24) /*!< EPWM_T::EADCTS0: TRGSEL3 Position */ 4349 #define EPWM_EADCTS0_TRGSEL3_Msk (0x1ful << EPWM_EADCTS0_TRGSEL3_Pos) /*!< EPWM_T::EADCTS0: TRGSEL3 Mask */ 4350 4351 #define EPWM_EADCTS0_TRGEN3_Pos (31) /*!< EPWM_T::EADCTS0: TRGEN3 Position */ 4352 #define EPWM_EADCTS0_TRGEN3_Msk (0x1ul << EPWM_EADCTS0_TRGEN3_Pos) /*!< EPWM_T::EADCTS0: TRGEN3 Mask */ 4353 4354 #define EPWM_EADCTS1_TRGSEL4_Pos (0) /*!< EPWM_T::EADCTS1: TRGSEL4 Position */ 4355 #define EPWM_EADCTS1_TRGSEL4_Msk (0x1ful << EPWM_EADCTS1_TRGSEL4_Pos) /*!< EPWM_T::EADCTS1: TRGSEL4 Mask */ 4356 4357 #define EPWM_EADCTS1_TRGEN4_Pos (7) /*!< EPWM_T::EADCTS1: TRGEN4 Position */ 4358 #define EPWM_EADCTS1_TRGEN4_Msk (0x1ul << EPWM_EADCTS1_TRGEN4_Pos) /*!< EPWM_T::EADCTS1: TRGEN4 Mask */ 4359 4360 #define EPWM_EADCTS1_TRGSEL5_Pos (8) /*!< EPWM_T::EADCTS1: TRGSEL5 Position */ 4361 #define EPWM_EADCTS1_TRGSEL5_Msk (0x1ful << EPWM_EADCTS1_TRGSEL5_Pos) /*!< EPWM_T::EADCTS1: TRGSEL5 Mask */ 4362 4363 #define EPWM_EADCTS1_TRGEN5_Pos (15) /*!< EPWM_T::EADCTS1: TRGEN5 Position */ 4364 #define EPWM_EADCTS1_TRGEN5_Msk (0x1ul << EPWM_EADCTS1_TRGEN5_Pos) /*!< EPWM_T::EADCTS1: TRGEN5 Mask */ 4365 4366 #define EPWM_FTCMPDAT0_1_FTCMP_Pos (0) /*!< EPWM_T::FTCMPDAT0_1: FTCMP Position */ 4367 #define EPWM_FTCMPDAT0_1_FTCMP_Msk (0xfffful << EPWM_FTCMPDAT0_1_FTCMP_Pos) /*!< EPWM_T::FTCMPDAT0_1: FTCMP Mask */ 4368 4369 #define EPWM_FTCMPDAT2_3_FTCMP_Pos (0) /*!< EPWM_T::FTCMPDAT2_3: FTCMP Position */ 4370 #define EPWM_FTCMPDAT2_3_FTCMP_Msk (0xfffful << EPWM_FTCMPDAT2_3_FTCMP_Pos) /*!< EPWM_T::FTCMPDAT2_3: FTCMP Mask */ 4371 4372 #define EPWM_FTCMPDAT4_5_FTCMP_Pos (0) /*!< EPWM_T::FTCMPDAT4_5: FTCMP Position */ 4373 #define EPWM_FTCMPDAT4_5_FTCMP_Msk (0xfffful << EPWM_FTCMPDAT4_5_FTCMP_Pos) /*!< EPWM_T::FTCMPDAT4_5: FTCMP Mask */ 4374 4375 #define EPWM_SSCTL_SSEN0_Pos (0) /*!< EPWM_T::SSCTL: SSEN0 Position */ 4376 #define EPWM_SSCTL_SSEN0_Msk (0x1ul << EPWM_SSCTL_SSEN0_Pos) /*!< EPWM_T::SSCTL: SSEN0 Mask */ 4377 4378 #define EPWM_SSCTL_SSEN1_Pos (1) /*!< EPWM_T::SSCTL: SSEN1 Position */ 4379 #define EPWM_SSCTL_SSEN1_Msk (0x1ul << EPWM_SSCTL_SSEN1_Pos) /*!< EPWM_T::SSCTL: SSEN1 Mask */ 4380 4381 #define EPWM_SSCTL_SSEN2_Pos (2) /*!< EPWM_T::SSCTL: SSEN2 Position */ 4382 #define EPWM_SSCTL_SSEN2_Msk (0x1ul << EPWM_SSCTL_SSEN2_Pos) /*!< EPWM_T::SSCTL: SSEN2 Mask */ 4383 4384 #define EPWM_SSCTL_SSEN3_Pos (3) /*!< EPWM_T::SSCTL: SSEN3 Position */ 4385 #define EPWM_SSCTL_SSEN3_Msk (0x1ul << EPWM_SSCTL_SSEN3_Pos) /*!< EPWM_T::SSCTL: SSEN3 Mask */ 4386 4387 #define EPWM_SSCTL_SSEN4_Pos (4) /*!< EPWM_T::SSCTL: SSEN4 Position */ 4388 #define EPWM_SSCTL_SSEN4_Msk (0x1ul << EPWM_SSCTL_SSEN4_Pos) /*!< EPWM_T::SSCTL: SSEN4 Mask */ 4389 4390 #define EPWM_SSCTL_SSEN5_Pos (5) /*!< EPWM_T::SSCTL: SSEN5 Position */ 4391 #define EPWM_SSCTL_SSEN5_Msk (0x1ul << EPWM_SSCTL_SSEN5_Pos) /*!< EPWM_T::SSCTL: SSEN5 Mask */ 4392 4393 #define EPWM_SSCTL_SSRC_Pos (8) /*!< EPWM_T::SSCTL: SSRC Position */ 4394 #define EPWM_SSCTL_SSRC_Msk (0x3ul << EPWM_SSCTL_SSRC_Pos) /*!< EPWM_T::SSCTL: SSRC Mask */ 4395 4396 #define EPWM_SSTRG_CNTSEN_Pos (0) /*!< EPWM_T::SSTRG: CNTSEN Position */ 4397 #define EPWM_SSTRG_CNTSEN_Msk (0x1ul << EPWM_SSTRG_CNTSEN_Pos) /*!< EPWM_T::SSTRG: CNTSEN Mask */ 4398 4399 #define EPWM_LEBCTL_LEBEN_Pos (0) /*!< EPWM_T::LEBCTL: LEBEN Position */ 4400 #define EPWM_LEBCTL_LEBEN_Msk (0x1ul << EPWM_LEBCTL_LEBEN_Pos) /*!< EPWM_T::LEBCTL: LEBEN Mask */ 4401 4402 #define EPWM_LEBCTL_SRCEN0_Pos (8) /*!< EPWM_T::LEBCTL: SRCEN0 Position */ 4403 #define EPWM_LEBCTL_SRCEN0_Msk (0x1ul << EPWM_LEBCTL_SRCEN0_Pos) /*!< EPWM_T::LEBCTL: SRCEN0 Mask */ 4404 4405 #define EPWM_LEBCTL_SRCEN2_Pos (9) /*!< EPWM_T::LEBCTL: SRCEN2 Position */ 4406 #define EPWM_LEBCTL_SRCEN2_Msk (0x1ul << EPWM_LEBCTL_SRCEN2_Pos) /*!< EPWM_T::LEBCTL: SRCEN2 Mask */ 4407 4408 #define EPWM_LEBCTL_SRCEN4_Pos (10) /*!< EPWM_T::LEBCTL: SRCEN4 Position */ 4409 #define EPWM_LEBCTL_SRCEN4_Msk (0x1ul << EPWM_LEBCTL_SRCEN4_Pos) /*!< EPWM_T::LEBCTL: SRCEN4 Mask */ 4410 4411 #define EPWM_LEBCTL_TRGTYPE_Pos (16) /*!< EPWM_T::LEBCTL: TRGTYPE Position */ 4412 #define EPWM_LEBCTL_TRGTYPE_Msk (0x3ul << EPWM_LEBCTL_TRGTYPE_Pos) /*!< EPWM_T::LEBCTL: TRGTYPE Mask */ 4413 4414 #define EPWM_LEBCNT_LEBCNT_Pos (0) /*!< EPWM_T::LEBCNT: LEBCNT Position */ 4415 #define EPWM_LEBCNT_LEBCNT_Msk (0x1fful << EPWM_LEBCNT_LEBCNT_Pos) /*!< EPWM_T::LEBCNT: LEBCNT Mask */ 4416 4417 #define EPWM_STATUS_CNTMAXF0_Pos (0) /*!< EPWM_T::STATUS: CNTMAXF0 Position */ 4418 #define EPWM_STATUS_CNTMAXF0_Msk (0x1ul << EPWM_STATUS_CNTMAXF0_Pos) /*!< EPWM_T::STATUS: CNTMAXF0 Mask */ 4419 4420 #define EPWM_STATUS_CNTMAXF1_Pos (1) /*!< EPWM_T::STATUS: CNTMAXF1 Position */ 4421 #define EPWM_STATUS_CNTMAXF1_Msk (0x1ul << EPWM_STATUS_CNTMAXF1_Pos) /*!< EPWM_T::STATUS: CNTMAXF1 Mask */ 4422 4423 #define EPWM_STATUS_CNTMAXF2_Pos (2) /*!< EPWM_T::STATUS: CNTMAXF2 Position */ 4424 #define EPWM_STATUS_CNTMAXF2_Msk (0x1ul << EPWM_STATUS_CNTMAXF2_Pos) /*!< EPWM_T::STATUS: CNTMAXF2 Mask */ 4425 4426 #define EPWM_STATUS_CNTMAXF3_Pos (3) /*!< EPWM_T::STATUS: CNTMAXF3 Position */ 4427 #define EPWM_STATUS_CNTMAXF3_Msk (0x1ul << EPWM_STATUS_CNTMAXF3_Pos) /*!< EPWM_T::STATUS: CNTMAXF3 Mask */ 4428 4429 #define EPWM_STATUS_CNTMAXF4_Pos (4) /*!< EPWM_T::STATUS: CNTMAXF4 Position */ 4430 #define EPWM_STATUS_CNTMAXF4_Msk (0x1ul << EPWM_STATUS_CNTMAXF4_Pos) /*!< EPWM_T::STATUS: CNTMAXF4 Mask */ 4431 4432 #define EPWM_STATUS_CNTMAXF5_Pos (5) /*!< EPWM_T::STATUS: CNTMAXF5 Position */ 4433 #define EPWM_STATUS_CNTMAXF5_Msk (0x1ul << EPWM_STATUS_CNTMAXF5_Pos) /*!< EPWM_T::STATUS: CNTMAXF5 Mask */ 4434 4435 #define EPWM_STATUS_SYNCINF0_Pos (8) /*!< EPWM_T::STATUS: SYNCINF0 Position */ 4436 #define EPWM_STATUS_SYNCINF0_Msk (0x1ul << EPWM_STATUS_SYNCINF0_Pos) /*!< EPWM_T::STATUS: SYNCINF0 Mask */ 4437 4438 #define EPWM_STATUS_SYNCINF2_Pos (9) /*!< EPWM_T::STATUS: SYNCINF2 Position */ 4439 #define EPWM_STATUS_SYNCINF2_Msk (0x1ul << EPWM_STATUS_SYNCINF2_Pos) /*!< EPWM_T::STATUS: SYNCINF2 Mask */ 4440 4441 #define EPWM_STATUS_SYNCINF4_Pos (10) /*!< EPWM_T::STATUS: SYNCINF4 Position */ 4442 #define EPWM_STATUS_SYNCINF4_Msk (0x1ul << EPWM_STATUS_SYNCINF4_Pos) /*!< EPWM_T::STATUS: SYNCINF4 Mask */ 4443 4444 #define EPWM_STATUS_EADCTRGF0_Pos (16) /*!< EPWM_T::STATUS: EADCTRGF0 Position */ 4445 #define EPWM_STATUS_EADCTRGF0_Msk (0x1ul << EPWM_STATUS_EADCTRGF0_Pos) /*!< EPWM_T::STATUS: EADCTRGF0 Mask */ 4446 4447 #define EPWM_STATUS_EADCTRGF1_Pos (17) /*!< EPWM_T::STATUS: EADCTRGF1 Position */ 4448 #define EPWM_STATUS_EADCTRGF1_Msk (0x1ul << EPWM_STATUS_EADCTRGF1_Pos) /*!< EPWM_T::STATUS: EADCTRGF1 Mask */ 4449 4450 #define EPWM_STATUS_EADCTRGF2_Pos (18) /*!< EPWM_T::STATUS: EADCTRGF2 Position */ 4451 #define EPWM_STATUS_EADCTRGF2_Msk (0x1ul << EPWM_STATUS_EADCTRGF2_Pos) /*!< EPWM_T::STATUS: EADCTRGF2 Mask */ 4452 4453 #define EPWM_STATUS_EADCTRGF3_Pos (19) /*!< EPWM_T::STATUS: EADCTRGF3 Position */ 4454 #define EPWM_STATUS_EADCTRGF3_Msk (0x1ul << EPWM_STATUS_EADCTRGF3_Pos) /*!< EPWM_T::STATUS: EADCTRGF3 Mask */ 4455 4456 #define EPWM_STATUS_EADCTRGF4_Pos (20) /*!< EPWM_T::STATUS: EADCTRGF4 Position */ 4457 #define EPWM_STATUS_EADCTRGF4_Msk (0x1ul << EPWM_STATUS_EADCTRGF4_Pos) /*!< EPWM_T::STATUS: EADCTRGF4 Mask */ 4458 4459 #define EPWM_STATUS_EADCTRGF5_Pos (21) /*!< EPWM_T::STATUS: EADCTRGF5 Position */ 4460 #define EPWM_STATUS_EADCTRGF5_Msk (0x1ul << EPWM_STATUS_EADCTRGF5_Pos) /*!< EPWM_T::STATUS: EADCTRGF5 Mask */ 4461 4462 #define EPWM_STATUS_DACTRGF_Pos (24) /*!< EPWM_T::STATUS: DACTRGF Position */ 4463 #define EPWM_STATUS_DACTRGF_Msk (0x1ul << EPWM_STATUS_DACTRGF_Pos) /*!< EPWM_T::STATUS: DACTRGF Mask */ 4464 4465 #define EPWM_IFA0_IFACNT_Pos (0) /*!< EPWM_T::IFA0: IFACNT Position */ 4466 #define EPWM_IFA0_IFACNT_Msk (0xfffful << EPWM_IFA0_IFACNT_Pos) /*!< EPWM_T::IFA0: IFACNT Mask */ 4467 4468 #define EPWM_IFA0_STPMOD_Pos (24) /*!< EPWM_T::IFA0: STPMOD Position */ 4469 #define EPWM_IFA0_STPMOD_Msk (0x1ul << EPWM_IFA0_STPMOD_Pos) /*!< EPWM_T::IFA0: STPMOD Mask */ 4470 4471 #define EPWM_IFA0_IFASEL_Pos (28) /*!< EPWM_T::IFA0: IFASEL Position */ 4472 #define EPWM_IFA0_IFASEL_Msk (0x3ul << EPWM_IFA0_IFASEL_Pos) /*!< EPWM_T::IFA0: IFASEL Mask */ 4473 4474 #define EPWM_IFA0_IFAEN_Pos (31) /*!< EPWM_T::IFA0: IFAEN Position */ 4475 #define EPWM_IFA0_IFAEN_Msk (0x1ul << EPWM_IFA0_IFAEN_Pos) /*!< EPWM_T::IFA0: IFAEN Mask */ 4476 4477 #define EPWM_IFA1_IFACNT_Pos (0) /*!< EPWM_T::IFA1: IFACNT Position */ 4478 #define EPWM_IFA1_IFACNT_Msk (0xfffful << EPWM_IFA1_IFACNT_Pos) /*!< EPWM_T::IFA1: IFACNT Mask */ 4479 4480 #define EPWM_IFA1_STPMOD_Pos (24) /*!< EPWM_T::IFA1: STPMOD Position */ 4481 #define EPWM_IFA1_STPMOD_Msk (0x1ul << EPWM_IFA1_STPMOD_Pos) /*!< EPWM_T::IFA1: STPMOD Mask */ 4482 4483 #define EPWM_IFA1_IFASEL_Pos (28) /*!< EPWM_T::IFA1: IFASEL Position */ 4484 #define EPWM_IFA1_IFASEL_Msk (0x3ul << EPWM_IFA1_IFASEL_Pos) /*!< EPWM_T::IFA1: IFASEL Mask */ 4485 4486 #define EPWM_IFA1_IFAEN_Pos (31) /*!< EPWM_T::IFA1: IFAEN Position */ 4487 #define EPWM_IFA1_IFAEN_Msk (0x1ul << EPWM_IFA1_IFAEN_Pos) /*!< EPWM_T::IFA1: IFAEN Mask */ 4488 4489 #define EPWM_IFA2_IFACNT_Pos (0) /*!< EPWM_T::IFA2: IFACNT Position */ 4490 #define EPWM_IFA2_IFACNT_Msk (0xfffful << EPWM_IFA2_IFACNT_Pos) /*!< EPWM_T::IFA2: IFACNT Mask */ 4491 4492 #define EPWM_IFA2_STPMOD_Pos (24) /*!< EPWM_T::IFA2: STPMOD Position */ 4493 #define EPWM_IFA2_STPMOD_Msk (0x1ul << EPWM_IFA2_STPMOD_Pos) /*!< EPWM_T::IFA2: STPMOD Mask */ 4494 4495 #define EPWM_IFA2_IFASEL_Pos (28) /*!< EPWM_T::IFA2: IFASEL Position */ 4496 #define EPWM_IFA2_IFASEL_Msk (0x3ul << EPWM_IFA2_IFASEL_Pos) /*!< EPWM_T::IFA2: IFASEL Mask */ 4497 4498 #define EPWM_IFA2_IFAEN_Pos (31) /*!< EPWM_T::IFA2: IFAEN Position */ 4499 #define EPWM_IFA2_IFAEN_Msk (0x1ul << EPWM_IFA2_IFAEN_Pos) /*!< EPWM_T::IFA2: IFAEN Mask */ 4500 4501 #define EPWM_IFA3_IFACNT_Pos (0) /*!< EPWM_T::IFA3: IFACNT Position */ 4502 #define EPWM_IFA3_IFACNT_Msk (0xfffful << EPWM_IFA3_IFACNT_Pos) /*!< EPWM_T::IFA3: IFACNT Mask */ 4503 4504 #define EPWM_IFA3_STPMOD_Pos (24) /*!< EPWM_T::IFA3: STPMOD Position */ 4505 #define EPWM_IFA3_STPMOD_Msk (0x1ul << EPWM_IFA3_STPMOD_Pos) /*!< EPWM_T::IFA3: STPMOD Mask */ 4506 4507 #define EPWM_IFA3_IFASEL_Pos (28) /*!< EPWM_T::IFA3: IFASEL Position */ 4508 #define EPWM_IFA3_IFASEL_Msk (0x3ul << EPWM_IFA3_IFASEL_Pos) /*!< EPWM_T::IFA3: IFASEL Mask */ 4509 4510 #define EPWM_IFA3_IFAEN_Pos (31) /*!< EPWM_T::IFA3: IFAEN Position */ 4511 #define EPWM_IFA3_IFAEN_Msk (0x1ul << EPWM_IFA3_IFAEN_Pos) /*!< EPWM_T::IFA3: IFAEN Mask */ 4512 4513 #define EPWM_IFA4_IFACNT_Pos (0) /*!< EPWM_T::IFA4: IFACNT Position */ 4514 #define EPWM_IFA4_IFACNT_Msk (0xfffful << EPWM_IFA4_IFACNT_Pos) /*!< EPWM_T::IFA4: IFACNT Mask */ 4515 4516 #define EPWM_IFA4_STPMOD_Pos (24) /*!< EPWM_T::IFA4: STPMOD Position */ 4517 #define EPWM_IFA4_STPMOD_Msk (0x1ul << EPWM_IFA4_STPMOD_Pos) /*!< EPWM_T::IFA4: STPMOD Mask */ 4518 4519 #define EPWM_IFA4_IFASEL_Pos (28) /*!< EPWM_T::IFA4: IFASEL Position */ 4520 #define EPWM_IFA4_IFASEL_Msk (0x3ul << EPWM_IFA4_IFASEL_Pos) /*!< EPWM_T::IFA4: IFASEL Mask */ 4521 4522 #define EPWM_IFA4_IFAEN_Pos (31) /*!< EPWM_T::IFA4: IFAEN Position */ 4523 #define EPWM_IFA4_IFAEN_Msk (0x1ul << EPWM_IFA4_IFAEN_Pos) /*!< EPWM_T::IFA4: IFAEN Mask */ 4524 4525 #define EPWM_IFA5_IFACNT_Pos (0) /*!< EPWM_T::IFA5: IFACNT Position */ 4526 #define EPWM_IFA5_IFACNT_Msk (0xfffful << EPWM_IFA5_IFACNT_Pos) /*!< EPWM_T::IFA5: IFACNT Mask */ 4527 4528 #define EPWM_IFA5_STPMOD_Pos (24) /*!< EPWM_T::IFA5: STPMOD Position */ 4529 #define EPWM_IFA5_STPMOD_Msk (0x1ul << EPWM_IFA5_STPMOD_Pos) /*!< EPWM_T::IFA5: STPMOD Mask */ 4530 4531 #define EPWM_IFA5_IFASEL_Pos (28) /*!< EPWM_T::IFA5: IFASEL Position */ 4532 #define EPWM_IFA5_IFASEL_Msk (0x3ul << EPWM_IFA5_IFASEL_Pos) /*!< EPWM_T::IFA5: IFASEL Mask */ 4533 4534 #define EPWM_IFA5_IFAEN_Pos (31) /*!< EPWM_T::IFA5: IFAEN Position */ 4535 #define EPWM_IFA5_IFAEN_Msk (0x1ul << EPWM_IFA5_IFAEN_Pos) /*!< EPWM_T::IFA5: IFAEN Mask */ 4536 4537 #define EPWM_AINTSTS_IFAIF0_Pos (0) /*!< EPWM_T::AINTSTS: IFAIF0 Position */ 4538 #define EPWM_AINTSTS_IFAIF0_Msk (0x1ul << EPWM_AINTSTS_IFAIF0_Pos) /*!< EPWM_T::AINTSTS: IFAIF0 Mask */ 4539 4540 #define EPWM_AINTSTS_IFAIF1_Pos (1) /*!< EPWM_T::AINTSTS: IFAIF1 Position */ 4541 #define EPWM_AINTSTS_IFAIF1_Msk (0x1ul << EPWM_AINTSTS_IFAIF1_Pos) /*!< EPWM_T::AINTSTS: IFAIF1 Mask */ 4542 4543 #define EPWM_AINTSTS_IFAIF2_Pos (2) /*!< EPWM_T::AINTSTS: IFAIF2 Position */ 4544 #define EPWM_AINTSTS_IFAIF2_Msk (0x1ul << EPWM_AINTSTS_IFAIF2_Pos) /*!< EPWM_T::AINTSTS: IFAIF2 Mask */ 4545 4546 #define EPWM_AINTSTS_IFAIF3_Pos (3) /*!< EPWM_T::AINTSTS: IFAIF3 Position */ 4547 #define EPWM_AINTSTS_IFAIF3_Msk (0x1ul << EPWM_AINTSTS_IFAIF3_Pos) /*!< EPWM_T::AINTSTS: IFAIF3 Mask */ 4548 4549 #define EPWM_AINTSTS_IFAIF4_Pos (4) /*!< EPWM_T::AINTSTS: IFAIF4 Position */ 4550 #define EPWM_AINTSTS_IFAIF4_Msk (0x1ul << EPWM_AINTSTS_IFAIF4_Pos) /*!< EPWM_T::AINTSTS: IFAIF4 Mask */ 4551 4552 #define EPWM_AINTSTS_IFAIF5_Pos (5) /*!< EPWM_T::AINTSTS: IFAIF5 Position */ 4553 #define EPWM_AINTSTS_IFAIF5_Msk (0x1ul << EPWM_AINTSTS_IFAIF5_Pos) /*!< EPWM_T::AINTSTS: IFAIF5 Mask */ 4554 4555 #define EPWM_AINTEN_IFAIEN0_Pos (0) /*!< EPWM_T::AINTEN: IFAIEN0 Position */ 4556 #define EPWM_AINTEN_IFAIEN0_Msk (0x1ul << EPWM_AINTEN_IFAIEN0_Pos) /*!< EPWM_T::AINTEN: IFAIEN0 Mask */ 4557 4558 #define EPWM_AINTEN_IFAIEN1_Pos (1) /*!< EPWM_T::AINTEN: IFAIEN1 Position */ 4559 #define EPWM_AINTEN_IFAIEN1_Msk (0x1ul << EPWM_AINTEN_IFAIEN1_Pos) /*!< EPWM_T::AINTEN: IFAIEN1 Mask */ 4560 4561 #define EPWM_AINTEN_IFAIEN2_Pos (2) /*!< EPWM_T::AINTEN: IFAIEN2 Position */ 4562 #define EPWM_AINTEN_IFAIEN2_Msk (0x1ul << EPWM_AINTEN_IFAIEN2_Pos) /*!< EPWM_T::AINTEN: IFAIEN2 Mask */ 4563 4564 #define EPWM_AINTEN_IFAIEN3_Pos (3) /*!< EPWM_T::AINTEN: IFAIEN3 Position */ 4565 #define EPWM_AINTEN_IFAIEN3_Msk (0x1ul << EPWM_AINTEN_IFAIEN3_Pos) /*!< EPWM_T::AINTEN: IFAIEN3 Mask */ 4566 4567 #define EPWM_AINTEN_IFAIEN4_Pos (4) /*!< EPWM_T::AINTEN: IFAIEN4 Position */ 4568 #define EPWM_AINTEN_IFAIEN4_Msk (0x1ul << EPWM_AINTEN_IFAIEN4_Pos) /*!< EPWM_T::AINTEN: IFAIEN4 Mask */ 4569 4570 #define EPWM_AINTEN_IFAIEN5_Pos (5) /*!< EPWM_T::AINTEN: IFAIEN5 Position */ 4571 #define EPWM_AINTEN_IFAIEN5_Msk (0x1ul << EPWM_AINTEN_IFAIEN5_Pos) /*!< EPWM_T::AINTEN: IFAIEN5 Mask */ 4572 4573 #define EPWM_APDMACTL_APDMAEN0_Pos (0) /*!< EPWM_T::APDMACTL: APDMAEN0 Position */ 4574 #define EPWM_APDMACTL_APDMAEN0_Msk (0x1ul << EPWM_APDMACTL_APDMAEN0_Pos) /*!< EPWM_T::APDMACTL: APDMAEN0 Mask */ 4575 4576 #define EPWM_APDMACTL_APDMAEN1_Pos (1) /*!< EPWM_T::APDMACTL: APDMAEN1 Position */ 4577 #define EPWM_APDMACTL_APDMAEN1_Msk (0x1ul << EPWM_APDMACTL_APDMAEN1_Pos) /*!< EPWM_T::APDMACTL: APDMAEN1 Mask */ 4578 4579 #define EPWM_APDMACTL_APDMAEN2_Pos (2) /*!< EPWM_T::APDMACTL: APDMAEN2 Position */ 4580 #define EPWM_APDMACTL_APDMAEN2_Msk (0x1ul << EPWM_APDMACTL_APDMAEN2_Pos) /*!< EPWM_T::APDMACTL: APDMAEN2 Mask */ 4581 4582 #define EPWM_APDMACTL_APDMAEN3_Pos (3) /*!< EPWM_T::APDMACTL: APDMAEN3 Position */ 4583 #define EPWM_APDMACTL_APDMAEN3_Msk (0x1ul << EPWM_APDMACTL_APDMAEN3_Pos) /*!< EPWM_T::APDMACTL: APDMAEN3 Mask */ 4584 4585 #define EPWM_APDMACTL_APDMAEN4_Pos (4) /*!< EPWM_T::APDMACTL: APDMAEN4 Position */ 4586 #define EPWM_APDMACTL_APDMAEN4_Msk (0x1ul << EPWM_APDMACTL_APDMAEN4_Pos) /*!< EPWM_T::APDMACTL: APDMAEN4 Mask */ 4587 4588 #define EPWM_APDMACTL_APDMAEN5_Pos (5) /*!< EPWM_T::APDMACTL: APDMAEN5 Position */ 4589 #define EPWM_APDMACTL_APDMAEN5_Msk (0x1ul << EPWM_APDMACTL_APDMAEN5_Pos) /*!< EPWM_T::APDMACTL: APDMAEN5 Mask */ 4590 4591 #define EPWM_FDEN_FDEN0_Pos (0) /*!< EPWM_T::FDEN: FDEN0 Position */ 4592 #define EPWM_FDEN_FDEN0_Msk (0x1ul << EPWM_FDEN_FDEN0_Pos) /*!< EPWM_T::FDEN: FDEN0 Mask */ 4593 4594 #define EPWM_FDEN_FDEN1_Pos (1) /*!< EPWM_T::FDEN: FDEN1 Position */ 4595 #define EPWM_FDEN_FDEN1_Msk (0x1ul << EPWM_FDEN_FDEN1_Pos) /*!< EPWM_T::FDEN: FDEN1 Mask */ 4596 4597 #define EPWM_FDEN_FDEN2_Pos (2) /*!< EPWM_T::FDEN: FDEN2 Position */ 4598 #define EPWM_FDEN_FDEN2_Msk (0x1ul << EPWM_FDEN_FDEN2_Pos) /*!< EPWM_T::FDEN: FDEN2 Mask */ 4599 4600 #define EPWM_FDEN_FDEN3_Pos (3) /*!< EPWM_T::FDEN: FDEN3 Position */ 4601 #define EPWM_FDEN_FDEN3_Msk (0x1ul << EPWM_FDEN_FDEN3_Pos) /*!< EPWM_T::FDEN: FDEN3 Mask */ 4602 4603 #define EPWM_FDEN_FDEN4_Pos (4) /*!< EPWM_T::FDEN: FDEN4 Position */ 4604 #define EPWM_FDEN_FDEN4_Msk (0x1ul << EPWM_FDEN_FDEN4_Pos) /*!< EPWM_T::FDEN: FDEN4 Mask */ 4605 4606 #define EPWM_FDEN_FDEN5_Pos (5) /*!< EPWM_T::FDEN: FDEN5 Position */ 4607 #define EPWM_FDEN_FDEN5_Msk (0x1ul << EPWM_FDEN_FDEN5_Pos) /*!< EPWM_T::FDEN: FDEN5 Mask */ 4608 4609 #define EPWM_FDEN_FDODIS0_Pos (8) /*!< EPWM_T::FDEN: FDODIS0 Position */ 4610 #define EPWM_FDEN_FDODIS0_Msk (0x1ul << EPWM_FDEN_FDODIS0_Pos) /*!< EPWM_T::FDEN: FDODIS0 Mask */ 4611 4612 #define EPWM_FDEN_FDODIS1_Pos (9) /*!< EPWM_T::FDEN: FDODIS1 Position */ 4613 #define EPWM_FDEN_FDODIS1_Msk (0x1ul << EPWM_FDEN_FDODIS1_Pos) /*!< EPWM_T::FDEN: FDODIS1 Mask */ 4614 4615 #define EPWM_FDEN_FDODIS2_Pos (10) /*!< EPWM_T::FDEN: FDODIS2 Position */ 4616 #define EPWM_FDEN_FDODIS2_Msk (0x1ul << EPWM_FDEN_FDODIS2_Pos) /*!< EPWM_T::FDEN: FDODIS2 Mask */ 4617 4618 #define EPWM_FDEN_FDODIS3_Pos (11) /*!< EPWM_T::FDEN: FDODIS3 Position */ 4619 #define EPWM_FDEN_FDODIS3_Msk (0x1ul << EPWM_FDEN_FDODIS3_Pos) /*!< EPWM_T::FDEN: FDODIS3 Mask */ 4620 4621 #define EPWM_FDEN_FDODIS4_Pos (12) /*!< EPWM_T::FDEN: FDODIS4 Position */ 4622 #define EPWM_FDEN_FDODIS4_Msk (0x1ul << EPWM_FDEN_FDODIS4_Pos) /*!< EPWM_T::FDEN: FDODIS4 Mask */ 4623 4624 #define EPWM_FDEN_FDODIS5_Pos (13) /*!< EPWM_T::FDEN: FDODIS5 Position */ 4625 #define EPWM_FDEN_FDODIS5_Msk (0x1ul << EPWM_FDEN_FDODIS5_Pos) /*!< EPWM_T::FDEN: FDODIS5 Mask */ 4626 4627 #define EPWM_FDEN_FDCKS0_Pos (16) /*!< EPWM_T::FDEN: FDCKS0 Position */ 4628 #define EPWM_FDEN_FDCKS0_Msk (0x1ul << EPWM_FDEN_FDCKS0_Pos) /*!< EPWM_T::FDEN: FDCKS0 Mask */ 4629 4630 #define EPWM_FDEN_FDCKS1_Pos (17) /*!< EPWM_T::FDEN: FDCKS1 Position */ 4631 #define EPWM_FDEN_FDCKS1_Msk (0x1ul << EPWM_FDEN_FDCKS1_Pos) /*!< EPWM_T::FDEN: FDCKS1 Mask */ 4632 4633 #define EPWM_FDEN_FDCKS2_Pos (18) /*!< EPWM_T::FDEN: FDCKS2 Position */ 4634 #define EPWM_FDEN_FDCKS2_Msk (0x1ul << EPWM_FDEN_FDCKS2_Pos) /*!< EPWM_T::FDEN: FDCKS2 Mask */ 4635 4636 #define EPWM_FDEN_FDCKS3_Pos (19) /*!< EPWM_T::FDEN: FDCKS3 Position */ 4637 #define EPWM_FDEN_FDCKS3_Msk (0x1ul << EPWM_FDEN_FDCKS3_Pos) /*!< EPWM_T::FDEN: FDCKS3 Mask */ 4638 4639 #define EPWM_FDEN_FDCKS4_Pos (20) /*!< EPWM_T::FDEN: FDCKS4 Position */ 4640 #define EPWM_FDEN_FDCKS4_Msk (0x1ul << EPWM_FDEN_FDCKS4_Pos) /*!< EPWM_T::FDEN: FDCKS4 Mask */ 4641 4642 #define EPWM_FDEN_FDCKS5_Pos (21) /*!< EPWM_T::FDEN: FDCKS5 Position */ 4643 #define EPWM_FDEN_FDCKS5_Msk (0x1ul << EPWM_FDEN_FDCKS5_Pos) /*!< EPWM_T::FDEN: FDCKS5 Mask */ 4644 4645 #define EPWM_FDCTL0_TRMSKCNT_Pos (0) /*!< EPWM_T::FDCTL0: TRMSKCNT Position */ 4646 #define EPWM_FDCTL0_TRMSKCNT_Msk (0x7ful << EPWM_FDCTL0_TRMSKCNT_Pos) /*!< EPWM_T::FDCTL0: TRMSKCNT Mask */ 4647 4648 #define EPWM_FDCTL0_FDMSKEN_Pos (15) /*!< EPWM_T::FDCTL0: FDMSKEN Position */ 4649 #define EPWM_FDCTL0_FDMSKEN_Msk (0x1ul << EPWM_FDCTL0_FDMSKEN_Pos) /*!< EPWM_T::FDCTL0: FDMSKEN Mask */ 4650 4651 #define EPWM_FDCTL0_DGSMPCYC_Pos (16) /*!< EPWM_T::FDCTL0: DGSMPCYC Position */ 4652 #define EPWM_FDCTL0_DGSMPCYC_Msk (0x7ul << EPWM_FDCTL0_DGSMPCYC_Pos) /*!< EPWM_T::FDCTL0: DGSMPCYC Mask */ 4653 4654 #define EPWM_FDCTL0_FDCKSEL_Pos (28) /*!< EPWM_T::FDCTL0: FDCKSEL Position */ 4655 #define EPWM_FDCTL0_FDCKSEL_Msk (0x3ul << EPWM_FDCTL0_FDCKSEL_Pos) /*!< EPWM_T::FDCTL0: FDCKSEL Mask */ 4656 4657 #define EPWM_FDCTL0_FDDGEN_Pos (31) /*!< EPWM_T::FDCTL0: FDDGEN Position */ 4658 #define EPWM_FDCTL0_FDDGEN_Msk (0x1ul << EPWM_FDCTL0_FDDGEN_Pos) /*!< EPWM_T::FDCTL0: FDDGEN Mask */ 4659 4660 #define EPWM_FDCTL1_TRMSKCNT_Pos (0) /*!< EPWM_T::FDCTL1: TRMSKCNT Position */ 4661 #define EPWM_FDCTL1_TRMSKCNT_Msk (0x7ful << EPWM_FDCTL1_TRMSKCNT_Pos) /*!< EPWM_T::FDCTL1: TRMSKCNT Mask */ 4662 4663 #define EPWM_FDCTL1_FDMSKEN_Pos (15) /*!< EPWM_T::FDCTL1: FDMSKEN Position */ 4664 #define EPWM_FDCTL1_FDMSKEN_Msk (0x1ul << EPWM_FDCTL1_FDMSKEN_Pos) /*!< EPWM_T::FDCTL1: FDMSKEN Mask */ 4665 4666 #define EPWM_FDCTL1_DGSMPCYC_Pos (16) /*!< EPWM_T::FDCTL1: DGSMPCYC Position */ 4667 #define EPWM_FDCTL1_DGSMPCYC_Msk (0x7ul << EPWM_FDCTL1_DGSMPCYC_Pos) /*!< EPWM_T::FDCTL1: DGSMPCYC Mask */ 4668 4669 #define EPWM_FDCTL1_FDCKSEL_Pos (28) /*!< EPWM_T::FDCTL1: FDCKSEL Position */ 4670 #define EPWM_FDCTL1_FDCKSEL_Msk (0x3ul << EPWM_FDCTL1_FDCKSEL_Pos) /*!< EPWM_T::FDCTL1: FDCKSEL Mask */ 4671 4672 #define EPWM_FDCTL1_FDDGEN_Pos (31) /*!< EPWM_T::FDCTL1: FDDGEN Position */ 4673 #define EPWM_FDCTL1_FDDGEN_Msk (0x1ul << EPWM_FDCTL1_FDDGEN_Pos) /*!< EPWM_T::FDCTL1: FDDGEN Mask */ 4674 4675 #define EPWM_FDCTL2_TRMSKCNT_Pos (0) /*!< EPWM_T::FDCTL2: TRMSKCNT Position */ 4676 #define EPWM_FDCTL2_TRMSKCNT_Msk (0x7ful << EPWM_FDCTL2_TRMSKCNT_Pos) /*!< EPWM_T::FDCTL2: TRMSKCNT Mask */ 4677 4678 #define EPWM_FDCTL2_FDMSKEN_Pos (15) /*!< EPWM_T::FDCTL2: FDMSKEN Position */ 4679 #define EPWM_FDCTL2_FDMSKEN_Msk (0x1ul << EPWM_FDCTL2_FDMSKEN_Pos) /*!< EPWM_T::FDCTL2: FDMSKEN Mask */ 4680 4681 #define EPWM_FDCTL2_DGSMPCYC_Pos (16) /*!< EPWM_T::FDCTL2: DGSMPCYC Position */ 4682 #define EPWM_FDCTL2_DGSMPCYC_Msk (0x7ul << EPWM_FDCTL2_DGSMPCYC_Pos) /*!< EPWM_T::FDCTL2: DGSMPCYC Mask */ 4683 4684 #define EPWM_FDCTL2_FDCKSEL_Pos (28) /*!< EPWM_T::FDCTL2: FDCKSEL Position */ 4685 #define EPWM_FDCTL2_FDCKSEL_Msk (0x3ul << EPWM_FDCTL2_FDCKSEL_Pos) /*!< EPWM_T::FDCTL2: FDCKSEL Mask */ 4686 4687 #define EPWM_FDCTL2_FDDGEN_Pos (31) /*!< EPWM_T::FDCTL2: FDDGEN Position */ 4688 #define EPWM_FDCTL2_FDDGEN_Msk (0x1ul << EPWM_FDCTL2_FDDGEN_Pos) /*!< EPWM_T::FDCTL2: FDDGEN Mask */ 4689 4690 #define EPWM_FDCTL3_TRMSKCNT_Pos (0) /*!< EPWM_T::FDCTL3: TRMSKCNT Position */ 4691 #define EPWM_FDCTL3_TRMSKCNT_Msk (0x7ful << EPWM_FDCTL3_TRMSKCNT_Pos) /*!< EPWM_T::FDCTL3: TRMSKCNT Mask */ 4692 4693 #define EPWM_FDCTL3_FDMSKEN_Pos (15) /*!< EPWM_T::FDCTL3: FDMSKEN Position */ 4694 #define EPWM_FDCTL3_FDMSKEN_Msk (0x1ul << EPWM_FDCTL3_FDMSKEN_Pos) /*!< EPWM_T::FDCTL3: FDMSKEN Mask */ 4695 4696 #define EPWM_FDCTL3_DGSMPCYC_Pos (16) /*!< EPWM_T::FDCTL3: DGSMPCYC Position */ 4697 #define EPWM_FDCTL3_DGSMPCYC_Msk (0x7ul << EPWM_FDCTL3_DGSMPCYC_Pos) /*!< EPWM_T::FDCTL3: DGSMPCYC Mask */ 4698 4699 #define EPWM_FDCTL3_FDCKSEL_Pos (28) /*!< EPWM_T::FDCTL3: FDCKSEL Position */ 4700 #define EPWM_FDCTL3_FDCKSEL_Msk (0x3ul << EPWM_FDCTL3_FDCKSEL_Pos) /*!< EPWM_T::FDCTL3: FDCKSEL Mask */ 4701 4702 #define EPWM_FDCTL3_FDDGEN_Pos (31) /*!< EPWM_T::FDCTL3: FDDGEN Position */ 4703 #define EPWM_FDCTL3_FDDGEN_Msk (0x1ul << EPWM_FDCTL3_FDDGEN_Pos) /*!< EPWM_T::FDCTL3: FDDGEN Mask */ 4704 4705 #define EPWM_FDCTL4_TRMSKCNT_Pos (0) /*!< EPWM_T::FDCTL4: TRMSKCNT Position */ 4706 #define EPWM_FDCTL4_TRMSKCNT_Msk (0x7ful << EPWM_FDCTL4_TRMSKCNT_Pos) /*!< EPWM_T::FDCTL4: TRMSKCNT Mask */ 4707 4708 #define EPWM_FDCTL4_FDMSKEN_Pos (15) /*!< EPWM_T::FDCTL4: FDMSKEN Position */ 4709 #define EPWM_FDCTL4_FDMSKEN_Msk (0x1ul << EPWM_FDCTL4_FDMSKEN_Pos) /*!< EPWM_T::FDCTL4: FDMSKEN Mask */ 4710 4711 #define EPWM_FDCTL4_DGSMPCYC_Pos (16) /*!< EPWM_T::FDCTL4: DGSMPCYC Position */ 4712 #define EPWM_FDCTL4_DGSMPCYC_Msk (0x7ul << EPWM_FDCTL4_DGSMPCYC_Pos) /*!< EPWM_T::FDCTL4: DGSMPCYC Mask */ 4713 4714 #define EPWM_FDCTL4_FDCKSEL_Pos (28) /*!< EPWM_T::FDCTL4: FDCKSEL Position */ 4715 #define EPWM_FDCTL4_FDCKSEL_Msk (0x3ul << EPWM_FDCTL4_FDCKSEL_Pos) /*!< EPWM_T::FDCTL4: FDCKSEL Mask */ 4716 4717 #define EPWM_FDCTL4_FDDGEN_Pos (31) /*!< EPWM_T::FDCTL4: FDDGEN Position */ 4718 #define EPWM_FDCTL4_FDDGEN_Msk (0x1ul << EPWM_FDCTL4_FDDGEN_Pos) /*!< EPWM_T::FDCTL4: FDDGEN Mask */ 4719 4720 #define EPWM_FDCTL5_TRMSKCNT_Pos (0) /*!< EPWM_T::FDCTL5: TRMSKCNT Position */ 4721 #define EPWM_FDCTL5_TRMSKCNT_Msk (0x7ful << EPWM_FDCTL5_TRMSKCNT_Pos) /*!< EPWM_T::FDCTL5: TRMSKCNT Mask */ 4722 4723 #define EPWM_FDCTL5_FDMSKEN_Pos (15) /*!< EPWM_T::FDCTL5: FDMSKEN Position */ 4724 #define EPWM_FDCTL5_FDMSKEN_Msk (0x1ul << EPWM_FDCTL5_FDMSKEN_Pos) /*!< EPWM_T::FDCTL5: FDMSKEN Mask */ 4725 4726 #define EPWM_FDCTL5_DGSMPCYC_Pos (16) /*!< EPWM_T::FDCTL5: DGSMPCYC Position */ 4727 #define EPWM_FDCTL5_DGSMPCYC_Msk (0x7ul << EPWM_FDCTL5_DGSMPCYC_Pos) /*!< EPWM_T::FDCTL5: DGSMPCYC Mask */ 4728 4729 #define EPWM_FDCTL5_FDCKSEL_Pos (28) /*!< EPWM_T::FDCTL5: FDCKSEL Position */ 4730 #define EPWM_FDCTL5_FDCKSEL_Msk (0x3ul << EPWM_FDCTL5_FDCKSEL_Pos) /*!< EPWM_T::FDCTL5: FDCKSEL Mask */ 4731 4732 #define EPWM_FDCTL5_FDDGEN_Pos (31) /*!< EPWM_T::FDCTL5: FDDGEN Position */ 4733 #define EPWM_FDCTL5_FDDGEN_Msk (0x1ul << EPWM_FDCTL5_FDDGEN_Pos) /*!< EPWM_T::FDCTL5: FDDGEN Mask */ 4734 4735 #define EPWM_FDIEN_FDIEN0_Pos (0) /*!< EPWM_T::FDIEN: FDIEN0 Position */ 4736 #define EPWM_FDIEN_FDIEN0_Msk (0x1ul << EPWM_FDIEN_FDIEN0_Pos) /*!< EPWM_T::FDIEN: FDIEN0 Mask */ 4737 4738 #define EPWM_FDIEN_FDIEN1_Pos (1) /*!< EPWM_T::FDIEN: FDIEN1 Position */ 4739 #define EPWM_FDIEN_FDIEN1_Msk (0x1ul << EPWM_FDIEN_FDIEN1_Pos) /*!< EPWM_T::FDIEN: FDIEN1 Mask */ 4740 4741 #define EPWM_FDIEN_FDIEN2_Pos (2) /*!< EPWM_T::FDIEN: FDIEN2 Position */ 4742 #define EPWM_FDIEN_FDIEN2_Msk (0x1ul << EPWM_FDIEN_FDIEN2_Pos) /*!< EPWM_T::FDIEN: FDIEN2 Mask */ 4743 4744 #define EPWM_FDIEN_FDIEN3_Pos (3) /*!< EPWM_T::FDIEN: FDIEN3 Position */ 4745 #define EPWM_FDIEN_FDIEN3_Msk (0x1ul << EPWM_FDIEN_FDIEN3_Pos) /*!< EPWM_T::FDIEN: FDIEN3 Mask */ 4746 4747 #define EPWM_FDIEN_FDIEN4_Pos (4) /*!< EPWM_T::FDIEN: FDIEN4 Position */ 4748 #define EPWM_FDIEN_FDIEN4_Msk (0x1ul << EPWM_FDIEN_FDIEN4_Pos) /*!< EPWM_T::FDIEN: FDIEN4 Mask */ 4749 4750 #define EPWM_FDIEN_FDIEN5_Pos (5) /*!< EPWM_T::FDIEN: FDIEN5 Position */ 4751 #define EPWM_FDIEN_FDIEN5_Msk (0x1ul << EPWM_FDIEN_FDIEN5_Pos) /*!< EPWM_T::FDIEN: FDIEN5 Mask */ 4752 4753 #define EPWM_FDSTS_FDIF0_Pos (0) /*!< EPWM_T::FDSTS: FDIF0 Position */ 4754 #define EPWM_FDSTS_FDIF0_Msk (0x1ul << EPWM_FDSTS_FDIF0_Pos) /*!< EPWM_T::FDSTS: FDIF0 Mask */ 4755 4756 #define EPWM_FDSTS_FDIF1_Pos (1) /*!< EPWM_T::FDSTS: FDIF1 Position */ 4757 #define EPWM_FDSTS_FDIF1_Msk (0x1ul << EPWM_FDSTS_FDIF1_Pos) /*!< EPWM_T::FDSTS: FDIF1 Mask */ 4758 4759 #define EPWM_FDSTS_FDIF2_Pos (2) /*!< EPWM_T::FDSTS: FDIF2 Position */ 4760 #define EPWM_FDSTS_FDIF2_Msk (0x1ul << EPWM_FDSTS_FDIF2_Pos) /*!< EPWM_T::FDSTS: FDIF2 Mask */ 4761 4762 #define EPWM_FDSTS_FDIF3_Pos (3) /*!< EPWM_T::FDSTS: FDIF3 Position */ 4763 #define EPWM_FDSTS_FDIF3_Msk (0x1ul << EPWM_FDSTS_FDIF3_Pos) /*!< EPWM_T::FDSTS: FDIF3 Mask */ 4764 4765 #define EPWM_FDSTS_FDIF4_Pos (4) /*!< EPWM_T::FDSTS: FDIF4 Position */ 4766 #define EPWM_FDSTS_FDIF4_Msk (0x1ul << EPWM_FDSTS_FDIF4_Pos) /*!< EPWM_T::FDSTS: FDIF4 Mask */ 4767 4768 #define EPWM_FDSTS_FDIF5_Pos (5) /*!< EPWM_T::FDSTS: FDIF5 Position */ 4769 #define EPWM_FDSTS_FDIF5_Msk (0x1ul << EPWM_FDSTS_FDIF5_Pos) /*!< EPWM_T::FDSTS: FDIF5 Mask */ 4770 4771 #define EPWM_EADCPSCCTL_PSCEN0_Pos (0) /*!< EPWM_T::EADCPSCCTL: PSCEN0 Position */ 4772 #define EPWM_EADCPSCCTL_PSCEN0_Msk (0x1ul << EPWM_EADCPSCCTL_PSCEN0_Pos) /*!< EPWM_T::EADCPSCCTL: PSCEN0 Mask */ 4773 4774 #define EPWM_EADCPSCCTL_PSCEN1_Pos (1) /*!< EPWM_T::EADCPSCCTL: PSCEN1 Position */ 4775 #define EPWM_EADCPSCCTL_PSCEN1_Msk (0x1ul << EPWM_EADCPSCCTL_PSCEN1_Pos) /*!< EPWM_T::EADCPSCCTL: PSCEN1 Mask */ 4776 4777 #define EPWM_EADCPSCCTL_PSCEN2_Pos (2) /*!< EPWM_T::EADCPSCCTL: PSCEN2 Position */ 4778 #define EPWM_EADCPSCCTL_PSCEN2_Msk (0x1ul << EPWM_EADCPSCCTL_PSCEN2_Pos) /*!< EPWM_T::EADCPSCCTL: PSCEN2 Mask */ 4779 4780 #define EPWM_EADCPSCCTL_PSCEN3_Pos (3) /*!< EPWM_T::EADCPSCCTL: PSCEN3 Position */ 4781 #define EPWM_EADCPSCCTL_PSCEN3_Msk (0x1ul << EPWM_EADCPSCCTL_PSCEN3_Pos) /*!< EPWM_T::EADCPSCCTL: PSCEN3 Mask */ 4782 4783 #define EPWM_EADCPSCCTL_PSCEN4_Pos (4) /*!< EPWM_T::EADCPSCCTL: PSCEN4 Position */ 4784 #define EPWM_EADCPSCCTL_PSCEN4_Msk (0x1ul << EPWM_EADCPSCCTL_PSCEN4_Pos) /*!< EPWM_T::EADCPSCCTL: PSCEN4 Mask */ 4785 4786 #define EPWM_EADCPSCCTL_PSCEN5_Pos (5) /*!< EPWM_T::EADCPSCCTL: PSCEN5 Position */ 4787 #define EPWM_EADCPSCCTL_PSCEN5_Msk (0x1ul << EPWM_EADCPSCCTL_PSCEN5_Pos) /*!< EPWM_T::EADCPSCCTL: PSCEN5 Mask */ 4788 4789 #define EPWM_EADCPSC0_EADCPSC0_Pos (0) /*!< EPWM_T::EADCPSC0: EADCPSC0 Position */ 4790 #define EPWM_EADCPSC0_EADCPSC0_Msk (0xful << EPWM_EADCPSC0_EADCPSC0_Pos) /*!< EPWM_T::EADCPSC0: EADCPSC0 Mask */ 4791 4792 #define EPWM_EADCPSC0_EADCPSC1_Pos (8) /*!< EPWM_T::EADCPSC0: EADCPSC1 Position */ 4793 #define EPWM_EADCPSC0_EADCPSC1_Msk (0xful << EPWM_EADCPSC0_EADCPSC1_Pos) /*!< EPWM_T::EADCPSC0: EADCPSC1 Mask */ 4794 4795 #define EPWM_EADCPSC0_EADCPSC2_Pos (16) /*!< EPWM_T::EADCPSC0: EADCPSC2 Position */ 4796 #define EPWM_EADCPSC0_EADCPSC2_Msk (0xful << EPWM_EADCPSC0_EADCPSC2_Pos) /*!< EPWM_T::EADCPSC0: EADCPSC2 Mask */ 4797 4798 #define EPWM_EADCPSC0_EADCPSC3_Pos (24) /*!< EPWM_T::EADCPSC0: EADCPSC3 Position */ 4799 #define EPWM_EADCPSC0_EADCPSC3_Msk (0xful << EPWM_EADCPSC0_EADCPSC3_Pos) /*!< EPWM_T::EADCPSC0: EADCPSC3 Mask */ 4800 4801 #define EPWM_EADCPSC1_EADCPSC4_Pos (0) /*!< EPWM_T::EADCPSC1: EADCPSC4 Position */ 4802 #define EPWM_EADCPSC1_EADCPSC4_Msk (0xful << EPWM_EADCPSC1_EADCPSC4_Pos) /*!< EPWM_T::EADCPSC1: EADCPSC4 Mask */ 4803 4804 #define EPWM_EADCPSC1_EADCPSC5_Pos (8) /*!< EPWM_T::EADCPSC1: EADCPSC5 Position */ 4805 #define EPWM_EADCPSC1_EADCPSC5_Msk (0xful << EPWM_EADCPSC1_EADCPSC5_Pos) /*!< EPWM_T::EADCPSC1: EADCPSC5 Mask */ 4806 4807 #define EPWM_EADCPSCNT0_PSCNT0_Pos (0) /*!< EPWM_T::EADCPSCNT0: PSCNT0 Position */ 4808 #define EPWM_EADCPSCNT0_PSCNT0_Msk (0xful << EPWM_EADCPSCNT0_PSCNT0_Pos) /*!< EPWM_T::EADCPSCNT0: PSCNT0 Mask */ 4809 4810 #define EPWM_EADCPSCNT0_PSCNT1_Pos (8) /*!< EPWM_T::EADCPSCNT0: PSCNT1 Position */ 4811 #define EPWM_EADCPSCNT0_PSCNT1_Msk (0xful << EPWM_EADCPSCNT0_PSCNT1_Pos) /*!< EPWM_T::EADCPSCNT0: PSCNT1 Mask */ 4812 4813 #define EPWM_EADCPSCNT0_PSCNT2_Pos (16) /*!< EPWM_T::EADCPSCNT0: PSCNT2 Position */ 4814 #define EPWM_EADCPSCNT0_PSCNT2_Msk (0xful << EPWM_EADCPSCNT0_PSCNT2_Pos) /*!< EPWM_T::EADCPSCNT0: PSCNT2 Mask */ 4815 4816 #define EPWM_EADCPSCNT0_PSCNT3_Pos (24) /*!< EPWM_T::EADCPSCNT0: PSCNT3 Position */ 4817 #define EPWM_EADCPSCNT0_PSCNT3_Msk (0xful << EPWM_EADCPSCNT0_PSCNT3_Pos) /*!< EPWM_T::EADCPSCNT0: PSCNT3 Mask */ 4818 4819 #define EPWM_EADCPSCNT1_PSCNT4_Pos (0) /*!< EPWM_T::EADCPSCNT1: PSCNT4 Position */ 4820 #define EPWM_EADCPSCNT1_PSCNT4_Msk (0xful << EPWM_EADCPSCNT1_PSCNT4_Pos) /*!< EPWM_T::EADCPSCNT1: PSCNT4 Mask */ 4821 4822 #define EPWM_EADCPSCNT1_PSCNT5_Pos (8) /*!< EPWM_T::EADCPSCNT1: PSCNT5 Position */ 4823 #define EPWM_EADCPSCNT1_PSCNT5_Msk (0xful << EPWM_EADCPSCNT1_PSCNT5_Pos) /*!< EPWM_T::EADCPSCNT1: PSCNT5 Mask */ 4824 4825 #define EPWM_CAPINEN_CAPINEN0_Pos (0) /*!< EPWM_T::CAPINEN: CAPINEN0 Position */ 4826 #define EPWM_CAPINEN_CAPINEN0_Msk (0x1ul << EPWM_CAPINEN_CAPINEN0_Pos) /*!< EPWM_T::CAPINEN: CAPINEN0 Mask */ 4827 4828 #define EPWM_CAPINEN_CAPINEN1_Pos (1) /*!< EPWM_T::CAPINEN: CAPINEN1 Position */ 4829 #define EPWM_CAPINEN_CAPINEN1_Msk (0x1ul << EPWM_CAPINEN_CAPINEN1_Pos) /*!< EPWM_T::CAPINEN: CAPINEN1 Mask */ 4830 4831 #define EPWM_CAPINEN_CAPINEN2_Pos (2) /*!< EPWM_T::CAPINEN: CAPINEN2 Position */ 4832 #define EPWM_CAPINEN_CAPINEN2_Msk (0x1ul << EPWM_CAPINEN_CAPINEN2_Pos) /*!< EPWM_T::CAPINEN: CAPINEN2 Mask */ 4833 4834 #define EPWM_CAPINEN_CAPINEN3_Pos (3) /*!< EPWM_T::CAPINEN: CAPINEN3 Position */ 4835 #define EPWM_CAPINEN_CAPINEN3_Msk (0x1ul << EPWM_CAPINEN_CAPINEN3_Pos) /*!< EPWM_T::CAPINEN: CAPINEN3 Mask */ 4836 4837 #define EPWM_CAPINEN_CAPINEN4_Pos (4) /*!< EPWM_T::CAPINEN: CAPINEN4 Position */ 4838 #define EPWM_CAPINEN_CAPINEN4_Msk (0x1ul << EPWM_CAPINEN_CAPINEN4_Pos) /*!< EPWM_T::CAPINEN: CAPINEN4 Mask */ 4839 4840 #define EPWM_CAPINEN_CAPINEN5_Pos (5) /*!< EPWM_T::CAPINEN: CAPINEN5 Position */ 4841 #define EPWM_CAPINEN_CAPINEN5_Msk (0x1ul << EPWM_CAPINEN_CAPINEN5_Pos) /*!< EPWM_T::CAPINEN: CAPINEN5 Mask */ 4842 4843 #define EPWM_CAPCTL_CAPEN0_Pos (0) /*!< EPWM_T::CAPCTL: CAPEN0 Position */ 4844 #define EPWM_CAPCTL_CAPEN0_Msk (0x1ul << EPWM_CAPCTL_CAPEN0_Pos) /*!< EPWM_T::CAPCTL: CAPEN0 Mask */ 4845 4846 #define EPWM_CAPCTL_CAPEN1_Pos (1) /*!< EPWM_T::CAPCTL: CAPEN1 Position */ 4847 #define EPWM_CAPCTL_CAPEN1_Msk (0x1ul << EPWM_CAPCTL_CAPEN1_Pos) /*!< EPWM_T::CAPCTL: CAPEN1 Mask */ 4848 4849 #define EPWM_CAPCTL_CAPEN2_Pos (2) /*!< EPWM_T::CAPCTL: CAPEN2 Position */ 4850 #define EPWM_CAPCTL_CAPEN2_Msk (0x1ul << EPWM_CAPCTL_CAPEN2_Pos) /*!< EPWM_T::CAPCTL: CAPEN2 Mask */ 4851 4852 #define EPWM_CAPCTL_CAPEN3_Pos (3) /*!< EPWM_T::CAPCTL: CAPEN3 Position */ 4853 #define EPWM_CAPCTL_CAPEN3_Msk (0x1ul << EPWM_CAPCTL_CAPEN3_Pos) /*!< EPWM_T::CAPCTL: CAPEN3 Mask */ 4854 4855 #define EPWM_CAPCTL_CAPEN4_Pos (4) /*!< EPWM_T::CAPCTL: CAPEN4 Position */ 4856 #define EPWM_CAPCTL_CAPEN4_Msk (0x1ul << EPWM_CAPCTL_CAPEN4_Pos) /*!< EPWM_T::CAPCTL: CAPEN4 Mask */ 4857 4858 #define EPWM_CAPCTL_CAPEN5_Pos (5) /*!< EPWM_T::CAPCTL: CAPEN5 Position */ 4859 #define EPWM_CAPCTL_CAPEN5_Msk (0x1ul << EPWM_CAPCTL_CAPEN5_Pos) /*!< EPWM_T::CAPCTL: CAPEN5 Mask */ 4860 4861 #define EPWM_CAPCTL_CAPINV0_Pos (8) /*!< EPWM_T::CAPCTL: CAPINV0 Position */ 4862 #define EPWM_CAPCTL_CAPINV0_Msk (0x1ul << EPWM_CAPCTL_CAPINV0_Pos) /*!< EPWM_T::CAPCTL: CAPINV0 Mask */ 4863 4864 #define EPWM_CAPCTL_CAPINV1_Pos (9) /*!< EPWM_T::CAPCTL: CAPINV1 Position */ 4865 #define EPWM_CAPCTL_CAPINV1_Msk (0x1ul << EPWM_CAPCTL_CAPINV1_Pos) /*!< EPWM_T::CAPCTL: CAPINV1 Mask */ 4866 4867 #define EPWM_CAPCTL_CAPINV2_Pos (10) /*!< EPWM_T::CAPCTL: CAPINV2 Position */ 4868 #define EPWM_CAPCTL_CAPINV2_Msk (0x1ul << EPWM_CAPCTL_CAPINV2_Pos) /*!< EPWM_T::CAPCTL: CAPINV2 Mask */ 4869 4870 #define EPWM_CAPCTL_CAPINV3_Pos (11) /*!< EPWM_T::CAPCTL: CAPINV3 Position */ 4871 #define EPWM_CAPCTL_CAPINV3_Msk (0x1ul << EPWM_CAPCTL_CAPINV3_Pos) /*!< EPWM_T::CAPCTL: CAPINV3 Mask */ 4872 4873 #define EPWM_CAPCTL_CAPINV4_Pos (12) /*!< EPWM_T::CAPCTL: CAPINV4 Position */ 4874 #define EPWM_CAPCTL_CAPINV4_Msk (0x1ul << EPWM_CAPCTL_CAPINV4_Pos) /*!< EPWM_T::CAPCTL: CAPINV4 Mask */ 4875 4876 #define EPWM_CAPCTL_CAPINV5_Pos (13) /*!< EPWM_T::CAPCTL: CAPINV5 Position */ 4877 #define EPWM_CAPCTL_CAPINV5_Msk (0x1ul << EPWM_CAPCTL_CAPINV5_Pos) /*!< EPWM_T::CAPCTL: CAPINV5 Mask */ 4878 4879 #define EPWM_CAPCTL_RCRLDEN0_Pos (16) /*!< EPWM_T::CAPCTL: RCRLDEN0 Position */ 4880 #define EPWM_CAPCTL_RCRLDEN0_Msk (0x1ul << EPWM_CAPCTL_RCRLDEN0_Pos) /*!< EPWM_T::CAPCTL: RCRLDEN0 Mask */ 4881 4882 #define EPWM_CAPCTL_RCRLDEN1_Pos (17) /*!< EPWM_T::CAPCTL: RCRLDEN1 Position */ 4883 #define EPWM_CAPCTL_RCRLDEN1_Msk (0x1ul << EPWM_CAPCTL_RCRLDEN1_Pos) /*!< EPWM_T::CAPCTL: RCRLDEN1 Mask */ 4884 4885 #define EPWM_CAPCTL_RCRLDEN2_Pos (18) /*!< EPWM_T::CAPCTL: RCRLDEN2 Position */ 4886 #define EPWM_CAPCTL_RCRLDEN2_Msk (0x1ul << EPWM_CAPCTL_RCRLDEN2_Pos) /*!< EPWM_T::CAPCTL: RCRLDEN2 Mask */ 4887 4888 #define EPWM_CAPCTL_RCRLDEN3_Pos (19) /*!< EPWM_T::CAPCTL: RCRLDEN3 Position */ 4889 #define EPWM_CAPCTL_RCRLDEN3_Msk (0x1ul << EPWM_CAPCTL_RCRLDEN3_Pos) /*!< EPWM_T::CAPCTL: RCRLDEN3 Mask */ 4890 4891 #define EPWM_CAPCTL_RCRLDEN4_Pos (20) /*!< EPWM_T::CAPCTL: RCRLDEN4 Position */ 4892 #define EPWM_CAPCTL_RCRLDEN4_Msk (0x1ul << EPWM_CAPCTL_RCRLDEN4_Pos) /*!< EPWM_T::CAPCTL: RCRLDEN4 Mask */ 4893 4894 #define EPWM_CAPCTL_RCRLDEN5_Pos (21) /*!< EPWM_T::CAPCTL: RCRLDEN5 Position */ 4895 #define EPWM_CAPCTL_RCRLDEN5_Msk (0x1ul << EPWM_CAPCTL_RCRLDEN5_Pos) /*!< EPWM_T::CAPCTL: RCRLDEN5 Mask */ 4896 4897 #define EPWM_CAPCTL_FCRLDEN0_Pos (24) /*!< EPWM_T::CAPCTL: FCRLDEN0 Position */ 4898 #define EPWM_CAPCTL_FCRLDEN0_Msk (0x1ul << EPWM_CAPCTL_FCRLDEN0_Pos) /*!< EPWM_T::CAPCTL: FCRLDEN0 Mask */ 4899 4900 #define EPWM_CAPCTL_FCRLDEN1_Pos (25) /*!< EPWM_T::CAPCTL: FCRLDEN1 Position */ 4901 #define EPWM_CAPCTL_FCRLDEN1_Msk (0x1ul << EPWM_CAPCTL_FCRLDEN1_Pos) /*!< EPWM_T::CAPCTL: FCRLDEN1 Mask */ 4902 4903 #define EPWM_CAPCTL_FCRLDEN2_Pos (26) /*!< EPWM_T::CAPCTL: FCRLDEN2 Position */ 4904 #define EPWM_CAPCTL_FCRLDEN2_Msk (0x1ul << EPWM_CAPCTL_FCRLDEN2_Pos) /*!< EPWM_T::CAPCTL: FCRLDEN2 Mask */ 4905 4906 #define EPWM_CAPCTL_FCRLDEN3_Pos (27) /*!< EPWM_T::CAPCTL: FCRLDEN3 Position */ 4907 #define EPWM_CAPCTL_FCRLDEN3_Msk (0x1ul << EPWM_CAPCTL_FCRLDEN3_Pos) /*!< EPWM_T::CAPCTL: FCRLDEN3 Mask */ 4908 4909 #define EPWM_CAPCTL_FCRLDEN4_Pos (28) /*!< EPWM_T::CAPCTL: FCRLDEN4 Position */ 4910 #define EPWM_CAPCTL_FCRLDEN4_Msk (0x1ul << EPWM_CAPCTL_FCRLDEN4_Pos) /*!< EPWM_T::CAPCTL: FCRLDEN4 Mask */ 4911 4912 #define EPWM_CAPCTL_FCRLDEN5_Pos (29) /*!< EPWM_T::CAPCTL: FCRLDEN5 Position */ 4913 #define EPWM_CAPCTL_FCRLDEN5_Msk (0x1ul << EPWM_CAPCTL_FCRLDEN5_Pos) /*!< EPWM_T::CAPCTL: FCRLDEN5 Mask */ 4914 4915 #define EPWM_CAPSTS_CRLIFOV0_Pos (0) /*!< EPWM_T::CAPSTS: CRLIFOV0 Position */ 4916 #define EPWM_CAPSTS_CRLIFOV0_Msk (0x1ul << EPWM_CAPSTS_CRLIFOV0_Pos) /*!< EPWM_T::CAPSTS: CRLIFOV0 Mask */ 4917 4918 #define EPWM_CAPSTS_CRLIFOV1_Pos (1) /*!< EPWM_T::CAPSTS: CRLIFOV1 Position */ 4919 #define EPWM_CAPSTS_CRLIFOV1_Msk (0x1ul << EPWM_CAPSTS_CRLIFOV1_Pos) /*!< EPWM_T::CAPSTS: CRLIFOV1 Mask */ 4920 4921 #define EPWM_CAPSTS_CRLIFOV2_Pos (2) /*!< EPWM_T::CAPSTS: CRLIFOV2 Position */ 4922 #define EPWM_CAPSTS_CRLIFOV2_Msk (0x1ul << EPWM_CAPSTS_CRLIFOV2_Pos) /*!< EPWM_T::CAPSTS: CRLIFOV2 Mask */ 4923 4924 #define EPWM_CAPSTS_CRLIFOV3_Pos (3) /*!< EPWM_T::CAPSTS: CRLIFOV3 Position */ 4925 #define EPWM_CAPSTS_CRLIFOV3_Msk (0x1ul << EPWM_CAPSTS_CRLIFOV3_Pos) /*!< EPWM_T::CAPSTS: CRLIFOV3 Mask */ 4926 4927 #define EPWM_CAPSTS_CRLIFOV4_Pos (4) /*!< EPWM_T::CAPSTS: CRLIFOV4 Position */ 4928 #define EPWM_CAPSTS_CRLIFOV4_Msk (0x1ul << EPWM_CAPSTS_CRLIFOV4_Pos) /*!< EPWM_T::CAPSTS: CRLIFOV4 Mask */ 4929 4930 #define EPWM_CAPSTS_CRLIFOV5_Pos (5) /*!< EPWM_T::CAPSTS: CRLIFOV5 Position */ 4931 #define EPWM_CAPSTS_CRLIFOV5_Msk (0x1ul << EPWM_CAPSTS_CRLIFOV5_Pos) /*!< EPWM_T::CAPSTS: CRLIFOV5 Mask */ 4932 4933 #define EPWM_CAPSTS_CFLIFOV0_Pos (8) /*!< EPWM_T::CAPSTS: CFLIFOV0 Position */ 4934 #define EPWM_CAPSTS_CFLIFOV0_Msk (0x1ul << EPWM_CAPSTS_CFLIFOV0_Pos) /*!< EPWM_T::CAPSTS: CFLIFOV0 Mask */ 4935 4936 #define EPWM_CAPSTS_CFLIFOV1_Pos (9) /*!< EPWM_T::CAPSTS: CFLIFOV1 Position */ 4937 #define EPWM_CAPSTS_CFLIFOV1_Msk (0x1ul << EPWM_CAPSTS_CFLIFOV1_Pos) /*!< EPWM_T::CAPSTS: CFLIFOV1 Mask */ 4938 4939 #define EPWM_CAPSTS_CFLIFOV2_Pos (10) /*!< EPWM_T::CAPSTS: CFLIFOV2 Position */ 4940 #define EPWM_CAPSTS_CFLIFOV2_Msk (0x1ul << EPWM_CAPSTS_CFLIFOV2_Pos) /*!< EPWM_T::CAPSTS: CFLIFOV2 Mask */ 4941 4942 #define EPWM_CAPSTS_CFLIFOV3_Pos (11) /*!< EPWM_T::CAPSTS: CFLIFOV3 Position */ 4943 #define EPWM_CAPSTS_CFLIFOV3_Msk (0x1ul << EPWM_CAPSTS_CFLIFOV3_Pos) /*!< EPWM_T::CAPSTS: CFLIFOV3 Mask */ 4944 4945 #define EPWM_CAPSTS_CFLIFOV4_Pos (12) /*!< EPWM_T::CAPSTS: CFLIFOV4 Position */ 4946 #define EPWM_CAPSTS_CFLIFOV4_Msk (0x1ul << EPWM_CAPSTS_CFLIFOV4_Pos) /*!< EPWM_T::CAPSTS: CFLIFOV4 Mask */ 4947 4948 #define EPWM_CAPSTS_CFLIFOV5_Pos (13) /*!< EPWM_T::CAPSTS: CFLIFOV5 Position */ 4949 #define EPWM_CAPSTS_CFLIFOV5_Msk (0x1ul << EPWM_CAPSTS_CFLIFOV5_Pos) /*!< EPWM_T::CAPSTS: CFLIFOV5 Mask */ 4950 4951 #define EPWM_RCAPDAT0_RCAPDAT_Pos (0) /*!< EPWM_T::RCAPDAT0: RCAPDAT Position */ 4952 #define EPWM_RCAPDAT0_RCAPDAT_Msk (0xfffful << EPWM_RCAPDAT0_RCAPDAT_Pos) /*!< EPWM_T::RCAPDAT0: RCAPDAT Mask */ 4953 4954 #define EPWM_FCAPDAT0_FCAPDAT_Pos (0) /*!< EPWM_T::FCAPDAT0: FCAPDAT Position */ 4955 #define EPWM_FCAPDAT0_FCAPDAT_Msk (0xfffful << EPWM_FCAPDAT0_FCAPDAT_Pos) /*!< EPWM_T::FCAPDAT0: FCAPDAT Mask */ 4956 4957 #define EPWM_RCAPDAT1_RCAPDAT_Pos (0) /*!< EPWM_T::RCAPDAT1: RCAPDAT Position */ 4958 #define EPWM_RCAPDAT1_RCAPDAT_Msk (0xfffful << EPWM_RCAPDAT1_RCAPDAT_Pos) /*!< EPWM_T::RCAPDAT1: RCAPDAT Mask */ 4959 4960 #define EPWM_FCAPDAT1_FCAPDAT_Pos (0) /*!< EPWM_T::FCAPDAT1: FCAPDAT Position */ 4961 #define EPWM_FCAPDAT1_FCAPDAT_Msk (0xfffful << EPWM_FCAPDAT1_FCAPDAT_Pos) /*!< EPWM_T::FCAPDAT1: FCAPDAT Mask */ 4962 4963 #define EPWM_RCAPDAT2_RCAPDAT_Pos (0) /*!< EPWM_T::RCAPDAT2: RCAPDAT Position */ 4964 #define EPWM_RCAPDAT2_RCAPDAT_Msk (0xfffful << EPWM_RCAPDAT2_RCAPDAT_Pos) /*!< EPWM_T::RCAPDAT2: RCAPDAT Mask */ 4965 4966 #define EPWM_FCAPDAT2_FCAPDAT_Pos (0) /*!< EPWM_T::FCAPDAT2: FCAPDAT Position */ 4967 #define EPWM_FCAPDAT2_FCAPDAT_Msk (0xfffful << EPWM_FCAPDAT2_FCAPDAT_Pos) /*!< EPWM_T::FCAPDAT2: FCAPDAT Mask */ 4968 4969 #define EPWM_RCAPDAT3_RCAPDAT_Pos (0) /*!< EPWM_T::RCAPDAT3: RCAPDAT Position */ 4970 #define EPWM_RCAPDAT3_RCAPDAT_Msk (0xfffful << EPWM_RCAPDAT3_RCAPDAT_Pos) /*!< EPWM_T::RCAPDAT3: RCAPDAT Mask */ 4971 4972 #define EPWM_FCAPDAT3_FCAPDAT_Pos (0) /*!< EPWM_T::FCAPDAT3: FCAPDAT Position */ 4973 #define EPWM_FCAPDAT3_FCAPDAT_Msk (0xfffful << EPWM_FCAPDAT3_FCAPDAT_Pos) /*!< EPWM_T::FCAPDAT3: FCAPDAT Mask */ 4974 4975 #define EPWM_RCAPDAT4_RCAPDAT_Pos (0) /*!< EPWM_T::RCAPDAT4: RCAPDAT Position */ 4976 #define EPWM_RCAPDAT4_RCAPDAT_Msk (0xfffful << EPWM_RCAPDAT4_RCAPDAT_Pos) /*!< EPWM_T::RCAPDAT4: RCAPDAT Mask */ 4977 4978 #define EPWM_FCAPDAT4_FCAPDAT_Pos (0) /*!< EPWM_T::FCAPDAT4: FCAPDAT Position */ 4979 #define EPWM_FCAPDAT4_FCAPDAT_Msk (0xfffful << EPWM_FCAPDAT4_FCAPDAT_Pos) /*!< EPWM_T::FCAPDAT4: FCAPDAT Mask */ 4980 4981 #define EPWM_RCAPDAT5_RCAPDAT_Pos (0) /*!< EPWM_T::RCAPDAT5: RCAPDAT Position */ 4982 #define EPWM_RCAPDAT5_RCAPDAT_Msk (0xfffful << EPWM_RCAPDAT5_RCAPDAT_Pos) /*!< EPWM_T::RCAPDAT5: RCAPDAT Mask */ 4983 4984 #define EPWM_FCAPDAT5_FCAPDAT_Pos (0) /*!< EPWM_T::FCAPDAT5: FCAPDAT Position */ 4985 #define EPWM_FCAPDAT5_FCAPDAT_Msk (0xfffful << EPWM_FCAPDAT5_FCAPDAT_Pos) /*!< EPWM_T::FCAPDAT5: FCAPDAT Mask */ 4986 4987 #define EPWM_PDMACTL_CHEN0_1_Pos (0) /*!< EPWM_T::PDMACTL: CHEN0_1 Position */ 4988 #define EPWM_PDMACTL_CHEN0_1_Msk (0x1ul << EPWM_PDMACTL_CHEN0_1_Pos) /*!< EPWM_T::PDMACTL: CHEN0_1 Mask */ 4989 4990 #define EPWM_PDMACTL_CAPMOD0_1_Pos (1) /*!< EPWM_T::PDMACTL: CAPMOD0_1 Position */ 4991 #define EPWM_PDMACTL_CAPMOD0_1_Msk (0x3ul << EPWM_PDMACTL_CAPMOD0_1_Pos) /*!< EPWM_T::PDMACTL: CAPMOD0_1 Mask */ 4992 4993 #define EPWM_PDMACTL_CAPORD0_1_Pos (3) /*!< EPWM_T::PDMACTL: CAPORD0_1 Position */ 4994 #define EPWM_PDMACTL_CAPORD0_1_Msk (0x1ul << EPWM_PDMACTL_CAPORD0_1_Pos) /*!< EPWM_T::PDMACTL: CAPORD0_1 Mask */ 4995 4996 #define EPWM_PDMACTL_CHSEL0_1_Pos (4) /*!< EPWM_T::PDMACTL: CHSEL0_1 Position */ 4997 #define EPWM_PDMACTL_CHSEL0_1_Msk (0x1ul << EPWM_PDMACTL_CHSEL0_1_Pos) /*!< EPWM_T::PDMACTL: CHSEL0_1 Mask */ 4998 4999 #define EPWM_PDMACTL_CHEN2_3_Pos (8) /*!< EPWM_T::PDMACTL: CHEN2_3 Position */ 5000 #define EPWM_PDMACTL_CHEN2_3_Msk (0x1ul << EPWM_PDMACTL_CHEN2_3_Pos) /*!< EPWM_T::PDMACTL: CHEN2_3 Mask */ 5001 5002 #define EPWM_PDMACTL_CAPMOD2_3_Pos (9) /*!< EPWM_T::PDMACTL: CAPMOD2_3 Position */ 5003 #define EPWM_PDMACTL_CAPMOD2_3_Msk (0x3ul << EPWM_PDMACTL_CAPMOD2_3_Pos) /*!< EPWM_T::PDMACTL: CAPMOD2_3 Mask */ 5004 5005 #define EPWM_PDMACTL_CAPORD2_3_Pos (11) /*!< EPWM_T::PDMACTL: CAPORD2_3 Position */ 5006 #define EPWM_PDMACTL_CAPORD2_3_Msk (0x1ul << EPWM_PDMACTL_CAPORD2_3_Pos) /*!< EPWM_T::PDMACTL: CAPORD2_3 Mask */ 5007 5008 #define EPWM_PDMACTL_CHSEL2_3_Pos (12) /*!< EPWM_T::PDMACTL: CHSEL2_3 Position */ 5009 #define EPWM_PDMACTL_CHSEL2_3_Msk (0x1ul << EPWM_PDMACTL_CHSEL2_3_Pos) /*!< EPWM_T::PDMACTL: CHSEL2_3 Mask */ 5010 5011 #define EPWM_PDMACTL_CHEN4_5_Pos (16) /*!< EPWM_T::PDMACTL: CHEN4_5 Position */ 5012 #define EPWM_PDMACTL_CHEN4_5_Msk (0x1ul << EPWM_PDMACTL_CHEN4_5_Pos) /*!< EPWM_T::PDMACTL: CHEN4_5 Mask */ 5013 5014 #define EPWM_PDMACTL_CAPMOD4_5_Pos (17) /*!< EPWM_T::PDMACTL: CAPMOD4_5 Position */ 5015 #define EPWM_PDMACTL_CAPMOD4_5_Msk (0x3ul << EPWM_PDMACTL_CAPMOD4_5_Pos) /*!< EPWM_T::PDMACTL: CAPMOD4_5 Mask */ 5016 5017 #define EPWM_PDMACTL_CAPORD4_5_Pos (19) /*!< EPWM_T::PDMACTL: CAPORD4_5 Position */ 5018 #define EPWM_PDMACTL_CAPORD4_5_Msk (0x1ul << EPWM_PDMACTL_CAPORD4_5_Pos) /*!< EPWM_T::PDMACTL: CAPORD4_5 Mask */ 5019 5020 #define EPWM_PDMACTL_CHSEL4_5_Pos (20) /*!< EPWM_T::PDMACTL: CHSEL4_5 Position */ 5021 #define EPWM_PDMACTL_CHSEL4_5_Msk (0x1ul << EPWM_PDMACTL_CHSEL4_5_Pos) /*!< EPWM_T::PDMACTL: CHSEL4_5 Mask */ 5022 5023 #define EPWM_PDMACAP0_1_CAPBUF_Pos (0) /*!< EPWM_T::PDMACAP0_1: CAPBUF Position */ 5024 #define EPWM_PDMACAP0_1_CAPBUF_Msk (0xfffful << EPWM_PDMACAP0_1_CAPBUF_Pos) /*!< EPWM_T::PDMACAP0_1: CAPBUF Mask */ 5025 5026 #define EPWM_PDMACAP2_3_CAPBUF_Pos (0) /*!< EPWM_T::PDMACAP2_3: CAPBUF Position */ 5027 #define EPWM_PDMACAP2_3_CAPBUF_Msk (0xfffful << EPWM_PDMACAP2_3_CAPBUF_Pos) /*!< EPWM_T::PDMACAP2_3: CAPBUF Mask */ 5028 5029 #define EPWM_PDMACAP4_5_CAPBUF_Pos (0) /*!< EPWM_T::PDMACAP4_5: CAPBUF Position */ 5030 #define EPWM_PDMACAP4_5_CAPBUF_Msk (0xfffful << EPWM_PDMACAP4_5_CAPBUF_Pos) /*!< EPWM_T::PDMACAP4_5: CAPBUF Mask */ 5031 5032 #define EPWM_CAPIEN_CAPRIEN0_Pos (0) /*!< EPWM_T::CAPIEN: CAPRIEN0 Position */ 5033 #define EPWM_CAPIEN_CAPRIEN0_Msk (0x1ul << EPWM_CAPIEN_CAPRIEN0_Pos) /*!< EPWM_T::CAPIEN: CAPRIEN0 Mask */ 5034 5035 #define EPWM_CAPIEN_CAPRIEN1_Pos (1) /*!< EPWM_T::CAPIEN: CAPRIEN1 Position */ 5036 #define EPWM_CAPIEN_CAPRIEN1_Msk (0x1ul << EPWM_CAPIEN_CAPRIEN1_Pos) /*!< EPWM_T::CAPIEN: CAPRIEN1 Mask */ 5037 5038 #define EPWM_CAPIEN_CAPRIEN2_Pos (2) /*!< EPWM_T::CAPIEN: CAPRIEN2 Position */ 5039 #define EPWM_CAPIEN_CAPRIEN2_Msk (0x1ul << EPWM_CAPIEN_CAPRIEN2_Pos) /*!< EPWM_T::CAPIEN: CAPRIEN2 Mask */ 5040 5041 #define EPWM_CAPIEN_CAPRIEN3_Pos (3) /*!< EPWM_T::CAPIEN: CAPRIEN3 Position */ 5042 #define EPWM_CAPIEN_CAPRIEN3_Msk (0x1ul << EPWM_CAPIEN_CAPRIEN3_Pos) /*!< EPWM_T::CAPIEN: CAPRIEN3 Mask */ 5043 5044 #define EPWM_CAPIEN_CAPRIEN4_Pos (4) /*!< EPWM_T::CAPIEN: CAPRIEN4 Position */ 5045 #define EPWM_CAPIEN_CAPRIEN4_Msk (0x1ul << EPWM_CAPIEN_CAPRIEN4_Pos) /*!< EPWM_T::CAPIEN: CAPRIEN4 Mask */ 5046 5047 #define EPWM_CAPIEN_CAPRIEN5_Pos (5) /*!< EPWM_T::CAPIEN: CAPRIEN5 Position */ 5048 #define EPWM_CAPIEN_CAPRIEN5_Msk (0x1ul << EPWM_CAPIEN_CAPRIEN5_Pos) /*!< EPWM_T::CAPIEN: CAPRIEN5 Mask */ 5049 5050 #define EPWM_CAPIEN_CAPFIEN0_Pos (8) /*!< EPWM_T::CAPIEN: CAPFIEN0 Position */ 5051 #define EPWM_CAPIEN_CAPFIEN0_Msk (0x1ul << EPWM_CAPIEN_CAPFIEN0_Pos) /*!< EPWM_T::CAPIEN: CAPFIEN0 Mask */ 5052 5053 #define EPWM_CAPIEN_CAPFIEN1_Pos (9) /*!< EPWM_T::CAPIEN: CAPFIEN1 Position */ 5054 #define EPWM_CAPIEN_CAPFIEN1_Msk (0x1ul << EPWM_CAPIEN_CAPFIEN1_Pos) /*!< EPWM_T::CAPIEN: CAPFIEN1 Mask */ 5055 5056 #define EPWM_CAPIEN_CAPFIEN2_Pos (10) /*!< EPWM_T::CAPIEN: CAPFIEN2 Position */ 5057 #define EPWM_CAPIEN_CAPFIEN2_Msk (0x1ul << EPWM_CAPIEN_CAPFIEN2_Pos) /*!< EPWM_T::CAPIEN: CAPFIEN2 Mask */ 5058 5059 #define EPWM_CAPIEN_CAPFIEN3_Pos (11) /*!< EPWM_T::CAPIEN: CAPFIEN3 Position */ 5060 #define EPWM_CAPIEN_CAPFIEN3_Msk (0x1ul << EPWM_CAPIEN_CAPFIEN3_Pos) /*!< EPWM_T::CAPIEN: CAPFIEN3 Mask */ 5061 5062 #define EPWM_CAPIEN_CAPFIEN4_Pos (12) /*!< EPWM_T::CAPIEN: CAPFIEN4 Position */ 5063 #define EPWM_CAPIEN_CAPFIEN4_Msk (0x1ul << EPWM_CAPIEN_CAPFIEN4_Pos) /*!< EPWM_T::CAPIEN: CAPFIEN4 Mask */ 5064 5065 #define EPWM_CAPIEN_CAPFIEN5_Pos (13) /*!< EPWM_T::CAPIEN: CAPFIEN5 Position */ 5066 #define EPWM_CAPIEN_CAPFIEN5_Msk (0x1ul << EPWM_CAPIEN_CAPFIEN5_Pos) /*!< EPWM_T::CAPIEN: CAPFIEN5 Mask */ 5067 5068 #define EPWM_CAPIF_CRLIF0_Pos (0) /*!< EPWM_T::CAPIF: CRLIF0 Position */ 5069 #define EPWM_CAPIF_CRLIF0_Msk (0x1ul << EPWM_CAPIF_CRLIF0_Pos) /*!< EPWM_T::CAPIF: CRLIF0 Mask */ 5070 5071 #define EPWM_CAPIF_CRLIF1_Pos (1) /*!< EPWM_T::CAPIF: CRLIF1 Position */ 5072 #define EPWM_CAPIF_CRLIF1_Msk (0x1ul << EPWM_CAPIF_CRLIF1_Pos) /*!< EPWM_T::CAPIF: CRLIF1 Mask */ 5073 5074 #define EPWM_CAPIF_CRLIF2_Pos (2) /*!< EPWM_T::CAPIF: CRLIF2 Position */ 5075 #define EPWM_CAPIF_CRLIF2_Msk (0x1ul << EPWM_CAPIF_CRLIF2_Pos) /*!< EPWM_T::CAPIF: CRLIF2 Mask */ 5076 5077 #define EPWM_CAPIF_CRLIF3_Pos (3) /*!< EPWM_T::CAPIF: CRLIF3 Position */ 5078 #define EPWM_CAPIF_CRLIF3_Msk (0x1ul << EPWM_CAPIF_CRLIF3_Pos) /*!< EPWM_T::CAPIF: CRLIF3 Mask */ 5079 5080 #define EPWM_CAPIF_CRLIF4_Pos (4) /*!< EPWM_T::CAPIF: CRLIF4 Position */ 5081 #define EPWM_CAPIF_CRLIF4_Msk (0x1ul << EPWM_CAPIF_CRLIF4_Pos) /*!< EPWM_T::CAPIF: CRLIF4 Mask */ 5082 5083 #define EPWM_CAPIF_CRLIF5_Pos (5) /*!< EPWM_T::CAPIF: CRLIF5 Position */ 5084 #define EPWM_CAPIF_CRLIF5_Msk (0x1ul << EPWM_CAPIF_CRLIF5_Pos) /*!< EPWM_T::CAPIF: CRLIF5 Mask */ 5085 5086 #define EPWM_CAPIF_CFLIF0_Pos (8) /*!< EPWM_T::CAPIF: CFLIF0 Position */ 5087 #define EPWM_CAPIF_CFLIF0_Msk (0x1ul << EPWM_CAPIF_CFLIF0_Pos) /*!< EPWM_T::CAPIF: CFLIF0 Mask */ 5088 5089 #define EPWM_CAPIF_CFLIF1_Pos (9) /*!< EPWM_T::CAPIF: CFLIF1 Position */ 5090 #define EPWM_CAPIF_CFLIF1_Msk (0x1ul << EPWM_CAPIF_CFLIF1_Pos) /*!< EPWM_T::CAPIF: CFLIF1 Mask */ 5091 5092 #define EPWM_CAPIF_CFLIF2_Pos (10) /*!< EPWM_T::CAPIF: CFLIF2 Position */ 5093 #define EPWM_CAPIF_CFLIF2_Msk (0x1ul << EPWM_CAPIF_CFLIF2_Pos) /*!< EPWM_T::CAPIF: CFLIF2 Mask */ 5094 5095 #define EPWM_CAPIF_CFLIF3_Pos (11) /*!< EPWM_T::CAPIF: CFLIF3 Position */ 5096 #define EPWM_CAPIF_CFLIF3_Msk (0x1ul << EPWM_CAPIF_CFLIF3_Pos) /*!< EPWM_T::CAPIF: CFLIF3 Mask */ 5097 5098 #define EPWM_CAPIF_CFLIF4_Pos (12) /*!< EPWM_T::CAPIF: CFLIF4 Position */ 5099 #define EPWM_CAPIF_CFLIF4_Msk (0x1ul << EPWM_CAPIF_CFLIF4_Pos) /*!< EPWM_T::CAPIF: CFLIF4 Mask */ 5100 5101 #define EPWM_CAPIF_CFLIF5_Pos (13) /*!< EPWM_T::CAPIF: CFLIF5 Position */ 5102 #define EPWM_CAPIF_CFLIF5_Msk (0x1ul << EPWM_CAPIF_CFLIF5_Pos) /*!< EPWM_T::CAPIF: CFLIF5 Mask */ 5103 5104 #define EPWM_CAPNF0_CAPNFEN_Pos (0) /*!< EPWM_T::CAPNF0: CAPNFEN Position */ 5105 #define EPWM_CAPNF0_CAPNFEN_Msk (0x1ul << EPWM_CAPNF0_CAPNFEN_Pos) /*!< EPWM_T::CAPNF0: CAPNFEN Mask */ 5106 5107 #define EPWM_CAPNF0_CAPNFSEL_Pos (4) /*!< EPWM_T::CAPNF0: CAPNFSEL Position */ 5108 #define EPWM_CAPNF0_CAPNFSEL_Msk (0x7ul << EPWM_CAPNF0_CAPNFSEL_Pos) /*!< EPWM_T::CAPNF0: CAPNFSEL Mask */ 5109 5110 #define EPWM_CAPNF0_CAPNFCNT_Pos (8) /*!< EPWM_T::CAPNF0: CAPNFCNT Position */ 5111 #define EPWM_CAPNF0_CAPNFCNT_Msk (0x7ul << EPWM_CAPNF0_CAPNFCNT_Pos) /*!< EPWM_T::CAPNF0: CAPNFCNT Mask */ 5112 5113 #define EPWM_CAPNF1_CAPNFEN_Pos (0) /*!< EPWM_T::CAPNF1: CAPNFEN Position */ 5114 #define EPWM_CAPNF1_CAPNFEN_Msk (0x1ul << EPWM_CAPNF1_CAPNFEN_Pos) /*!< EPWM_T::CAPNF1: CAPNFEN Mask */ 5115 5116 #define EPWM_CAPNF1_CAPNFSEL_Pos (4) /*!< EPWM_T::CAPNF1: CAPNFSEL Position */ 5117 #define EPWM_CAPNF1_CAPNFSEL_Msk (0x7ul << EPWM_CAPNF1_CAPNFSEL_Pos) /*!< EPWM_T::CAPNF1: CAPNFSEL Mask */ 5118 5119 #define EPWM_CAPNF1_CAPNFCNT_Pos (8) /*!< EPWM_T::CAPNF1: CAPNFCNT Position */ 5120 #define EPWM_CAPNF1_CAPNFCNT_Msk (0x7ul << EPWM_CAPNF1_CAPNFCNT_Pos) /*!< EPWM_T::CAPNF1: CAPNFCNT Mask */ 5121 5122 #define EPWM_CAPNF2_CAPNFEN_Pos (0) /*!< EPWM_T::CAPNF2: CAPNFEN Position */ 5123 #define EPWM_CAPNF2_CAPNFEN_Msk (0x1ul << EPWM_CAPNF2_CAPNFEN_Pos) /*!< EPWM_T::CAPNF2: CAPNFEN Mask */ 5124 5125 #define EPWM_CAPNF2_CAPNFSEL_Pos (4) /*!< EPWM_T::CAPNF2: CAPNFSEL Position */ 5126 #define EPWM_CAPNF2_CAPNFSEL_Msk (0x7ul << EPWM_CAPNF2_CAPNFSEL_Pos) /*!< EPWM_T::CAPNF2: CAPNFSEL Mask */ 5127 5128 #define EPWM_CAPNF2_CAPNFCNT_Pos (8) /*!< EPWM_T::CAPNF2: CAPNFCNT Position */ 5129 #define EPWM_CAPNF2_CAPNFCNT_Msk (0x7ul << EPWM_CAPNF2_CAPNFCNT_Pos) /*!< EPWM_T::CAPNF2: CAPNFCNT Mask */ 5130 5131 #define EPWM_CAPNF3_CAPNFEN_Pos (0) /*!< EPWM_T::CAPNF3: CAPNFEN Position */ 5132 #define EPWM_CAPNF3_CAPNFEN_Msk (0x1ul << EPWM_CAPNF3_CAPNFEN_Pos) /*!< EPWM_T::CAPNF3: CAPNFEN Mask */ 5133 5134 #define EPWM_CAPNF3_CAPNFSEL_Pos (4) /*!< EPWM_T::CAPNF3: CAPNFSEL Position */ 5135 #define EPWM_CAPNF3_CAPNFSEL_Msk (0x7ul << EPWM_CAPNF3_CAPNFSEL_Pos) /*!< EPWM_T::CAPNF3: CAPNFSEL Mask */ 5136 5137 #define EPWM_CAPNF3_CAPNFCNT_Pos (8) /*!< EPWM_T::CAPNF3: CAPNFCNT Position */ 5138 #define EPWM_CAPNF3_CAPNFCNT_Msk (0x7ul << EPWM_CAPNF3_CAPNFCNT_Pos) /*!< EPWM_T::CAPNF3: CAPNFCNT Mask */ 5139 5140 #define EPWM_CAPNF4_CAPNFEN_Pos (0) /*!< EPWM_T::CAPNF4: CAPNFEN Position */ 5141 #define EPWM_CAPNF4_CAPNFEN_Msk (0x1ul << EPWM_CAPNF4_CAPNFEN_Pos) /*!< EPWM_T::CAPNF4: CAPNFEN Mask */ 5142 5143 #define EPWM_CAPNF4_CAPNFSEL_Pos (4) /*!< EPWM_T::CAPNF4: CAPNFSEL Position */ 5144 #define EPWM_CAPNF4_CAPNFSEL_Msk (0x7ul << EPWM_CAPNF4_CAPNFSEL_Pos) /*!< EPWM_T::CAPNF4: CAPNFSEL Mask */ 5145 5146 #define EPWM_CAPNF4_CAPNFCNT_Pos (8) /*!< EPWM_T::CAPNF4: CAPNFCNT Position */ 5147 #define EPWM_CAPNF4_CAPNFCNT_Msk (0x7ul << EPWM_CAPNF4_CAPNFCNT_Pos) /*!< EPWM_T::CAPNF4: CAPNFCNT Mask */ 5148 5149 #define EPWM_CAPNF5_CAPNFEN_Pos (0) /*!< EPWM_T::CAPNF5: CAPNFEN Position */ 5150 #define EPWM_CAPNF5_CAPNFEN_Msk (0x1ul << EPWM_CAPNF5_CAPNFEN_Pos) /*!< EPWM_T::CAPNF5: CAPNFEN Mask */ 5151 5152 #define EPWM_CAPNF5_CAPNFSEL_Pos (4) /*!< EPWM_T::CAPNF5: CAPNFSEL Position */ 5153 #define EPWM_CAPNF5_CAPNFSEL_Msk (0x7ul << EPWM_CAPNF5_CAPNFSEL_Pos) /*!< EPWM_T::CAPNF5: CAPNFSEL Mask */ 5154 5155 #define EPWM_CAPNF5_CAPNFCNT_Pos (8) /*!< EPWM_T::CAPNF5: CAPNFCNT Position */ 5156 #define EPWM_CAPNF5_CAPNFCNT_Msk (0x7ul << EPWM_CAPNF5_CAPNFCNT_Pos) /*!< EPWM_T::CAPNF5: CAPNFCNT Mask */ 5157 5158 #define EPWM_EXTETCTL0_EXETEN_Pos (0) /*!< EPWM_T::EXTETCTL0: EXETEN Position */ 5159 #define EPWM_EXTETCTL0_EXETEN_Msk (0x1ul << EPWM_EXTETCTL0_EXETEN_Pos) /*!< EPWM_T::EXTETCTL0: EXETEN Mask */ 5160 5161 #define EPWM_EXTETCTL0_CNTACTS_Pos (4) /*!< EPWM_T::EXTETCTL0: CNTACTS Position */ 5162 #define EPWM_EXTETCTL0_CNTACTS_Msk (0x3ul << EPWM_EXTETCTL0_CNTACTS_Pos) /*!< EPWM_T::EXTETCTL0: CNTACTS Mask */ 5163 5164 #define EPWM_EXTETCTL0_EXTTRGS_Pos (8) /*!< EPWM_T::EXTETCTL0: EXTTRGS Position */ 5165 #define EPWM_EXTETCTL0_EXTTRGS_Msk (0xful << EPWM_EXTETCTL0_EXTTRGS_Pos) /*!< EPWM_T::EXTETCTL0: EXTTRGS Mask */ 5166 5167 #define EPWM_EXTETCTL1_EXETEN_Pos (0) /*!< EPWM_T::EXTETCTL1: EXETEN Position */ 5168 #define EPWM_EXTETCTL1_EXETEN_Msk (0x1ul << EPWM_EXTETCTL1_EXETEN_Pos) /*!< EPWM_T::EXTETCTL1: EXETEN Mask */ 5169 5170 #define EPWM_EXTETCTL1_CNTACTS_Pos (4) /*!< EPWM_T::EXTETCTL1: CNTACTS Position */ 5171 #define EPWM_EXTETCTL1_CNTACTS_Msk (0x3ul << EPWM_EXTETCTL1_CNTACTS_Pos) /*!< EPWM_T::EXTETCTL1: CNTACTS Mask */ 5172 5173 #define EPWM_EXTETCTL1_EXTTRGS_Pos (8) /*!< EPWM_T::EXTETCTL1: EXTTRGS Position */ 5174 #define EPWM_EXTETCTL1_EXTTRGS_Msk (0xful << EPWM_EXTETCTL1_EXTTRGS_Pos) /*!< EPWM_T::EXTETCTL1: EXTTRGS Mask */ 5175 5176 #define EPWM_EXTETCTL2_EXETEN_Pos (0) /*!< EPWM_T::EXTETCTL2: EXETEN Position */ 5177 #define EPWM_EXTETCTL2_EXETEN_Msk (0x1ul << EPWM_EXTETCTL2_EXETEN_Pos) /*!< EPWM_T::EXTETCTL2: EXETEN Mask */ 5178 5179 #define EPWM_EXTETCTL2_CNTACTS_Pos (4) /*!< EPWM_T::EXTETCTL2: CNTACTS Position */ 5180 #define EPWM_EXTETCTL2_CNTACTS_Msk (0x3ul << EPWM_EXTETCTL2_CNTACTS_Pos) /*!< EPWM_T::EXTETCTL2: CNTACTS Mask */ 5181 5182 #define EPWM_EXTETCTL2_EXTTRGS_Pos (8) /*!< EPWM_T::EXTETCTL2: EXTTRGS Position */ 5183 #define EPWM_EXTETCTL2_EXTTRGS_Msk (0xful << EPWM_EXTETCTL2_EXTTRGS_Pos) /*!< EPWM_T::EXTETCTL2: EXTTRGS Mask */ 5184 5185 #define EPWM_EXTETCTL3_EXETEN_Pos (0) /*!< EPWM_T::EXTETCTL3: EXETEN Position */ 5186 #define EPWM_EXTETCTL3_EXETEN_Msk (0x1ul << EPWM_EXTETCTL3_EXETEN_Pos) /*!< EPWM_T::EXTETCTL3: EXETEN Mask */ 5187 5188 #define EPWM_EXTETCTL3_CNTACTS_Pos (4) /*!< EPWM_T::EXTETCTL3: CNTACTS Position */ 5189 #define EPWM_EXTETCTL3_CNTACTS_Msk (0x3ul << EPWM_EXTETCTL3_CNTACTS_Pos) /*!< EPWM_T::EXTETCTL3: CNTACTS Mask */ 5190 5191 #define EPWM_EXTETCTL3_EXTTRGS_Pos (8) /*!< EPWM_T::EXTETCTL3: EXTTRGS Position */ 5192 #define EPWM_EXTETCTL3_EXTTRGS_Msk (0xful << EPWM_EXTETCTL3_EXTTRGS_Pos) /*!< EPWM_T::EXTETCTL3: EXTTRGS Mask */ 5193 5194 #define EPWM_EXTETCTL4_EXETEN_Pos (0) /*!< EPWM_T::EXTETCTL4: EXETEN Position */ 5195 #define EPWM_EXTETCTL4_EXETEN_Msk (0x1ul << EPWM_EXTETCTL4_EXETEN_Pos) /*!< EPWM_T::EXTETCTL4: EXETEN Mask */ 5196 5197 #define EPWM_EXTETCTL4_CNTACTS_Pos (4) /*!< EPWM_T::EXTETCTL4: CNTACTS Position */ 5198 #define EPWM_EXTETCTL4_CNTACTS_Msk (0x3ul << EPWM_EXTETCTL4_CNTACTS_Pos) /*!< EPWM_T::EXTETCTL4: CNTACTS Mask */ 5199 5200 #define EPWM_EXTETCTL4_EXTTRGS_Pos (8) /*!< EPWM_T::EXTETCTL4: EXTTRGS Position */ 5201 #define EPWM_EXTETCTL4_EXTTRGS_Msk (0xful << EPWM_EXTETCTL4_EXTTRGS_Pos) /*!< EPWM_T::EXTETCTL4: EXTTRGS Mask */ 5202 5203 #define EPWM_EXTETCTL5_EXETEN_Pos (0) /*!< EPWM_T::EXTETCTL5: EXETEN Position */ 5204 #define EPWM_EXTETCTL5_EXETEN_Msk (0x1ul << EPWM_EXTETCTL5_EXETEN_Pos) /*!< EPWM_T::EXTETCTL5: EXETEN Mask */ 5205 5206 #define EPWM_EXTETCTL5_CNTACTS_Pos (4) /*!< EPWM_T::EXTETCTL5: CNTACTS Position */ 5207 #define EPWM_EXTETCTL5_CNTACTS_Msk (0x3ul << EPWM_EXTETCTL5_CNTACTS_Pos) /*!< EPWM_T::EXTETCTL5: CNTACTS Mask */ 5208 5209 #define EPWM_EXTETCTL5_EXTTRGS_Pos (8) /*!< EPWM_T::EXTETCTL5: EXTTRGS Position */ 5210 #define EPWM_EXTETCTL5_EXTTRGS_Msk (0xful << EPWM_EXTETCTL5_EXTTRGS_Pos) /*!< EPWM_T::EXTETCTL5: EXTTRGS Mask */ 5211 5212 #define EPWM_SWEOFCTL_OUTACTS0_Pos (0) /*!< EPWM_T::SWEOFCTL: OUTACTS0 Position */ 5213 #define EPWM_SWEOFCTL_OUTACTS0_Msk (0x3ul << EPWM_SWEOFCTL_OUTACTS0_Pos) /*!< EPWM_T::SWEOFCTL: OUTACTS0 Mask */ 5214 5215 #define EPWM_SWEOFCTL_OUTACTS1_Pos (2) /*!< EPWM_T::SWEOFCTL: OUTACTS1 Position */ 5216 #define EPWM_SWEOFCTL_OUTACTS1_Msk (0x3ul << EPWM_SWEOFCTL_OUTACTS1_Pos) /*!< EPWM_T::SWEOFCTL: OUTACTS1 Mask */ 5217 5218 #define EPWM_SWEOFCTL_OUTACTS2_Pos (4) /*!< EPWM_T::SWEOFCTL: OUTACTS2 Position */ 5219 #define EPWM_SWEOFCTL_OUTACTS2_Msk (0x3ul << EPWM_SWEOFCTL_OUTACTS2_Pos) /*!< EPWM_T::SWEOFCTL: OUTACTS2 Mask */ 5220 5221 #define EPWM_SWEOFCTL_OUTACTS3_Pos (6) /*!< EPWM_T::SWEOFCTL: OUTACTS3 Position */ 5222 #define EPWM_SWEOFCTL_OUTACTS3_Msk (0x3ul << EPWM_SWEOFCTL_OUTACTS3_Pos) /*!< EPWM_T::SWEOFCTL: OUTACTS3 Mask */ 5223 5224 #define EPWM_SWEOFCTL_OUTACTS4_Pos (8) /*!< EPWM_T::SWEOFCTL: OUTACTS4 Position */ 5225 #define EPWM_SWEOFCTL_OUTACTS4_Msk (0x3ul << EPWM_SWEOFCTL_OUTACTS4_Pos) /*!< EPWM_T::SWEOFCTL: OUTACTS4 Mask */ 5226 5227 #define EPWM_SWEOFCTL_OUTACTS5_Pos (10) /*!< EPWM_T::SWEOFCTL: OUTACTS5 Position */ 5228 #define EPWM_SWEOFCTL_OUTACTS5_Msk (0x3ul << EPWM_SWEOFCTL_OUTACTS5_Pos) /*!< EPWM_T::SWEOFCTL: OUTACTS5 Mask */ 5229 5230 #define EPWM_SWEOFTRG_SWETRG0_Pos (0) /*!< EPWM_T::SWEOFTRG: SWETRG0 Position */ 5231 #define EPWM_SWEOFTRG_SWETRG0_Msk (0x1ul << EPWM_SWEOFTRG_SWETRG0_Pos) /*!< EPWM_T::SWEOFTRG: SWETRG0 Mask */ 5232 5233 #define EPWM_SWEOFTRG_SWETRG1_Pos (1) /*!< EPWM_T::SWEOFTRG: SWETRG1 Position */ 5234 #define EPWM_SWEOFTRG_SWETRG1_Msk (0x1ul << EPWM_SWEOFTRG_SWETRG1_Pos) /*!< EPWM_T::SWEOFTRG: SWETRG1 Mask */ 5235 5236 #define EPWM_SWEOFTRG_SWETRG2_Pos (2) /*!< EPWM_T::SWEOFTRG: SWETRG2 Position */ 5237 #define EPWM_SWEOFTRG_SWETRG2_Msk (0x1ul << EPWM_SWEOFTRG_SWETRG2_Pos) /*!< EPWM_T::SWEOFTRG: SWETRG2 Mask */ 5238 5239 #define EPWM_SWEOFTRG_SWETRG3_Pos (3) /*!< EPWM_T::SWEOFTRG: SWETRG3 Position */ 5240 #define EPWM_SWEOFTRG_SWETRG3_Msk (0x1ul << EPWM_SWEOFTRG_SWETRG3_Pos) /*!< EPWM_T::SWEOFTRG: SWETRG3 Mask */ 5241 5242 #define EPWM_SWEOFTRG_SWETRG4_Pos (4) /*!< EPWM_T::SWEOFTRG: SWETRG4 Position */ 5243 #define EPWM_SWEOFTRG_SWETRG4_Msk (0x1ul << EPWM_SWEOFTRG_SWETRG4_Pos) /*!< EPWM_T::SWEOFTRG: SWETRG4 Mask */ 5244 5245 #define EPWM_SWEOFTRG_SWETRG5_Pos (5) /*!< EPWM_T::SWEOFTRG: SWETRG5 Position */ 5246 #define EPWM_SWEOFTRG_SWETRG5_Msk (0x1ul << EPWM_SWEOFTRG_SWETRG5_Pos) /*!< EPWM_T::SWEOFTRG: SWETRG5 Mask */ 5247 5248 #define EPWM_CLKPSC0_CLKPSC_Pos (0) /*!< EPWM_T::CLKPSC0: CLKPSC Position */ 5249 #define EPWM_CLKPSC0_CLKPSC_Msk (0xffful << EPWM_CLKPSC0_CLKPSC_Pos) /*!< EPWM_T::CLKPSC0: CLKPSC Mask */ 5250 5251 #define EPWM_CLKPSC1_CLKPSC_Pos (0) /*!< EPWM_T::CLKPSC1: CLKPSC Position */ 5252 #define EPWM_CLKPSC1_CLKPSC_Msk (0xffful << EPWM_CLKPSC1_CLKPSC_Pos) /*!< EPWM_T::CLKPSC1: CLKPSC Mask */ 5253 5254 #define EPWM_CLKPSC2_CLKPSC_Pos (0) /*!< EPWM_T::CLKPSC2: CLKPSC Position */ 5255 #define EPWM_CLKPSC2_CLKPSC_Msk (0xffful << EPWM_CLKPSC2_CLKPSC_Pos) /*!< EPWM_T::CLKPSC2: CLKPSC Mask */ 5256 5257 #define EPWM_CLKPSC3_CLKPSC_Pos (0) /*!< EPWM_T::CLKPSC3: CLKPSC Position */ 5258 #define EPWM_CLKPSC3_CLKPSC_Msk (0xffful << EPWM_CLKPSC3_CLKPSC_Pos) /*!< EPWM_T::CLKPSC3: CLKPSC Mask */ 5259 5260 #define EPWM_CLKPSC4_CLKPSC_Pos (0) /*!< EPWM_T::CLKPSC4: CLKPSC Position */ 5261 #define EPWM_CLKPSC4_CLKPSC_Msk (0xffful << EPWM_CLKPSC4_CLKPSC_Pos) /*!< EPWM_T::CLKPSC4: CLKPSC Mask */ 5262 5263 #define EPWM_CLKPSC5_CLKPSC_Pos (0) /*!< EPWM_T::CLKPSC5: CLKPSC Position */ 5264 #define EPWM_CLKPSC5_CLKPSC_Msk (0xffful << EPWM_CLKPSC5_CLKPSC_Pos) /*!< EPWM_T::CLKPSC5: CLKPSC Mask */ 5265 5266 #define EPWM_RDTCNT0_1_RDTCNT_Pos (0) /*!< EPWM_T::RDTCNT0_1: RDTCNT Position */ 5267 #define EPWM_RDTCNT0_1_RDTCNT_Msk (0xffful << EPWM_RDTCNT0_1_RDTCNT_Pos) /*!< EPWM_T::RDTCNT0_1: RDTCNT Mask */ 5268 5269 #define EPWM_RDTCNT2_3_RDTCNT_Pos (0) /*!< EPWM_T::RDTCNT2_3: RDTCNT Position */ 5270 #define EPWM_RDTCNT2_3_RDTCNT_Msk (0xffful << EPWM_RDTCNT2_3_RDTCNT_Pos) /*!< EPWM_T::RDTCNT2_3: RDTCNT Mask */ 5271 5272 #define EPWM_RDTCNT4_5_RDTCNT_Pos (0) /*!< EPWM_T::RDTCNT4_5: RDTCNT Position */ 5273 #define EPWM_RDTCNT4_5_RDTCNT_Msk (0xffful << EPWM_RDTCNT4_5_RDTCNT_Pos) /*!< EPWM_T::RDTCNT4_5: RDTCNT Mask */ 5274 5275 #define EPWM_FDTCNT0_1_FDTCNT_Pos (0) /*!< EPWM_T::FDTCNT0_1: FDTCNT Position */ 5276 #define EPWM_FDTCNT0_1_FDTCNT_Msk (0xffful << EPWM_FDTCNT0_1_FDTCNT_Pos) /*!< EPWM_T::FDTCNT0_1: FDTCNT Mask */ 5277 5278 #define EPWM_FDTCNT2_3_FDTCNT_Pos (0) /*!< EPWM_T::FDTCNT2_3: FDTCNT Position */ 5279 #define EPWM_FDTCNT2_3_FDTCNT_Msk (0xffful << EPWM_FDTCNT2_3_FDTCNT_Pos) /*!< EPWM_T::FDTCNT2_3: FDTCNT Mask */ 5280 5281 #define EPWM_FDTCNT4_5_FDTCNT_Pos (0) /*!< EPWM_T::FDTCNT4_5: FDTCNT Position */ 5282 #define EPWM_FDTCNT4_5_FDTCNT_Msk (0xffful << EPWM_FDTCNT4_5_FDTCNT_Pos) /*!< EPWM_T::FDTCNT4_5: FDTCNT Mask */ 5283 5284 #define EPWM_DTCTL_RDTEN0_Pos (0) /*!< EPWM_T::DTCTL: RDTEN0 Position */ 5285 #define EPWM_DTCTL_RDTEN0_Msk (0x1ul << EPWM_DTCTL_RDTEN0_Pos) /*!< EPWM_T::DTCTL: RDTEN0 Mask */ 5286 5287 #define EPWM_DTCTL_RDTEN2_Pos (1) /*!< EPWM_T::DTCTL: RDTEN2 Position */ 5288 #define EPWM_DTCTL_RDTEN2_Msk (0x1ul << EPWM_DTCTL_RDTEN2_Pos) /*!< EPWM_T::DTCTL: RDTEN2 Mask */ 5289 5290 #define EPWM_DTCTL_RDTEN4_Pos (2) /*!< EPWM_T::DTCTL: RDTEN4 Position */ 5291 #define EPWM_DTCTL_RDTEN4_Msk (0x1ul << EPWM_DTCTL_RDTEN4_Pos) /*!< EPWM_T::DTCTL: RDTEN4 Mask */ 5292 5293 #define EPWM_DTCTL_FDTEN0_Pos (8) /*!< EPWM_T::DTCTL: FDTEN0 Position */ 5294 #define EPWM_DTCTL_FDTEN0_Msk (0x1ul << EPWM_DTCTL_FDTEN0_Pos) /*!< EPWM_T::DTCTL: FDTEN0 Mask */ 5295 5296 #define EPWM_DTCTL_FDTEN2_Pos (9) /*!< EPWM_T::DTCTL: FDTEN2 Position */ 5297 #define EPWM_DTCTL_FDTEN2_Msk (0x1ul << EPWM_DTCTL_FDTEN2_Pos) /*!< EPWM_T::DTCTL: FDTEN2 Mask */ 5298 5299 #define EPWM_DTCTL_FDTEN4_Pos (10) /*!< EPWM_T::DTCTL: FDTEN4 Position */ 5300 #define EPWM_DTCTL_FDTEN4_Msk (0x1ul << EPWM_DTCTL_FDTEN4_Pos) /*!< EPWM_T::DTCTL: FDTEN4 Mask */ 5301 5302 #define EPWM_DTCTL_DTCKSEL0_Pos (16) /*!< EPWM_T::DTCTL: DTCKSEL0 Position */ 5303 #define EPWM_DTCTL_DTCKSEL0_Msk (0x1ul << EPWM_DTCTL_DTCKSEL0_Pos) /*!< EPWM_T::DTCTL: DTCKSEL0 Mask */ 5304 5305 #define EPWM_DTCTL_DTCKSEL2_Pos (17) /*!< EPWM_T::DTCTL: DTCKSEL2 Position */ 5306 #define EPWM_DTCTL_DTCKSEL2_Msk (0x1ul << EPWM_DTCTL_DTCKSEL2_Pos) /*!< EPWM_T::DTCTL: DTCKSEL2 Mask */ 5307 5308 #define EPWM_DTCTL_DTCKSEL4_Pos (18) /*!< EPWM_T::DTCTL: DTCKSEL4 Position */ 5309 #define EPWM_DTCTL_DTCKSEL4_Msk (0x1ul << EPWM_DTCTL_DTCKSEL4_Pos) /*!< EPWM_T::DTCTL: DTCKSEL4 Mask */ 5310 5311 #define EPWM_PBUF0_PBUF_Pos (0) /*!< EPWM_T::PBUF0: PBUF Position */ 5312 #define EPWM_PBUF0_PBUF_Msk (0xfffful << EPWM_PBUF0_PBUF_Pos) /*!< EPWM_T::PBUF0: PBUF Mask */ 5313 5314 #define EPWM_PBUF1_PBUF_Pos (0) /*!< EPWM_T::PBUF1: PBUF Position */ 5315 #define EPWM_PBUF1_PBUF_Msk (0xfffful << EPWM_PBUF1_PBUF_Pos) /*!< EPWM_T::PBUF1: PBUF Mask */ 5316 5317 #define EPWM_PBUF2_PBUF_Pos (0) /*!< EPWM_T::PBUF2: PBUF Position */ 5318 #define EPWM_PBUF2_PBUF_Msk (0xfffful << EPWM_PBUF2_PBUF_Pos) /*!< EPWM_T::PBUF2: PBUF Mask */ 5319 5320 #define EPWM_PBUF3_PBUF_Pos (0) /*!< EPWM_T::PBUF3: PBUF Position */ 5321 #define EPWM_PBUF3_PBUF_Msk (0xfffful << EPWM_PBUF3_PBUF_Pos) /*!< EPWM_T::PBUF3: PBUF Mask */ 5322 5323 #define EPWM_PBUF4_PBUF_Pos (0) /*!< EPWM_T::PBUF4: PBUF Position */ 5324 #define EPWM_PBUF4_PBUF_Msk (0xfffful << EPWM_PBUF4_PBUF_Pos) /*!< EPWM_T::PBUF4: PBUF Mask */ 5325 5326 #define EPWM_PBUF5_PBUF_Pos (0) /*!< EPWM_T::PBUF5: PBUF Position */ 5327 #define EPWM_PBUF5_PBUF_Msk (0xfffful << EPWM_PBUF5_PBUF_Pos) /*!< EPWM_T::PBUF5: PBUF Mask */ 5328 5329 #define EPWM_CMPBUF0_CMPBUF_Pos (0) /*!< EPWM_T::CMPBUF0: CMPBUF Position */ 5330 #define EPWM_CMPBUF0_CMPBUF_Msk (0xfffful << EPWM_CMPBUF0_CMPBUF_Pos) /*!< EPWM_T::CMPBUF0: CMPBUF Mask */ 5331 5332 #define EPWM_CMPBUF1_CMPBUF_Pos (0) /*!< EPWM_T::CMPBUF1: CMPBUF Position */ 5333 #define EPWM_CMPBUF1_CMPBUF_Msk (0xfffful << EPWM_CMPBUF1_CMPBUF_Pos) /*!< EPWM_T::CMPBUF1: CMPBUF Mask */ 5334 5335 #define EPWM_CMPBUF2_CMPBUF_Pos (0) /*!< EPWM_T::CMPBUF2: CMPBUF Position */ 5336 #define EPWM_CMPBUF2_CMPBUF_Msk (0xfffful << EPWM_CMPBUF2_CMPBUF_Pos) /*!< EPWM_T::CMPBUF2: CMPBUF Mask */ 5337 5338 #define EPWM_CMPBUF3_CMPBUF_Pos (0) /*!< EPWM_T::CMPBUF3: CMPBUF Position */ 5339 #define EPWM_CMPBUF3_CMPBUF_Msk (0xfffful << EPWM_CMPBUF3_CMPBUF_Pos) /*!< EPWM_T::CMPBUF3: CMPBUF Mask */ 5340 5341 #define EPWM_CMPBUF4_CMPBUF_Pos (0) /*!< EPWM_T::CMPBUF4: CMPBUF Position */ 5342 #define EPWM_CMPBUF4_CMPBUF_Msk (0xfffful << EPWM_CMPBUF4_CMPBUF_Pos) /*!< EPWM_T::CMPBUF4: CMPBUF Mask */ 5343 5344 #define EPWM_CMPBUF5_CMPBUF_Pos (0) /*!< EPWM_T::CMPBUF5: CMPBUF Position */ 5345 #define EPWM_CMPBUF5_CMPBUF_Msk (0xfffful << EPWM_CMPBUF5_CMPBUF_Pos) /*!< EPWM_T::CMPBUF5: CMPBUF Mask */ 5346 5347 #define EPWM_FTCBUF0_1_FTCMPBUF_Pos (0) /*!< EPWM_T::FTCBUF0_1: FTCMPBUF Position */ 5348 #define EPWM_FTCBUF0_1_FTCMPBUF_Msk (0xfffful << EPWM_FTCBUF0_1_FTCMPBUF_Pos) /*!< EPWM_T::FTCBUF0_1: FTCMPBUF Mask */ 5349 5350 #define EPWM_FTCBUF2_3_FTCMPBUF_Pos (0) /*!< EPWM_T::FTCBUF2_3: FTCMPBUF Position */ 5351 #define EPWM_FTCBUF2_3_FTCMPBUF_Msk (0xfffful << EPWM_FTCBUF2_3_FTCMPBUF_Pos) /*!< EPWM_T::FTCBUF2_3: FTCMPBUF Mask */ 5352 5353 #define EPWM_FTCBUF4_5_FTCMPBUF_Pos (0) /*!< EPWM_T::FTCBUF4_5: FTCMPBUF Position */ 5354 #define EPWM_FTCBUF4_5_FTCMPBUF_Msk (0xfffful << EPWM_FTCBUF4_5_FTCMPBUF_Pos) /*!< EPWM_T::FTCBUF4_5: FTCMPBUF Mask */ 5355 5356 #define EPWM_FTCI_FTCMU0_Pos (0) /*!< EPWM_T::FTCI: FTCMU0 Position */ 5357 #define EPWM_FTCI_FTCMU0_Msk (0x1ul << EPWM_FTCI_FTCMU0_Pos) /*!< EPWM_T::FTCI: FTCMU0 Mask */ 5358 5359 #define EPWM_FTCI_FTCMU2_Pos (1) /*!< EPWM_T::FTCI: FTCMU2 Position */ 5360 #define EPWM_FTCI_FTCMU2_Msk (0x1ul << EPWM_FTCI_FTCMU2_Pos) /*!< EPWM_T::FTCI: FTCMU2 Mask */ 5361 5362 #define EPWM_FTCI_FTCMU4_Pos (2) /*!< EPWM_T::FTCI: FTCMU4 Position */ 5363 #define EPWM_FTCI_FTCMU4_Msk (0x1ul << EPWM_FTCI_FTCMU4_Pos) /*!< EPWM_T::FTCI: FTCMU4 Mask */ 5364 5365 #define EPWM_FTCI_FTCMD0_Pos (8) /*!< EPWM_T::FTCI: FTCMD0 Position */ 5366 #define EPWM_FTCI_FTCMD0_Msk (0x1ul << EPWM_FTCI_FTCMD0_Pos) /*!< EPWM_T::FTCI: FTCMD0 Mask */ 5367 5368 #define EPWM_FTCI_FTCMD2_Pos (9) /*!< EPWM_T::FTCI: FTCMD2 Position */ 5369 #define EPWM_FTCI_FTCMD2_Msk (0x1ul << EPWM_FTCI_FTCMD2_Pos) /*!< EPWM_T::FTCI: FTCMD2 Mask */ 5370 5371 #define EPWM_FTCI_FTCMD4_Pos (10) /*!< EPWM_T::FTCI: FTCMD4 Position */ 5372 #define EPWM_FTCI_FTCMD4_Msk (0x1ul << EPWM_FTCI_FTCMD4_Pos) /*!< EPWM_T::FTCI: FTCMD4 Mask */ 5373 5374 #define EPWM_CPSCBUF0_CPSCBUF_Pos (0) /*!< EPWM_T::CPSCBUF0: CPSCBUF Position */ 5375 #define EPWM_CPSCBUF0_CPSCBUF_Msk (0xffful << EPWM_CPSCBUF0_CPSCBUF_Pos) /*!< EPWM_T::CPSCBUF0: CPSCBUF Mask */ 5376 5377 #define EPWM_CPSCBUF1_CPSCBUF_Pos (0) /*!< EPWM_T::CPSCBUF1: CPSCBUF Position */ 5378 #define EPWM_CPSCBUF1_CPSCBUF_Msk (0xffful << EPWM_CPSCBUF1_CPSCBUF_Pos) /*!< EPWM_T::CPSCBUF1: CPSCBUF Mask */ 5379 5380 #define EPWM_CPSCBUF2_CPSCBUF_Pos (0) /*!< EPWM_T::CPSCBUF2: CPSCBUF Position */ 5381 #define EPWM_CPSCBUF2_CPSCBUF_Msk (0xffful << EPWM_CPSCBUF2_CPSCBUF_Pos) /*!< EPWM_T::CPSCBUF2: CPSCBUF Mask */ 5382 5383 #define EPWM_CPSCBUF3_CPSCBUF_Pos (0) /*!< EPWM_T::CPSCBUF3: CPSCBUF Position */ 5384 #define EPWM_CPSCBUF3_CPSCBUF_Msk (0xffful << EPWM_CPSCBUF3_CPSCBUF_Pos) /*!< EPWM_T::CPSCBUF3: CPSCBUF Mask */ 5385 5386 #define EPWM_CPSCBUF4_CPSCBUF_Pos (0) /*!< EPWM_T::CPSCBUF4: CPSCBUF Position */ 5387 #define EPWM_CPSCBUF4_CPSCBUF_Msk (0xffful << EPWM_CPSCBUF4_CPSCBUF_Pos) /*!< EPWM_T::CPSCBUF4: CPSCBUF Mask */ 5388 5389 #define EPWM_CPSCBUF5_CPSCBUF_Pos (0) /*!< EPWM_T::CPSCBUF5: CPSCBUF Position */ 5390 #define EPWM_CPSCBUF5_CPSCBUF_Msk (0xffful << EPWM_CPSCBUF5_CPSCBUF_Pos) /*!< EPWM_T::CPSCBUF5: CPSCBUF Mask */ 5391 5392 #define EPWM_IFACNT0_ACUCNT_Pos (0) /*!< EPWM_T::IFACNT0: ACUCNT Position */ 5393 #define EPWM_IFACNT0_ACUCNT_Msk (0xfffful << EPWM_IFACNT0_ACUCNT_Pos) /*!< EPWM_T::IFACNT0: ACUCNT Mask */ 5394 5395 #define EPWM_IFACNT1_ACUCNT_Pos (0) /*!< EPWM_T::IFACNT1: ACUCNT Position */ 5396 #define EPWM_IFACNT1_ACUCNT_Msk (0xfffful << EPWM_IFACNT1_ACUCNT_Pos) /*!< EPWM_T::IFACNT1: ACUCNT Mask */ 5397 5398 #define EPWM_IFACNT2_ACUCNT_Pos (0) /*!< EPWM_T::IFACNT2: ACUCNT Position */ 5399 #define EPWM_IFACNT2_ACUCNT_Msk (0xfffful << EPWM_IFACNT2_ACUCNT_Pos) /*!< EPWM_T::IFACNT2: ACUCNT Mask */ 5400 5401 #define EPWM_IFACNT3_ACUCNT_Pos (0) /*!< EPWM_T::IFACNT3: ACUCNT Position */ 5402 #define EPWM_IFACNT3_ACUCNT_Msk (0xfffful << EPWM_IFACNT3_ACUCNT_Pos) /*!< EPWM_T::IFACNT3: ACUCNT Mask */ 5403 5404 #define EPWM_IFACNT4_ACUCNT_Pos (0) /*!< EPWM_T::IFACNT4: ACUCNT Position */ 5405 #define EPWM_IFACNT4_ACUCNT_Msk (0xfffful << EPWM_IFACNT4_ACUCNT_Pos) /*!< EPWM_T::IFACNT4: ACUCNT Mask */ 5406 5407 #define EPWM_IFACNT5_ACUCNT_Pos (0) /*!< EPWM_T::IFACNT5: ACUCNT Position */ 5408 #define EPWM_IFACNT5_ACUCNT_Msk (0xfffful << EPWM_IFACNT5_ACUCNT_Pos) /*!< EPWM_T::IFACNT5: ACUCNT Mask */ 5409 5410 /**@}*/ /* EPWM_CONST */ 5411 /**@}*/ /* end of EPWM register group */ 5412 /**@}*/ /* end of REGISTER group */ 5413 5414 #if defined ( __CC_ARM ) 5415 #pragma no_anon_unions 5416 #endif 5417 5418 #endif /* __EPWM_REG_H__ */ 5419
