1 /*! 2 \file gd32f4xx_rcu.h 3 \brief definitions for the RCU 4 5 \version 2016-08-15, V1.0.0, firmware for GD32F4xx 6 \version 2018-12-12, V2.0.0, firmware for GD32F4xx 7 \version 2020-09-30, V2.1.0, firmware for GD32F4xx 8 \version 2022-03-09, V3.0.0, firmware for GD32F4xx 9 */ 10 11 /* 12 Copyright (c) 2022, GigaDevice Semiconductor Inc. 13 14 Redistribution and use in source and binary forms, with or without modification, 15 are permitted provided that the following conditions are met: 16 17 1. Redistributions of source code must retain the above copyright notice, this 18 list of conditions and the following disclaimer. 19 2. Redistributions in binary form must reproduce the above copyright notice, 20 this list of conditions and the following disclaimer in the documentation 21 and/or other materials provided with the distribution. 22 3. Neither the name of the copyright holder nor the names of its contributors 23 may be used to endorse or promote products derived from this software without 24 specific prior written permission. 25 26 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 27 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 28 WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 29 IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 30 INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 31 NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 32 PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 33 WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 35 OF SUCH DAMAGE. 36 */ 37 38 #ifndef GD32F4XX_RCU_H 39 #define GD32F4XX_RCU_H 40 41 #include "gd32f4xx.h" 42 43 /* RCU definitions */ 44 #define RCU RCU_BASE 45 46 /* registers definitions */ 47 #define RCU_CTL REG32(RCU + 0x00U) /*!< control register */ 48 #define RCU_PLL REG32(RCU + 0x04U) /*!< PLL register */ 49 #define RCU_CFG0 REG32(RCU + 0x08U) /*!< clock configuration register 0 */ 50 #define RCU_INT REG32(RCU + 0x0CU) /*!< clock interrupt register */ 51 #define RCU_AHB1RST REG32(RCU + 0x10U) /*!< AHB1 reset register */ 52 #define RCU_AHB2RST REG32(RCU + 0x14U) /*!< AHB2 reset register */ 53 #define RCU_AHB3RST REG32(RCU + 0x18U) /*!< AHB3 reset register */ 54 #define RCU_APB1RST REG32(RCU + 0x20U) /*!< APB1 reset register */ 55 #define RCU_APB2RST REG32(RCU + 0x24U) /*!< APB2 reset register */ 56 #define RCU_AHB1EN REG32(RCU + 0x30U) /*!< AHB1 enable register */ 57 #define RCU_AHB2EN REG32(RCU + 0x34U) /*!< AHB2 enable register */ 58 #define RCU_AHB3EN REG32(RCU + 0x38U) /*!< AHB3 enable register */ 59 #define RCU_APB1EN REG32(RCU + 0x40U) /*!< APB1 enable register */ 60 #define RCU_APB2EN REG32(RCU + 0x44U) /*!< APB2 enable register */ 61 #define RCU_AHB1SPEN REG32(RCU + 0x50U) /*!< AHB1 sleep mode enable register */ 62 #define RCU_AHB2SPEN REG32(RCU + 0x54U) /*!< AHB2 sleep mode enable register */ 63 #define RCU_AHB3SPEN REG32(RCU + 0x58U) /*!< AHB3 sleep mode enable register */ 64 #define RCU_APB1SPEN REG32(RCU + 0x60U) /*!< APB1 sleep mode enable register */ 65 #define RCU_APB2SPEN REG32(RCU + 0x64U) /*!< APB2 sleep mode enable register */ 66 #define RCU_BDCTL REG32(RCU + 0x70U) /*!< backup domain control register */ 67 #define RCU_RSTSCK REG32(RCU + 0x74U) /*!< reset source / clock register */ 68 #define RCU_PLLSSCTL REG32(RCU + 0x80U) /*!< PLL clock spread spectrum control register */ 69 #define RCU_PLLI2S REG32(RCU + 0x84U) /*!< PLLI2S register */ 70 #define RCU_PLLSAI REG32(RCU + 0x88U) /*!< PLLSAI register */ 71 #define RCU_CFG1 REG32(RCU + 0x8CU) /*!< clock configuration register 1 */ 72 #define RCU_ADDCTL REG32(RCU + 0xC0U) /*!< Additional clock control register */ 73 #define RCU_ADDINT REG32(RCU + 0xCCU) /*!< Additional clock interrupt register */ 74 #define RCU_ADDAPB1RST REG32(RCU + 0xE0U) /*!< APB1 additional reset register */ 75 #define RCU_ADDAPB1EN REG32(RCU + 0xE4U) /*!< APB1 additional enable register */ 76 #define RCU_ADDAPB1SPEN REG32(RCU + 0xE8U) /*!< APB1 additional sleep mode enable register */ 77 #define RCU_VKEY REG32(RCU + 0x100U) /*!< voltage key register */ 78 #define RCU_DSV REG32(RCU + 0x134U) /*!< deep-sleep mode voltage register */ 79 80 /* bits definitions */ 81 /* RCU_CTL */ 82 #define RCU_CTL_IRC16MEN BIT(0) /*!< internal high speed oscillator enable */ 83 #define RCU_CTL_IRC16MSTB BIT(1) /*!< IRC16M high speed internal oscillator stabilization flag */ 84 #define RCU_CTL_IRC16MADJ BITS(3,7) /*!< high speed internal oscillator clock trim adjust value */ 85 #define RCU_CTL_IRC16MCALIB BITS(8,15) /*!< high speed internal oscillator calibration value register */ 86 #define RCU_CTL_HXTALEN BIT(16) /*!< external high speed oscillator enable */ 87 #define RCU_CTL_HXTALSTB BIT(17) /*!< external crystal oscillator clock stabilization flag */ 88 #define RCU_CTL_HXTALBPS BIT(18) /*!< external crystal oscillator clock bypass mode enable */ 89 #define RCU_CTL_CKMEN BIT(19) /*!< HXTAL clock monitor enable */ 90 #define RCU_CTL_PLLEN BIT(24) /*!< PLL enable */ 91 #define RCU_CTL_PLLSTB BIT(25) /*!< PLL Clock Stabilization Flag */ 92 #define RCU_CTL_PLLI2SEN BIT(26) /*!< PLLI2S enable */ 93 #define RCU_CTL_PLLI2SSTB BIT(27) /*!< PLLI2S Clock Stabilization Flag */ 94 #define RCU_CTL_PLLSAIEN BIT(28) /*!< PLLSAI enable */ 95 #define RCU_CTL_PLLSAISTB BIT(29) /*!< PLLSAI Clock Stabilization Flag */ 96 97 /* RCU_PLL */ 98 #define RCU_PLL_PLLPSC BITS(0,5) /*!< The PLL VCO source clock prescaler */ 99 #define RCU_PLL_PLLN BITS(6,14) /*!< The PLL VCO clock multi factor */ 100 #define RCU_PLL_PLLP BITS(16,17) /*!< The PLLP output frequency division factor from PLL VCO clock */ 101 #define RCU_PLL_PLLSEL BIT(22) /*!< PLL Clock Source Selection */ 102 #define RCU_PLL_PLLQ BITS(24,27) /*!< The PLL Q output frequency division factor from PLL VCO clock */ 103 104 /* RCU_CFG0 */ 105 #define RCU_CFG0_SCS BITS(0,1) /*!< system clock switch */ 106 #define RCU_CFG0_SCSS BITS(2,3) /*!< system clock switch status */ 107 #define RCU_CFG0_AHBPSC BITS(4,7) /*!< AHB prescaler selection */ 108 #define RCU_CFG0_APB1PSC BITS(10,12) /*!< APB1 prescaler selection */ 109 #define RCU_CFG0_APB2PSC BITS(13,15) /*!< APB2 prescaler selection */ 110 #define RCU_CFG0_RTCDIV BITS(16,20) /*!< RTC clock divider factor */ 111 #define RCU_CFG0_CKOUT0SEL BITS(21,22) /*!< CKOUT0 Clock Source Selection */ 112 #define RCU_CFG0_I2SSEL BIT(23) /*!< I2S Clock Source Selection */ 113 #define RCU_CFG0_CKOUT0DIV BITS(24,26) /*!< The CK_OUT0 divider which the CK_OUT0 frequency can be reduced */ 114 #define RCU_CFG0_CKOUT1DIV BITS(27,29) /*!< The CK_OUT1 divider which the CK_OUT1 frequency can be reduced */ 115 #define RCU_CFG0_CKOUT1SEL BITS(30,31) /*!< CKOUT1 Clock Source Selection */ 116 117 /* RCU_INT */ 118 #define RCU_INT_IRC32KSTBIF BIT(0) /*!< IRC32K stabilization interrupt flag */ 119 #define RCU_INT_LXTALSTBIF BIT(1) /*!< LXTAL stabilization interrupt flag */ 120 #define RCU_INT_IRC16MSTBIF BIT(2) /*!< IRC16M stabilization interrupt flag */ 121 #define RCU_INT_HXTALSTBIF BIT(3) /*!< HXTAL stabilization interrupt flag */ 122 #define RCU_INT_PLLSTBIF BIT(4) /*!< PLL stabilization interrupt flag */ 123 #define RCU_INT_PLLI2SSTBIF BIT(5) /*!< PLLI2S stabilization interrupt flag */ 124 #define RCU_INT_PLLSAISTBIF BIT(6) /*!< PLLSAI stabilization interrupt flag */ 125 #define RCU_INT_CKMIF BIT(7) /*!< HXTAL clock stuck interrupt flag */ 126 #define RCU_INT_IRC32KSTBIE BIT(8) /*!< IRC32K stabilization interrupt enable */ 127 #define RCU_INT_LXTALSTBIE BIT(9) /*!< LXTAL stabilization interrupt enable */ 128 #define RCU_INT_IRC16MSTBIE BIT(10) /*!< IRC16M stabilization interrupt enable */ 129 #define RCU_INT_HXTALSTBIE BIT(11) /*!< HXTAL stabilization interrupt enable */ 130 #define RCU_INT_PLLSTBIE BIT(12) /*!< PLL stabilization interrupt enable */ 131 #define RCU_INT_PLLI2SSTBIE BIT(13) /*!< PLLI2S Stabilization Interrupt Enable */ 132 #define RCU_INT_PLLSAISTBIE BIT(14) /*!< PLLSAI Stabilization Interrupt Enable */ 133 #define RCU_INT_IRC32KSTBIC BIT(16) /*!< IRC32K Stabilization Interrupt Clear */ 134 #define RCU_INT_LXTALSTBIC BIT(17) /*!< LXTAL Stabilization Interrupt Clear */ 135 #define RCU_INT_IRC16MSTBIC BIT(18) /*!< IRC16M Stabilization Interrupt Clear */ 136 #define RCU_INT_HXTALSTBIC BIT(19) /*!< HXTAL Stabilization Interrupt Clear */ 137 #define RCU_INT_PLLSTBIC BIT(20) /*!< PLL stabilization Interrupt Clear */ 138 #define RCU_INT_PLLI2SSTBIC BIT(21) /*!< PLLI2S stabilization Interrupt Clear */ 139 #define RCU_INT_PLLSAISTBIC BIT(22) /*!< PLLSAI stabilization Interrupt Clear */ 140 #define RCU_INT_CKMIC BIT(23) /*!< HXTAL Clock Stuck Interrupt Clear */ 141 142 /* RCU_AHB1RST */ 143 #define RCU_AHB1RST_PARST BIT(0) /*!< GPIO port A reset */ 144 #define RCU_AHB1RST_PBRST BIT(1) /*!< GPIO port B reset */ 145 #define RCU_AHB1RST_PCRST BIT(2) /*!< GPIO port C reset */ 146 #define RCU_AHB1RST_PDRST BIT(3) /*!< GPIO port D reset */ 147 #define RCU_AHB1RST_PERST BIT(4) /*!< GPIO port E reset */ 148 #define RCU_AHB1RST_PFRST BIT(5) /*!< GPIO port F reset */ 149 #define RCU_AHB1RST_PGRST BIT(6) /*!< GPIO port G reset */ 150 #define RCU_AHB1RST_PHRST BIT(7) /*!< GPIO port H reset */ 151 #define RCU_AHB1RST_PIRST BIT(8) /*!< GPIO port I reset */ 152 #define RCU_AHB1RST_CRCRST BIT(12) /*!< CRC reset */ 153 #define RCU_AHB1RST_DMA0RST BIT(21) /*!< DMA0 reset */ 154 #define RCU_AHB1RST_DMA1RST BIT(22) /*!< DMA1 reset */ 155 #define RCU_AHB1RST_IPARST BIT(23) /*!< IPA reset */ 156 #define RCU_AHB1RST_ENETRST BIT(25) /*!< ENET reset */ 157 #define RCU_AHB1RST_USBHSRST BIT(29) /*!< USBHS reset */ 158 159 /* RCU_AHB2RST */ 160 #define RCU_AHB2RST_DCIRST BIT(0) /*!< DCI reset */ 161 #define RCU_AHB2RST_TRNGRST BIT(6) /*!< TRNG reset */ 162 #define RCU_AHB2RST_USBFSRST BIT(7) /*!< USBFS reset */ 163 164 /* RCU_AHB3RST */ 165 #define RCU_AHB3RST_EXMCRST BIT(0) /*!< EXMC reset */ 166 167 /* RCU_APB1RST */ 168 #define RCU_APB1RST_TIMER1RST BIT(0) /*!< TIMER1 reset */ 169 #define RCU_APB1RST_TIMER2RST BIT(1) /*!< TIMER2 reset */ 170 #define RCU_APB1RST_TIMER3RST BIT(2) /*!< TIMER3 reset */ 171 #define RCU_APB1RST_TIMER4RST BIT(3) /*!< TIMER4 reset */ 172 #define RCU_APB1RST_TIMER5RST BIT(4) /*!< TIMER5 reset */ 173 #define RCU_APB1RST_TIMER6RST BIT(5) /*!< TIMER6 reset */ 174 #define RCU_APB1RST_TIMER11RST BIT(6) /*!< TIMER11 reset */ 175 #define RCU_APB1RST_TIMER12RST BIT(7) /*!< TIMER12 reset */ 176 #define RCU_APB1RST_TIMER13RST BIT(8) /*!< TIMER13 reset */ 177 #define RCU_APB1RST_WWDGTRST BIT(11) /*!< WWDGT reset */ 178 #define RCU_APB1RST_SPI1RST BIT(14) /*!< SPI1 reset */ 179 #define RCU_APB1RST_SPI2RST BIT(15) /*!< SPI2 reset */ 180 #define RCU_APB1RST_USART1RST BIT(17) /*!< USART1 reset */ 181 #define RCU_APB1RST_USART2RST BIT(18) /*!< USART2 reset */ 182 #define RCU_APB1RST_UART3RST BIT(19) /*!< UART3 reset */ 183 #define RCU_APB1RST_UART4RST BIT(20) /*!< UART4 reset */ 184 #define RCU_APB1RST_I2C0RST BIT(21) /*!< I2C0 reset */ 185 #define RCU_APB1RST_I2C1RST BIT(22) /*!< I2C1 reset */ 186 #define RCU_APB1RST_I2C2RST BIT(23) /*!< I2C2 reset */ 187 #define RCU_APB1RST_CAN0RST BIT(25) /*!< CAN0 reset */ 188 #define RCU_APB1RST_CAN1RST BIT(26) /*!< CAN1 reset */ 189 #define RCU_APB1RST_PMURST BIT(28) /*!< PMU reset */ 190 #define RCU_APB1RST_DACRST BIT(29) /*!< DAC reset */ 191 #define RCU_APB1RST_UART6RST BIT(30) /*!< UART6 reset */ 192 #define RCU_APB1RST_UART7RST BIT(31) /*!< UART7 reset */ 193 194 /* RCU_APB2RST */ 195 #define RCU_APB2RST_TIMER0RST BIT(0) /*!< TIMER0 reset */ 196 #define RCU_APB2RST_TIMER7RST BIT(1) /*!< TIMER7 reset */ 197 #define RCU_APB2RST_USART0RST BIT(4) /*!< USART0 reset */ 198 #define RCU_APB2RST_USART5RST BIT(5) /*!< USART5 reset */ 199 #define RCU_APB2RST_ADCRST BIT(8) /*!< ADC reset */ 200 #define RCU_APB2RST_SDIORST BIT(11) /*!< SDIO reset */ 201 #define RCU_APB2RST_SPI0RST BIT(12) /*!< SPI0 reset */ 202 #define RCU_APB2RST_SPI3RST BIT(13) /*!< SPI3 reset */ 203 #define RCU_APB2RST_SYSCFGRST BIT(14) /*!< SYSCFG reset */ 204 #define RCU_APB2RST_TIMER8RST BIT(16) /*!< TIMER8 reset */ 205 #define RCU_APB2RST_TIMER9RST BIT(17) /*!< TIMER9 reset */ 206 #define RCU_APB2RST_TIMER10RST BIT(18) /*!< TIMER10 reset */ 207 #define RCU_APB2RST_SPI4RST BIT(20) /*!< SPI4 reset */ 208 #define RCU_APB2RST_SPI5RST BIT(21) /*!< SPI5 reset */ 209 #define RCU_APB2RST_TLIRST BIT(26) /*!< TLI reset */ 210 211 /* RCU_AHB1EN */ 212 #define RCU_AHB1EN_PAEN BIT(0) /*!< GPIO port A clock enable */ 213 #define RCU_AHB1EN_PBEN BIT(1) /*!< GPIO port B clock enable */ 214 #define RCU_AHB1EN_PCEN BIT(2) /*!< GPIO port C clock enable */ 215 #define RCU_AHB1EN_PDEN BIT(3) /*!< GPIO port D clock enable */ 216 #define RCU_AHB1EN_PEEN BIT(4) /*!< GPIO port E clock enable */ 217 #define RCU_AHB1EN_PFEN BIT(5) /*!< GPIO port F clock enable */ 218 #define RCU_AHB1EN_PGEN BIT(6) /*!< GPIO port G clock enable */ 219 #define RCU_AHB1EN_PHEN BIT(7) /*!< GPIO port H clock enable */ 220 #define RCU_AHB1EN_PIEN BIT(8) /*!< GPIO port I clock enable */ 221 #define RCU_AHB1EN_CRCEN BIT(12) /*!< CRC clock enable */ 222 #define RCU_AHB1EN_BKPSRAMEN BIT(18) /*!< BKPSRAM clock enable */ 223 #define RCU_AHB1EN_TCMSRAMEN BIT(20) /*!< TCMSRAM clock enable */ 224 #define RCU_AHB1EN_DMA0EN BIT(21) /*!< DMA0 clock enable */ 225 #define RCU_AHB1EN_DMA1EN BIT(22) /*!< DMA1 clock enable */ 226 #define RCU_AHB1EN_IPAEN BIT(23) /*!< IPA clock enable */ 227 #define RCU_AHB1EN_ENETEN BIT(25) /*!< ENET clock enable */ 228 #define RCU_AHB1EN_ENETTXEN BIT(26) /*!< Ethernet TX clock enable */ 229 #define RCU_AHB1EN_ENETRXEN BIT(27) /*!< Ethernet RX clock enable */ 230 #define RCU_AHB1EN_ENETPTPEN BIT(28) /*!< Ethernet PTP clock enable */ 231 #define RCU_AHB1EN_USBHSEN BIT(29) /*!< USBHS clock enable */ 232 #define RCU_AHB1EN_USBHSULPIEN BIT(30) /*!< USBHS ULPI clock enable */ 233 234 /* RCU_AHB2EN */ 235 #define RCU_AHB2EN_DCIEN BIT(0) /*!< DCI clock enable */ 236 #define RCU_AHB2EN_TRNGEN BIT(6) /*!< TRNG clock enable */ 237 #define RCU_AHB2EN_USBFSEN BIT(7) /*!< USBFS clock enable */ 238 239 /* RCU_AHB3EN */ 240 #define RCU_AHB3EN_EXMCEN BIT(0) /*!< EXMC clock enable */ 241 242 /* RCU_APB1EN */ 243 #define RCU_APB1EN_TIMER1EN BIT(0) /*!< TIMER1 clock enable */ 244 #define RCU_APB1EN_TIMER2EN BIT(1) /*!< TIMER2 clock enable */ 245 #define RCU_APB1EN_TIMER3EN BIT(2) /*!< TIMER3 clock enable */ 246 #define RCU_APB1EN_TIMER4EN BIT(3) /*!< TIMER4 clock enable */ 247 #define RCU_APB1EN_TIMER5EN BIT(4) /*!< TIMER5 clock enable */ 248 #define RCU_APB1EN_TIMER6EN BIT(5) /*!< TIMER6 clock enable */ 249 #define RCU_APB1EN_TIMER11EN BIT(6) /*!< TIMER11 clock enable */ 250 #define RCU_APB1EN_TIMER12EN BIT(7) /*!< TIMER12 clock enable */ 251 #define RCU_APB1EN_TIMER13EN BIT(8) /*!< TIMER13 clock enable */ 252 #define RCU_APB1EN_WWDGTEN BIT(11) /*!< WWDGT clock enable */ 253 #define RCU_APB1EN_SPI1EN BIT(14) /*!< SPI1 clock enable */ 254 #define RCU_APB1EN_SPI2EN BIT(15) /*!< SPI2 clock enable */ 255 #define RCU_APB1EN_USART1EN BIT(17) /*!< USART1 clock enable */ 256 #define RCU_APB1EN_USART2EN BIT(18) /*!< USART2 clock enable */ 257 #define RCU_APB1EN_UART3EN BIT(19) /*!< UART3 clock enable */ 258 #define RCU_APB1EN_UART4EN BIT(20) /*!< UART4 clock enable */ 259 #define RCU_APB1EN_I2C0EN BIT(21) /*!< I2C0 clock enable */ 260 #define RCU_APB1EN_I2C1EN BIT(22) /*!< I2C1 clock enable */ 261 #define RCU_APB1EN_I2C2EN BIT(23) /*!< I2C2 clock enable */ 262 #define RCU_APB1EN_CAN0EN BIT(25) /*!< CAN0 clock enable */ 263 #define RCU_APB1EN_CAN1EN BIT(26) /*!< CAN1 clock enable */ 264 #define RCU_APB1EN_PMUEN BIT(28) /*!< PMU clock enable */ 265 #define RCU_APB1EN_DACEN BIT(29) /*!< DAC clock enable */ 266 #define RCU_APB1EN_UART6EN BIT(30) /*!< UART6 clock enable */ 267 #define RCU_APB1EN_UART7EN BIT(31) /*!< UART7 clock enable */ 268 269 /* RCU_APB2EN */ 270 #define RCU_APB2EN_TIMER0EN BIT(0) /*!< TIMER0 clock enable */ 271 #define RCU_APB2EN_TIMER7EN BIT(1) /*!< TIMER7 clock enable */ 272 #define RCU_APB2EN_USART0EN BIT(4) /*!< USART0 clock enable */ 273 #define RCU_APB2EN_USART5EN BIT(5) /*!< USART5 clock enable */ 274 #define RCU_APB2EN_ADC0EN BIT(8) /*!< ADC0 clock enable */ 275 #define RCU_APB2EN_ADC1EN BIT(9) /*!< ADC1 clock enable */ 276 #define RCU_APB2EN_ADC2EN BIT(10) /*!< ADC2 clock enable */ 277 #define RCU_APB2EN_SDIOEN BIT(11) /*!< SDIO clock enable */ 278 #define RCU_APB2EN_SPI0EN BIT(12) /*!< SPI0 clock enable */ 279 #define RCU_APB2EN_SPI3EN BIT(13) /*!< SPI3 clock enable */ 280 #define RCU_APB2EN_SYSCFGEN BIT(14) /*!< SYSCFG clock enable */ 281 #define RCU_APB2EN_TIMER8EN BIT(16) /*!< TIMER8 clock enable */ 282 #define RCU_APB2EN_TIMER9EN BIT(17) /*!< TIMER9 clock enable */ 283 #define RCU_APB2EN_TIMER10EN BIT(18) /*!< TIMER10 clock enable */ 284 #define RCU_APB2EN_SPI4EN BIT(20) /*!< SPI4 clock enable */ 285 #define RCU_APB2EN_SPI5EN BIT(21) /*!< SPI5 clock enable */ 286 #define RCU_APB2EN_TLIEN BIT(26) /*!< TLI clock enable */ 287 288 /* RCU_AHB1SPEN */ 289 #define RCU_AHB1SPEN_PASPEN BIT(0) /*!< GPIO port A clock enable when sleep mode */ 290 #define RCU_AHB1SPEN_PBSPEN BIT(1) /*!< GPIO port B clock enable when sleep mode */ 291 #define RCU_AHB1SPEN_PCSPEN BIT(2) /*!< GPIO port C clock enable when sleep mode */ 292 #define RCU_AHB1SPEN_PDSPEN BIT(3) /*!< GPIO port D clock enable when sleep mode */ 293 #define RCU_AHB1SPEN_PESPEN BIT(4) /*!< GPIO port E clock enable when sleep mode */ 294 #define RCU_AHB1SPEN_PFSPEN BIT(5) /*!< GPIO port F clock enable when sleep mode */ 295 #define RCU_AHB1SPEN_PGSPEN BIT(6) /*!< GPIO port G clock enable when sleep mode */ 296 #define RCU_AHB1SPEN_PHSPEN BIT(7) /*!< GPIO port H clock enable when sleep mode */ 297 #define RCU_AHB1SPEN_PISPEN BIT(8) /*!< GPIO port I clock enable when sleep mode */ 298 #define RCU_AHB1SPEN_CRCSPEN BIT(12) /*!< CRC clock enable when sleep mode */ 299 #define RCU_AHB1SPEN_FMCSPEN BIT(15) /*!< FMC clock enable when sleep mode */ 300 #define RCU_AHB1SPEN_SRAM0SPEN BIT(16) /*!< SRAM0 clock enable when sleep mode */ 301 #define RCU_AHB1SPEN_SRAM1SPEN BIT(17) /*!< SRAM1 clock enable when sleep mode */ 302 #define RCU_AHB1SPEN_BKPSRAMSPEN BIT(18) /*!< BKPSRAM clock enable when sleep mode */ 303 #define RCU_AHB1SPEN_SRAM2SPEN BIT(19) /*!< SRAM2 clock enable when sleep mode */ 304 #define RCU_AHB1SPEN_DMA0SPEN BIT(21) /*!< DMA0 clock when sleep mode enable */ 305 #define RCU_AHB1SPEN_DMA1SPEN BIT(22) /*!< DMA1 clock when sleep mode enable */ 306 #define RCU_AHB1SPEN_IPASPEN BIT(23) /*!< IPA clock enable when sleep mode */ 307 #define RCU_AHB1SPEN_ENETSPEN BIT(25) /*!< ENET clock enable when sleep mode */ 308 #define RCU_AHB1SPEN_ENETTXSPEN BIT(26) /*!< Ethernet TX clock enable when sleep mode */ 309 #define RCU_AHB1SPEN_ENETRXSPEN BIT(27) /*!< Ethernet RX clock enable when sleep mode */ 310 #define RCU_AHB1SPEN_ENETPTPSPEN BIT(28) /*!< Ethernet PTP clock enable when sleep mode */ 311 #define RCU_AHB1SPEN_USBHSSPEN BIT(29) /*!< USBHS clock enable when sleep mode */ 312 #define RCU_AHB1SPEN_USBHSULPISPEN BIT(30) /*!< USBHS ULPI clock enable when sleep mode */ 313 314 /* RCU_AHB2SPEN */ 315 #define RCU_AHB2SPEN_DCISPEN BIT(0) /*!< DCI clock enable when sleep mode */ 316 #define RCU_AHB2SPEN_TRNGSPEN BIT(6) /*!< TRNG clock enable when sleep mode */ 317 #define RCU_AHB2SPEN_USBFSSPEN BIT(7) /*!< USBFS clock enable when sleep mode */ 318 319 /* RCU_AHB3SPEN */ 320 #define RCU_AHB3SPEN_EXMCSPEN BIT(0) /*!< EXMC clock enable when sleep mode */ 321 322 /* RCU_APB1SPEN */ 323 #define RCU_APB1SPEN_TIMER1SPEN BIT(0) /*!< TIMER1 clock enable when sleep mode */ 324 #define RCU_APB1SPEN_TIMER2SPEN BIT(1) /*!< TIMER2 clock enable when sleep mode */ 325 #define RCU_APB1SPEN_TIMER3SPEN BIT(2) /*!< TIMER3 clock enable when sleep mode */ 326 #define RCU_APB1SPEN_TIMER4SPEN BIT(3) /*!< TIMER4 clock enable when sleep mode */ 327 #define RCU_APB1SPEN_TIMER5SPEN BIT(4) /*!< TIMER5 clock enable when sleep mode */ 328 #define RCU_APB1SPEN_TIMER6SPEN BIT(5) /*!< TIMER6 clock enable when sleep mode */ 329 #define RCU_APB1SPEN_TIMER11SPEN BIT(6) /*!< TIMER11 clock enable when sleep mode */ 330 #define RCU_APB1SPEN_TIMER12SPEN BIT(7) /*!< TIMER12 clock enable when sleep mode */ 331 #define RCU_APB1SPEN_TIMER13SPEN BIT(8) /*!< TIMER13 clock enable when sleep mode */ 332 #define RCU_APB1SPEN_WWDGTSPEN BIT(11) /*!< WWDGT clock enable when sleep mode */ 333 #define RCU_APB1SPEN_SPI1SPEN BIT(14) /*!< SPI1 clock enable when sleep mode */ 334 #define RCU_APB1SPEN_SPI2SPEN BIT(15) /*!< SPI2 clock enable when sleep mode */ 335 #define RCU_APB1SPEN_USART1SPEN BIT(17) /*!< USART1 clock enable when sleep mode*/ 336 #define RCU_APB1SPEN_USART2SPEN BIT(18) /*!< USART2 clock enable when sleep mode*/ 337 #define RCU_APB1SPEN_UART3SPEN BIT(19) /*!< UART3 clock enable when sleep mode*/ 338 #define RCU_APB1SPEN_UART4SPEN BIT(20) /*!< UART4 clock enable when sleep mode */ 339 #define RCU_APB1SPEN_I2C0SPEN BIT(21) /*!< I2C0 clock enable when sleep mode */ 340 #define RCU_APB1SPEN_I2C1SPEN BIT(22) /*!< I2C1 clock enable when sleep mode*/ 341 #define RCU_APB1SPEN_I2C2SPEN BIT(23) /*!< I2C2 clock enable when sleep mode */ 342 #define RCU_APB1SPEN_CAN0SPEN BIT(25) /*!< CAN0 clock enable when sleep mode*/ 343 #define RCU_APB1SPEN_CAN1SPEN BIT(26) /*!< CAN1 clock enable when sleep mode */ 344 #define RCU_APB1SPEN_PMUSPEN BIT(28) /*!< PMU clock enable when sleep mode */ 345 #define RCU_APB1SPEN_DACSPEN BIT(29) /*!< DAC clock enable when sleep mode */ 346 #define RCU_APB1SPEN_UART6SPEN BIT(30) /*!< UART6 clock enable when sleep mode */ 347 #define RCU_APB1SPEN_UART7SPEN BIT(31) /*!< UART7 clock enable when sleep mode */ 348 349 /* RCU_APB2SPEN */ 350 #define RCU_APB2SPEN_TIMER0SPEN BIT(0) /*!< TIMER0 clock enable when sleep mode */ 351 #define RCU_APB2SPEN_TIMER7SPEN BIT(1) /*!< TIMER7 clock enable when sleep mode */ 352 #define RCU_APB2SPEN_USART0SPEN BIT(4) /*!< USART0 clock enable when sleep mode */ 353 #define RCU_APB2SPEN_USART5SPEN BIT(5) /*!< USART5 clock enable when sleep mode */ 354 #define RCU_APB2SPEN_ADC0SPEN BIT(8) /*!< ADC0 clock enable when sleep mode */ 355 #define RCU_APB2SPEN_ADC1SPEN BIT(9) /*!< ADC1 clock enable when sleep mode */ 356 #define RCU_APB2SPEN_ADC2SPEN BIT(10) /*!< ADC2 clock enable when sleep mode */ 357 #define RCU_APB2SPEN_SDIOSPEN BIT(11) /*!< SDIO clock enable when sleep mode */ 358 #define RCU_APB2SPEN_SPI0SPEN BIT(12) /*!< SPI0 clock enable when sleep mode */ 359 #define RCU_APB2SPEN_SPI3SPEN BIT(13) /*!< SPI3 clock enable when sleep mode */ 360 #define RCU_APB2SPEN_SYSCFGSPEN BIT(14) /*!< SYSCFG clock enable when sleep mode */ 361 #define RCU_APB2SPEN_TIMER8SPEN BIT(16) /*!< TIMER8 clock enable when sleep mode */ 362 #define RCU_APB2SPEN_TIMER9SPEN BIT(17) /*!< TIMER9 clock enable when sleep mode */ 363 #define RCU_APB2SPEN_TIMER10SPEN BIT(18) /*!< TIMER10 clock enable when sleep mode */ 364 #define RCU_APB2SPEN_SPI4SPEN BIT(20) /*!< SPI4 clock enable when sleep mode */ 365 #define RCU_APB2SPEN_SPI5SPEN BIT(21) /*!< SPI5 clock enable when sleep mode */ 366 #define RCU_APB2SPEN_TLISPEN BIT(26) /*!< TLI clock enable when sleep mode*/ 367 368 /* RCU_BDCTL */ 369 #define RCU_BDCTL_LXTALEN BIT(0) /*!< LXTAL enable */ 370 #define RCU_BDCTL_LXTALSTB BIT(1) /*!< low speed crystal oscillator stabilization flag */ 371 #define RCU_BDCTL_LXTALBPS BIT(2) /*!< LXTAL bypass mode enable */ 372 #define RCU_BDCTL_LXTALDRI BIT(3) /*!< LXTAL drive capability */ 373 #define RCU_BDCTL_RTCSRC BITS(8,9) /*!< RTC clock entry selection */ 374 #define RCU_BDCTL_RTCEN BIT(15) /*!< RTC clock enable */ 375 #define RCU_BDCTL_BKPRST BIT(16) /*!< backup domain reset */ 376 377 /* RCU_RSTSCK */ 378 #define RCU_RSTSCK_IRC32KEN BIT(0) /*!< IRC32K enable */ 379 #define RCU_RSTSCK_IRC32KSTB BIT(1) /*!< IRC32K stabilization flag */ 380 #define RCU_RSTSCK_RSTFC BIT(24) /*!< reset flag clear */ 381 #define RCU_RSTSCK_BORRSTF BIT(25) /*!< BOR reset flag */ 382 #define RCU_RSTSCK_EPRSTF BIT(26) /*!< external pin reset flag */ 383 #define RCU_RSTSCK_PORRSTF BIT(27) /*!< power reset flag */ 384 #define RCU_RSTSCK_SWRSTF BIT(28) /*!< software reset flag */ 385 #define RCU_RSTSCK_FWDGTRSTF BIT(29) /*!< free watchdog timer reset flag */ 386 #define RCU_RSTSCK_WWDGTRSTF BIT(30) /*!< window watchdog timer reset flag */ 387 #define RCU_RSTSCK_LPRSTF BIT(31) /*!< low-power reset flag */ 388 389 /* RCU_PLLSSCTL */ 390 #define RCU_PLLSSCTL_MODCNT BITS(0,12) /*!< these bits configure PLL spread spectrum modulation 391 profile amplitude and frequency. the following criteria 392 must be met: MODSTEP*MODCNT=215-1 */ 393 #define RCU_PLLSSCTL_MODSTEP BITS(13,27) /*!< these bits configure PLL spread spectrum modulation 394 profile amplitude and frequency. the following criteria 395 must be met: MODSTEP*MODCNT=215-1 */ 396 #define RCU_PLLSSCTL_SS_TYPE BIT(30) /*!< PLL spread spectrum modulation type select */ 397 #define RCU_PLLSSCTL_SSCGON BIT(31) /*!< PLL spread spectrum modulation enable */ 398 399 /* RCU_PLLI2S */ 400 #define RCU_PLLI2S_PLLI2SN BITS(6,14) /*!< the PLLI2S VCO clock multi factor */ 401 #define RCU_PLLI2S_PLLI2SQ BITS(24,27) /*!< the PLLI2S Q output frequency division factor from PLLI2S VCO clock */ 402 #define RCU_PLLI2S_PLLI2SR BITS(28,30) /*!< the PLLI2S R output frequency division factor from PLLI2S VCO clock */ 403 404 /* RCU_PLLSAI */ 405 #define RCU_PLLSAI_PLLSAIN BITS(6,14) /*!< the PLLSAI VCO clock multi factor */ 406 #define RCU_PLLSAI_PLLSAIP BITS(16,17) /*!< the PLLSAI P output frequency division factor from PLLSAI VCO clock */ 407 #define RCU_PLLSAI_PLLSAIQ BITS(24,27) /*!< the PLLSAI Q output frequency division factor from PLLSAI VCO clock */ 408 #define RCU_PLLSAI_PLLSAIR BITS(28,30) /*!< the PLLSAI R output frequency division factor from PLLSAI VCO clock */ 409 410 /* RCU_CFG1 */ 411 #define RCU_CFG1_PLLSAIRDIV BITS(16,17) /*!< the divider factor from PLLSAIR clock */ 412 #define RCU_CFG1_TIMERSEL BIT(24) /*!< TIMER clock selection */ 413 414 /* RCU_ADDCTL */ 415 #define RCU_ADDCTL_CK48MSEL BIT(0) /*!< 48MHz clock selection */ 416 #define RCU_ADDCTL_PLL48MSEL BIT(1) /*!< PLL48M clock selection */ 417 #define RCU_ADDCTL_IRC48MEN BIT(16) /*!< internal 48MHz RC oscillator enable */ 418 #define RCU_ADDCTL_IRC48MSTB BIT(17) /*!< internal 48MHz RC oscillator clock stabilization flag */ 419 #define RCU_ADDCTL_IRC48MCAL BITS(24,31) /*!< internal 48MHz RC oscillator calibration value register */ 420 421 /* RCU_ADDINT */ 422 #define RCU_ADDINT_IRC48MSTBIF BIT(6) /*!< IRC48M stabilization interrupt flag */ 423 #define RCU_ADDINT_IRC48MSTBIE BIT(14) /*!< internal 48 MHz RC oscillator stabilization interrupt enable */ 424 #define RCU_ADDINT_IRC48MSTBIC BIT(22) /*!< internal 48 MHz RC oscillator stabilization interrupt clear */ 425 426 /* RCU_ADDAPB1RST */ 427 #define RCU_ADDAPB1RST_CTCRST BIT(27) /*!< CTC reset */ 428 #define RCU_ADDAPB1RST_IREFRST BIT(31) /*!< IREF reset */ 429 430 /* RCU_ADDAPB1EN */ 431 #define RCU_ADDAPB1EN_CTCEN BIT(27) /*!< CTC clock enable */ 432 #define RCU_ADDAPB1EN_IREFEN BIT(31) /*!< IREF interface clock enable */ 433 434 /* RCU_ADDAPB1SPEN */ 435 #define RCU_ADDAPB1SPEN_CTCSPEN BIT(27) /*!< CTC clock enable during sleep mode */ 436 #define RCU_ADDAPB1SPEN_IREFSPEN BIT(31) /*!< IREF interface clock enable during sleep mode */ 437 438 /* RCU_VKEY */ 439 #define RCU_VKEY_KEY BITS(0,31) /*!< RCU_DSV key register */ 440 441 /* RCU_DSV */ 442 #define RCU_DSV_DSLPVS BITS(0,2) /*!< deep-sleep mode voltage select */ 443 444 /* constants definitions */ 445 /* define the peripheral clock enable bit position and its register index offset */ 446 #define RCU_REGIDX_BIT(regidx, bitpos) (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos)) 447 #define RCU_REG_VAL(periph) (REG32(RCU + ((uint32_t)(periph) >> 6))) 448 #define RCU_BIT_POS(val) ((uint32_t)(val) & 0x1FU) 449 /* define the voltage key unlock value */ 450 #define RCU_VKEY_UNLOCK ((uint32_t)0x1A2B3C4DU) 451 452 /* register offset */ 453 /* peripherals enable */ 454 #define AHB1EN_REG_OFFSET 0x30U /*!< AHB1 enable register offset */ 455 #define AHB2EN_REG_OFFSET 0x34U /*!< AHB2 enable register offset */ 456 #define AHB3EN_REG_OFFSET 0x38U /*!< AHB3 enable register offset */ 457 #define APB1EN_REG_OFFSET 0x40U /*!< APB1 enable register offset */ 458 #define APB2EN_REG_OFFSET 0x44U /*!< APB2 enable register offset */ 459 #define AHB1SPEN_REG_OFFSET 0x50U /*!< AHB1 sleep mode enable register offset */ 460 #define AHB2SPEN_REG_OFFSET 0x54U /*!< AHB2 sleep mode enable register offset */ 461 #define AHB3SPEN_REG_OFFSET 0x58U /*!< AHB3 sleep mode enable register offset */ 462 #define APB1SPEN_REG_OFFSET 0x60U /*!< APB1 sleep mode enable register offset */ 463 #define APB2SPEN_REG_OFFSET 0x64U /*!< APB2 sleep mode enable register offset */ 464 #define ADD_APB1EN_REG_OFFSET 0xE4U /*!< APB1 additional enable register offset */ 465 #define ADD_APB1SPEN_REG_OFFSET 0xE8U /*!< APB1 additional sleep mode enable register offset */ 466 467 /* peripherals reset */ 468 #define AHB1RST_REG_OFFSET 0x10U /*!< AHB1 reset register offset */ 469 #define AHB2RST_REG_OFFSET 0x14U /*!< AHB2 reset register offset */ 470 #define AHB3RST_REG_OFFSET 0x18U /*!< AHB3 reset register offset */ 471 #define APB1RST_REG_OFFSET 0x20U /*!< APB1 reset register offset */ 472 #define APB2RST_REG_OFFSET 0x24U /*!< APB2 reset register offset */ 473 #define ADD_APB1RST_REG_OFFSET 0xE0U /*!< APB1 additional reset register offset */ 474 #define RSTSCK_REG_OFFSET 0x74U /*!< reset source/clock register offset */ 475 476 /* clock control */ 477 #define CTL_REG_OFFSET 0x00U /*!< control register offset */ 478 #define BDCTL_REG_OFFSET 0x70U /*!< backup domain control register offset */ 479 #define ADDCTL_REG_OFFSET 0xC0U /*!< additional clock control register offset */ 480 481 /* clock stabilization and stuck interrupt */ 482 #define INT_REG_OFFSET 0x0CU /*!< clock interrupt register offset */ 483 #define ADDINT_REG_OFFSET 0xCCU /*!< additional clock interrupt register offset */ 484 485 /* configuration register */ 486 #define PLL_REG_OFFSET 0x04U /*!< PLL register offset */ 487 #define CFG0_REG_OFFSET 0x08U /*!< clock configuration register 0 offset */ 488 #define PLLSSCTL_REG_OFFSET 0x80U /*!< PLL clock spread spectrum control register offset */ 489 #define PLLI2S_REG_OFFSET 0x84U /*!< PLLI2S register offset */ 490 #define PLLSAI_REG_OFFSET 0x88U /*!< PLLSAI register offset */ 491 #define CFG1_REG_OFFSET 0x8CU /*!< clock configuration register 1 offset */ 492 493 /* peripheral clock enable */ 494 typedef enum 495 { 496 /* AHB1 peripherals */ 497 RCU_GPIOA = RCU_REGIDX_BIT(AHB1EN_REG_OFFSET, 0U), /*!< GPIOA clock */ 498 RCU_GPIOB = RCU_REGIDX_BIT(AHB1EN_REG_OFFSET, 1U), /*!< GPIOB clock */ 499 RCU_GPIOC = RCU_REGIDX_BIT(AHB1EN_REG_OFFSET, 2U), /*!< GPIOC clock */ 500 RCU_GPIOD = RCU_REGIDX_BIT(AHB1EN_REG_OFFSET, 3U), /*!< GPIOD clock */ 501 RCU_GPIOE = RCU_REGIDX_BIT(AHB1EN_REG_OFFSET, 4U), /*!< GPIOE clock */ 502 RCU_GPIOF = RCU_REGIDX_BIT(AHB1EN_REG_OFFSET, 5U), /*!< GPIOF clock */ 503 RCU_GPIOG = RCU_REGIDX_BIT(AHB1EN_REG_OFFSET, 6U), /*!< GPIOG clock */ 504 RCU_GPIOH = RCU_REGIDX_BIT(AHB1EN_REG_OFFSET, 7U), /*!< GPIOH clock */ 505 RCU_GPIOI = RCU_REGIDX_BIT(AHB1EN_REG_OFFSET, 8U), /*!< GPIOI clock */ 506 RCU_CRC = RCU_REGIDX_BIT(AHB1EN_REG_OFFSET, 12U), /*!< CRC clock */ 507 RCU_BKPSRAM = RCU_REGIDX_BIT(AHB1EN_REG_OFFSET, 18U), /*!< BKPSRAM clock */ 508 RCU_TCMSRAM = RCU_REGIDX_BIT(AHB1EN_REG_OFFSET, 20U), /*!< TCMSRAM clock */ 509 RCU_DMA0 = RCU_REGIDX_BIT(AHB1EN_REG_OFFSET, 21U), /*!< DMA0 clock */ 510 RCU_DMA1 = RCU_REGIDX_BIT(AHB1EN_REG_OFFSET, 22U), /*!< DMA1 clock */ 511 RCU_IPA = RCU_REGIDX_BIT(AHB1EN_REG_OFFSET, 23U), /*!< IPA clock */ 512 RCU_ENET = RCU_REGIDX_BIT(AHB1EN_REG_OFFSET, 25U), /*!< ENET clock */ 513 RCU_ENETTX = RCU_REGIDX_BIT(AHB1EN_REG_OFFSET, 26U), /*!< ENETTX clock */ 514 RCU_ENETRX = RCU_REGIDX_BIT(AHB1EN_REG_OFFSET, 27U), /*!< ENETRX clock */ 515 RCU_ENETPTP = RCU_REGIDX_BIT(AHB1EN_REG_OFFSET, 28U), /*!< ENETPTP clock */ 516 RCU_USBHS = RCU_REGIDX_BIT(AHB1EN_REG_OFFSET, 29U), /*!< USBHS clock */ 517 RCU_USBHSULPI = RCU_REGIDX_BIT(AHB1EN_REG_OFFSET, 30U), /*!< USBHSULPI clock */ 518 /* AHB2 peripherals */ 519 RCU_DCI = RCU_REGIDX_BIT(AHB2EN_REG_OFFSET, 0U), /*!< DCI clock */ 520 RCU_TRNG = RCU_REGIDX_BIT(AHB2EN_REG_OFFSET, 6U), /*!< TRNG clock */ 521 RCU_USBFS = RCU_REGIDX_BIT(AHB2EN_REG_OFFSET, 7U), /*!< USBFS clock */ 522 /* AHB3 peripherals */ 523 RCU_EXMC = RCU_REGIDX_BIT(AHB3EN_REG_OFFSET, 0U), /*!< EXMC clock */ 524 /* APB1 peripherals */ 525 RCU_TIMER1 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 0U), /*!< TIMER1 clock */ 526 RCU_TIMER2 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 1U), /*!< TIMER2 clock */ 527 RCU_TIMER3 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 2U), /*!< TIMER3 clock */ 528 RCU_TIMER4 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 3U), /*!< TIMER4 clock */ 529 RCU_TIMER5 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 4U), /*!< TIMER5 clock */ 530 RCU_TIMER6 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 5U), /*!< TIMER6 clock */ 531 RCU_TIMER11 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 6U), /*!< TIMER11 clock */ 532 RCU_TIMER12 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 7U), /*!< TIMER12 clock */ 533 RCU_TIMER13 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 8U), /*!< TIMER13 clock */ 534 RCU_WWDGT = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 11U), /*!< WWDGT clock */ 535 RCU_SPI1 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 14U), /*!< SPI1 clock */ 536 RCU_SPI2 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 15U), /*!< SPI2 clock */ 537 RCU_USART1 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 17U), /*!< USART1 clock */ 538 RCU_USART2 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 18U), /*!< USART2 clock */ 539 RCU_UART3 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 19U), /*!< UART3 clock */ 540 RCU_UART4 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 20U), /*!< UART4 clock */ 541 RCU_I2C0 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 21U), /*!< I2C0 clock */ 542 RCU_I2C1 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 22U), /*!< I2C1 clock */ 543 RCU_I2C2 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 23U), /*!< I2C2 clock */ 544 RCU_CAN0 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 25U), /*!< CAN0 clock */ 545 RCU_CAN1 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 26U), /*!< CAN1 clock */ 546 RCU_PMU = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 28U), /*!< PMU clock */ 547 RCU_DAC = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 29U), /*!< DAC clock */ 548 RCU_UART6 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 30U), /*!< UART6 clock */ 549 RCU_UART7 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 31U), /*!< UART7 clock */ 550 RCU_RTC = RCU_REGIDX_BIT(BDCTL_REG_OFFSET, 15U), /*!< RTC clock */ 551 /* APB2 peripherals */ 552 RCU_TIMER0 = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 0U), /*!< TIMER0 clock */ 553 RCU_TIMER7 = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 1U), /*!< TIMER7 clock */ 554 RCU_USART0 = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 4U), /*!< USART0 clock */ 555 RCU_USART5 = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 5U), /*!< USART5 clock */ 556 RCU_ADC0 = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 8U), /*!< ADC0 clock */ 557 RCU_ADC1 = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 9U), /*!< ADC1 clock */ 558 RCU_ADC2 = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 10U), /*!< ADC2 clock */ 559 RCU_SDIO = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 11U), /*!< SDIO clock */ 560 RCU_SPI0 = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 12U), /*!< SPI0 clock */ 561 RCU_SPI3 = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 13U), /*!< SPI3 clock */ 562 RCU_SYSCFG = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 14U), /*!< SYSCFG clock */ 563 RCU_TIMER8 = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 16U), /*!< TIMER8 clock */ 564 RCU_TIMER9 = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 17U), /*!< TIMER9 clock */ 565 RCU_TIMER10 = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 18U), /*!< TIMER10 clock */ 566 RCU_SPI4 = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 20U), /*!< SPI4 clock */ 567 RCU_SPI5 = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 21U), /*!< SPI5 clock */ 568 RCU_TLI = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 26U), /*!< TLI clock */ 569 /* APB1 additional peripherals */ 570 RCU_CTC = RCU_REGIDX_BIT(ADD_APB1EN_REG_OFFSET, 27U), /*!< CTC clock */ 571 RCU_IREF = RCU_REGIDX_BIT(ADD_APB1EN_REG_OFFSET, 31U), /*!< IREF clock */ 572 }rcu_periph_enum; 573 574 /* peripheral clock enable when sleep mode*/ 575 typedef enum 576 { 577 /* AHB1 peripherals */ 578 RCU_GPIOA_SLP = RCU_REGIDX_BIT(AHB1SPEN_REG_OFFSET, 0U), /*!< GPIOA clock */ 579 RCU_GPIOB_SLP = RCU_REGIDX_BIT(AHB1SPEN_REG_OFFSET, 1U), /*!< GPIOB clock */ 580 RCU_GPIOC_SLP = RCU_REGIDX_BIT(AHB1SPEN_REG_OFFSET, 2U), /*!< GPIOC clock */ 581 RCU_GPIOD_SLP = RCU_REGIDX_BIT(AHB1SPEN_REG_OFFSET, 3U), /*!< GPIOD clock */ 582 RCU_GPIOE_SLP = RCU_REGIDX_BIT(AHB1SPEN_REG_OFFSET, 4U), /*!< GPIOE clock */ 583 RCU_GPIOF_SLP = RCU_REGIDX_BIT(AHB1SPEN_REG_OFFSET, 5U), /*!< GPIOF clock */ 584 RCU_GPIOG_SLP = RCU_REGIDX_BIT(AHB1SPEN_REG_OFFSET, 6U), /*!< GPIOG clock */ 585 RCU_GPIOH_SLP = RCU_REGIDX_BIT(AHB1SPEN_REG_OFFSET, 7U), /*!< GPIOH clock */ 586 RCU_GPIOI_SLP = RCU_REGIDX_BIT(AHB1SPEN_REG_OFFSET, 8U), /*!< GPIOI clock */ 587 RCU_CRC_SLP = RCU_REGIDX_BIT(AHB1SPEN_REG_OFFSET, 12U), /*!< CRC clock */ 588 RCU_FMC_SLP = RCU_REGIDX_BIT(AHB1SPEN_REG_OFFSET, 15U), /*!< FMC clock */ 589 RCU_SRAM0_SLP = RCU_REGIDX_BIT(AHB1SPEN_REG_OFFSET, 16U), /*!< SRAM0 clock */ 590 RCU_SRAM1_SLP = RCU_REGIDX_BIT(AHB1SPEN_REG_OFFSET, 17U), /*!< SRAM1 clock */ 591 RCU_BKPSRAM_SLP = RCU_REGIDX_BIT(AHB1SPEN_REG_OFFSET, 18U), /*!< BKPSRAM clock */ 592 RCU_SRAM2_SLP = RCU_REGIDX_BIT(AHB1SPEN_REG_OFFSET, 19U), /*!< SRAM2 clock */ 593 RCU_DMA0_SLP = RCU_REGIDX_BIT(AHB1SPEN_REG_OFFSET, 21U), /*!< DMA0 clock */ 594 RCU_DMA1_SLP = RCU_REGIDX_BIT(AHB1SPEN_REG_OFFSET, 22U), /*!< DMA1 clock */ 595 RCU_IPA_SLP = RCU_REGIDX_BIT(AHB1SPEN_REG_OFFSET, 23U), /*!< IPA clock */ 596 RCU_ENET_SLP = RCU_REGIDX_BIT(AHB1SPEN_REG_OFFSET, 25U), /*!< ENET clock */ 597 RCU_ENETTX_SLP = RCU_REGIDX_BIT(AHB1SPEN_REG_OFFSET, 26U), /*!< ENETTX clock */ 598 RCU_ENETRX_SLP = RCU_REGIDX_BIT(AHB1SPEN_REG_OFFSET, 27U), /*!< ENETRX clock */ 599 RCU_ENETPTP_SLP = RCU_REGIDX_BIT(AHB1SPEN_REG_OFFSET, 28U), /*!< ENETPTP clock */ 600 RCU_USBHS_SLP = RCU_REGIDX_BIT(AHB1SPEN_REG_OFFSET, 29U), /*!< USBHS clock */ 601 RCU_USBHSULPI_SLP = RCU_REGIDX_BIT(AHB1SPEN_REG_OFFSET, 30U), /*!< USBHSULPI clock */ 602 /* AHB2 peripherals */ 603 RCU_DCI_SLP = RCU_REGIDX_BIT(AHB2SPEN_REG_OFFSET, 0U), /*!< DCI clock */ 604 RCU_TRNG_SLP = RCU_REGIDX_BIT(AHB2SPEN_REG_OFFSET, 6U), /*!< TRNG clock */ 605 RCU_USBFS_SLP = RCU_REGIDX_BIT(AHB2SPEN_REG_OFFSET, 7U), /*!< USBFS clock */ 606 /* AHB3 peripherals */ 607 RCU_EXMC_SLP = RCU_REGIDX_BIT(AHB3SPEN_REG_OFFSET, 0U), /*!< EXMC clock */ 608 /* APB1 peripherals */ 609 RCU_TIMER1_SLP = RCU_REGIDX_BIT(APB1SPEN_REG_OFFSET, 0U), /*!< TIMER1 clock */ 610 RCU_TIMER2_SLP = RCU_REGIDX_BIT(APB1SPEN_REG_OFFSET, 1U), /*!< TIMER2 clock */ 611 RCU_TIMER3_SLP = RCU_REGIDX_BIT(APB1SPEN_REG_OFFSET, 2U), /*!< TIMER3 clock */ 612 RCU_TIMER4_SLP = RCU_REGIDX_BIT(APB1SPEN_REG_OFFSET, 3U), /*!< TIMER4 clock */ 613 RCU_TIMER5_SLP = RCU_REGIDX_BIT(APB1SPEN_REG_OFFSET, 4U), /*!< TIMER5 clock */ 614 RCU_TIMER6_SLP = RCU_REGIDX_BIT(APB1SPEN_REG_OFFSET, 5U), /*!< TIMER6 clock */ 615 RCU_TIMER11_SLP = RCU_REGIDX_BIT(APB1SPEN_REG_OFFSET, 6U), /*!< TIMER11 clock */ 616 RCU_TIMER12_SLP = RCU_REGIDX_BIT(APB1SPEN_REG_OFFSET, 7U), /*!< TIMER12 clock */ 617 RCU_TIMER13_SLP = RCU_REGIDX_BIT(APB1SPEN_REG_OFFSET, 8U), /*!< TIMER13 clock */ 618 RCU_WWDGT_SLP = RCU_REGIDX_BIT(APB1SPEN_REG_OFFSET, 11U), /*!< WWDGT clock */ 619 RCU_SPI1_SLP = RCU_REGIDX_BIT(APB1SPEN_REG_OFFSET, 14U), /*!< SPI1 clock */ 620 RCU_SPI2_SLP = RCU_REGIDX_BIT(APB1SPEN_REG_OFFSET, 15U), /*!< SPI2 clock */ 621 RCU_USART1_SLP = RCU_REGIDX_BIT(APB1SPEN_REG_OFFSET, 17U), /*!< USART1 clock */ 622 RCU_USART2_SLP = RCU_REGIDX_BIT(APB1SPEN_REG_OFFSET, 18U), /*!< USART2 clock */ 623 RCU_UART3_SLP = RCU_REGIDX_BIT(APB1SPEN_REG_OFFSET, 19U), /*!< UART3 clock */ 624 RCU_UART4_SLP = RCU_REGIDX_BIT(APB1SPEN_REG_OFFSET, 20U), /*!< UART4 clock */ 625 RCU_I2C0_SLP = RCU_REGIDX_BIT(APB1SPEN_REG_OFFSET, 21U), /*!< I2C0 clock */ 626 RCU_I2C1_SLP = RCU_REGIDX_BIT(APB1SPEN_REG_OFFSET, 22U), /*!< I2C1 clock */ 627 RCU_I2C2_SLP = RCU_REGIDX_BIT(APB1SPEN_REG_OFFSET, 23U), /*!< I2C2 clock */ 628 RCU_CAN0_SLP = RCU_REGIDX_BIT(APB1SPEN_REG_OFFSET, 25U), /*!< CAN0 clock */ 629 RCU_CAN1_SLP = RCU_REGIDX_BIT(APB1SPEN_REG_OFFSET, 26U), /*!< CAN1 clock */ 630 RCU_PMU_SLP = RCU_REGIDX_BIT(APB1SPEN_REG_OFFSET, 28U), /*!< PMU clock */ 631 RCU_DAC_SLP = RCU_REGIDX_BIT(APB1SPEN_REG_OFFSET, 29U), /*!< DAC clock */ 632 RCU_UART6_SLP = RCU_REGIDX_BIT(APB1SPEN_REG_OFFSET, 30U), /*!< UART6 clock */ 633 RCU_UART7_SLP = RCU_REGIDX_BIT(APB1SPEN_REG_OFFSET, 31U), /*!< UART7 clock */ 634 /* APB2 peripherals */ 635 RCU_TIMER0_SLP = RCU_REGIDX_BIT(APB2SPEN_REG_OFFSET, 0U), /*!< TIMER0 clock */ 636 RCU_TIMER7_SLP = RCU_REGIDX_BIT(APB2SPEN_REG_OFFSET, 1U), /*!< TIMER7 clock */ 637 RCU_USART0_SLP = RCU_REGIDX_BIT(APB2SPEN_REG_OFFSET, 4U), /*!< USART0 clock */ 638 RCU_USART5_SLP = RCU_REGIDX_BIT(APB2SPEN_REG_OFFSET, 5U), /*!< USART5 clock */ 639 RCU_ADC0_SLP = RCU_REGIDX_BIT(APB2SPEN_REG_OFFSET, 8U), /*!< ADC0 clock */ 640 RCU_ADC1_SLP = RCU_REGIDX_BIT(APB2SPEN_REG_OFFSET, 9U), /*!< ADC1 clock */ 641 RCU_ADC2_SLP = RCU_REGIDX_BIT(APB2SPEN_REG_OFFSET, 10U), /*!< ADC2 clock */ 642 RCU_SDIO_SLP = RCU_REGIDX_BIT(APB2SPEN_REG_OFFSET, 11U), /*!< SDIO clock */ 643 RCU_SPI0_SLP = RCU_REGIDX_BIT(APB2SPEN_REG_OFFSET, 12U), /*!< SPI0 clock */ 644 RCU_SPI3_SLP = RCU_REGIDX_BIT(APB2SPEN_REG_OFFSET, 13U), /*!< SPI3 clock */ 645 RCU_SYSCFG_SLP = RCU_REGIDX_BIT(APB2SPEN_REG_OFFSET, 14U), /*!< SYSCFG clock */ 646 RCU_TIMER8_SLP = RCU_REGIDX_BIT(APB2SPEN_REG_OFFSET, 16U), /*!< TIMER8 clock */ 647 RCU_TIMER9_SLP = RCU_REGIDX_BIT(APB2SPEN_REG_OFFSET, 17U), /*!< TIMER9 clock */ 648 RCU_TIMER10_SLP = RCU_REGIDX_BIT(APB2SPEN_REG_OFFSET, 18U), /*!< TIMER10 clock */ 649 RCU_SPI4_SLP = RCU_REGIDX_BIT(APB2SPEN_REG_OFFSET, 20U), /*!< SPI4 clock */ 650 RCU_SPI5_SLP = RCU_REGIDX_BIT(APB2SPEN_REG_OFFSET, 21U), /*!< SPI5 clock */ 651 RCU_TLI_SLP = RCU_REGIDX_BIT(APB2SPEN_REG_OFFSET, 26U), /*!< TLI clock */ 652 /* APB1 additional peripherals */ 653 RCU_CTC_SLP = RCU_REGIDX_BIT(ADD_APB1SPEN_REG_OFFSET, 27U), /*!< CTC clock */ 654 RCU_IREF_SLP = RCU_REGIDX_BIT(ADD_APB1SPEN_REG_OFFSET, 31U), /*!< IREF clock */ 655 }rcu_periph_sleep_enum; 656 657 /* peripherals reset */ 658 typedef enum 659 { 660 /* AHB1 peripherals */ 661 RCU_GPIOARST = RCU_REGIDX_BIT(AHB1RST_REG_OFFSET, 0U), /*!< GPIOA clock reset */ 662 RCU_GPIOBRST = RCU_REGIDX_BIT(AHB1RST_REG_OFFSET, 1U), /*!< GPIOB clock reset */ 663 RCU_GPIOCRST = RCU_REGIDX_BIT(AHB1RST_REG_OFFSET, 2U), /*!< GPIOC clock reset */ 664 RCU_GPIODRST = RCU_REGIDX_BIT(AHB1RST_REG_OFFSET, 3U), /*!< GPIOD clock reset */ 665 RCU_GPIOERST = RCU_REGIDX_BIT(AHB1RST_REG_OFFSET, 4U), /*!< GPIOE clock reset */ 666 RCU_GPIOFRST = RCU_REGIDX_BIT(AHB1RST_REG_OFFSET, 5U), /*!< GPIOF clock reset */ 667 RCU_GPIOGRST = RCU_REGIDX_BIT(AHB1RST_REG_OFFSET, 6U), /*!< GPIOG clock reset */ 668 RCU_GPIOHRST = RCU_REGIDX_BIT(AHB1RST_REG_OFFSET, 7U), /*!< GPIOH clock reset */ 669 RCU_GPIOIRST = RCU_REGIDX_BIT(AHB1RST_REG_OFFSET, 8U), /*!< GPIOI clock reset */ 670 RCU_CRCRST = RCU_REGIDX_BIT(AHB1RST_REG_OFFSET, 12U), /*!< CRC clock reset */ 671 RCU_DMA0RST = RCU_REGIDX_BIT(AHB1RST_REG_OFFSET, 21U), /*!< DMA0 clock reset */ 672 RCU_DMA1RST = RCU_REGIDX_BIT(AHB1RST_REG_OFFSET, 22U), /*!< DMA1 clock reset */ 673 RCU_IPARST = RCU_REGIDX_BIT(AHB1RST_REG_OFFSET, 23U), /*!< IPA clock reset */ 674 RCU_ENETRST = RCU_REGIDX_BIT(AHB1RST_REG_OFFSET, 25U), /*!< ENET clock reset */ 675 RCU_USBHSRST = RCU_REGIDX_BIT(AHB1RST_REG_OFFSET, 29U), /*!< USBHS clock reset */ 676 /* AHB2 peripherals */ 677 RCU_DCIRST = RCU_REGIDX_BIT(AHB2RST_REG_OFFSET, 0U), /*!< DCI clock reset */ 678 RCU_TRNGRST = RCU_REGIDX_BIT(AHB2RST_REG_OFFSET, 6U), /*!< TRNG clock reset */ 679 RCU_USBFSRST = RCU_REGIDX_BIT(AHB2RST_REG_OFFSET, 7U), /*!< USBFS clock reset */ 680 /* AHB3 peripherals */ 681 RCU_EXMCRST = RCU_REGIDX_BIT(AHB3RST_REG_OFFSET, 0U), /*!< EXMC clock reset */ 682 /* APB1 peripherals */ 683 RCU_TIMER1RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 0U), /*!< TIMER1 clock reset */ 684 RCU_TIMER2RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 1U), /*!< TIMER2 clock reset */ 685 RCU_TIMER3RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 2U), /*!< TIMER3 clock reset */ 686 RCU_TIMER4RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 3U), /*!< TIMER4 clock reset */ 687 RCU_TIMER5RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 4U), /*!< TIMER5 clock reset */ 688 RCU_TIMER6RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 5U), /*!< TIMER6 clock reset */ 689 RCU_TIMER11RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 6U), /*!< TIMER11 clock reset */ 690 RCU_TIMER12RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 7U), /*!< TIMER12 clock reset */ 691 RCU_TIMER13RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 8U), /*!< TIMER13 clock reset */ 692 RCU_WWDGTRST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 11U), /*!< WWDGT clock reset */ 693 RCU_SPI1RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 14U), /*!< SPI1 clock reset */ 694 RCU_SPI2RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 15U), /*!< SPI2 clock reset */ 695 RCU_USART1RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 17U), /*!< USART1 clock reset */ 696 RCU_USART2RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 18U), /*!< USART2 clock reset */ 697 RCU_UART3RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 19U), /*!< UART3 clock reset */ 698 RCU_UART4RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 20U), /*!< UART4 clock reset */ 699 RCU_I2C0RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 21U), /*!< I2C0 clock reset */ 700 RCU_I2C1RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 22U), /*!< I2C1 clock reset */ 701 RCU_I2C2RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 23U), /*!< I2C2 clock reset */ 702 RCU_CAN0RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 25U), /*!< CAN0 clock reset */ 703 RCU_CAN1RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 26U), /*!< CAN1 clock reset */ 704 RCU_PMURST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 28U), /*!< PMU clock reset */ 705 RCU_DACRST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 29U), /*!< DAC clock reset */ 706 RCU_UART6RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 30U), /*!< UART6 clock reset */ 707 RCU_UART7RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 31U), /*!< UART7 clock reset */ 708 /* APB2 peripherals */ 709 RCU_TIMER0RST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 0U), /*!< TIMER0 clock reset */ 710 RCU_TIMER7RST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 1U), /*!< TIMER7 clock reset */ 711 RCU_USART0RST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 4U), /*!< USART0 clock reset */ 712 RCU_USART5RST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 5U), /*!< USART5 clock reset */ 713 RCU_ADCRST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 8U), /*!< ADCs all clock reset */ 714 RCU_SDIORST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 11U), /*!< SDIO clock reset */ 715 RCU_SPI0RST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 12U), /*!< SPI0 clock reset */ 716 RCU_SPI3RST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 13U), /*!< SPI3 clock reset */ 717 RCU_SYSCFGRST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 14U), /*!< SYSCFG clock reset */ 718 RCU_TIMER8RST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 16U), /*!< TIMER8 clock reset */ 719 RCU_TIMER9RST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 17U), /*!< TIMER9 clock reset */ 720 RCU_TIMER10RST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 18U), /*!< TIMER10 clock reset */ 721 RCU_SPI4RST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 20U), /*!< SPI4 clock reset */ 722 RCU_SPI5RST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 21U), /*!< SPI5 clock reset */ 723 RCU_TLIRST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 26U), /*!< TLI clock reset */ 724 /* APB1 additional peripherals */ 725 RCU_CTCRST = RCU_REGIDX_BIT(ADD_APB1RST_REG_OFFSET, 27U), /*!< CTC clock reset */ 726 RCU_IREFRST = RCU_REGIDX_BIT(ADD_APB1RST_REG_OFFSET, 31U) /*!< IREF clock reset */ 727 }rcu_periph_reset_enum; 728 729 /* clock stabilization and peripheral reset flags */ 730 typedef enum 731 { 732 /* clock stabilization flags */ 733 RCU_FLAG_IRC16MSTB = RCU_REGIDX_BIT(CTL_REG_OFFSET, 1U), /*!< IRC16M stabilization flags */ 734 RCU_FLAG_HXTALSTB = RCU_REGIDX_BIT(CTL_REG_OFFSET, 17U), /*!< HXTAL stabilization flags */ 735 RCU_FLAG_PLLSTB = RCU_REGIDX_BIT(CTL_REG_OFFSET, 25U), /*!< PLL stabilization flags */ 736 RCU_FLAG_PLLI2SSTB = RCU_REGIDX_BIT(CTL_REG_OFFSET, 27U), /*!< PLLI2S stabilization flags */ 737 RCU_FLAG_PLLSAISTB = RCU_REGIDX_BIT(CTL_REG_OFFSET, 29U), /*!< PLLSAI stabilization flags */ 738 RCU_FLAG_LXTALSTB = RCU_REGIDX_BIT(BDCTL_REG_OFFSET, 1U), /*!< LXTAL stabilization flags */ 739 RCU_FLAG_IRC32KSTB = RCU_REGIDX_BIT(RSTSCK_REG_OFFSET, 1U), /*!< IRC32K stabilization flags */ 740 RCU_FLAG_IRC48MSTB = RCU_REGIDX_BIT(ADDCTL_REG_OFFSET, 17U), /*!< IRC48M stabilization flags */ 741 /* reset source flags */ 742 RCU_FLAG_BORRST = RCU_REGIDX_BIT(RSTSCK_REG_OFFSET, 25U), /*!< BOR reset flags */ 743 RCU_FLAG_EPRST = RCU_REGIDX_BIT(RSTSCK_REG_OFFSET, 26U), /*!< External PIN reset flags */ 744 RCU_FLAG_PORRST = RCU_REGIDX_BIT(RSTSCK_REG_OFFSET, 27U), /*!< power reset flags */ 745 RCU_FLAG_SWRST = RCU_REGIDX_BIT(RSTSCK_REG_OFFSET, 28U), /*!< Software reset flags */ 746 RCU_FLAG_FWDGTRST = RCU_REGIDX_BIT(RSTSCK_REG_OFFSET, 29U), /*!< FWDGT reset flags */ 747 RCU_FLAG_WWDGTRST = RCU_REGIDX_BIT(RSTSCK_REG_OFFSET, 30U), /*!< WWDGT reset flags */ 748 RCU_FLAG_LPRST = RCU_REGIDX_BIT(RSTSCK_REG_OFFSET, 31U), /*!< Low-power reset flags */ 749 }rcu_flag_enum; 750 751 /* clock stabilization and ckm interrupt flags */ 752 typedef enum 753 { 754 RCU_INT_FLAG_IRC32KSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 0U), /*!< IRC32K stabilization interrupt flag */ 755 RCU_INT_FLAG_LXTALSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 1U), /*!< LXTAL stabilization interrupt flag */ 756 RCU_INT_FLAG_IRC16MSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 2U), /*!< IRC16M stabilization interrupt flag */ 757 RCU_INT_FLAG_HXTALSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 3U), /*!< HXTAL stabilization interrupt flag */ 758 RCU_INT_FLAG_PLLSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 4U), /*!< PLL stabilization interrupt flag */ 759 RCU_INT_FLAG_PLLI2SSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 5U), /*!< PLLI2S stabilization interrupt flag */ 760 RCU_INT_FLAG_PLLSAISTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 6U), /*!< PLLSAI stabilization interrupt flag */ 761 RCU_INT_FLAG_CKM = RCU_REGIDX_BIT(INT_REG_OFFSET, 7U), /*!< HXTAL clock stuck interrupt flag */ 762 RCU_INT_FLAG_IRC48MSTB = RCU_REGIDX_BIT(ADDINT_REG_OFFSET, 6U), /*!< IRC48M stabilization interrupt flag */ 763 }rcu_int_flag_enum; 764 765 /* clock stabilization and stuck interrupt flags clear */ 766 typedef enum 767 { 768 RCU_INT_FLAG_IRC32KSTB_CLR = RCU_REGIDX_BIT(INT_REG_OFFSET, 16U), /*!< IRC32K stabilization interrupt flags clear */ 769 RCU_INT_FLAG_LXTALSTB_CLR = RCU_REGIDX_BIT(INT_REG_OFFSET, 17U), /*!< LXTAL stabilization interrupt flags clear */ 770 RCU_INT_FLAG_IRC16MSTB_CLR = RCU_REGIDX_BIT(INT_REG_OFFSET, 18U), /*!< IRC16M stabilization interrupt flags clear */ 771 RCU_INT_FLAG_HXTALSTB_CLR = RCU_REGIDX_BIT(INT_REG_OFFSET, 19U), /*!< HXTAL stabilization interrupt flags clear */ 772 RCU_INT_FLAG_PLLSTB_CLR = RCU_REGIDX_BIT(INT_REG_OFFSET, 20U), /*!< PLL stabilization interrupt flags clear */ 773 RCU_INT_FLAG_PLLI2SSTB_CLR = RCU_REGIDX_BIT(INT_REG_OFFSET, 21U), /*!< PLLI2S stabilization interrupt flags clear */ 774 RCU_INT_FLAG_PLLSAISTB_CLR = RCU_REGIDX_BIT(INT_REG_OFFSET, 22U), /*!< PLLSAI stabilization interrupt flags clear */ 775 RCU_INT_FLAG_CKM_CLR = RCU_REGIDX_BIT(INT_REG_OFFSET, 23U), /*!< CKM interrupt flags clear */ 776 RCU_INT_FLAG_IRC48MSTB_CLR = RCU_REGIDX_BIT(ADDINT_REG_OFFSET, 22U), /*!< internal 48 MHz RC oscillator stabilization interrupt clear */ 777 }rcu_int_flag_clear_enum; 778 779 /* clock stabilization interrupt enable or disable */ 780 typedef enum 781 { 782 RCU_INT_IRC32KSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 8U), /*!< IRC32K stabilization interrupt */ 783 RCU_INT_LXTALSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 9U), /*!< LXTAL stabilization interrupt */ 784 RCU_INT_IRC16MSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 10U), /*!< IRC16M stabilization interrupt */ 785 RCU_INT_HXTALSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 11U), /*!< HXTAL stabilization interrupt */ 786 RCU_INT_PLLSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 12U), /*!< PLL stabilization interrupt */ 787 RCU_INT_PLLI2SSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 13U), /*!< PLLI2S stabilization interrupt */ 788 RCU_INT_PLLSAISTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 14U), /*!< PLLSAI stabilization interrupt */ 789 RCU_INT_IRC48MSTB = RCU_REGIDX_BIT(ADDINT_REG_OFFSET, 14U), /*!< internal 48 MHz RC oscillator stabilization interrupt */ 790 }rcu_int_enum; 791 792 /* oscillator types */ 793 typedef enum 794 { 795 RCU_HXTAL = RCU_REGIDX_BIT(CTL_REG_OFFSET, 16U), /*!< HXTAL */ 796 RCU_LXTAL = RCU_REGIDX_BIT(BDCTL_REG_OFFSET, 0U), /*!< LXTAL */ 797 RCU_IRC16M = RCU_REGIDX_BIT(CTL_REG_OFFSET, 0U), /*!< IRC16M */ 798 RCU_IRC48M = RCU_REGIDX_BIT(ADDCTL_REG_OFFSET, 16U), /*!< IRC48M */ 799 RCU_IRC32K = RCU_REGIDX_BIT(RSTSCK_REG_OFFSET, 0U), /*!< IRC32K */ 800 RCU_PLL_CK = RCU_REGIDX_BIT(CTL_REG_OFFSET, 24U), /*!< PLL */ 801 RCU_PLLI2S_CK = RCU_REGIDX_BIT(CTL_REG_OFFSET, 26U), /*!< PLLI2S */ 802 RCU_PLLSAI_CK = RCU_REGIDX_BIT(CTL_REG_OFFSET, 28U), /*!< PLLSAI */ 803 }rcu_osci_type_enum; 804 805 /* rcu clock frequency */ 806 typedef enum 807 { 808 CK_SYS = 0, /*!< system clock */ 809 CK_AHB, /*!< AHB clock */ 810 CK_APB1, /*!< APB1 clock */ 811 CK_APB2, /*!< APB2 clock */ 812 }rcu_clock_freq_enum; 813 814 /* RCU_CFG0 register bit define */ 815 /* system clock source select */ 816 #define CFG0_SCS(regval) (BITS(0,1) & ((uint32_t)(regval) << 0)) 817 #define RCU_CKSYSSRC_IRC16M CFG0_SCS(0) /*!< system clock source select IRC16M */ 818 #define RCU_CKSYSSRC_HXTAL CFG0_SCS(1) /*!< system clock source select HXTAL */ 819 #define RCU_CKSYSSRC_PLLP CFG0_SCS(2) /*!< system clock source select PLLP */ 820 821 /* system clock source select status */ 822 #define CFG0_SCSS(regval) (BITS(2,3) & ((uint32_t)(regval) << 2)) 823 #define RCU_SCSS_IRC16M CFG0_SCSS(0) /*!< system clock source select IRC16M */ 824 #define RCU_SCSS_HXTAL CFG0_SCSS(1) /*!< system clock source select HXTAL */ 825 #define RCU_SCSS_PLLP CFG0_SCSS(2) /*!< system clock source select PLLP */ 826 827 /* AHB prescaler selection */ 828 #define CFG0_AHBPSC(regval) (BITS(4,7) & ((uint32_t)(regval) << 4)) 829 #define RCU_AHB_CKSYS_DIV1 CFG0_AHBPSC(0) /*!< AHB prescaler select CK_SYS */ 830 #define RCU_AHB_CKSYS_DIV2 CFG0_AHBPSC(8) /*!< AHB prescaler select CK_SYS/2 */ 831 #define RCU_AHB_CKSYS_DIV4 CFG0_AHBPSC(9) /*!< AHB prescaler select CK_SYS/4 */ 832 #define RCU_AHB_CKSYS_DIV8 CFG0_AHBPSC(10) /*!< AHB prescaler select CK_SYS/8 */ 833 #define RCU_AHB_CKSYS_DIV16 CFG0_AHBPSC(11) /*!< AHB prescaler select CK_SYS/16 */ 834 #define RCU_AHB_CKSYS_DIV64 CFG0_AHBPSC(12) /*!< AHB prescaler select CK_SYS/64 */ 835 #define RCU_AHB_CKSYS_DIV128 CFG0_AHBPSC(13) /*!< AHB prescaler select CK_SYS/128 */ 836 #define RCU_AHB_CKSYS_DIV256 CFG0_AHBPSC(14) /*!< AHB prescaler select CK_SYS/256 */ 837 #define RCU_AHB_CKSYS_DIV512 CFG0_AHBPSC(15) /*!< AHB prescaler select CK_SYS/512 */ 838 839 /* APB1 prescaler selection */ 840 #define CFG0_APB1PSC(regval) (BITS(10,12) & ((uint32_t)(regval) << 10)) 841 #define RCU_APB1_CKAHB_DIV1 CFG0_APB1PSC(0) /*!< APB1 prescaler select CK_AHB */ 842 #define RCU_APB1_CKAHB_DIV2 CFG0_APB1PSC(4) /*!< APB1 prescaler select CK_AHB/2 */ 843 #define RCU_APB1_CKAHB_DIV4 CFG0_APB1PSC(5) /*!< APB1 prescaler select CK_AHB/4 */ 844 #define RCU_APB1_CKAHB_DIV8 CFG0_APB1PSC(6) /*!< APB1 prescaler select CK_AHB/8 */ 845 #define RCU_APB1_CKAHB_DIV16 CFG0_APB1PSC(7) /*!< APB1 prescaler select CK_AHB/16 */ 846 847 /* APB2 prescaler selection */ 848 #define CFG0_APB2PSC(regval) (BITS(13,15) & ((uint32_t)(regval) << 13)) 849 #define RCU_APB2_CKAHB_DIV1 CFG0_APB2PSC(0) /*!< APB2 prescaler select CK_AHB */ 850 #define RCU_APB2_CKAHB_DIV2 CFG0_APB2PSC(4) /*!< APB2 prescaler select CK_AHB/2 */ 851 #define RCU_APB2_CKAHB_DIV4 CFG0_APB2PSC(5) /*!< APB2 prescaler select CK_AHB/4 */ 852 #define RCU_APB2_CKAHB_DIV8 CFG0_APB2PSC(6) /*!< APB2 prescaler select CK_AHB/8 */ 853 #define RCU_APB2_CKAHB_DIV16 CFG0_APB2PSC(7) /*!< APB2 prescaler select CK_AHB/16 */ 854 855 /* RTC clock divider factor from HXTAL clock */ 856 #define CFG0_RTCDIV(regval) (BITS(16,20) & ((uint32_t)(regval) << 16)) 857 #define RCU_RTC_HXTAL_NONE CFG0_RTCDIV(0) /*!< no clock for RTC */ 858 #define RCU_RTC_HXTAL_DIV2 CFG0_RTCDIV(2) /*!< RTCDIV clock select CK_HXTAL/2 */ 859 #define RCU_RTC_HXTAL_DIV3 CFG0_RTCDIV(3) /*!< RTCDIV clock select CK_HXTAL/3 */ 860 #define RCU_RTC_HXTAL_DIV4 CFG0_RTCDIV(4) /*!< RTCDIV clock select CK_HXTAL/4 */ 861 #define RCU_RTC_HXTAL_DIV5 CFG0_RTCDIV(5) /*!< RTCDIV clock select CK_HXTAL/5 */ 862 #define RCU_RTC_HXTAL_DIV6 CFG0_RTCDIV(6) /*!< RTCDIV clock select CK_HXTAL/6 */ 863 #define RCU_RTC_HXTAL_DIV7 CFG0_RTCDIV(7) /*!< RTCDIV clock select CK_HXTAL/7 */ 864 #define RCU_RTC_HXTAL_DIV8 CFG0_RTCDIV(8) /*!< RTCDIV clock select CK_HXTAL/8 */ 865 #define RCU_RTC_HXTAL_DIV9 CFG0_RTCDIV(9) /*!< RTCDIV clock select CK_HXTAL/9 */ 866 #define RCU_RTC_HXTAL_DIV10 CFG0_RTCDIV(10) /*!< RTCDIV clock select CK_HXTAL/10 */ 867 #define RCU_RTC_HXTAL_DIV11 CFG0_RTCDIV(11) /*!< RTCDIV clock select CK_HXTAL/11 */ 868 #define RCU_RTC_HXTAL_DIV12 CFG0_RTCDIV(12) /*!< RTCDIV clock select CK_HXTAL/12 */ 869 #define RCU_RTC_HXTAL_DIV13 CFG0_RTCDIV(13) /*!< RTCDIV clock select CK_HXTAL/13 */ 870 #define RCU_RTC_HXTAL_DIV14 CFG0_RTCDIV(14) /*!< RTCDIV clock select CK_HXTAL/14 */ 871 #define RCU_RTC_HXTAL_DIV15 CFG0_RTCDIV(15) /*!< RTCDIV clock select CK_HXTAL/15 */ 872 #define RCU_RTC_HXTAL_DIV16 CFG0_RTCDIV(16) /*!< RTCDIV clock select CK_HXTAL/16 */ 873 #define RCU_RTC_HXTAL_DIV17 CFG0_RTCDIV(17) /*!< RTCDIV clock select CK_HXTAL/17 */ 874 #define RCU_RTC_HXTAL_DIV18 CFG0_RTCDIV(18) /*!< RTCDIV clock select CK_HXTAL/18 */ 875 #define RCU_RTC_HXTAL_DIV19 CFG0_RTCDIV(19) /*!< RTCDIV clock select CK_HXTAL/19 */ 876 #define RCU_RTC_HXTAL_DIV20 CFG0_RTCDIV(20) /*!< RTCDIV clock select CK_HXTAL/20 */ 877 #define RCU_RTC_HXTAL_DIV21 CFG0_RTCDIV(21) /*!< RTCDIV clock select CK_HXTAL/21 */ 878 #define RCU_RTC_HXTAL_DIV22 CFG0_RTCDIV(22) /*!< RTCDIV clock select CK_HXTAL/22 */ 879 #define RCU_RTC_HXTAL_DIV23 CFG0_RTCDIV(23) /*!< RTCDIV clock select CK_HXTAL/23 */ 880 #define RCU_RTC_HXTAL_DIV24 CFG0_RTCDIV(24) /*!< RTCDIV clock select CK_HXTAL/24 */ 881 #define RCU_RTC_HXTAL_DIV25 CFG0_RTCDIV(25) /*!< RTCDIV clock select CK_HXTAL/25 */ 882 #define RCU_RTC_HXTAL_DIV26 CFG0_RTCDIV(26) /*!< RTCDIV clock select CK_HXTAL/26 */ 883 #define RCU_RTC_HXTAL_DIV27 CFG0_RTCDIV(27) /*!< RTCDIV clock select CK_HXTAL/27 */ 884 #define RCU_RTC_HXTAL_DIV28 CFG0_RTCDIV(28) /*!< RTCDIV clock select CK_HXTAL/28 */ 885 #define RCU_RTC_HXTAL_DIV29 CFG0_RTCDIV(29) /*!< RTCDIV clock select CK_HXTAL/29 */ 886 #define RCU_RTC_HXTAL_DIV30 CFG0_RTCDIV(30) /*!< RTCDIV clock select CK_HXTAL/30 */ 887 #define RCU_RTC_HXTAL_DIV31 CFG0_RTCDIV(31) /*!< RTCDIV clock select CK_HXTAL/31 */ 888 889 /* CKOUT0 Clock source selection */ 890 #define CFG0_CKOUT0SEL(regval) (BITS(21,22) & ((uint32_t)(regval) << 21)) 891 #define RCU_CKOUT0SRC_IRC16M CFG0_CKOUT0SEL(0) /*!< internal 16M RC oscillator clock selected */ 892 #define RCU_CKOUT0SRC_LXTAL CFG0_CKOUT0SEL(1) /*!< low speed crystal oscillator clock (LXTAL) selected */ 893 #define RCU_CKOUT0SRC_HXTAL CFG0_CKOUT0SEL(2) /*!< high speed crystal oscillator clock (HXTAL) selected */ 894 #define RCU_CKOUT0SRC_PLLP CFG0_CKOUT0SEL(3) /*!< CK_PLLP clock selected */ 895 896 /* I2S Clock source selection */ 897 #define RCU_I2SSRC_PLLI2S ((uint32_t)0x00000000U) /*!< PLLI2S output clock selected as I2S source clock */ 898 #define RCU_I2SSRC_I2S_CKIN RCU_CFG0_I2SSEL /*!< external I2S_CKIN pin selected as I2S source clock */ 899 900 /* The CK_OUT0 divider */ 901 #define CFG0_CKOUT0DIV(regval) (BITS(24,26) & ((uint32_t)(regval) << 24)) 902 #define RCU_CKOUT0_DIV1 CFG0_CKOUT0DIV(0) /*!< CK_OUT0 is divided by 1 */ 903 #define RCU_CKOUT0_DIV2 CFG0_CKOUT0DIV(4) /*!< CK_OUT0 is divided by 2 */ 904 #define RCU_CKOUT0_DIV3 CFG0_CKOUT0DIV(5) /*!< CK_OUT0 is divided by 3 */ 905 #define RCU_CKOUT0_DIV4 CFG0_CKOUT0DIV(6) /*!< CK_OUT0 is divided by 4 */ 906 #define RCU_CKOUT0_DIV5 CFG0_CKOUT0DIV(7) /*!< CK_OUT0 is divided by 5 */ 907 908 /* The CK_OUT1 divider */ 909 #define CFG0_CKOUT1DIV(regval) (BITS(27,29) & ((uint32_t)(regval) << 27)) 910 #define RCU_CKOUT1_DIV1 CFG0_CKOUT1DIV(0) /*!< CK_OUT1 is divided by 1 */ 911 #define RCU_CKOUT1_DIV2 CFG0_CKOUT1DIV(4) /*!< CK_OUT1 is divided by 2 */ 912 #define RCU_CKOUT1_DIV3 CFG0_CKOUT1DIV(5) /*!< CK_OUT1 is divided by 3 */ 913 #define RCU_CKOUT1_DIV4 CFG0_CKOUT1DIV(6) /*!< CK_OUT1 is divided by 4 */ 914 #define RCU_CKOUT1_DIV5 CFG0_CKOUT1DIV(7) /*!< CK_OUT1 is divided by 5 */ 915 916 /* CKOUT1 Clock source selection */ 917 #define CFG0_CKOUT1SEL(regval) (BITS(30,31) & ((uint32_t)(regval) << 30)) 918 #define RCU_CKOUT1SRC_SYSTEMCLOCK CFG0_CKOUT1SEL(0) /*!< system clock selected */ 919 #define RCU_CKOUT1SRC_PLLI2SR CFG0_CKOUT1SEL(1) /*!< CK_PLLI2SR clock selected */ 920 #define RCU_CKOUT1SRC_HXTAL CFG0_CKOUT1SEL(2) /*!< high speed crystal oscillator clock (HXTAL) selected */ 921 #define RCU_CKOUT1SRC_PLLP CFG0_CKOUT1SEL(3) /*!< CK_PLLP clock selected */ 922 923 /* RCU_CFG1 register bit define */ 924 /* the divider factor from PLLI2SQ clock */ 925 #define CFG1_PLLI2SQDIV(regval) (BITS(0,4) & ((uint32_t)(regval) << 0)) 926 #define RCU_PLLI2SQ_DIV1 CFG1_PLLI2SQDIV(0) /*!< CK_PLLI2SQDIV clock select CK_PLLI2SQ/1 */ 927 #define RCU_PLLI2SQ_DIV2 CFG1_PLLI2SQDIV(1) /*!< CK_PLLI2SQDIV clock select CK_PLLI2SQ/2 */ 928 #define RCU_PLLI2SQ_DIV3 CFG1_PLLI2SQDIV(2) /*!< CK_PLLI2SQDIV clock select CK_PLLI2SQ/3 */ 929 #define RCU_PLLI2SQ_DIV4 CFG1_PLLI2SQDIV(3) /*!< CK_PLLI2SQDIV clock select CK_PLLI2SQ/4 */ 930 #define RCU_PLLI2SQ_DIV5 CFG1_PLLI2SQDIV(4) /*!< CK_PLLI2SQDIV clock select CK_PLLI2SQ/5 */ 931 #define RCU_PLLI2SQ_DIV6 CFG1_PLLI2SQDIV(5) /*!< CK_PLLI2SQDIV clock select CK_PLLI2SQ/6 */ 932 #define RCU_PLLI2SQ_DIV7 CFG1_PLLI2SQDIV(6) /*!< CK_PLLI2SQDIV clock select CK_PLLI2SQ/7 */ 933 #define RCU_PLLI2SQ_DIV8 CFG1_PLLI2SQDIV(7) /*!< CK_PLLI2SQDIV clock select CK_PLLI2SQ/8 */ 934 #define RCU_PLLI2SQ_DIV9 CFG1_PLLI2SQDIV(8) /*!< CK_PLLI2SQDIV clock select CK_PLLI2SQ/9 */ 935 #define RCU_PLLI2SQ_DIV10 CFG1_PLLI2SQDIV(9) /*!< CK_PLLI2SQDIV clock select CK_PLLI2SQ/10 */ 936 #define RCU_PLLI2SQ_DIV11 CFG1_PLLI2SQDIV(10) /*!< CK_PLLI2SQDIV clock select CK_PLLI2SQ/11 */ 937 #define RCU_PLLI2SQ_DIV12 CFG1_PLLI2SQDIV(11) /*!< CK_PLLI2SQDIV clock select CK_PLLI2SQ/12 */ 938 #define RCU_PLLI2SQ_DIV13 CFG1_PLLI2SQDIV(12) /*!< CK_PLLI2SQDIV clock select CK_PLLI2SQ/13 */ 939 #define RCU_PLLI2SQ_DIV14 CFG1_PLLI2SQDIV(13) /*!< CK_PLLI2SQDIV clock select CK_PLLI2SQ/14 */ 940 #define RCU_PLLI2SQ_DIV15 CFG1_PLLI2SQDIV(14) /*!< CK_PLLI2SQDIV clock select CK_PLLI2SQ/15 */ 941 #define RCU_PLLI2SQ_DIV16 CFG1_PLLI2SQDIV(15) /*!< CK_PLLI2SQDIV clock select CK_PLLI2SQ/16 */ 942 #define RCU_PLLI2SQ_DIV17 CFG1_PLLI2SQDIV(16) /*!< CK_PLLI2SQDIV clock select CK_PLLI2SQ/17 */ 943 #define RCU_PLLI2SQ_DIV18 CFG1_PLLI2SQDIV(17) /*!< CK_PLLI2SQDIV clock select CK_PLLI2SQ/18 */ 944 #define RCU_PLLI2SQ_DIV19 CFG1_PLLI2SQDIV(18) /*!< CK_PLLI2SQDIV clock select CK_PLLI2SQ/19 */ 945 #define RCU_PLLI2SQ_DIV20 CFG1_PLLI2SQDIV(19) /*!< CK_PLLI2SQDIV clock select CK_PLLI2SQ/20 */ 946 #define RCU_PLLI2SQ_DIV21 CFG1_PLLI2SQDIV(20) /*!< CK_PLLI2SQDIV clock select CK_PLLI2SQ/21 */ 947 #define RCU_PLLI2SQ_DIV22 CFG1_PLLI2SQDIV(21) /*!< CK_PLLI2SQDIV clock select CK_PLLI2SQ/22 */ 948 #define RCU_PLLI2SQ_DIV23 CFG1_PLLI2SQDIV(22) /*!< CK_PLLI2SQDIV clock select CK_PLLI2SQ/23 */ 949 #define RCU_PLLI2SQ_DIV24 CFG1_PLLI2SQDIV(23) /*!< CK_PLLI2SQDIV clock select CK_PLLI2SQ/24 */ 950 #define RCU_PLLI2SQ_DIV25 CFG1_PLLI2SQDIV(24) /*!< CK_PLLI2SQDIV clock select CK_PLLI2SQ/25 */ 951 #define RCU_PLLI2SQ_DIV26 CFG1_PLLI2SQDIV(25) /*!< CK_PLLI2SQDIV clock select CK_PLLI2SQ/26 */ 952 #define RCU_PLLI2SQ_DIV27 CFG1_PLLI2SQDIV(26) /*!< CK_PLLI2SQDIV clock select CK_PLLI2SQ/27 */ 953 #define RCU_PLLI2SQ_DIV28 CFG1_PLLI2SQDIV(27) /*!< CK_PLLI2SQDIV clock select CK_PLLI2SQ/28 */ 954 #define RCU_PLLI2SQ_DIV29 CFG1_PLLI2SQDIV(28) /*!< CK_PLLI2SQDIV clock select CK_PLLI2SQ/29 */ 955 #define RCU_PLLI2SQ_DIV30 CFG1_PLLI2SQDIV(29) /*!< CK_PLLI2SQDIV clock select CK_PLLI2SQ/30 */ 956 #define RCU_PLLI2SQ_DIV31 CFG1_PLLI2SQDIV(30) /*!< CK_PLLI2SQDIV clock select CK_PLLI2SQ/31 */ 957 #define RCU_PLLI2SQ_DIV32 CFG1_PLLI2SQDIV(31) /*!< CK_PLLI2SQDIV clock select CK_PLLI2SQ/32 */ 958 959 /* the divider factor from PLLSAIR clock */ 960 #define CFG1_PLLSAIRDIV(regval) (BITS(16,17) & ((uint32_t)(regval) << 16)) 961 #define RCU_PLLSAIR_DIV2 CFG1_PLLSAIRDIV(0) /*!< CK_PLLSAIRDIV clock select CK_PLLSAIR/2 */ 962 #define RCU_PLLSAIR_DIV4 CFG1_PLLSAIRDIV(1) /*!< CK_PLLSAIRDIV clock select CK_PLLSAIR/4 */ 963 #define RCU_PLLSAIR_DIV8 CFG1_PLLSAIRDIV(2) /*!< CK_PLLSAIRDIV clock select CK_PLLSAIR/8 */ 964 #define RCU_PLLSAIR_DIV16 CFG1_PLLSAIRDIV(3) /*!< CK_PLLSAIRDIV clock select CK_PLLSAIR/16 */ 965 966 /* TIMER clock selection */ 967 #define RCU_TIMER_PSC_MUL2 ~RCU_CFG1_TIMERSEL /*!< if APB1PSC/APB2PSC in RCU_CFG0 register is 0b0xx(CK_APBx = CK_AHB) 968 or 0b100(CK_APBx = CK_AHB/2), the TIMER clock is equal to CK_AHB(CK_TIMERx = CK_AHB). 969 or else, the TIMER clock is twice the corresponding APB clock (TIMER in APB1 domain: CK_TIMERx = 2 x CK_APB1; 970 TIMER in APB2 domain: CK_TIMERx = 2 x CK_APB2) */ 971 #define RCU_TIMER_PSC_MUL4 RCU_CFG1_TIMERSEL /*!< if APB1PSC/APB2PSC in RCU_CFG0 register is 0b0xx(CK_APBx = CK_AHB), 972 0b100(CK_APBx = CK_AHB/2), or 0b101(CK_APBx = CK_AHB/4), the TIMER clock is equal to CK_AHB(CK_TIMERx = CK_AHB). 973 or else, the TIMER clock is four timers the corresponding APB clock (TIMER in APB1 domain: CK_TIMERx = 4 x CK_APB1; 974 TIMER in APB2 domain: CK_TIMERx = 4 x CK_APB2) */ 975 976 /* RCU_PLLSSCTL register bit define */ 977 /* PLL spread spectrum modulation type select */ 978 #define RCU_SS_TYPE_CENTER ((uint32_t)0x00000000U) /*!< center type is selected */ 979 #define RCU_SS_TYPE_DOWN RCU_PLLSSCTL_SS_TYPE /*!< down type is selected */ 980 981 /* RCU_PLL register bit define */ 982 /* The PLL VCO source clock prescaler */ 983 #define RCU_PLLPSC_DIV_MIN ((uint32_t)2U) /*!< PLLPSC_DIV min value */ 984 #define RCU_PLLPSC_DIV_MAX ((uint32_t)63U) /*!< PLLPSC_DIV max value */ 985 986 /* The PLL VCO clock multi factor */ 987 #define RCU_PLLN_MUL_MIN ((uint32_t)64U) /*!< PLLN_MUL min value */ 988 #define RCU_PLLN_MUL_MAX ((uint32_t)500U) /*!< PLLN_MUL max value */ 989 #define RCU_SS_MODULATION_CENTER_INC ((uint32_t)5U) /*!< minimum factor of PLLN in center mode */ 990 #define RCU_SS_MODULATION_DOWN_INC ((uint32_t)7U) /*!< minimum factor of PLLN in down mode */ 991 992 /* The PLLP output frequency division factor from PLL VCO clock */ 993 #define RCU_PLLP_DIV_MIN ((uint32_t)2U) /*!< PLLP_DIV min value */ 994 #define RCU_PLLP_DIV_MAX ((uint32_t)8U) /*!< PLLP_DIV max value */ 995 996 /* PLL Clock Source Selection */ 997 #define RCU_PLLSRC_IRC16M ((uint32_t)0x00000000U) /*!< IRC16M clock selected as source clock of PLL, PLLSAI, PLLI2S */ 998 #define RCU_PLLSRC_HXTAL RCU_PLL_PLLSEL /*!< HXTAL clock selected as source clock of PLL, PLLSAI, PLLI2S */ 999 1000 /* The PLL Q output frequency division factor from PLL VCO clock */ 1001 #define RCU_PLLQ_DIV_MIN ((uint32_t)2U) /*!< PLLQ_DIV min value */ 1002 #define RCU_PLLQ_DIV_MAX ((uint32_t)15U) /*!< PLLQ_DIV max value */ 1003 1004 #define CHECK_PLL_PSC_VALID(val) (((val) >= RCU_PLLPSC_DIV_MIN)&&((val) <= RCU_PLLPSC_DIV_MAX)) 1005 #define CHECK_PLL_N_VALID(val, inc) (((val) >= (RCU_PLLN_MUL_MIN + (inc)))&&((val) <= RCU_PLLN_MUL_MAX)) 1006 #define CHECK_PLL_P_VALID(val) (((val) == 2U) || ((val) == 4U) || ((val) == 6U) || ((val) == 8U)) 1007 #define CHECK_PLL_Q_VALID(val) (((val) >= RCU_PLLQ_DIV_MIN)&&((val) <= RCU_PLLQ_DIV_MAX)) 1008 1009 /* RCU_BDCTL register bit define */ 1010 /* LXTAL drive capability */ 1011 #define RCU_LXTALDRI_LOWER_DRIVE ((uint32_t)0x00000000) /*!< LXTAL drive capability is selected lower */ 1012 #define RCU_LXTALDRI_HIGHER_DRIVE RCU_BDCTL_LXTALDRI /*!< LXTAL drive capability is selected higher */ 1013 1014 /* RTC clock entry selection */ 1015 #define BDCTL_RTCSRC(regval) (BITS(8,9) & ((uint32_t)(regval) << 8)) 1016 #define RCU_RTCSRC_NONE BDCTL_RTCSRC(0) /*!< no clock selected */ 1017 #define RCU_RTCSRC_LXTAL BDCTL_RTCSRC(1) /*!< RTC source clock select LXTAL */ 1018 #define RCU_RTCSRC_IRC32K BDCTL_RTCSRC(2) /*!< RTC source clock select IRC32K */ 1019 #define RCU_RTCSRC_HXTAL_DIV_RTCDIV BDCTL_RTCSRC(3) /*!< RTC source clock select HXTAL/RTCDIV */ 1020 1021 /* RCU_PLLI2S register bit define */ 1022 /* The PLLI2S VCO clock multi factor */ 1023 #define RCU_PLLI2SN_MUL_MIN 50U 1024 #define RCU_PLLI2SN_MUL_MAX 500U 1025 1026 /* The PLLI2S Q output frequency division factor from PLLI2S VCO clock */ 1027 #define RCU_PLLI2SQ_DIV_MIN 2U 1028 #define RCU_PLLI2SQ_DIV_MAX 15U 1029 1030 /* The PLLI2S R output frequency division factor from PLLI2S VCO clock */ 1031 #define RCU_PLLI2SR_DIV_MIN 2U 1032 #define RCU_PLLI2SR_DIV_MAX 7U 1033 1034 /* RCU_PLLSAI register bit define */ 1035 /* The PLLSAI VCO clock multi factor */ 1036 #define RCU_PLLSAIN_MUL_MIN 50U 1037 #define RCU_PLLSAIN_MUL_MAX 500U 1038 1039 /* The PLLSAI P output frequency division factor from PLLSAI VCO clock */ 1040 #define RCU_PLLSAIP_DIV_MIN 2U 1041 #define RCU_PLLSAIP_DIV_MAX 8U 1042 1043 /* The PLLSAI Q output frequency division factor from PLLSAI VCO clock */ 1044 #define RCU_PLLSAIQ_DIV_MIN 2U 1045 #define RCU_PLLSAIQ_DIV_MAX 15U 1046 1047 /* The PLLSAI R output frequency division factor from PLLSAI VCO clock */ 1048 #define RCU_PLLSAIR_DIV_MIN 2U 1049 #define RCU_PLLSAIR_DIV_MAX 7U 1050 1051 #define CHECK_PLLI2S_PSC_VALID(val) (((val) >= RCU_PLLI2SPSC_DIV_MIN)&&((val) <= RCU_PLLI2SPSC_DIV_MAX)) 1052 #define CHECK_PLLI2S_N_VALID(val) (((val) >= RCU_PLLI2SN_MUL_MIN)&&((val) <= RCU_PLLI2SN_MUL_MAX)) 1053 #define CHECK_PLLI2S_Q_VALID(val) (((val) >= RCU_PLLI2SQ_DIV_MIN)&&((val) <= RCU_PLLI2SQ_DIV_MAX)) 1054 #define CHECK_PLLI2S_R_VALID(val) (((val) >= RCU_PLLI2SR_DIV_MIN)&&((val) <= RCU_PLLI2SR_DIV_MAX)) 1055 1056 #define CHECK_PLLSAI_N_VALID(val) (((val) >= (RCU_PLLSAIN_MUL_MIN))&&((val) <= RCU_PLLSAIN_MUL_MAX)) 1057 #define CHECK_PLLSAI_P_VALID(val) (((val) == 2U) || ((val) == 4U) || ((val) == 6U) || ((val) == 8U)) 1058 #define CHECK_PLLSAI_Q_VALID(val) (((val) >= RCU_PLLSAIQ_DIV_MIN)&&((val) <= RCU_PLLSAIQ_DIV_MAX)) 1059 #define CHECK_PLLSAI_R_VALID(val) (((val) >= RCU_PLLSAIR_DIV_MIN)&&((val) <= RCU_PLLSAIR_DIV_MAX)) 1060 1061 /* RCU_ADDCTL register bit define */ 1062 /* 48MHz clock selection */ 1063 #define RCU_CK48MSRC_PLL48M ((uint32_t)0x00000000U) /*!< CK48M source clock select PLL48M */ 1064 #define RCU_CK48MSRC_IRC48M RCU_ADDCTL_CK48MSEL /*!< CK48M source clock select IRC48M */ 1065 1066 /* PLL48M clock selection */ 1067 #define RCU_PLL48MSRC_PLLQ ((uint32_t)0x00000000U) /*!< PLL48M source clock select PLLQ */ 1068 #define RCU_PLL48MSRC_PLLSAIP RCU_ADDCTL_PLL48MSEL /*!< PLL48M source clock select PLLSAIP */ 1069 1070 /* Deep-sleep mode voltage */ 1071 #define DSV_DSLPVS(regval) (BITS(0,2) & ((uint32_t)(regval) << 0)) 1072 #define RCU_DEEPSLEEP_V_0 DSV_DSLPVS(0) /*!< core voltage is default value in deep-sleep mode */ 1073 #define RCU_DEEPSLEEP_V_1 DSV_DSLPVS(1) /*!< core voltage is (default value-0.1)V in deep-sleep mode(customers are not recommended to use it)*/ 1074 #define RCU_DEEPSLEEP_V_2 DSV_DSLPVS(2) /*!< core voltage is (default value-0.2)V in deep-sleep mode(customers are not recommended to use it)*/ 1075 #define RCU_DEEPSLEEP_V_3 DSV_DSLPVS(3) /*!< core voltage is (default value-0.3)V in deep-sleep mode(customers are not recommended to use it)*/ 1076 1077 1078 /* function declarations */ 1079 /* deinitialize the RCU */ 1080 void rcu_deinit(void); 1081 /* enable the peripherals clock */ 1082 void rcu_periph_clock_enable(rcu_periph_enum periph); 1083 /* disable the peripherals clock */ 1084 void rcu_periph_clock_disable(rcu_periph_enum periph); 1085 /* enable the peripherals clock when sleep mode */ 1086 void rcu_periph_clock_sleep_enable(rcu_periph_sleep_enum periph); 1087 /* disable the peripherals clock when sleep mode */ 1088 void rcu_periph_clock_sleep_disable(rcu_periph_sleep_enum periph); 1089 /* reset the peripherals */ 1090 void rcu_periph_reset_enable(rcu_periph_reset_enum periph_reset); 1091 /* disable reset the peripheral */ 1092 void rcu_periph_reset_disable(rcu_periph_reset_enum periph_reset); 1093 /* reset the BKP */ 1094 void rcu_bkp_reset_enable(void); 1095 /* disable the BKP reset */ 1096 void rcu_bkp_reset_disable(void); 1097 1098 /* configure the system clock source */ 1099 void rcu_system_clock_source_config(uint32_t ck_sys); 1100 /* get the system clock source */ 1101 uint32_t rcu_system_clock_source_get(void); 1102 /* configure the AHB prescaler selection */ 1103 void rcu_ahb_clock_config(uint32_t ck_ahb); 1104 /* configure the APB1 prescaler selection */ 1105 void rcu_apb1_clock_config(uint32_t ck_apb1); 1106 /* configure the APB2 prescaler selection */ 1107 void rcu_apb2_clock_config(uint32_t ck_apb2); 1108 /* configure the CK_OUT0 clock source and divider */ 1109 void rcu_ckout0_config(uint32_t ckout0_src, uint32_t ckout0_div); 1110 /* configure the CK_OUT1 clock source and divider */ 1111 void rcu_ckout1_config(uint32_t ckout1_src, uint32_t ckout1_div); 1112 /* configure the PLL clock source selection and PLL multiply factor */ 1113 ErrStatus rcu_pll_config(uint32_t pll_src, uint32_t pll_psc, uint32_t pll_n, uint32_t pll_p, uint32_t pll_q); 1114 /* configure the PLLI2S clock */ 1115 ErrStatus rcu_plli2s_config(uint32_t plli2s_n, uint32_t plli2s_r); 1116 /* configure the PLLSAI clock */ 1117 ErrStatus rcu_pllsai_config(uint32_t pllsai_n, uint32_t pllsai_p, uint32_t pllsai_r); 1118 /* configure the RTC clock source selection */ 1119 void rcu_rtc_clock_config(uint32_t rtc_clock_source); 1120 /* cconfigure the frequency division of RTC clock when HXTAL was selected as its clock source */ 1121 void rcu_rtc_div_config(uint32_t rtc_div); 1122 /* configure the I2S clock source selection */ 1123 void rcu_i2s_clock_config(uint32_t i2s_clock_source); 1124 /* configure the CK48M clock selection */ 1125 void rcu_ck48m_clock_config(uint32_t ck48m_clock_source); 1126 /* configure the PLL48M clock selection */ 1127 void rcu_pll48m_clock_config(uint32_t pll48m_clock_source); 1128 /* configure the TIMER clock prescaler selection */ 1129 void rcu_timer_clock_prescaler_config(uint32_t timer_clock_prescaler); 1130 /* configure the TLI clock division selection */ 1131 void rcu_tli_clock_div_config(uint32_t pllsai_r_div); 1132 1133 1134 /* get the clock stabilization and periphral reset flags */ 1135 FlagStatus rcu_flag_get(rcu_flag_enum flag); 1136 /* clear the reset flag */ 1137 void rcu_all_reset_flag_clear(void); 1138 /* get the clock stabilization interrupt and ckm flags */ 1139 FlagStatus rcu_interrupt_flag_get(rcu_int_flag_enum int_flag); 1140 /* clear the interrupt flags */ 1141 void rcu_interrupt_flag_clear(rcu_int_flag_clear_enum int_flag); 1142 /* enable the stabilization interrupt */ 1143 void rcu_interrupt_enable(rcu_int_enum interrupt); 1144 /* disable the stabilization interrupt */ 1145 void rcu_interrupt_disable(rcu_int_enum interrupt); 1146 1147 /* configure the LXTAL drive capability */ 1148 void rcu_lxtal_drive_capability_config(uint32_t lxtal_dricap); 1149 /* wait for oscillator stabilization flags is SET or oscillator startup is timeout */ 1150 ErrStatus rcu_osci_stab_wait(rcu_osci_type_enum osci); 1151 /* turn on the oscillator */ 1152 void rcu_osci_on(rcu_osci_type_enum osci); 1153 /* turn off the oscillator */ 1154 void rcu_osci_off(rcu_osci_type_enum osci); 1155 /* enable the oscillator bypass mode, HXTALEN or LXTALEN must be reset before it */ 1156 void rcu_osci_bypass_mode_enable(rcu_osci_type_enum osci); 1157 /* disable the oscillator bypass mode, HXTALEN or LXTALEN must be reset before it */ 1158 void rcu_osci_bypass_mode_disable(rcu_osci_type_enum osci); 1159 /* enable the HXTAL clock monitor */ 1160 void rcu_hxtal_clock_monitor_enable(void); 1161 /* disable the HXTAL clock monitor */ 1162 void rcu_hxtal_clock_monitor_disable(void); 1163 1164 /* set the IRC16M adjust value */ 1165 void rcu_irc16m_adjust_value_set(uint32_t irc16m_adjval); 1166 /* configure the spread spectrum modulation for the main PLL clock */ 1167 void rcu_spread_spectrum_config(uint32_t spread_spectrum_type, uint32_t modstep, uint32_t modcnt); 1168 /* enable the spread spectrum modulation for the main PLL clock */ 1169 void rcu_spread_spectrum_enable(void); 1170 /* disable the spread spectrum modulation for the main PLL clock */ 1171 void rcu_spread_spectrum_disable(void); 1172 /* unlock the voltage key */ 1173 void rcu_voltage_key_unlock(void); 1174 /* set the deep sleep mode voltage */ 1175 void rcu_deepsleep_voltage_set(uint32_t dsvol); 1176 1177 /* get the system clock, bus and peripheral clock frequency */ 1178 uint32_t rcu_clock_freq_get(rcu_clock_freq_enum clock); 1179 1180 #endif /* GD32F4XX_RCU_H */ 1181
